Feedback loop for controlling a pulsed voltage waveform

Abstract

To provide an apparatus and method of controlling the delivery of power to plasma formed in a plasma processing chamber used in semiconductor manufacturing.SOLUTION: A feedback loop 100 electrically coupled to one or more electrical components found in a plasma processing system 50 is used to maintain a nearly constant sheath voltage and thus create a mono-energetic ion energy distribution function (IEDF) at a surface of a substrate. Multiple input channels 110N electrically coupled to respective acquisition channels 122N of a fast data acquisition module within the feedback loop have different degrees of attenuation of an incoming signal because of differences in types of components such as voltage dividing components or filtering components found within the respective input channels. The fast data acquisition module also comprises a data acquisition controller and a non-volatile memory.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001]

[0001] The embodiments described herein generally relate to plasma processing chambers used in semiconductor manufacturing, and more specifically, to an apparatus and method for controlling the supply of power to the plasma formed within a plasma processing chamber.

Background Art

[0002]

[0002] Reliably manufacturing high aspect ratio features is one of the important technical challenges in next-generation very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process (e.g., a reactive ion etch (RIE) plasma process) to form high aspect ratio openings in a material layer of a substrate (e.g., a dielectric layer). In a typical RIE plasma process, plasma is formed within an RIE processing chamber, ions from the plasma are accelerated towards the surface of the substrate, and an opening is formed in the material layer disposed beneath the mask layer formed on the surface of the substrate.

[0003]

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias generator. The RF bias generator supplies an RF voltage to a “power electrode” (e.g., a bias electrode), more commonly referred to as a “cathode”, such as a metal base plate embedded in an “electrostatic chuck” (ESC) assembly. The power electrode is capacitively coupled to the plasma of the processing system through a thick layer of a dielectric material (e.g., a ceramic material) that is part of the ESC assembly. The application of the RF voltage to the power electrode forms an electron-repelling plasma sheath (also called a “cathode sheath”) on the processing surface of the substrate disposed on the substrate support surface of the ESC assembly during processing. The non-linear diode-like nature of the plasma sheath causes rectification of the applied RF electric field, resulting in a direct current (DC) voltage drop (i.e., a “self-bias”) appearing between the substrate and the plasma, and the substrate potential becoming negative with respect to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated towards the substrate and, thus, determines the etching anisotropy. More specifically, the ion directionality, feature profile, and etching selectivity with respect to the mask layer and the stop layer are controlled by the Ion Energy Distribution Function (IEDF). In a plasma with an RF bias, the IEDF typically has two peaks. One is at low energy and the other is at high energy, with some ion population in between. The presence of an ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates at the RF bias frequency. When using an RF bias generator with a lower frequency (e.g., 2 MHz) to achieve a higher self-bias voltage, the energy difference between these two peaks can be important. And since the etching profile caused by the ions at the low energy peak is more isotropic, curvature of the etched feature walls may result.Compared with high-energy ions, low-energy ions have a lower effect of reaching the corners at the bottom of the etched feature (e.g., due to the charging effect), but do not cause much sputtering of the mask material. This is important in high aspect ratio etching applications such as hard mask opening or dielectric mold etching. As the feature size continues to decrease, the aspect ratio increases, and on the other hand, as the requirements for controlling the feature profile become more stringent, it becomes more desirable to have a well-controlled IEDF on the substrate surface during processing.

[0004]

[0004] Using a pulsed voltage waveform generator (PVWG), a pulsed voltage waveform is generated by electrodes embedded in an electrostatic chuck (ESC) assembly in a semiconductor plasma chamber to maintain a specific substrate voltage waveform, and the sheath voltage and IEDF can be controlled on the substrate during plasma processing. When a semiconductor plasma chamber is used as a load, difficulties in controlling the generated waveform can occur due to real-time changes in the load (e.g., plasma density flow, chamber wall conditions, substrate temperature, degree and state of chemical dissociation). Therefore, in order to perform real-time adjustment of PVWG control parameters (e.g., charging voltage of the DC power supply or pulse width controlled by any waveform generator) and thus maintain a predetermined voltage waveform regardless of load changes, real-time information about the waveform can be very useful. Such real-time measurement and analysis performed along with real-time control are often referred to as "closed feedback loop operation". However, in the measurement and analysis of pulsed voltage waveforms, certain difficulties arise due to their very high amplitudes (e.g., from several kV to tens of kV as frequently seen in plasma processing) and due to the complex characteristics of loads such as semiconductor plasma chambers. When the PVWG is connected to a complex load (which may include series and / or parallel combinations of discrete, capacitive, inductive, resistive, and non-linear elements (e.g., plasma sheath at the substrate surface in the process chamber) and distributed elements (e.g., part of a transmission line)), the generated waveform has a much more complex structure than the theoretically predicted (expected) waveform and may include high-frequency oscillations, which can affect the ability to repeatedly control the plasma process.

[0005]

[0005] Therefore, in the art, there is a need for a new biasing method that enables the maintenance of a substantially constant sheath voltage and thus generates a desired and repeatable single-energetic IEDF on the substrate surface in order to enable precise control over the shape of the IEDF and the profile of the features formed on the surface of the substrate.

[0006]

[0006] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and, therefore, should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be permitted.

Brief Description of the Drawings

[0007]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 2

Figure 3

Figure 4

Figure 5A-5D

Figure 6A-6B

Figure 7A

Figure 7B

Figure 8A

Figure 8B

Figure 9A

Figure 9B

Figure 9C

Figure 10

Figure 11

[0008]

[0025] For ease of understanding, where possible, the same reference numbers are used to indicate the same elements common to the figures. Even without further description, it is contemplated that the elements and features of one embodiment can be beneficially incorporated into other embodiments. SUMMARY OF THE INVENTION

[0009]

[0026] Embodiments of the disclosure provided herein are feedback loops for controlling a pulsed voltage waveform, comprising a data collection system, a first input channel including a first conditioning circuit configured to generate a first conditioned voltage waveform from a first input voltage waveform, and a feedback loop comprising a high-speed data collection module. The high-speed data collection module may include a first collection channel electrically coupled to the first conditioning circuit of the first input channel and configured to generate a first digitized voltage waveform from the first conditioned voltage waveform, and a data collection controller configured to determine one or more one-cycle waveform characteristics of the first conditioned voltage waveform by analyzing the first digitized voltage waveform. The feedback loop may further include a feedback processor configured to process information regarding the first conditioned voltage waveform processed by the high-speed data collection module. In some embodiments, the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically coupled to a bias electrode disposed within a substrate support assembly disposed within a plasma processing chamber.

[0010]

[0027] Embodiments of the disclosure provided herein are feedback loops for controlling a pulsed voltage waveform with a data collection system, including a first input channel including a first adjustment circuit configured to generate a first adjusted voltage waveform from a first input voltage waveform, a second input channel including a second adjustment circuit configured to generate a second adjusted voltage waveform from a second input voltage waveform, and may further include a high-speed data collection module. The high-speed data collection module is electrically connected to the first adjustment circuit of the first input channel, and includes a first collection channel configured to generate a first digitized voltage waveform from the first adjusted voltage waveform, a second collection channel electrically connected to the second adjustment circuit of the second input channel and configured to generate a second digitized voltage waveform from the second adjusted voltage waveform, and may include a data collection controller configured to determine one or more one-cycle waveform characteristics of at least one of the first adjusted voltage waveform and the second adjusted voltage waveform by analyzing at least one of the first digitized voltage waveform and the second digitized voltage waveform. In some embodiments, the pulsed voltage waveform is established by a pulsed voltage waveform generator electrically connected to a bias electrode disposed within a substrate support assembly disposed within a plasma processing chamber. In some embodiments, the pulsed voltage waveform generator is further electrically connected to the bias electrode via an electrical conductor using a generator connection assembly, the input end of the first input channel is electrically connected to an end of the generator connection assembly, the input end of the second input channel is electrically connected to one of an output of a current monitor and a non-grounded end of a current sensing resistor, the current monitor is configured to sense a current flowing through the electrical conductor, and the current sensing resistor is disposed within the pulsed voltage waveform generator.

Best Mode for Carrying Out the Invention

[0011]

[0028] Embodiments of the disclosure provided herein include a closed feedback loop scheme suitable for operation with a pulsed voltage waveform generator to generate a controlled and repeatable pulsed voltage waveform. Thus, the embodiments described herein can be used in many different types of plasma-assisted processing chambers or plasma-enhanced processing chambers used to perform plasma-assisted processing or plasma-enhanced processing of substrates. Although not intended to limit the scope of the disclosure provided herein, in some embodiments, a pulsed voltage bias scheme is used during plasma processing to maintain a substantially constant sheath voltage up to approximately 90% of the maximum substrate processing time, resulting in a single (narrow) peak IEDF that can also be used to generate an IEDF of any shape. Further, in one or more of the embodiments disclosed herein, the plasma processing method includes a pulsed voltage waveform that further includes a plurality of cycles (e.g., a series of cycles of short positive pulses repeating at a period Ts (e.g., 2.5 microseconds)), where the total period Tp of each pulse is typically on the order of tens of nanoseconds (e.g., 10 to 100 nanoseconds), and each cycle of the plurality of cycles corresponds to one or more pulses.

[0012]

[0029] FIG. 1A schematically shows a feedback loop 100 electrically coupled to one or more electrical components found within a plasma processing system 50. Generally, feedback loop 100 includes one or more input channels 110 and a high-speed data collection module 120. One or more input channels 110 are electrically coupled to high-speed data collection module 120. In some embodiments, high-speed data collection module 120 is configured to control and maintain the generated pulsed voltage waveform (e.g., a high-voltage nanosecond substrate voltage waveform), whereby the sheath voltage and IEDF are controlled at the substrate during plasma processing. Further, high-speed data collection module 120 includes one or more collection channels 122.

[0013]

[0030] The input ends of one or more input channels 110 are coupled to a connection point 135 within the plasma processing system 50. Thus, control parameters can be supplied to a pulsed waveform generator (e.g., the pulsed voltage waveform generator (PVWG) 150 of FIG. 1B) within the plasma processing system 50 to control the characteristics of a pulsed voltage waveform established by an electrode (e.g., a bias electrode disposed within a substrate support) positioned within the processing chamber of the plasma processing system 50. An input pulsed voltage waveform 140 received and then adjusted by one or more input channels 110 can be processed by components within the high-speed data collection module 120 and components within the feedback processor 125. The one or more input channels 110 receive the input pulsed voltage waveform 140 and generate an output waveform 144 from the input pulsed voltage waveform 140. As will be described in more detail in the following description, the input pulsed voltage waveform 140 can be processed by the input channels 110 to generate an output waveform 144 that includes an adjusted waveform. For example, the input channels 110 can adjust the received input pulsed voltage waveform 140 via an adjustment circuit to generate the output waveform 144. Thus, for example, the amplitude and / or shape of the output waveform 144 may be different from the amplitude and / or shape of the input pulsed voltage waveform 140. Note that the characteristics of the pulsed voltage waveform (i.e., the input pulsed voltage waveform 140) received by the input channels 110 can have different characteristics depending on the position of the connection point 135 with respect to inductive, capacitive, or resistive elements formed and / or disposed within one or more circuits coupled to the complex load 130 (FIG. 1B) of the plasma processing system 50. In some embodiments, the input channels 110 within the feedback loop 100 can each have a different degree of attenuation of various input signals due to differences in the types of components (e.g., voltage-dividing components or filtering components) within each input channel. Thus, herein, the input channels 110 can be referred to as high-attenuation, medium-attenuation, or low-attenuation, or non-attenuated channels based on the degree of attenuation or adjustment of the received input pulsed voltage waveform 140.

[0014]

[0031] FIG. 1B schematically shows an example of the feedback loop 100 shown in FIG. 1A. This includes a plurality of input channels 110 each electrically connected to a corresponding collection channel 122 of the high-speed data collection module 120. As shown in FIG. 1B, the input channels 110 can be connected to connection points connected to conductive elements disposed on both sides of the generator connection assembly 133. All of these are used in combination to connect the output of the PVWG 150 to the composite load 130. Generally, the conductive elements and the generator connection assembly 133 used to connect the output of the PVWG 150 to the composite load 130 are often referred to herein as elements within the transmission line 131. Thus, the PVWG 150 is electrically connected to the composite load 130 via the transmission line 131 and the reference line 132. Generally, the terms "electrical conductor" or "conductor" as used herein can include the following: (a) a coaxial transmission line that can include a flexible coaxial cable in series with a rigid coaxial transmission line, (b) an insulating high-voltage corona-resistant hook-up wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). FIG. 1B schematically shows a configuration in which a plurality of input channels 110 are connected to connection points connected to one of one or more conductive elements used to connect the output of the PVWG 150 to the composite load 130 and / or one or more circuits within the PVWG 150, but this configuration is not intended to limit the scope of the disclosure provided herein. This is because the number of input channels 110 and / or the number of various positions where the various input channels 110 can be connected within the plasma processing system 50 can be increased or decreased as needed to control the desired chamber processing applications.

[0015]

[0032] As shown in FIG. 1B, the plasma processing system 50 includes a pulsed voltage waveform generator (PVWG), such as PVWG 150 of the processing chamber 800 schematically illustrated in FIGS. 8A and 8B. Further, the plasma processing system 50 includes a composite load 130. The composite load 130 includes a pulsed voltage waveform at a bias electrode (e.g., bias electrode 804 in FIG. 8A) during plasma processing and / or is formed by the generation of a pulsed voltage waveform. The feedback loop 100 is generally configured to control the pulsed voltage waveform by adjusting one or more characteristics of the pulsed voltage waveform generated by the PVWG 150.

[0016]

[0033] One or more of the input channels 110 may include conditioning circuits 111 such as, for example, a conditioning circuit 1111 within input channel 1101 and a conditioning circuit 1112 within input channel 1102. Further, one or more input channels 110 are configured to generate a conditioned output waveform 144. In some embodiments, each conditioning circuit 111 may include a voltage divider (e.g., voltage divider 112 of FIG. 2), a low-pass filter 114 (e.g., the low-pass filter of FIG. 3), both a voltage divider and a low-pass filter 114, or in some cases, may include a state where there is no voltage divider nor low-pass filter 114, which is herein referred to as an unattenuated conditioning circuit. In one example, feedback loop 100 includes at least three conditioning circuits 111, one conditioning circuit includes a high-ratio voltage divider, another conditioning circuit includes a medium-ratio voltage divider, and yet another conditioning circuit includes only a filter and thus does not include a voltage divider. In embodiments where the conditioning circuit 111 of input channel 110 includes a voltage divider and further a low-pass filter, the voltage divider 112 is electrically coupled to the low-pass filter 114. Further, in such embodiments, the voltage divider generates a divided voltage waveform from the input pulsed voltage waveform 140, and the low-pass filter generates a filtered voltage waveform from the divided voltage waveform. In embodiments where the low-pass filter is omitted, the voltage divider generates a divided voltage waveform from the input pulsed voltage waveform 140, and the divided voltage waveform is communicated to the high-speed data acquisition module 120. In such embodiments, the divided voltage waveform is a conditioned voltage waveform, which is the output waveform 144. In embodiments where both the voltage divider and the low-pass filter are omitted from input channel 110, the input pulsed voltage waveform 140 is also the output waveform 144. In embodiments where the voltage divider is omitted but the low-pass filter is present within conditioning circuit 111, the low-pass filter generates a filtered voltage waveform from the input pulsed voltage waveform 140, and the filtered waveform is communicated to the high-speed data acquisition module 120.

[0017]

[0034] FIG. 1B shows input channels 1101-110 Nis shown. Here, N is generally a number greater than 1 (e.g., a number greater than 3), as shown in FIG. 1B. Input channels 1101 to 110 N each may be connected to various points within the plasma processing system 50. For example, input channel 1101 may be connected to electrical conductors disposed on both sides of the generator connection assembly 133, which may include a blocking capacitor (e.g., capacitor C of FIG. 8B HVM ). For example, input channel 1101 may be connected between the composite load 130 and the generator connection assembly 133, or input channel 1101 may be connected between the output of the PVWG 150 and the generator connection assembly 133. In an embodiment where input channel 1101 is connected between the output of the PVWG 150 and the generator connection assembly 133, input channel 1101 receives the input pulsed voltage waveform 140 1A and the adjustment circuit 1111 generates an output waveform (e.g., an adjusted waveform) 144 1A . In one example, the received or measured input pulsed voltage waveform 140 1A includes voltage pulses (i.e., the pulses are above and below the dashed zero-volt reference line) that include positive and negative voltage levels at various phases of each voltage pulse, as well as high-frequency oscillations within various phases of the pulses within the input pulsed voltage waveform 140 1A (see, e.g., the dashed circles highlighting the regions of the pulses), which, when adjusted by components such as voltage dividers within the adjustment circuit 111 1A , form the output waveform 144 that is supplied at at least a lower voltage level by the use of the voltage divider 1A . In an embodiment where input channel 1101 is connected between the composite load 130 and the generator connection assembly 133, input channel 1101 receives the input pulsed voltage waveform 140 1B and the adjustment circuit 1111 generates an output waveform (e.g., an adjusted waveform) 144 1B . As shown in FIG. 1B, the input pulsed voltage waveform 140 1A is, due to the position of each connection point along the transmission line 131 within the plasma processing system 50, the input pulsed voltage waveform 140 1BIt has different waveform characteristics. Alternatively, in one embodiment, as shown in FIG. 1B, the received or measured input pulsed voltage waveform 140 1B is the input pulsed voltage waveform 140 1B (e.g., in pulse region I 1B ) includes a positive voltage pulse containing high-frequency oscillations within the phase of the pulse (i.e., the pulse is above the dashed zero-volt reference line), which, when adjusted by components such as a voltage divider and a low-pass filter within the adjustment circuit 111 1B forms an output waveform 144 that is a filtered waveform with a reduced voltage level 1B .

[0018]

[0035] Referring further to FIG. 1B, the input channel 1102 is connected to or attached to the current monitor 134 within the PVWG 150. Thus, the input channel 1102 receives the input pulsed voltage waveform 1402, and the adjustment circuit 1112 generates an output waveform (adjusted waveform) 1442. In one embodiment, as shown in FIG. 1B, the received or measured input pulsed voltage waveform 1402 includes voltage pulses containing positive and negative voltage levels at various phases of each voltage pulse, as well as high-frequency oscillations (e.g., refer to the dashed circle highlighting the pulse region) within at least one of the phases of each pulse within the input pulsed voltage waveform 1402, which, when adjusted by components such as a voltage divider and a low-pass filter, form an output waveform 1442 within the adjustment circuit 1112 that is a filtered waveform with a reduced voltage level

[0019]

[0036] Furthermore, input channel 1103 is connected to the current detection resistor 139 of PVWG150. Accordingly, input channel 1103 receives input pulsed voltage waveform 1403, and adjustment circuit 1113 generates an output waveform (adjusted waveform) 1443. In one embodiment, as shown in FIG. 1B, the received or measured input pulsed voltage waveform 1403 includes a positive voltage pulse and high-frequency oscillations within at least one of the phases of each pulse within input pulsed voltage waveform 1403 (see, for example, the dashed circle), and when these are adjusted by components within adjustment circuit 1113 such as a low-pass filter, they form output waveform 1443 which is a filtered waveform.

[0020]

[0037] In some embodiments, additional input channels such as input channels 1104 through 110 N are connected to other connection points within plasma processing system 50 to receive additional information regarding the supplied pulsed voltage waveform and / or the state of the plasma processing being performed within the plasma processing chamber. Further, adjustment circuit 111 N is configured to generate a corresponding output waveform 144 N Input channels 110 N receive the input pulsed voltage waveform 140 N and adjustment circuit 111 N generates an output waveform (adjusted waveform) 144 N Accordingly, any of adjustment circuits 111 such as adjustment circuit 111 N may include any combination of voltage divider 112 (FIG. 2) and low-pass filter 114 (FIG. 3), or may include neither voltage divider 112 nor low-pass filter 114.

[0021]

[0038] As shown in FIG. 1B, input pulsed voltage waveforms 140 1A through 1403 are each different from one another. Accordingly, the corresponding output waveforms 144 1A~1443 are also different from each other. Therefore, depending on the position where the input end of the input channel 110 is connected to the plasma processing system 50, the characteristics of the input pulse-shaped voltage waveform and the output waveform change. Thus, the selection of the connection position of each input channel affects the information received by the feedback loop 100, and thereby can affect the ability of the feedback loop 100 to control the pulse-shaped voltage waveform.

[0022] High-speed data acquisition module

[0039] The high-speed data acquisition module 120 is generally configured to receive an analog voltage waveform (e.g., the adjustment waveform 144) and transmit a digitized voltage waveform. The high-speed data acquisition module 120 includes one or more acquisition channels 122 electrically connected to the respective adjustment circuits 111 of the first input channels 110. The high-speed data acquisition module 120 is configured to generate a digitized voltage waveform from the received adjustment voltage waveform (e.g., the output waveform 144). The data acquisition controller 123 of the high-speed data acquisition module 120 is configured to determine one or more waveform characteristics of the adjustment voltage waveform (e.g., the output waveform 144) by analyzing the first digitized voltage waveform. As shown in FIG. 1B, the high-speed data acquisition module 120 includes a plurality of acquisition channels 1221~122 N , a data acquisition controller 123, and a memory 124 (e.g., a non-volatile memory). Each acquisition channel 122 is electrically connected to the output of the corresponding channel among the input channels 110 so that the acquisition channel 122 receives the output waveform 144 from the corresponding channel among the input channels 110. For example, the acquisition channel 1221 is electrically connected to the output end of the input channel 1101, and depending on the position of the connection point of the input end of the input channel 1101, the output waveform 144 1A or 144 1BReceives any one of them. Further, the collection channel 1222 is electrically connected to the output terminal of the input channel 1102 and receives the output waveform 1442. Additionally, or alternatively, the collection channel 1223 is electrically connected to the output terminal of the input channel 1103 and receives the output waveform 1443. The collection channel 122 N is electrically connected to the output terminal of the input channel 110 N and receives the output waveform 144 N .

[0023]

[0040] In some embodiments, the high-speed data collection module 120 is connected to the feedback processor 125 via the data communication interface 125A. The feedback processor 125 is configured to generate one or more control parameters using one or more waveform characteristics determined by one or more algorithms executed by a processor in the data collection controller 123. The one or more algorithms stored in the memory 124 include instructions that, when executed by the processor 121 in the high-speed data collection module, cause the high-speed data collection module to process the output waveform 144 (e.g., one or more regulated voltage waveforms) and determine one or more waveform characteristics of the received output waveform 144. As further described below, the feedback processor 125 includes a memory containing instructions that, when executed by a processor (CPU) in the feedback processor 125, cause the feedback processor 125 to use one or more determined waveform characteristics supplied from the high-speed data collection module 120 to generate one or more control parameters. The instructions executed by the feedback processor may be further configured to cause the feedback processor to transmit information regarding the generated one or more control parameters to the PVWG 150. The PVWG 150 may further include a memory containing instructions that, when executed by a processor in the PVWG 150, cause the PVWG 150 to establish an adjusted pulsed voltage waveform based on one or more control parameters generated by the feedback processor 125.

[0024]

[0041] As described above, each collection channel 122 processes the corresponding output waveform 144 output by the corresponding input channel 110 to generate a digitized voltage waveform from the output waveform. For example, collection channel 1221 processes output waveform 144 1A or 144 1B to generate a digitized voltage waveform. Further, collection channel 1222 processes output waveform 1442 to generate a digitized voltage waveform, and collection channel 1223 processes output waveform 1443 to generate a digitized voltage waveform. Additionally or alternatively, collection channel 122 N processes output waveform 144 N to generate a digitized voltage waveform.

[0025]

[0042] The data collection module 120 further includes a data collection controller 123. The data collection controller 123 is electrically connected to the output of each collection channel 122 and is configured to receive the digitized voltage waveform from each collection channel 122. Further, the algorithm stored in the memory 124 of the data collection controller 123 is adapted to determine one or more waveform characteristics of each adjusted waveform (e.g., output waveform 144) by analyzing each digitized voltage waveform. The analysis may include a comparison of the information received in the digitized voltage waveform with the information regarding one or more waveform characteristics stored in the memory 124, which will be further described below.

[0026]

[0043] The data collection controller 123 may include one or more of an analog-to-digital converter (ADC), a processor 121 (FIG. 1C), a communication interface (not shown), a clock (not shown), and an optional driver (not shown). The processor may be any general-purpose arithmetic processor. Further, the processor may be a Field Programmable Gate Array (FPGA). The ADC converts the signal in the output waveform 144 from the analog domain to the digital domain, and the output digital signal of the ADC is supplied to the processor 121 for processing. The processor 121 of the data collection controller 123 determines one or more waveform characteristics of the output waveform by analyzing the output digital signal supplied from the ADC.

[0027]

[0044] In various embodiments, the data collection module 120 further includes a memory 124. The memory 124 may be any non-volatile memory. Further, the data collection controller 123 is electrically connected to the memory 124 and is configured to store the waveform characteristics in the memory 124. In various embodiments, the memory 124 includes instructions executable by the data collection controller 123, and the instructions cause the data collection controller 123 to analyze the received output waveform 144 and / or transmit information corresponding to the waveform characteristics determined based on the analysis of the received output waveform 144.

[0028]

[0045] In various embodiments, the memory 124 includes one or more of a data logger 124A, a waveform analyzer 124B, and executable instructions 124C. The data collection controller 123 may be configured to store information corresponding to waveform characteristics in the data logger 124A of the memory 124. For example, the data logger 124A may include a database accessible by the data collection controller 123 to store information corresponding to waveform characteristics. The waveform analyzer 124B includes instructions executable by the data collection controller 123, which when executed, cause the data collection controller 123 to analyze the output waveform 144 and determine waveform characteristics. The executable instructions 124C are executable by the data collection controller 123, which when executed, cause the data collection controller 123 to transmit waveform characteristics or information corresponding to waveform characteristics to one or more of the feedback processor 125, the controller 127, the controller 128, and the controller 191. In one embodiment, when the executable instructions 124C are executed by the data collection controller 123, the data collection controller 123 stores waveform characteristics in the data logger 124A and, in particular, analyzes waveform characteristics in relation to one or more thresholds.

[0029]

[0046] The data collection controller 123 is configured to receive and / or analyze the digitized voltage waveforms from the respective corresponding collection channels 122 in parallel. Alternatively, the data collection controller 123 is configured to receive and / or analyze the digitized voltage waveforms from the respective corresponding collection channels 122 in series.

[0030]

[0047] As described above, the data collection module 120 can be electrically (wired or wirelessly) connected to the feedback processor 125. The feedback processor 125 may be any general-purpose arithmetic processor. In some embodiments, the feedback processor 125 is generally an external processor connected to the high-speed data collection module 120 via a data communication interface, an internal processor integrated within the high-speed data collection module 120, or a controller for a substrate processing chamber (e.g., the processing chamber controller 126) connected to the high-speed data collection module via a data communication interface. The data collection module 120 can communicate information corresponding to one or more of the received output waveforms 144 to the feedback processor 125. For example, the data collection module 120 can communicate information regarding one or more detected and / or processed waveform characteristics of one or more of the received output waveforms 144 to the feedback processor 125. Further, the feedback processor 125 may be communicatively coupled to the plasma processing system 50. In various embodiments, as described above, the feedback processor 125 includes or is coupled to a memory, and the memory further includes software algorithms for instructing the processor within the feedback processor 125 to execute one or more portions of the methods described herein.

[0031]

[0048] In one or more embodiments, the data collection module 120 may be electrically (wired or wirelessly) coupled to a process chamber controller 126 of a process chamber (e.g., the process chamber 800 of FIG. 8A), or to a process system that includes the process chamber. For example, the data collection module 120 communicates data with the process chamber controller 126 (FIG. 1D). For example, the data collection module 120 communicates information regarding one or more waveform characteristics to the process chamber controller 126. Further, the process chamber controller 126 may be communicatively coupled to the plasma processing system 50. In various embodiments, the process chamber controller 126 is omitted. The process chamber controller 126 may separately include a controller CPU (not shown), non-volatile memory (not shown), a graphical user interface (GUI) (not shown), and other useful hardware and software components that are encoded to command the CPU and may be stored in the memory. Algorithms stored in the memory of the process chamber controller 126 may include instructions that, when executed by the controller CPU, cause adjustments to various process chamber set points (e.g., chucking voltage set points on a chucking power supply) based on information regarding one or more waveform characteristics determined by the data collection controller 123.

[0032]

[0049] In one or more embodiments, the data collection module 120 is electrically (wired or wirelessly) coupled to a controller 127 that includes a removable memory device. For example, the data collection module 120 communicates data with the controller 127. For example, the data collection module 120 communicates information regarding one or more waveform characteristics to the removable memory device of the controller 127.

[0033]

[0050] In various embodiments, the data collection module 120 is electrically (wired or wirelessly) coupled to an external computing device via a communication interface. The data collection module 120 transmits and receives data with an external computing device (e.g., a computing device external to the high-speed data collection module 120). For example, the data collection module 120 communicates (e.g., transmits and receives data) with a controller of a computing device such as controller 128 (FIGS. 1B-1D). The data collection module 120 can communicate one or more detected and / or processed waveform characteristics to the controller 128. The controller 128 can be, among other things, a personal computer (PC) or a mobile computing device. Further, the controller 128 may be communicatively coupled to the data collection module 120 and / or the plasma processing system 50 (e.g., via an Ethernet connection). In various embodiments, the controller 128 is omitted.

[0034]

[0051] As will be described in more detail in the following description and the description of FIGS. 5A-5D, determining one or more waveform characteristics generally involves a period (T cycle ) of one cycle of a pulse, a rise time (T rise ) of the pulse, a fall time (T fall ) of the pulse, an offset of the pulse from a reference voltage (e.g., zero volts), an amplitude of the pulse, a pulse width, a direct current (DC) voltage offset, and a phase of the pulsed voltage waveform (e.g., an ion current phase (also referred to herein as an "ion current" waveform characteristic)), including but not limited to determining one or more of the pulse waveform characteristics generated between one or more of the phases. Additionally or alternatively, determining one or more waveform characteristics includes determining waveform characteristics of a burst of pulses (e.g., a T on period, a T off period) as illustrated in FIG. 7B.

[0035]

[0052] Figure 1C shows a part of the feedback loop 100A according to one or more embodiments. The feedback loop 100A is configured in a similar manner to the feedback loop 100 of Figure 1B. For example, the feedback loop 100A includes a high-speed data collection module 120 having a collection channel 122, a data collection controller 123A, and a memory 124. However, compared with the feedback loop 100 of Figure 1B, the feedback processor 125 can be integrated with the process chamber controller 126. The integrated feedback processor 125 may, in this case, include a processor 126B and a memory 126A, and the memory 126A includes a data logger and an algorithm solver (e.g., software instructions for determining control parameters). In the configuration shown in Figure 1C, since the functions of the feedback processor 125 are executed by components within the process chamber controller 126, the feedback loop 100 may not include an individual feedback processor 125.

[0036]

[0053] Figure 1D shows a part of the feedback loop 100B according to one or more embodiments. The feedback loop 100B is configured in a similar manner to the feedback loop 100 of Figure 1B. For example, the feedback loop 100B includes a high-speed data collection module 120 including a collection channel 122 and a memory 124'. However, compared with the feedback loop 100 of Figure 1B, the feedback loop 100B does not include a feedback processor 125. For example, in the embodiment of Figure 1D, the data collection controller 123B has the functionality of the data collection controller 123 of Figure 1B and the feedback processor 125 of Figure 1B. In this embodiment, the data collection controller 123B functions to both analyze the output waveform 144 to determine waveform characteristics and determine control parameters and communicate them to the PVWG 150.

[0037]

[0054] In one or more embodiments, data collection controller 123 is coupled to monitor 129 within controller 191 via a digital interface. For example, data collection controller 123 is coupled to controller 191 and monitor 129 via, among other things, a Digital Visual Interface (DVI), a High-Definition Multimedia Interface (HDMI), or a Video Graphics Array (VGA). Data collection controller 123 communicates information corresponding to one or more waveform characteristics to monitor 129 for display on monitor 129 for a user to view.

[0038]

[0055] FIG. 2 is a schematic diagram of a voltage divider (e.g., voltage divider 112) of the adjustment circuit 111 according to one or more embodiments. As shown in FIG. 2, the voltage divider 112 may include a first cascade voltage divider 210 and a second voltage divider cascade 212. The voltage divider 112 is electrically coupled to the low-pass filter 114 via one or more electrical connections such as signal line 221 and ground reference line 223. The first cascade voltage divider 210 includes resistor R1, resistor R2, capacitor C1, and capacitor C2. The second cascade voltage divider 212 includes resistor R4, resistor R5, capacitor C3, and capacitor C4. The resistance of resistor R1, the resistance of resistor R2, the capacitance of capacitor C1, and the capacitance of capacitor C2 are selected to generate a first voltage division ratio. For example, the first voltage division ratio may range from about 1 to 20 to about 1 to 60. Further, the resistance of resistor R1 is greater than the resistance of resistor R2, and the capacitance of capacitor C2 is greater than the capacitance of capacitor C1. For example, the resistance of resistor R1 may be about 950 kiloohms, and the resistance of resistor R2 may be about 20 kiloohms. Alternatively, the resistance of resistor R1 may be less than or greater than 950 kiloohms, and the resistance of resistor R2 may be less than or greater than 20 kiloohms. Additionally, the capacitance of capacitor C2 may be about 650 pF, and the capacitance of capacitor C1 may be about 15 pF. Alternatively, the capacitance of capacitor C2 may be less than or greater than 650 pF, and the capacitance of capacitor C1 may be less than or greater than 15 pF.

[0039]

[0056] The resistance of resistor R4, the resistance of resistor R5, the capacitance of capacitor C3, and the capacitance of capacitor C4 are selected to generate a second voltage division ratio of the second voltage divider cascade 212. In some embodiments, the second voltage division ratio is greater than the first voltage division ratio. For example, the second voltage division ratio may be in the range of about 1 to 80 to about 1 to 120. Further, the resistance of resistor R4 is greater than the resistance of resistor R5, and the capacitance of capacitor C4 is greater than the capacitance of capacitor C1. For example, the resistance of resistor R4 may be about 1000 kiloohms, and the resistance of resistor R5 may be about 10 kiloohms. Alternatively, the resistance of resistor R4 may be less than or greater than 1000 kiloohms, and the resistance of resistor R5 may be less than or greater than 10 kiloohms. Additionally, the capacitance of capacitor C4 may be about 1.5 nF, and the capacitance of capacitor C3 may be about 15 pF. Alternatively, the capacitance of capacitor C4 may be less than or greater than 1.5 nF, and the capacitance of capacitor C3 may be less than or greater than 15 pF.

[0040]

[0057] In some embodiments, the first cascade voltage divider 210 is connected to the second voltage divider cascade 212 via resistor R3. The resistance of resistor R3 may be, for example, about 200 kiloohms. Alternatively, the resistance of resistor R3 may be greater than or less than about 200 kiloohms. Resistor R3 can filter out high frequencies from the input pulsed voltage waveform 140. By changing the values of capacitors C1 - C4 and resistors R1, R2, R4, and R5, the voltage division ratio of voltage divider 112 can be varied. For example, increasing the difference between R1 and R2 and the difference between C1 and C2, and / or increasing the difference between R4 and R5 and the difference between C3 and C4 will increase the voltage division ratio, while decreasing the difference between R1 and R2 and the difference between C1 and C2, and / or decreasing the difference between R4 and R5 and the difference between C3 and C4 will decrease the voltage division ratio. In some embodiments, the first voltage divider cascade 210 has a voltage division ratio in the range of about 1 to 10 to about 1 to 100, and the second voltage divider cascade 212 has a voltage division ratio in the range of about 1 to 20 to about 1 to 120.

[0041]

[0058] In embodiments where input channel 110 includes voltage divider 112 and low - pass filter 114, the input of low - pass filter 114 is electrically connected to the output of voltage divider 112 such that low - pass filter 114 receives the divided voltage waveform from voltage divider 112. Further, low - pass filter 114 has a frequency response curve including a plateau and a cut - off frequency. For example, the filter response of low - pass filter 114 has a plateau at frequencies below the bandwidth frequency of about - 3dB. The plateau of low - pass filter 114 is within the range from DC to about 7 MHz, and the cut - off frequency is within the range from about 5 MHz to about 10 MHz. FIG. 4 shows an example of the frequency response curve (e.g., frequency response curve 400) of low - pass filter 114. As shown, the filter response curve has a plateau at frequencies below the bandwidth (e.g., - 3dB) frequency of about 7.3 MHz. Alternatively, the bandwidth frequency may be greater than or less than about 7.3 MHz.

[0042]

[0059] FIG. 3 is a schematic diagram of a low-pass filter (e.g., low-pass filter 114) of the adjustment circuit 111 according to one or more embodiments. As shown in FIG. 3, the low-pass filter 114 includes a filter cascade 222 and a filter cascade 224. The filter cascade 222 may be a two-stage Chebyshev filter. For example, the filter cascade 222 may be a two-stage Chebyshev filter having a stop-band attenuation of about 0.1 dB. Alternatively, a two-stage Chebyshev filter having a stop-band attenuation lower or higher than 0.1 dB may be utilized. The filter cascade 222 includes resistors R6 and R7, capacitors C6 and C5, and an operational amplifier 225. The resistances of the resistors R6 and R7 may be the same. For example, the resistances of the resistors R6 and R7 may be about 50 ohms. However, other resistance values may be utilized. Further, in one example, the capacitance of the capacitor C6 may be about 360 pF, and the capacitance of the capacitor C5 may be about 147 pF. However, other capacitance values may be utilized. In addition, the filter cascade 222 may have a cut-off frequency of about 15 MHz. Alternatively, the filter cascade 222 may have a cut-off frequency smaller or larger than about 15 MHz.

[0043]

[0060] The input of filter cascade 224 is electrically connected to the output of filter cascade 222. Filter cascade 224 is an LCL filter cascade. Further, filter cascade 224 may be a fifth-order Butterworth filter. Additionally, filter cascade 224 may have a cut-off frequency less than the cut-off frequency of filter cascade 222. For example, filter cascade 224 may have a cut-off frequency of about 7.3 MHz. Alternatively, filter cascade 224 may have a cut-off frequency less than or greater than about 7.3 MHz. Filter cascade 224 includes resistors R8 and R9, inductors L1, L2, and L3, and capacitors C10 and C11. The resistance of resistor R8 can be about 400 kiloohms, but other resistance values may be utilized. Further, the inductance of inductor L1 may be about 5.4 uH, the inductance of inductor L2 may be about 17.5 uH, and the inductance of inductor L3 may be about 5.4 uH. However, other inductance values may be utilized. Further, the inductance of inductor L2 is greater than the inductances of inductors L1 and L3. Further, the inductance of inductor L1 may be equal to the inductance of inductor L3. The capacitances of capacitors C10 and C11 may be the same. For example, the capacitances of capacitors C10 and C11 may be about 88 pF. However, other capacitance values may be utilized. Further, the resistances of resistors R8 and R9 may be about 400 kiloohms. However, other resistance values may be used.

[0044]

[0061] In some embodiments, filter cascade 222 and filter cascade 224 each have a frequency response curve including a plateau and a cut-off frequency, the plateau being between 1 MHz and about 7 MHz, and the cut-off frequency being in the range of about 5 MHz to about 10 MHz.

[0045]

[0062] Figures 5A, 5B, 5C, and 5D each show an output waveform (i.e., an adjusted waveform) 1441A , 144 1B , 1442, and 1443 are shown. The output waveforms shown in FIGS. 5A, 5B, 5C, and 5D include a series of cycles of short pulses that repeat at a period "T" cycle "(e.g., 2.5 microseconds). In one example of plasma processing, as described below, the short pulse forms only about 10% of the period "T" cycle ".

[0046]

[0063] Briefly described above, as shown in FIG. 5A, the output waveform 144 1A is analyzed by the collection channel 1221 to determine waveform characteristics including, for one cycle of the pulse (T cycle ), the rise time of the pulse (T rise ), the fall time of the pulse (T fall ), and the DC voltage offset of the pulse from a reference voltage (e.g., zero volts). In one embodiment, the adjustment circuit 111 of the input channel 1101 connected to the bias electrode 804 (FIG. 8A) side of the generator connection assembly 133 1A includes only the voltage divider 112 used to form the output waveform 144 1A . In this configuration, since there is no low-pass filter 114, accurate determination of pulse timing characteristics (e.g., period, rise time, fall time, etc.) can be achieved. Further, in some embodiments, the chucking force applied to the substrate by using the high DC voltage power supplies V of the bias electrode 804 (FIG. 8A) and the HVM 816 (FIG. 8B) HVM can be determined by measuring the difference between the DC voltage on the bias electrode 804 (FIG. 8A) and the DC voltage on the substrate 803.

[0047]

[0064] Furthermore, as illustrated in FIG. 5B, the output waveform 144 1Bis analyzed by the collection channel 1221, and waveform characteristics including the amplitude "Ampl" of the pulse, the pulse width "W", and the DC voltage offset can be determined. The determined pulse width "W" can be equal to the full width at half maximum. In one embodiment, an adjustment circuit 111 of an input channel 1101 having an input end connected to the generator side of the generator connection assembly 133 1B is the output waveform 144 1B and includes a voltage divider 112 and a low-pass filter 114 used to form it. In this configuration, the determination of the sheath voltage (V sh )(FIG. 10B) and the ion energy (Ei) can be achieved during plasma processing by pre-determining a scaling factor (α). Here, is TIFF0007695430000001.tif7170. Further, in some embodiments, the chucking force applied to the substrate can be determined by measuring the difference between the DC voltage on the bias electrode 804 (FIG. 8A) and the DC voltage on the substrate 803. Further, the characteristics of the ion current (I ion ) generated within the ion current phase of the pulse waveform can be determined. This will be described later.

[0048]

[0065] As shown in FIG. 5C, the output waveform 1442 is analyzed by the collection channel 1222, and waveform characteristics including the ion current offset can be determined. In one embodiment, an adjustment circuit 1112 of an input channel 1102 whose input end is connected to the current monitor 134 (FIGS. 1B and 9B) includes a voltage divider 112 and a low-pass filter 114, and these are used to form the output waveform 1442. In this configuration, the determination of information regarding the ion current offset can be achieved during plasma processing by using the formula I ion =(ion current offset) / factor. Here, "I ion " is the ion current, and "factor" is the voltage output characteristic per ampere of the current monitor 134.

[0049]

[0066] Additionally, or alternatively, the output waveform 1443 (FIG. 5D) can be analyzed by the acquisition channel 1223 to determine waveform characteristics including the maximum ion current during plasma processing. In one embodiment, the conditioning circuit 1113 of the input channel 1103 whose input terminal is connected to the current sensing resistor 139 within the PVWG 150 includes only the low-pass filter 114 used to form the output waveform 1443. In this configuration, since there is no voltage divider 112, an accurate determination of the magnitude of the ion current (I ion ) can be achieved. The determination of the maximum ion current "Max" can be accomplished during plasma processing by using the formula I ion = (MAx) / R sense . Here, "R sense " is the value of the R sense resistance.

[0050]

[0067] The feedback processor 125 can receive information regarding one or more of the waveform characteristics from the high-speed data acquisition module 120 and generate corresponding control parameters. The feedback processor 125 communicates the control parameters to the PVWG 150, and the PVWG 150 adjusts the pulsed voltage waveform established on the composite load 130 based on the received control parameters. For example, the PVWG 150 can increase the amplitude and / or width of the pulsed voltage waveform established on the composite load 130 based on the received control parameters. By adjusting the parameters utilized to generate the pulsed voltage waveform, undesirable variations or process variable drifts within the processing chamber during substrate processing can be mitigated. For example, by adjusting the parameters utilized to generate the pulsed voltage waveform, changes to the sheath voltage and ion energy distribution function in the substrate during plasma processing can be mitigated. This will be described in more detail later. Changes to the sheath voltage (V sh ) and ion energy distribution function can occur in response to changes in the load, plasma density drift, state of the chamber walls, substrate temperature, and / or degree and state of chemical dissociation.

[0051]

[0068] Referring further to FIG. 1B, the PVWG 150 establishes a pulsed voltage waveform on the composite load 130 via the generator connection assembly 133. The PVWG 150 can establish a pulsed voltage waveform based on control parameters derived from waveform characteristics (e.g., amplitude, pulse width, DC offset, and ion current) determined by the data collection module 120. In the simplest case, the waveform characteristics determined by the data collection module 120 can be provided to the user (e.g., displayed on the monitor of the controller 127), and the user can then adjust the control parameters used by the PVWG 150 to improve the pulsed waveform characteristics of one or more pulse waveforms generated by the PVWG 150 based on the determined waveform characteristics. The control parameters may be received alternately from the feedback processor 125, the controller 128, or the process chamber controller 126. The control parameters may include information used by the PVWG 150 to form a subsequently generated adjusted pulse voltage waveform, and the control parameters may include that one or more determined waveform characteristics of the first adjusted voltage waveform have reached their target values or limits, that the maximum DC charging voltage has been reached, that the maximum power limit has been reached, that the maximum time limit for algorithm convergence has been reached, that the maximum pulse width has been reached, and that the minimum pulse width has been reached, among others, but are not limited thereto. The control parameters may be communicated to the PVWG 150 at a predetermined rate. The predetermined rate may be about 10 transmissions per second. Alternatively, the predetermined rate may be less than or more than 10 transmissions per second.

[0052]

[0069] Additionally, or alternatively, the process chamber controller 126 can receive one or more waveform characteristics from the high-speed data collection module 120 and then generate corresponding control parameters. The process chamber controller 126 can communicate the control parameters to the PVWG 150. Alternatively, the process chamber controller 126 may communicate the control parameters to the feedback processor 125, and the feedback processor 125 communicates the control parameters to the PVWG 150. The PVWG 150 adjusts the input pulsed voltage waveform 140 output by the PVWG 150 based on the determined control parameters. The PVWG 150 can increase the amplitude and / or width of the pulsed voltage waveform output by the PVWG 150. Further, the process chamber controller 126 can be configured to provide at least once per process recipe the target amplitude and pulse width, as well as values for the control parameters. Further, the high-speed data collection module 120 can communicate one or more of the amplitude, pulse width, and DC offset of the output waveform 144 at a certain transmission rate. For example, the transmission rate can be about 10 transmissions per second. However, a transmission rate greater than or less than 10 transmissions per second may be utilized.

[0053]

[0070] Further, or alternatively, the controller 128 can receive one or more of amplitude, pulse width, DC offset, and ion current from the high-speed data collection module 120 and then generate corresponding control parameters. Alternatively, the high-speed data collection module 120 can communicate the processed waveform to the controller 128, and the controller 128 can determine one or more control parameters from the waveform. The controller 128 communicates the control parameters to the PVWG 150, and the PVWG 150 adjusts the pulsed voltage waveform output by the PVWG 150 based on the determined control parameters. Alternatively, the controller 128 communicates the control parameters to the feedback processor 125, the feedback processor 125 transmits the control parameters to the PVWG 150, and the PVWG 150 adjusts the pulsed voltage waveform output by the PVWG 150 based on the determined control parameters.

[0054]

[0071] Figures 6A and 6B include an example of a portion of one waveform cycle of an input and conditioned (e.g., split and filtered) voltage waveform resulting from signal source 1B (the generator end of the generator connection assembly) measured using an embodiment of a data collection system including an adjustment circuit and a high-speed data collection module. Digital information included in a portion of the waveform recorded over this period can be analyzed by the data collection controller 123 to determine voltage waveform characteristics such as amplitude (Ampl), full width at half maximum (W), and offset. Specifically, FIG. 6A shows an input pulsed voltage waveform 140 1B and a portion of one waveform cycle of the split waveform 610. The split waveform can be generated by voltage-dividing the input pulsed voltage waveform 140 1B For example, referring to FIG. 1B, the voltage divider of the adjustment circuit 111 1B voltage-divides the input pulsed voltage waveform 140 1B FIG. 6B shows a portion of one waveform cycle of the input pulsed voltage waveform 140 1B and the output waveform 144 1B The output waveform 144 1Bcan be generated by low-pass filtering the segmented waveform 610 (FIG. 6A). In various embodiments, the output waveform 144 1B is analyzed by the data collection controller 123, and one or more waveform characteristics can be determined.

[0055]

[0072] FIG. 7A shows multiple cycles of the input pulsed voltage waveform 140 1B . More specifically, FIG. 7A includes an example of multiple cycles (pulses) of the input voltage waveform generated from signal source 1B (the generator end of the generator connection assembly) measured using an embodiment of a data collection system including an adjustment circuit and a high-speed data collection module. As described with respect to FIG. 1B, the input pulsed voltage waveform 140 1B is received by the input channel 110 1B and analyzed by the collection channel 1201, and one or more waveform characteristics can be determined. The digital information included in the waveform recorded over this period is analyzed by the data collection controller 123 to determine voltage waveform characteristics such as amplitude (Ampl), offset, pulse period (T P ), (pulse repetition frequency (f P =1 / T P ), etc.

[0056]

[0073] FIG. 7B shows multiple bursts 710 of the input pulsed voltage waveform 140 1B . Each burst 710 has a burst period that includes an on-time 720 and an off-time 732. Further, the frequency of the input pulsed voltage waveform 140 1B is based on the burst period, and the burst duty cycle is based on the on-time 720 and the burst period. More specifically, FIG. 7B includes an example of multiple bursts (each including multiple waveform cycles) of the input pulsed voltage waveform generated from signal source 1B (the generator end of the generator connection assembly) measured using an embodiment of a data collection system including an adjustment circuit and a high-speed data collection module. The digital information included in the waveform recorded over this period is analyzed by the data collection controller to determine the offset, burst period (TB =T on +T off )、burst frequency (f B =1 / T B )、and burst duty cycle (Duty = T on / T B ) and other voltage waveform characteristics can be determined.

[0057] Example of a plasma processing chamber

[0074] Figure 8A is a schematic cross-sectional view of a processing chamber 800, in which a composite load 130 is formed during plasma processing in the processing chamber 800. According to one embodiment, the processing chamber 800 is configured to implement the bias scheme proposed herein. In one embodiment, the processing chamber is a plasma processing chamber such as a reactive ion etching (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma enhanced deposition chamber (e.g., a plasma chemical vapor deposition (PECVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber). In some other embodiments, the processing chamber is a plasma treatment chamber, or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. Here, the processing chamber includes an inductively coupled plasma (ICP) source electrically connected to a radio frequency (RF) power source. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source (e.g., a source electrode disposed in the processing space facing the substrate support and electrically connected to the RF power source).

[0058]

[0075] The processing chamber 800 features a chamber body 813 that includes a chamber lid 823, one or more sidewalls 822, and a chamber base 824 that defines a processing space 826. A gas inlet 828 disposed through the chamber lid 823 is used to supply one or more processing gases from a processing gas source 819 that is in fluid communication with the gas inlet 828 to the processing space 826. Here, the plasma generator is configured to ignite and maintain a processing plasma 801 from the processing gas and includes one or more induction coils 817 disposed proximate to the chamber lid 823 outside the processing space 826. The one or more induction coils 817 are electrically coupled to an RF power source 818 via an RF matching circuit 830. The plasma generator is used to ignite and maintain the processing plasma 801 using the processing gas and the electromagnetic field generated by the induction coils 817 and the RF power source 818. The processing space 826 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 820. The vacuum outlet 820 maintains the processing space 826 at a near-atmospheric state and evacuates processing gas and / or other gases therefrom. A substrate support assembly 836 disposed within the processing space 826 is disposed on a support shaft 838 that extends sealingly through the chamber base 824.

[0059]

[0076] The substrate 803 is loaded into and removed from the processing space 826 through an opening (not shown) in one or more of the sidewalls 822. The opening in the one or more sidewalls 822 is sealed with a door or valve (not shown) during plasma processing of the substrate 803. Here, a lift pin system (not shown) is used to transfer the substrate 803 to and from a receiving surface of the ESC substrate support 805.

[0060]

[0077] The substrate support assembly 836 includes a support base 807 and an ESC substrate support 805 that is thermally coupled to the support base 807 and disposed on the support base 807. Typically, the support base 807 is used to regulate the temperature of the ESC substrate support 805 and the substrate 803 disposed on the ESC substrate support 805 during substrate processing. In some embodiments, the support base 807 has one or more cooling channels (not shown) disposed therein, and the cooling channels are fluidly coupled and in fluid communication with a coolant source (not shown) (e.g., a refrigerant source or a water source having a relatively high electrical resistance). In some embodiments, the ESC substrate support 805 includes a heater (not shown), e.g., a resistive heating element embedded in its dielectric material. Here, the support base 807 is formed of a corrosion-resistant heat-conductive material such as a corrosion-resistant metal (e.g., aluminum, an aluminum alloy, or stainless steel) and is coupled to the substrate support by an adhesive or mechanical means. Typically, the ESC substrate support 805 is formed from a dielectric material (e.g., a bulk-sintered ceramic material such as a corrosion-resistant metal oxide material or a metal nitride material), which is, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the ESC substrate support 805 further includes a bias electrode 804 embedded in its dielectric material. In one configuration, the bias electrode 804 is a chucking pole used to fix (chuck) the substrate 803 to the support surface of the ESC substrate support 805 and bias the substrate 803 with respect to the processing plasma 801 using the pulsed voltage bias scheme described herein. Typically, the bias electrode 804 is formed from one or more conductive components (e.g., one or more metal meshes, foils, plates, or combinations thereof). Here, the bias electrode 804 is electrically coupled to the HVM 816. The HVM 816 supplies a chucking voltage (e.g., a static DC voltage) between approximately -5000V and approximately 5000V to the bias electrode 804 using an electrical conductor such as a coaxial transmission line 806 (e.g., a coaxial cable).

[0061]

[0078] The support base 807 is electrically insulated from the chamber base 824 by an insulating plate 811, and a ground plate 812 is interposed between the insulating plate 811 and the chamber base 824. In some embodiments, the processing chamber 800 further includes a quartz tube 810 or a collar. The quartz tube 810 or the collar surrounds the substrate support assembly 836 to prevent the ESC substrate support 805 and / or the support base 807 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their by-products. Typically, the quartz tube 810, the insulating plate 811, and the ground plate are externally enclosed by a liner 808. Here, a plasma screen 809 that is substantially coplanar with the substrate receiving surface of the ESC substrate support 805 prevents plasma from being formed in the space between the liner 808 and one or more sidewalls 822.

[0062]

[0079] The bias electrode 804 is separated from the substrate receiving surface of the ESC substrate support 805, and thus from the substrate 803, by a layer of dielectric material of the ESC substrate support 805. In this configuration, the bias electrode 804 and the layer of dielectric material form a parallel plate-like structure. The dielectric material can have an effective capacitance between about 5 nF and about 50 nF. Typically, the layer of dielectric material has a thickness between about 0.1 mm and about 1 mm, such as between about 0.1 mm and about 0.5 mm (e.g., about 0.3 mm). Here, the bias electrode 804 is electrically connected to the PVWG 150 using an external conductor such as a transmission line 806 disposed within the transmission line 131. The PVWG 150 and its components have been described in detail above in the context of the present disclosure. In some embodiments, the dielectric material and the thickness of the layer are such that the capacitance C e of the layer of dielectric material can be selected to be between about 5 nF and about 50 nF (e.g., between about 7 and about 10 nF).

[0063]

[0080] Generally, when the neutral fill pressure in the processing space 826 of the processing chamber 800 is low, the heat conduction between the surfaces disposed therein deteriorates. For example, the heat conduction between the dielectric material of the ESC substrate support 805 and the substrate 803 disposed on the substrate receiving surface of the ESC substrate support 805 deteriorates, and the effect of the ESC substrate support 805 heating or cooling the substrate 803 decreases. Therefore, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into the space (not shown) between the non-device side surface of the substrate 803 and the substrate receiving surface of the ESC substrate support 805 to improve the heat transfer between these surfaces. The heat transfer gas supplied by a heat transfer gas source (not shown) flows through a gas communication path (not shown) into the back space. The gas communication path is disposed through the support base 807 and further through the ESC substrate support 805.

[0064]

[0081] The processing chamber 800 further includes a processing chamber controller 126. The controller 126 here includes a central processing unit (CPU) 833, a memory 834, and support circuits 835. The processing chamber controller 126 is used to control the process sequence (including the substrate bias method described in this specification) used to process the substrate 803. The CPU 833 is a general-purpose computer processor configured for use in an industrial environment to control sub-processors associated with the processing chamber. The memory 834 described in this specification may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage, local or remote. The support circuits 835 are conventionally connected to the CPU 833 and include caches, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data can be encoded and stored in the memory 834 to instruct the processor within the CPU 833. The software program (or computer instructions) readable by the CPU 833 within the processing chamber controller 126 determines which tasks are executable by the components within the processing chamber 800. Preferably, the program readable by the CPU 833 within the processing chamber controller 126 includes code that, when executed by the processor (CPU 833), performs tasks related to monitoring and executing the electrode bias scheme described in this specification. The program includes instructions that are used to control various hardware and electrical components within the processing chamber 800 to perform various process tasks and various process sequences used to implement the electrode bias scheme described in this specification.

[0065]

[0082] PVWG150 establishes a pulsed voltage waveform formed by the use of bias electrode 804 across a load (e.g., composite load 130). PVWG150 includes the nanosecond pulse generator 814 and the current return output stage 815 schematically shown in FIGS. 8A and 8B. The nanosecond pulse generator 814 maintains a predetermined substantially constant positive voltage across its output (i.e., the output to ground) during regularly repeated time intervals of a predetermined length by repeatedly opening and closing an internal switch at a predetermined rate. FIG. 8A shows a simplified, functionally equivalent schematic of the nanosecond pulse generator 814. In FIG. 8A, the nanosecond pulse generator 814 is reduced to a minimal combination of components that are important to understand their role in establishing the desired pulsed voltage waveform at the bias electrode 804. These components generally include, among others, an internal voltage source, a high repetition rate switch, and a reflux diode. It should be understood that an actual nanosecond pulse generator may include any number of internal components and may be based on an electrical circuit more complex than the circuit of FIG. 8A. Instead, the schematic of FIG. 8A provides only a functionally equivalent diagram of the nanosecond pulse generator 814 and the components of its electrical circuit to the extent necessary to explain the basic principles of operation, the interaction with the plasma within the processing space, and the role in establishing a pulsed voltage waveform (e.g., input pulsed voltage waveform 140) at the bias electrode 804. As can be determined from the schematic shown in FIG. 8A, when switch S1 moves from the open (off) position to the closed (on) position, the output section of the nanosecond pulse generator is connected to its internal voltage source that generates a substantially constant output voltage. In one or more embodiments, the purpose of the reflux diode, which may also be replaced with a different snubber circuit, is to suppress or "snub" the voltage spikes that may occur upon the opening of switch S1, after which the magnetic energy stored in the inductive element is rapidly released. These inductive elements include (A) an external electrical conductor such as transmission line 806 having a combined inductance L transm and (B) the combined inductance L of the nanosecond pulse generator 814 and the current return output stage 815 internalIt includes components of PVWG150 that contain internal electrical conductors for connection. The nanosecond pulse generator 814 is mainly used as a charge injector (current source) and may not be used as a constant voltage source. Therefore, even when the switch is in the closed (on) position, the output voltage can change over time, so there is no need to impose strict requirements on the stability of the output voltage. Furthermore, in some configurations, the nanosecond pulse generator 814 only allows current to flow in one direction (for example, the output can charge a capacitor but cannot discharge it), so basically it is sourcing but not a sinking supply. In addition, when the switch is in the open (off) position, the voltage V0 flowing through the output part of the nanosecond pulse generator is not controlled by the internal voltage source. Instead, it is determined by the interaction between its internal components and other circuit elements.

[0066]

[0083] The current return output stage 815 has one end 815B connected to ground, and the other end 815A is connected to the positive output part of the nanosecond pulse generator via an internal electrical conductor. At the same time, it is connected to an external electrical conductor connected to one side of the generator connection assembly 133 (Figure 1B). The current return output stage 815 may be composed of a resistor, a resistor and an inductor connected in series, a switch, or a more complex combination of electrical elements (including parallel capacitors) that allow the flow of positive current towards ground.

[0067]

[0084] The transmission line 131 electrically connects the output part of PVWG150 to the chucking pole (for example, the bias electrode 804). The output part of PVWG150 is the end 815A, and the output part of the nanosecond pulse generator 814 is connected to the current return output stage 815 via an internal electrical conductor. The electrical conductors of the transmission line 131 connected to the bias electrode side of the generator connection assembly 133 and the bias electrode 804 are (a) a rigid coaxial transmission line having an inductance L rigid in series with an inductance L flexA coaxial transmission line 806 that may include a flexible coaxial cable having, (b) an insulating high-voltage corona-resistant hook-up wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or any combination of the electrical elements (a) to (e). It should be noted that the internal electrical conductor may include the same basic elements as the external electrical conductor.

[0068]

[0085] The bias electrode 804 is typically a metal plate embedded in an electrostatic chuck and separated from the plasma by a thin layer of dielectric material. The chucking pole may be the bias electrode 804 embedded in the electrostatic chuck portion (i.e., the ESC substrate support 805). The external conductor such as the transmission line 806 and the bias electrode 804 have some combined floating capacitance C s with respect to ground.

[0069]

[0086] FIG. 8B shows a functionally equivalent and simplified electrical circuit 840 of the pulsed voltage bias scheme proposed herein, including the plasma in the processing space. These circuits are used to model the main aspects of the interaction between a pulsed voltage waveform generator (e.g., PVWG150) and the processing chamber 800, to explain the basic principles of operation and the role of the pulsed voltage waveform generator in establishing a pulsed voltage waveform at the bias electrode (e.g., bias electrode 804), to explain the incidental physical phenomena occurring between various phases of the pulsed voltage waveform, and generally to explain the basic principles of operation of the pulsed voltage bias scheme. For clarity, the following definitions are used throughout this disclosure. (1) Unless otherwise specified, all potentials are referenced to ground. (2) The voltage at any physical point (such as a substrate or a bias electrode) is similarly defined as the potential of this physical point with respect to ground (the zero potential point). (3) The cathode sheath is suggested to be an electron-repelling ion acceleration sheath corresponding to the negative substrate potential with respect to the plasma. (4) The sheath voltage (also called "sheath voltage drop") V sh is defined as the absolute value of the potential difference between the surface adjacent to the plasma (e.g., the surface of the substrate or the chamber wall) and the plasma. (5) The substrate potential is the potential at the substrate surface facing the plasma.

[0070]

[0087] First, the dielectric layer within the electrostatic chuck and the processed substrate disposed on its surface (e.g., a doped silicon slab 0.3 - 0.8 mm thick having a capacitance > 10 nF) isolate the chucking pole (e.g., bias electrode 804) from the plasma, and in the circuit of FIG. 8B, the capacitance C e (e.g., ~7 to 10 nF) is represented by a single chuck capacitor 843 (which is actually two capacitors connected in series). In other words, the substrate (typically made of a thin layer of semiconductor and / or dielectric material) may be regarded as being electrically part of the ESC dielectric layer, and when referring to the chuck capacitance C e (i.e., item 843), C e is the combined series capacitance of the ESC and the substrate (i.e., C w ), which is suggested to be (i.e., C ESC (~dielectric layer capacitance). The substrate capacitance C w is typically very large (> 10 nF), or the substrate can be conductive (infinite capacitance), so the series capacitance is mainly determined by the actual C ESC .

[0071]

[0088] Second, the bias electrode 804, PVWG150, and the external electrical conductor (e.g., transmission line 131) connecting the bias electrode 804 to PVWG150 have (A) some combined floating capacitance with respect to ground, represented by a single floating capacitor 842 having a capacitance C s (e.g., ~500 pF), and (B) some inductances, including the inductance L internal of the internal electrical conductor of PVWG150 and the inductances L interconnect and L external (i.e., items 845A and 845B) of external electrical conductors such as transmission line 806. The current return output stage 815 has a resistor R ros(e.g., ~150 ohms) and inductor L ROS represented by, which may optionally also include switch S2.

[0072]

[0089] As shown in FIG. 8B, PVWG150 may include a bypass resistor R bypass , and a current sensing circuit 821 connected in parallel with the current return output stage 815. The current sensing circuit 821 includes a current sensing resistor R sense (i.e., item 139), and a switch S3 that can be used to sense the current flowing through the current return output stage 815 during one or more phases of the pulse.

[0073]

[0090] Thirdly, a standard electrical plasma model representing the entire plasma in the processing space as three series elements can be utilized. For example, an electron-repelling cathode sheath 844 adjacent to the substrate (which may also be referred to as a "plasma sheath" or simply a "sheath"). The cathode sheath is represented in FIG. 8B by a conventional three-component circuit element, (a) a diode D that represents the collapse of the sheath when open SH , (b) a current source I that represents the ion current flowing to the substrate in the presence of the sheath i (e.g., ~0.5 to 5 A), (c) a capacitor C that represents the sheath for the main period (~90%) of the bias cycle during which ion acceleration and etching occur, i.e., the ion current phase (e.g., the phase after a short pulse is supplied) SH (e.g., for high aspect ratio applications, ~100 to 300 pF).

[0074]

[0091] The bulk plasma 846 is represented in FIG. 8B by a single resistor of ~5 to 10 ohms. The electron-repelling wall sheath formed at the chamber wall is represented in FIG. 8B by a three-component circuit element, (a) a diode D W , (b) a current source I that represents the ion current to the wall iw (e.g., ~5 to 10 A), and (c) a capacitor C W(e.g., ~5 to 10 nF), without an electron-repelling cathode sheath, and when the wall sheath capacitor is charged by a large current pushed through the ESC by a nanosecond pulse generator, mainly representing the wall sheath during the ESC recharge phase, capacitor C W is included. The cathode sheath is much thicker than the wall sheath (due to the high voltage), and the total area of the wall is much larger than the area of the substrate, so C W ≫ C SH is presumed to be the case. The inner surface of the grounded metal wall is thought to be coated with a thin layer of dielectric material, which is represented by a large capacitor C coat (e.g., ~300 to 1000 nF) in FIG. 8B.

[0075]

[0092] In some embodiments, as shown in FIGS. 8A and 8B, the system includes a high-voltage module (HVM). The HVM is used for chucking to "electrically clamp" the substrate to the substrate receiving surface of the ESC substrate support as shown in FIG. 8A. By chucking the substrate, the gap between the substrate receiving surface and the non-device side of the substrate can be filled with helium gas (He), which provides good thermal contact between the two and enables substrate temperature control by adjusting the temperature of the ESC substrate support. The combination of the DC chucking voltage generated by the HVM and the pulsed voltage generated by the PVWG150 at the bias electrode 804 results in an additional voltage offset with a pulsed voltage waveform equal to the DC chucking voltage. By appropriately selecting a large blocking capacitor C hvm and R hvm2 , the influence of the HVM816 on the operation of the PVWG150 can be made negligible. The resistor R hvm2 schematically represents a resistor disposed within a component that connects the HVM816 to a point within the transmission line 131. The main function of the blocking C hvm in the simplified electrical circuit 840 is to isolate the PVWG150 from the DC power supply V hvmTo protect against the HVM DC voltage generated thereby, the HVM DC voltage thus drops across C hvm without disturbing the output of the PVWG150. While only blocking the HVM DC voltage, C is selected such that no load is imposed on the high-frequency output voltage of the pulsed bias generator hvm . By selecting a sufficiently large C hvm (e.g., from 40 to 80 nF), C hvm is much larger than any other relevant capacitance in the system, for example, and the voltage drop across this element is much smaller compared to the voltage drop across other relevant capacitors (e.g., the chuck capacitance C e and the sheath capacitance C SH ), being almost transparent to the 400 kHz signal. Instead, the purpose of the blocking resistor R hvm2 is to block the voltage of the high-frequency pulsed bias generator and minimize the current induced by it in the HVM DC voltage supply. This blocking resistor R hvm2 must be large enough to efficiently minimize the current flowing through it. For example, to be insufficient to draw the 400 kHz current from the pulsed bias generator into the HVM, R hvm2 > 1 MΩ is typically large enough. The resulting average induced current of approximately 0.5 to 1 mA is much smaller than the typical limit of the HVM power supply (about 5 mA of DC current). C hvm1 and R hvm1 , as well as R hvm2 together form a current suppression / filtering circuit for the pulsed voltage, such that the pulsed voltage does not induce current through the HVM816.

[0076]

[0093] In some embodiments, the feedback loop 100 is connected to one or more points within the PVWG150 or to the PVWG150 and a blocking capacitor C disposed within the generator connection assembly 133 hvmis connected along an electrical conductor disposed between them. For example, one or more input channels 110 of the feedback loop 100 are connected via connections to one or more points along an electrical conductor disposed between the PVWG 150 and the blocking capacitor C hvm is connected via connections to one or more points along an electrical conductor disposed between them. Further, in some embodiments, one or more of the input channels 110 are connected electrically via connections to one or more points along an electrical conductor disposed between the blocking capacitor C hvm and a bias electrode 804 within the processing chamber 800. For example, one or more input channels 110 are electrically connected via connections to one or more points along an electrical conductor disposed between the blocking capacitor C hvm and a bias electrode 804 within the processing chamber 800. Alternatively, in other embodiments, one or more of the input channels 110 are connected to one or more points along an electrical conductor disposed on both sides of the blocking capacitor C hvm For example, the first one or more input channels 110 are electrically connected to a point along an electrical conductor disposed between the PVWG 150 and the blocking capacitor C hvm and the second one or more input channels 110 are connected to a point along an electrical conductor disposed between the blocking capacitor C hvm and a bias electrode 804 within the processing chamber 800.

[0077] Example of a Pulse Waveform

[0094] FIG. 9A shows an example of a pulsed voltage waveform 950 established at the bias electrode 804. The pulsed voltage waveform 950 shown in FIG. 9A results in the substrate voltage waveform 951 shown in FIG. 9B and can thus make it possible to maintain the sheath voltage substantially constant over approximately 90% of the substrate processing time during plasma processing. The pulsed voltage waveforms 950 and 951 shown in FIGS. 9A and 9B are generally based on waveforms that can be generated from the simplified electrical circuit 840 shown in FIG. 8B. The waveforms shown in FIGS. 9A and 9B are only intended to show a simplified schematic of a pulsed voltage waveform that can be used in one of the methods described herein and that can be used during plasma processing of a substrate. The actual waveform generated by the PVWG150 is quite complex and can include numerous microscale features (e.g., high-frequency oscillations caused by the presence of inductive elements) not shown in FIGS. 9A and 9B. However, examples of some types of microscale features can be identified in FIGS. 6A and 6B, and 7A and 7B. However, these microscale features are not essential for understanding the physical phenomena underlying the determination of the general shape of the actual pulsed voltage waveform generated by the pulsed voltage bias scheme and control method proposed herein.

[0078]

[0095] In FIG. 9A, the pulsed voltage waveform 950 includes a short series of positive periods repeated at a period T (e.g., 2.5 microseconds) on top of a voltage offset. The waveform within each period (repetition period) includes the following.

[0079]

[0096] (1) A positive voltage jump (i.e., sheath collapse phase 961) to charge the system's floating capacitor and collapse the cathode sheath. During the sheath collapse phase 961, the sheath capacitor C SH is discharged and the substrate potential is brought to the level of the local plasma potential (as shown in FIG. 9B). The sheath collapse phase 961 is followed by the ESC recharge phase 962 during which electrons supplied from the plasma charge the chuck capacitor C eEnables rapid recharge. Switch S1 (see Fig. 8B) closes and remains in the closed (on) position during phase 961, which allows a nanosecond pulse generator such as PVWG150 to maintain a substantially constant positive voltage across its output and supply current to the system. The period T1 of phase 961 is much shorter than the period T4 of the ion current phase 964 (described below) or the overall period T, typically on the order of tens of nanoseconds (e.g., 20 to 50 nanoseconds). This is because the plasma current during phase 961 is carried by electrons. That is, the electron cloud moves towards the substrate and gradually sweeps the ion space charge, eliminating the sheath voltage drop. Due to the very large mass ratio between the two species, the electron velocity is much greater than the ion velocity.

[0080]

[0097] (2) By rapidly injecting a charge equal in value and opposite in polarity to the total charge accumulated on the substrate surface during the ion current phase 964, the chuck capacitor C is recharged during the ESC recharge phase 962 (described below). Similar to during phase 961, PVWG150 maintains a substantially constant positive voltage across its output (switch S1 remains in the "on" position). Similar to phase 961, the period T2 of phase 962 is much shorter than the period T4 of the ion current phase 964 (described below) or the overall period T, typically on the order of tens of nanoseconds (e.g., 30 to 80 nanoseconds). This is because the plasma current during phase 962 is also carried by electrons. That is, in the absence of a cathode sheath, electrons reach the substrate, accumulate surface charge, and thus charge the capacitor C e .. e is charged.

[0081]

[0098] (3) Discharge the floating capacitor of the processing chamber, reform the sheath, and provide a negative voltage spike (V SH ) to set the value of the sheath voltage (V OUT ) during the sheath formation phase 963. Switch S1 in Fig. 8B opens at the start of the sheath formation phase 963, and the inductor releases its stored magnetic energy to the chuck capacitor C e and the floating capacitor C srapidly discharges (e.g., within about 10 nanoseconds) to. The inductive element has an inductance L internal internal components of the PVWG150 (e.g., internal conductors) represented by, and the inductance L in circuit 840 interconnect and L external and may include external conductors (e.g., transmission line 806) represented by. While the magnetic energy is being released, the corresponding current flows through a flyback diode or a different snubber circuit with a similar function that suppresses (or "snubs") possible voltage spikes. Here, without a flyback diode (or a different component with a similar function that "snubs" possible voltage spikes), the magnetic energy would have to be released through the resistive current-return output stage, resulting in an unrealistically large negative voltage (e.g., -20 kV that could damage internal components of the pulse bias generator 240) across R1 for several nanoseconds instead of converging to a near-zero value. Note that when the magnetic energy is released and the current through the inductances L interconnect and L external (and L internal ) drops to zero, it reverses direction and flows from the plasma and floating capacitor through the current-return output stage to ground (the flyback diode is reverse-biased and blocks the flow of current through itself), thereby discharging the floating capacitor C s and charging the sheath capacitor C sh (i.e., reforming the sheath). The start of sheath formation (C shThe charging (in FIG. 9B) can be clearly identified as the point where the substrate potential starts to drop below the local plasma potential. Similar to phase 961, the period T3 of phase 963 is much shorter than the period T4 of the ion current phase 964 (described below) or the entire cycle T, typically on the order of 100 to 300 nanoseconds. This is because the plasma current during phase 963 is also carried by electrons. That is, the electron cloud moves away from the substrate, gradually exposing the ion space charge, and ultimately forming a sheath and causing a sheath voltage drop. (1) T3 is determined mainly by the floating capacitance and the value of the element (e.g., resistor) including the current-return output stage, and (2) the jump-up of the negative voltage V OUT and the established sheath voltage V SH is V m (the magnitude of the nanosecond pulse generator output voltage between phases 961 - 962), and the total pulse width, T tot = T rise + Tp = T1 + T2. Note that it is determined by this.

[0082]

[0099] (4) PVWG150 similarly does not maintain a positive voltage across its output (switch S1 remains in the off position), and has a long ion current phase 964 (about 85 - 90% of the cycle period T) with a period T4 during which the ion current flows from the plasma to ground through the current-return output stage. The ion current causes the accumulation of positive charge on the substrate surface, gradually discharges the sheath and the chuck capacitor, slowly reduces the sheath voltage drop, and brings the substrate potential closer to zero. This results in the voltage droop ΔV SH shown in the substrate voltage waveform 951 in FIG. 9B. Due to the resulting sheath voltage droop, the pulsed voltage waveform 950 needs to move to the next cycle as described in (1) - (3) above, during which PVWG150 removes the charge accumulated during the ion current phase (or restores the initial ESC charge) to the desired sheath voltage V SHRe - establish. Note that surface charge and sheath voltage droop will always accumulate when there is an unbalanced net current (equal to the ion current) from the electron - repulsive cathode sheath and the bulk plasma. This is because the ion current from the bulk plasma is not balanced by the electron current from the bulk plasma due to the sheath electric field that repels electrons away from the substrate. Thus, surface charge accumulation and voltage droop also occur during the sheath - forming phase 963 where there is a non - zero sheath voltage droop from the start.

[0083]

[0100] As can be seen from the above (1) - (4), the combined period of the "electron current" phases 961 - 963 that make up a single voltage pulse of the pulsed voltage waveform (e.g., pulsed voltage waveform 950) is from about 200 to 400 nanoseconds, which corresponds to a relatively short duty cycle of about 10 to 15%. This short duty - cycle characteristic of the pulsed voltage waveform 950 is a result of the large mass ratio of ions to electrons that is typical in all plasmas. Thus, in the pulsed voltage bias scheme described herein, the PVWG150 actively interacts with the plasma only for a short time during each cycle, thereby allowing the cathode sheath to develop naturally over the remaining time. By effectively using the basic plasma characteristics, this bias scheme makes it possible to maintain a sheath voltage that is nearly constant up to 90% of the processing time, resulting in a single - peak IEDF (e.g., IEDF970 in FIG. 9C). Conversely, in a conventional bias scheme, the applied RF voltage adjusts the cathode sheath throughout the RF period, and thus causes the sheath voltage to vary excessively with droop over the entire period, resulting in a dual - peak IEDF.

[0084]

[0101] The pulsed voltage bias scheme described in this specification enables the maintenance of a specific substrate voltage waveform, such as the substrate voltage waveform 951 shown in FIG. 9B, which can be described as a series of cycles of short positive pulses 971 above a negative voltage offset 972. During each pulse (having a total duration of T5 = T1 + T2 + T3), the substrate potential reaches the local plasma potential and the sheath collapses for a short time. However, for approximately 90% of each cycle (having a cycle period T), the sheath voltage droop remains approximately constant and is approximately equal to the absolute value of V SH (FIG. 9B), and thus the average ion energy at the substrate surface is determined. During the sheath collapse phase 961 of the bias cycle, the current from the nanosecond pulse generator (e.g., 814) is divided between the processing plasma and the floating capacitor C SH / C s connected in parallel, approximately according to, and is not very important. For the reasons described above, and also because C s is generally very large, the voltage droop that accumulates across the wall sheath during phase 961 is relatively small. As a result, the plasma potential V w near the wall, which is equal to the sum of the wall sheath voltage droop and the small voltage droop expected across the wall dielectric coating, remains near zero. Thus, the local (near the substrate) plasma potential V w , which is equal to the sum of the plasma potential near the wall and the voltage droop across the bulk plasma, is mainly determined by the latter and increases to a value slightly above zero. Instead, during the ESC recharge phase 962, there is no electron-repelling cathode sheath, and the wall sheath capacitor is charged to a substantial voltage (e.g., several hundred volts) by the large current pushed through the ESC by the PVWG150. Due to the increase in the plasma potential near the wall and the presence of an equally large voltage droop across the bulk plasma (caused by the same large current), the local (near the substrate) plasma potential V pl , and the substrate potential V pl reach the established sheath voltage V sub SH ​experiences a substantial increase up to about one-third of. Finally, during the sheath formation phase 963, the current through the processing plasma again (as in phase 961) C SH / C s is determined by the ratio and is relatively small (and rapidly decaying), similar to the resulting voltage drop across the bulk plasma. Thus, the local (near the substrate) plasma potential remains approximately equal to the plasma potential near the wall, and since the wall sheath is mainly discharged to the chamber wall by the ion current, both relax to values close to zero as they approach the end of phase 963. As a result of the perturbation of the local plasma potential between phases 961 - 963, the established sheath voltage V SH constitutes only ~75% of the overall negative spike in the substrate voltage waveform 951 at the end of phase 963. The negative spike V’ SH is close to the maximum sheath voltage for a given V w and T pl (achievable only with approximately infinite C m and approximately zero R tot ), and is close to the negative spike in the pulsed voltage waveform 950, or V’ SH ~V OUT . The reason for the latter is that during phase 963, the chuck capacitor transfers only a small portion (∝C SH / C e ≪1) of its initial charge to the sheath, and thus maintains approximately a constant potential difference between the electrode and the substrate. The relationship V SH / V OUT ~0.75 - 0.8 is actually used to estimate V OUT from the measured V SH .

[0085]

[0102] As described further hereinbelow, in one or more of the embodiments of the disclosure provided herein, the feedback loop 100 and the method of using it are provided to detect and adjust the output of the PVWG 150 to achieve a pulsed voltage waveform having desired waveform characteristics (e.g., the pulsed voltage waveform 950 and / or the substrate voltage waveform 951). In addition to the above-described pulse waveform characteristics that can be detected and adjusted, other pulse waveform characteristics can be detected and adjusted, and the other pulse waveform characteristics may include, for example, the shape or gradient of the pulse waveform between one or more of the pulse phases, one or more periods of the phases (e.g., T1, T2, T3, T4, and T5), and other features of the pulse waveform.

[0086] Example of the method

[0103] FIG. 10 is a flowchart of a method 1000 for processing a pulsed voltage waveform according to one or more embodiments. In operation 1010, an input pulsed voltage waveform 140 is processed by components found within the input channel 110 to form an output waveform 144. In one configuration of the input channel 110, the input pulsed voltage waveform is divided using a first voltage division ratio to generate a first divided voltage waveform. For example, the input channel 1101 obtains the input pulsed voltage waveform 140 1B and the voltage divider 112 of the adjustment circuit 111 of the input channel 1101 1B receives the input pulsed voltage waveform and generates a first divided voltage waveform.

[0087]

[0104] In operation 1020, the divided voltage waveform coming from the voltage divider 112 is low-pass filtered to generate a filtered voltage waveform. In one example, the low-pass filter 114 of the input channel 1101 receives the first divided voltage waveform from the voltage divider 112, generates a filtered voltage waveform, and then forms the output waveform 144 1B . Operation 1020 may be optional and may be excluded from the method 1000. Further, in some embodiments of the method 1000, operation 1020 may be performed while operation 1010 is omitted.

[0088]

[0105] After operations 1010 and / or 1020 are executed and after output waveform 144 1B is generated by each input channel 1101, operation 1030 is executed. In operation 1030, one or more waveform characteristics received from each input channel such as input channel 1101 and processed by its respective collection channel 122 are determined by an algorithm executed by data collection controller 123. For example, collection channel 1221 receives the output waveform from input channel 1101, and the algorithm determines one or more waveform characteristics from output waveform 144 1B therefrom.

[0089]

[0106] In some embodiments, during operation 1030, the output waveform 144 from each input channel 110 is received by a driver (not shown) respectively connected to the corresponding collection channel 122. In one example, the output waveform 144 from input channel 1101 1B is received by the driver of collection channel 1221. The driver is used to convert the output waveform received from input channel 110 into a differential signal. In this configuration, the differential signal is then received by an ADC (not shown) connected to or within collection channel 122. The ADC converts the differential signal from the analog domain to the digital domain, and the output digital signal of the ADC is supplied to a processor 121 connected to collection channel 122. The processor of data collection controller 123 determines one or more waveform characteristics of the output waveform by analyzing the output digital signal supplied from the ADC. For example, processor 121 analyzes the output digital signal to determine one or more of the amplitude, pulse width, and DC offset of the pulses within output waveform 144 received from input channel 110.

[0090]

[0107] Operation 1030 may further include combining measurement values received over a period of time from corresponding input channels. For example, data collection controller 123 may receive "Z" digitized waveforms from collection channel 1221 over a first period of time. Here, Z is an integer equal to or greater than 2. The first period of time may correspond to "M" cycles of the input pulsed voltage waveform. Here, M is an integer equal to or greater than 1. Collection channel 1221 can combine the Z output waveforms. For example, collection channel 1221 may average the data corresponding to the Z output waveforms.

[0091]

[0108] Operation 1030 may further include the data collection controller 123 performing at least one of: 1) sending information regarding one or more determined waveform characteristics of the regulated voltage waveform to a controller (e.g., the controller of feedback processor 125), and 2) sending information regarding a second digitized voltage waveform generated by a collection channel to a second controller (e.g., controllers 126, 127, 128, or 191).

[0092]

[0109] In operation 1040, one or more control parameters are generated from one or more waveform characteristics received from one or more input channels 110. For example, data collection controller 123 transmits information corresponding to one or more waveform characteristics to feedback processor 125, and feedback processor 125 generates one or more control parameters from the one or more waveform characteristics. Referring also to the previous example of the configuration of the input channels, in one embodiment of operation 1040, after operations 1010 to 1030 of the desired operation are executed, the processor receives output waveforms from input channels 1101, 1102, and 1103, and transmits information corresponding to one or more waveform characteristics derived from the waveforms received and processed by collection channels 1221, 1222, and 1223, respectively, to feedback processor 125. Next, feedback processor 125 may generate one or more control parameters from the one or more received waveform characteristics. In one embodiment, the one or more control parameters are based on a comparison between the received waveform characteristics and target waveform characteristics stored in the memory of feedback processor 125 or in a memory coupled to feedback processor 125, and may include instructions to adjust the DC charging voltage, adjust the pulse width, and adjust the amplitude of the pulsed voltage waveform. The stored target waveform characteristics may be waveform characteristics generated by feedback loop 100 at a previous instant, an average of a series of waveform characteristics generated by feedback loop 100 over a period of time, idealized waveform characteristics generated by the user and input into the memory (e.g., model-based waveform characteristics), or waveform characteristics generated by other desirable means.

[0093]

[0110] Alternatively or additionally, the data collection controller 123 can communicate information corresponding to one or more waveform characteristics to a separate controller (e.g., controller 127, controller 128, controller 191, and / or process chamber controller 126), and the separate controller generates one or more control parameters from the one or more waveform characteristics. Similarly, in one embodiment, one or more control parameters generated by the controller can include, for example, instructions for adjusting the pulse width and adjust the amplitude of the pulsed voltage waveform based on a comparison of the received waveform characteristics with target waveform characteristics stored in the controller's memory. The stored target waveform characteristics can be waveform characteristics generated by the feedback loop 100 at a previous instant, an average of a series of waveform characteristics generated by the feedback loop 100 over a period of time, idealized waveform characteristics (e.g., model-based waveform characteristics) generated by the user and input into the memory, or waveform characteristics generated by other desirable means.

[0094]

[0111] In operation 1050, the feedback processor 125 or a separate controller transmits information corresponding to one or more control parameters to the PVWG 150. Further, in some embodiments, the data collection controller 123 can communicate information corresponding to one or more waveform characteristics to the controller 128, and the controller 128 generates one or more control parameters based on a comparison of the determined waveform characteristics with information corresponding to one or more target waveform characteristics. Thus, in one embodiment, in operation 1050, the controller 128 transmits information corresponding to one or more control parameters to the PVWG 150 and / or another controller.

[0095]

[0112] During operation 1060, the regulated pulsed voltage waveform is supplied from the PVWG 150 based on the one or more received control parameters. For example, the PVWG 150 generates an adjusted pulsed voltage waveform that is supplied to the bias electrode 804.

[0096]

[0113] In operation 1070, optionally, the plasma processing chamber process variables are adjusted individually or additionally. The plasma processing chamber process variables can include setpoints for the chucking power supply. For example, adjusting the setpoint for the chucking power supply (e.g., HVM816) can include increasing or decreasing the chucking voltage output by the chucking power supply. Adjusting the setpoint for the chucking power supply will adjust the DC offset of the subsequent pulsed voltage waveform generated by PVWG150. The setpoint for the chucking power supply can be adjusted to be a DC voltage between approximately -5000V and approximately 5000V. In some embodiments, method 1000 may omit operation 1060.

[0097]

[0114] In some embodiments of method 1000, the adjusted pulsed voltage waveform is continuously executed until a pulsed voltage waveform with desired pulse waveform characteristics (e.g., target waveform characteristics) is achieved. In some embodiments, operations 1010 to 1050 or operations 1010 to 1060 are executed multiple times until one or more target waveform characteristics of the pulsed voltage waveform within one waveform cycle are reached. For example, the controller 128 and / or the feedback processor 125 can change one or more control parameters based on the updated waveform characteristics determined by the data collection controller 123. The updated waveform characteristics are collected by continuously processing the input pulsed voltage waveform collected by one or more of the input channels 110. In one example, the pulse width and / or amplitude may be increased until they reach the corresponding target values stored in the memory of the feedback processor connected to the data collection controller 123 or in the memory. Further, the adjusted pulsed voltage waveform can be continuously adjusted by changing one or more of the control parameters until the maximum DC offset voltage is reached. For example, one or more control parameters may be continuously changed until the maximum DC offset voltage is reached.

[0098]

[0115] In some embodiments, establishing an adjusted pulsed voltage waveform includes changing one or more of the control parameters until a maximum time limit for algorithm convergence is reached. For example, feedback processor 125 monitors how long it takes PVWG 150 to generate an adjusted pulsed voltage waveform having one or more of the target waveform characteristics. If PVWG 150 fails to generate an adjusted pulsed voltage waveform capable of achieving the target pulsed waveform characteristics within a certain time limit, feedback processor 125 may instruct PVWG 150 to change to another waveform characteristic. Additionally, or alternatively, establishing an adjusted pulsed voltage waveform includes changing one or more of the control parameters until a predetermined maximum limit of the pulse width of the pulsed voltage waveform is reached. Further, establishing an adjusted pulsed voltage waveform includes changing one or more of the control parameters until a minimum limit of the pulse width of the pulsed voltage waveform is reached. The time limit and maximum limit of the pulse width are generally stored in a memory (e.g., memory 124 or 126A) and are drawn by a processor (e.g., feedback processor 125 or controller 128) for comparing one or more pulsed voltage waveforms received by one or more input channels 110, including predetermined values.

[0099]

[0116] FIG. 11 is a flow diagram showing a method 1100 for controlling a pulsed voltage waveform according to one or more embodiments. In operation 1110, an output waveform 144 is generated by a first input channel 110. For example, input channel 1101 acquires an input pulsed voltage waveform 140 1B and outputs waveform 144 1B from input pulsed voltage waveform 140 1BGenerate it. Input channel 1101 may include a voltage divider 112 and a low-pass filter 114. Generating the first output waveform includes generating a divided voltage waveform from the input pulsed voltage waveform by the voltage divider 112 and generating a filtered voltage waveform by low-pass filtering the divided voltage waveform with the low-pass filter 114. In another embodiment, input channel 1101 excludes the low-pass filter 114, and generating the output waveform includes generating a divided voltage waveform from the input pulsed voltage waveform by the voltage divider 112.

[0100]

[0117] In operation 1120, a second output waveform is generated by the second input channel 110. For example, input channel 1102 acquires an input pulsed voltage waveform 1402 and generates an output waveform 1442 from the input pulsed voltage waveform 1402. Input channel 1102 may include a voltage divider 112 and a low-pass filter 114. Generating the output waveform 1442 includes generating a divided voltage waveform from the input pulsed voltage waveform by the voltage divider 112 and generating a filtered voltage waveform by low-pass filtering the divided voltage waveform with the low-pass filter 114.

[0101]

[0118] In operation 1130, a third output waveform is generated by the third input channel 110. For example, in one embodiment, input channel 1103 acquires an input pulsed voltage waveform 1403 and generates an output waveform 1443 from the input pulsed voltage waveform 1403. Input channel 1103 may include a low-pass filter 114. Generating the output waveform 1443 includes generating a filtered voltage waveform formed by low-pass filtering the input pulsed voltage waveform 1403 by using the low-pass filter 114.

[0102]

[0119] In operation 1140, one or more waveform characteristics are determined. For example, acquisition channels 1221, 1222, and 1223 receive respective output waveforms 1441, 1442, and 1443 from input channels 110, 1102, and 1103, and supply the output waveforms to data acquisition controller 123 to determine one or more waveform characteristics based on various types of voltage waveform information received from the output waveforms 1441, 1442, and 1443. In some embodiments, one or more waveform characteristics determined by acquisition channel 1221 are different from one or more waveform characteristics determined by acquisition channel 1222, and one or more waveform characteristics determined by acquisition channel 1223 are different from one or more waveform characteristics determined by acquisition channel 1221 and acquisition channel 1222. Further, in one example, data acquisition controller 123 in combination with acquisition channel 1221 determines amplitude (Ampl) and pulse width W from the corresponding measured waveform, data acquisition controller 123 in combination with acquisition channel 1222 determines the ion current offset from the corresponding measured waveform, and data acquisition controller 123 in combination with acquisition channel 1223 determines the maximum ion current from the corresponding received output waveform.

[0103]

[0120] In operation 1150, one or more control parameters are generated from waveform characteristics determined by data collection controller 123 based on information received within output waveforms 1441, 1442, and 1443. For example, data collection controller 123 transmits information corresponding to one or more waveform characteristics to feedback processor 125 (or a separate controller), and feedback processor 125 (or a separate controller) generates one or more control parameters from the one or more determined waveform characteristics. During operation 1150, feedback processor 125 receives the one or more determined waveform characteristics and then generates one or more control parameters based on the one or more received waveform characteristics by using one or more algorithms. In one embodiment, the one or more control parameters may include instructions for adjusting the DC charging voltage, adjusting the pulse width, and adjusting the amplitude of the pulsed voltage waveform based on a comparison of waveform characteristics received from two or more different input channels and target waveform characteristics stored in the memory of feedback processor 125 or in a memory coupled to feedback processor 125.

[0104]

[0121] Similar to that described above for operation 1050, in operation 1160, feedback processor 125 transmits information corresponding to the generated control parameters to PVWG 150.

[0105]

[0122] Furthermore, operation 1170 is generally similar to operation 1060, and thus, the adjusted pulsed voltage waveform is supplied from PVWG 150 based on the one or more received control parameters. For example, PVWG 150 generates an adjusted pulsed voltage waveform that is supplied to bias electrode 804. Additionally, in operation 1170, the set point for the checking power supply is also optionally adjusted.

[0106]

[0123] In some embodiments of method 1100, operations 1110-1170 are performed multiple times until an adjusted pulsed voltage waveform having desired pulse waveform characteristics (e.g., target waveform characteristics) is achieved. In some embodiments, operations 1110-1170 are performed multiple times until one or more target waveform characteristics of the pulsed voltage waveform within one waveform cycle are reached.

[0107]

[0124] The foregoing description has been directed to embodiments of the present disclosure, but other and additional embodiments of the present disclosure may be devised without departing from the basic scope thereof. The scope of the present disclosure is determined by the following claims.

Claims

1. 1. A method for controlling a pulsed voltage waveform, comprising: (a) generating, by a first input channel, a first regulated voltage waveform from a first input voltage waveform; the first input voltage waveform is received by the first input channel electrically coupled to a transmission line electrically connecting a pulsed voltage waveform generator to a bias electrode disposed within a plasma processing chamber; the received first input voltage waveform is based on a pulsed voltage waveform generated by the pulsed voltage waveform generator; the first input channel having a first end coupled to a high speed data acquisition module and a second end coupled to the transmission line. Generating a first regulated voltage waveform; (b) generating, by the high speed data acquisition module, a first digitized voltage waveform from the first conditioned voltage waveform; (c) determining one or more waveform characteristics of the first regulated voltage waveform by analyzing the generated first digitized voltage waveform; and (d) generating one or more control parameters based on the determined one or more waveform characteristics; and (e) transmitting the one or more control parameters to the pulsed voltage waveform generator, the pulsed voltage waveform generator being configured to adjust one or more waveform characteristics of a plurality of pulsed voltage waveforms subsequently generated by the pulsed voltage waveform generator based at least in part on receipt of the transmitted one or more control parameters; A method comprising:

2. 2. The method of claim 1, wherein the one or more waveform characteristics determined are selected from the group consisting of a pulse amplitude, a pulse voltage offset, a duration of one cycle of a pulse, a pulse rise time, a pulse fall time, and a pulse repetition frequency.

3. 10. The method of claim 1, wherein determining the one or more waveform characteristics of the first regulated voltage waveform further comprises comparing properties of the first digitized voltage waveform to information stored in a memory.

4. 4. The method of claim 3, wherein the information stored in the memory of the high speed data collection module includes target voltage waveform characteristics selected from the group consisting of pulse amplitude, pulse voltage offset, duration of one cycle of a pulse, pulse rise time, pulse fall time, and pulse repetition frequency.

5. 2. The method of claim 1, wherein the first input channel includes a first voltage divider, and the generated first regulated voltage waveform includes a divided waveform generated using the first voltage divider.

6. 6. The method of claim 5, wherein the first voltage divider includes a first voltage divider cascade and a second voltage divider cascade, the first voltage divider cascade having a voltage division ratio in the range of 1:10 to 1:100, and the second voltage divider cascade having a voltage division ratio in the range of 1:20 to 1:

120.

7. 6. The method of claim 5, wherein the first input channel further comprises a first low pass filter, and the generated first regulated voltage waveform comprises a filtered waveform formed by filtering the divided waveform with the first low pass filter.

8. 2. The method of claim 1, wherein the first input channel further comprises a low pass filter having a frequency response curve including a plateau and a cutoff frequency, the plateau being between 1 MHz and 7 MHz and the cutoff frequency being within a range of 5 MHz to 10 MHz.

9. The method of claim 1 , wherein the bias electrode is disposed within a substrate support assembly that is disposed within the plasma processing chamber.

10. 2. The method of claim 1 , wherein the transmission line comprises a blocking capacitor electrically coupled between the pulsed voltage waveform generator and the bias electrode, and the second end of the first input channel is coupled to a location on the transmission line between the blocking capacitor and the bias electrode.

11. 2. The method of claim 1 , wherein the transmission line comprises a blocking capacitor electrically coupled between the pulsed voltage waveform generator and the bias electrode, and the second end of the first input channel is coupled to a location on the transmission line between the blocking capacitor and the pulsed voltage waveform generator.

12. The method of claim 1 , wherein the second end of the first input channel is coupled to an output of a current sensor positioned to measure a current flowing in the transmission line.

13. 2. The method of claim 1, further comprising repeating (a)-(e) a plurality of times until the determined one or more waveform characteristics of the first regulated voltage waveform reaches a target waveform characteristic value or limit, a maximum offset voltage, a maximum pulse power limit, a maximum pulse width, or a minimum pulse width.

14. 1. A method for controlling a pulsed voltage waveform, comprising: (a) generating, by a first input channel, a first regulated voltage waveform from a first input voltage waveform; the first input voltage waveform is received by the first input channel electrically coupled to a first location on a transmission line electrically connecting a pulsed voltage waveform generator to a bias electrode disposed within a plasma processing chamber; the received first input voltage waveform is based on a pulsed voltage waveform generated by the pulsed voltage waveform generator; the first input channel having a first end coupled to a high speed data acquisition module and a second end coupled to the first location of the transmission line. Generating a first regulated voltage waveform; (b) generating, by the high speed data acquisition module, a first digitized voltage waveform from the first conditioned voltage waveform; (c) generating, by a second input channel, a second regulated voltage waveform from the second input voltage waveform; the second input voltage waveform is received by the second input channel electrically coupled to a second location on the transmission line; the second input channel having a first end coupled to the high speed data collection module and a second end coupled to the second location on the transmission line. generating a second regulated voltage waveform; (d) generating, by the high speed data acquisition module, a second digitized voltage waveform from the second conditioned voltage waveform; and (e) determining one or more waveform characteristics by analyzing the first digitized voltage waveform and the second digitized voltage waveform; (f) generating one or more control parameters based on the determined one or more waveform characteristics; and (g) transmitting the one or more control parameters to the pulsed voltage waveform generator, the pulsed voltage waveform generator configured to adjust one or more waveform characteristics of a plurality of pulsed voltage waveforms subsequently generated by the pulsed voltage waveform generator based at least in part on receipt of the transmitted one or more control parameters; A method comprising:

15. 15. The method of claim 14, wherein the one or more waveform characteristics determined are selected from the group consisting of a pulse amplitude, a pulse voltage offset, a duration of one cycle of a pulse, a pulse rise time, a pulse fall time, and a pulse repetition frequency.

16. 15. The method of claim 14, wherein determining the one or more waveform characteristics of the first regulated voltage waveform further comprises comparing properties of the first digitized voltage waveform and the second digitized voltage waveform to information stored in a memory.

17. 15. The method of claim 14, wherein the information stored in the memory of the high speed data collection module includes target voltage waveform characteristics selected from the group consisting of pulse amplitude, pulse voltage offset, duration of one cycle of the pulse, pulse rise time, pulse fall time, and pulse repetition frequency.

18. 17. The method of claim 16, wherein the first input channel includes a first voltage divider, and the generated first regulated voltage waveform includes a divided waveform generated using the first voltage divider.

19. 20. The method of claim 18, wherein the second input channel comprises a second voltage divider, and the generated second regulated voltage waveform comprises a divided waveform generated using the second voltage divider.

20. the first voltage divider and the second voltage divider each comprise a first voltage divider cascade and a second voltage divider cascade; the first voltage divider cascade has a voltage division ratio in the range of 1:10 to 1:100; the second voltage divider cascade has a voltage division ratio in the range of 1:20 to 1:120; the first voltage divider and the second voltage divider each have a different voltage division ratio; 20. The method of claim 19.

21. 20. The method of claim 18, wherein the first input channel further comprises a low pass filter, and the generated first regulated voltage waveform further comprises a filtered waveform formed by filtering the divided waveform.

22. 15. The method of claim 14, wherein the first input channel and the second input channel each further comprise a low pass filter having a frequency response curve including a plateau and a cutoff frequency, the plateau being between 1 MHz and 7 MHz and the cutoff frequency being within a range of 5 MHz to 10 MHz.

23. 15. The method of claim 14, wherein the transmission line comprises a blocking capacitor electrically coupled between the pulsed voltage waveform generator and the bias electrode, and the first location on the transmission line is between the blocking capacitor and the bias electrode.

24. 24. The method of claim 23, wherein the second location on the transmission line is between the blocking capacitor and the pulsed voltage waveform generator.

25. 24. The method of claim 23, wherein the second end of the second input channel is coupled to an output of a current sensor positioned to measure a current flowing in the transmission line.

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