Optical detection device

Abstract

To provide a light detection device that increases a degree of freedom in arrangement of active elements.SOLUTION: A solid-state imaging device 1B as a light detecting device includes: a plurality of pixels 3 provided in a two-dimensional manner; and five semiconductor regions partitioned by an element isolation region 33 in each pixel of the plurality of pixels. The five semiconductor regions respectively include: two p-type semiconductor regions 24; two pairs of main electrode regions (n-type semiconductor regions) 46 and 47; and one p-type contact region (p-type semiconductor region) 48. The two p-type semiconductor regions 24 respectively include: a first semiconductor region in which a first transfer transistor (transfer transistor TR1) is provided; and a second semiconductor region in which a second transfer transistor (transfer transistor TR2) is provided.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present technology (the technology according to the present disclosure) relates to a light detection device, and more particularly to a technology effective when applied to a light detection device having a phase difference detection pixel.

Background Art

[0002] As a light detection device, a solid-state imaging device is known. In this solid-state imaging device, there is a method of performing pupil division by embedding a plurality of photoelectric conversion elements under one on-chip lens, and it is adopted for a light detection device for a built-in camera of an electronic device such as a single-lens reflex camera or a smartphone. Further, in the light detection device, there is a method of performing phase difference detection by reading out signal charges photoelectrically converted by a plurality of photoelectric conversion elements arranged under one on-chip lens as independent signals during phase difference detection.

[0003] This type of solid-state imaging device includes a semiconductor layer provided with a photoelectric conversion cell partitioned for each pixel by a pixel isolation region extending in the thickness direction of the semiconductor layer. Then, the photoelectric conversion cell is partitioned into a plurality of photoelectric conversion regions by an in-pixel isolation region extending in the thickness direction of the semiconductor layer, and a photoelectric conversion section, a transfer transistor, and a charge holding region (Floating Diffusion) are arranged in each of the plurality of photoelectric conversion regions.

[0004] On the other hand, on the side opposite to the light incident surface side of the photoelectric conversion cell, an element formation region partitioned by an element isolation region is provided, and pixel transistors such as an amplification transistor, a transfer transistor, and a reset transistor included in the readout circuit are arranged in this element formation region.

[0005] Note that a solid-state imaging device having a pixel isolation region, an in-pixel isolation region, and an element isolation region is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0006] Patent Document 1 US Patent Application Publication No. 2017 / 0012066 SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION

[0007] By the way, in a solid-state imaging device, with the increase in the number of pixels accompanying higher image quality, miniaturization of pixels is required. However, with the miniaturization of pixels, it becomes difficult to arrange active elements such as transfer transistors and pixel transistors included in a readout circuit within a photoelectric conversion cell. In particular, in a photoelectric conversion cell including an intra-pixel isolation region, it is difficult to arrange an active element in the intra-pixel isolation region, so the degree of freedom in arranging active elements is lower.

[0008] An object of the present technology is to increase the degree of freedom in arranging active elements. MEANS FOR SOLVING THE PROBLEM

[0009] (1) A photodetection device according to one aspect of the present technology includes a semiconductor layer having a first surface and a second surface located on opposite sides in the thickness direction, and a photoelectric conversion cell provided on the semiconductor layer and partitioned by a first separation region extending in the thickness direction of the semiconductor layer. The photoelectric conversion cell includes a first photoelectric conversion region and a second photoelectric conversion region each provided adjacent to each other in a plan view on the semiconductor layer and each having a photoelectric conversion unit and a transfer transistor, and a second separation region disposed between the first photoelectric conversion region and the second photoelectric conversion region in a plan view and extending in the thickness direction of the semiconductor layer, and an element formation region partitioned by a third separation region on the first surface side of the semiconductor layer and provided with a pixel transistor, and the element formation region extends across the first and second photoelectric conversion regions in a plan view.

[0010] (2) The photoelectric conversion device according to another aspect of the present technology is a semiconductor layer having a first surface and a second surface located on opposite sides in the thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and sectioned by a first separation region extending in the thickness direction of the semiconductor layer. And the photoelectric conversion cell has a first photoelectric conversion region and a second photoelectric conversion region each provided adjacent to each other in a plan view of the semiconductor layer and each having a photoelectric conversion section and a transfer transistor, a second separation region provided between the first photoelectric conversion region and the second photoelectric conversion region in a plan view and extending in the thickness direction of the semiconductor layer, an element formation region partitioned by a third separation region on the first surface side of the semiconductor layer and provided with a pixel transistor, a charge holding region provided on the first surface side of the semiconductor layer, a first conductivity type semiconductor region provided in the semiconductor layer across the element formation region, the first photoelectric conversion region, and the second photoelectric conversion region, and a first conductivity type contact region provided in the semiconductor region. And at least one of the charge holding region and the contact region is shared by the first and second photoelectric conversion regions and disposed between the first photoelectric conversion region and the second photoelectric conversion region in a plan view.

[0011] (3) The photodetection device according to another aspect of the present technology is a semiconductor layer having a plurality of photoelectric conversion cells arranged adjacent to each other via a separation region in a plan view and each provided with a photoelectric conversion section and a transfer transistor, semiconductor regions respectively provided on the separation region side of each of the plurality of photoelectric conversion cells in a plan view, and a conductive pad partially embedded in the separation region and connected to the semiconductor regions of each of the plurality of photoelectric conversion cells across the separation region in a plan view.

[0012] (4) The photodetection device according to another aspect of the present technology is a semiconductor layer having a first surface and a second surface located on opposite sides in the thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by an element isolation region. The photoelectric conversion cell has a transfer transistor, a charge holding region, and a contact region on the first surface side of the semiconductor layer, and has a photoelectric conversion portion on the second surface side. The isolation region has a first portion in which the charge holding region contacts in a plan view, and a second portion in which the contact region contacts and has a width narrower than that of the first portion. (5) The photodetection device according to another aspect of the present technology is provided with a pixel unit having four pixels each having two photoelectric conversion regions, two transfer transistors, and two charge holding regions, and the charge holding regions of each pixel in the pixel unit are electrically connected to each other. (6) The photodetection device according to another aspect of the present technology is provided with a plurality of pixels arranged two-dimensionally, and each of the plurality of pixels has five semiconductor regions partitioned by an element isolation region. (7) The photodetection device according to another form of the present technology is provided with a plurality of pixels arranged two-dimensionally, and each pixel has five semiconductor regions partitioned by an element isolation region, and the five semiconductor regions are a first semiconductor region provided with a first transfer transistor, a second semiconductor region provided with a second transfer transistor, a third semiconductor region provided with a first pixel transistor other than the first and second transfer transistors, a fourth semiconductor region provided with a second pixel transistor other than the first and second transfer transistors, and a p-type semiconductor region. It has.

[0013] (8) The photodetection device according to another form of the present technology is a first pixel provided on a semiconductor substrate, a trench including a first region that separates the first pixel from an adjacent pixel and a second region where a photoelectric conversion unit provided within the pixel is blocked in plan view, in plan view, the second region has a first portion between a first floating diffusion region and a second floating diffusion region provided in the first pixel, in plan view, the second region has a second portion between a first transistor and a second transistor provided in the first pixel, a contact region is provided between the first portion and the second portion in plan view. (9) An optical detection device according to another aspect of the present technology, includes a first pixel provided on a semiconductor substrate, and a separation region that separates the first pixel from an adjacent pixel, in plan view, the first pixel is surrounded by first to fourth portions of the separation region, in plan view, the first pixel has a fifth portion and a sixth portion provided between the first portion and the third portion, a contact region is provided between the fifth portion and the sixth portion in plan view, the fifth portion is in contact with the first portion, and the sixth portion is in contact with the third portion. (10) An electronic device according to another aspect of the present technology includes the optical detection device according to any one of (1) to (9) above, an optical lens that forms image light from a subject on an imaging surface of the optical detection device, and a signal processing circuit that performs signal processing on a signal output from the optical detection device.

Brief Description of Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21A

Figure 21B

Figure 21C

Figure 21D

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42A

Figure 42B

Figure 42C

Figure 42D

Figure 43A

Figure 43B

Figure 43C

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Figure 54

Figure 55

Figure 56

Figure 57

Figure 58

Figure 59

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the description of the drawings referred to in the following explanation, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following explanation.

[0016] Also, it goes without saying that there are parts where the dimensional relationships and ratios are different between the drawings. Also, the effects described in this specification are merely examples and are not limited, and there may be other effects.

[0017] Also, the following embodiments illustrate devices and methods for embodying the technical idea of the present technology, and do not specify the configuration to the following. That is, various changes can be made to the technical idea of the present technology within the technical scope described in the claims.

[0018] Also, the definitions of directions such as up and down in the following explanation are merely definitions for convenience of explanation and do not limit the technical idea of the present technology. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, of course.

[0019] Also, in the following embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type will be exemplarily described, but the conductivity types may be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type.

[0020] In the following embodiments, in three directions orthogonal to each other in space, the first direction and the second direction orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and the third direction orthogonal to each of the first direction and the second direction is defined as the Z direction. In the following embodiments, the thickness direction of the semiconductor layer 21 described later will be described as the Z direction.

[0021] 〔First Embodiment〕 In this Embodiment 1, as an example of applying this technology to a solid-state imaging device which is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a light detection device, an example will be described.

[0022] ≪Overall Configuration of Solid-State Imaging Device≫ First, the overall configuration of the solid-state imaging device 1A will be described. As shown in FIG. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in plan. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2. As shown in FIG. 55, this solid-state imaging device 1A (201) takes in image light (incident light 206) from a subject via an optical lens 202, and converts the amount of the incident light 206 imaged on the imaging surface into an electrical signal in pixel units and outputs it as a pixel signal.

[0023] As shown in FIG. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a rectangular pixel region 2A provided at the center and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A in a two-dimensional plane including the X direction and the Y direction orthogonal to each other.

[0024] The pixel region 2A is a light-receiving surface that receives light condensed by, for example, the optical lens (optical system) 202 shown in FIG. 55. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix in a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in the respective directions of the X direction and the Y direction orthogonal to each other in the two-dimensional plane.

[0025] As shown in FIG. 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in the two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0026] <Logic circuit> As shown in FIG. 2, the semiconductor chip 2 includes a logic circuit 13 including a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like. The logic circuit 13 is a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-channel MOSFET.

[0027] The vertical drive circuit 4 is constituted by, for example, a shift register. The vertical drive circuit 4 sequentially selects a desired pixel drive line 10, supplies a pulse for driving the pixel 3 to the selected pixel drive line 10, and drives each pixel 3 in row units. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A in the vertical direction in row units, and supplies a pixel signal from the pixel 3 based on the signal charge generated by the photoelectric conversion element of each pixel 3 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 11.

[0028] The column signal processing circuit 5 is arranged, for example, for each column of the pixels 3, and performs signal processing such as noise removal for each column of the signals output from the pixels 3 for one row. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog Digital) conversion.

[0029] The horizontal drive circuit 6 is constituted by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuit 5 to select each of the column signal processing circuits 5 in order, and causes the pixel signals that have undergone signal processing from each of the column signal processing circuits 5 to be output to the horizontal signal lines 12.

[0030] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal lines 12 and outputs them. As the signal processing, for example, buffering, black level adjustment, column variation correction, various digital signal processings, etc. can be used.

[0031] The control circuit 8 generates clock signals and control signals that serve as the basis for the operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0032] <Pixel> As shown in FIG. 3, each of the plurality of pixels 3 includes a photoelectric conversion cell 22A. The photoelectric conversion cell 22A includes two photoelectric conversion regions 23L and 23R. The first photoelectric conversion region 23L includes a photoelectric conversion element PD1, a charge holding region (Floating Diffusion) FD1 that holds (accumulates) the signal charge photoelectrically converted by this photoelectric conversion element PD1, and a transfer transistor TR1 that transfers the signal charge photoelectrically converted by this photoelectric conversion element PD1 to the charge accumulation region FD1. Similarly, in the second photoelectric conversion region 23R, there are provided a photoelectric conversion element PD2, a charge holding region FD2 that holds (accumulates) the signal charge photoelectrically converted by this photoelectric conversion element PD2, and a transfer transistor TR2 that transfers the signal charge photoelectrically converted by this photoelectric conversion element PD2 to the charge accumulation region FD2.

[0033] Each of the two photoelectric conversion elements PD1 and PD2 generates signal charges according to the amount of received light. Also, each of the two photoelectric conversion elements PD1 and PD2 temporarily holds (accumulates) the generated signal charges. The cathode side of the photoelectric conversion element PD1 is electrically connected to the source region of the transfer transistor TR1, and the anode side is electrically connected to the reference potential line (e.g., ground). The cathode side of the photoelectric conversion element PD2 is electrically connected to the source region of the transfer transistor TR2, and the anode side is electrically connected to the reference potential line (e.g., ground). For example, photodiodes are used as the photoelectric conversion elements PD1 and PD2.

[0034] In the two transfer transistors TR1 and TR2, for the transfer transistor TR1, the source region is electrically connected to the cathode side of the photoelectric conversion element PD1, and the drain region is electrically connected to the charge holding region FD1. And the gate electrode of the transfer transistor TR1 is electrically connected to the transfer transistor drive line among the pixel drive lines 10 (see Figure 2). For the transfer transistor TR2, the source region is electrically connected to the cathode side of the photoelectric conversion element PD2, and the drain region is electrically connected to the charge holding region FD2. And the gate electrode of the transfer transistor TR2 is electrically connected to the transfer transistor drive line among the pixel drive lines 10.

[0035] In the two charge holding regions FD1 and FD2, the charge holding region FD1 temporarily accumulates and holds the signal charges transferred from the photoelectric conversion element PD1 via the transfer transistor TR1. The charge holding region FD2 temporarily accumulates and holds the signal charges transferred from the photoelectric conversion element PD2 via the transfer transistor TR2.

[0036] As shown in FIG. 3, the input stage of the readout circuit 15 is connected to each of the two charge holding regions FD1 and FD2. The readout circuit 15 reads the signal charges held in the charge holding regions FD1 and FD2 and outputs a pixel signal based on the signal charges. The readout circuit 15 is, but not limited to, shared by, for example, two pixels 3, in other words, two photoelectric conversion cells 22A. The readout circuit 15 includes an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are constituted by pixel transistors Qt (see FIG. 4) described later.

[0037] The source region of the amplification transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line VDD and the drain region of the reset transistor RST. The gate electrode of the amplification transistor AMP is electrically connected to each of the charge holding regions FD1 and FD2 of the two photoelectric conversion cells 22A and the source region of the reset transistor RST, respectively.

[0038] The source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0039] The source region of the reset transistor RST is electrically connected to each of the charge holding regions FD1 and FD2 of the two photoelectric conversion cells 22A and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line VDD and the drain region of the amplification transistor AMP, respectively. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 10 (see FIG. 2).

[0040] When the transfer transistor TR1 is turned on, the transfer transistor TR1 transfers the signal charge generated by the photoelectric conversion element PD1 to the charge holding region FD1. When the transfer transistor TR2 is turned on, the transfer transistor TR2 transfers the signal charge generated by the photoelectric conversion element PD2 to the charge holding region FD2.

[0041] When the reset transistor RST is turned on, the reset transistor RST resets the potentials (signal charges) of the charge holding regions FD1 and FD2 to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 15.

[0042] The amplification transistor AMP generates, as a pixel signal, a voltage signal corresponding to the level of the signal charge held in the charge holding regions FD1 and FD2. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal of a voltage corresponding to the level of the signal charge generated by the photoelectric conversion elements PD1 and PD2. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potentials of the charge holding regions FD1 and FD2 and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0043] Here, in the electronic device including the solid-state imaging device 1A of the first embodiment, signal charges are read out from each of the two photoelectric conversion elements PD1 and PD2 for each pixel 3, and the phase difference is detected. When the focus is correct, there is no difference in the amount of signal charge accumulated in the photoelectric conversion element PD1 and the photoelectric conversion element PD2. On the other hand, when the focus is not correct, a difference occurs between the amount of signal charge Q1 accumulated in the photoelectric conversion element PD1 and the amount of signal charge Q2 accumulated in the photoelectric conversion element PD2. Then, when the focus is not correct, the electronic device performs an operation such as operating the objective lens so that Q1 and Q2 match. This is autofocus.

[0044] ≪Specific Configuration of Solid-State Imaging Device≫ Next, the specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4 to 7. For ease of viewing the drawings, in FIGS. 4 to 7, the illustration of the multilayer wiring layer described later is omitted. Also, FIG. 4 is inverted vertically with respect to FIG. 1. That is, in FIG. 1, the light incident surface side of the semiconductor chip 2 is depicted, while FIG. 4 is a plan view when viewed from the side opposite to the light incident surface side (multilayer wiring layer side) of the semiconductor chip 2 shown in FIG. 1.

[0045] <Semiconductor chip> As shown in FIGS. 4 to 7, the semiconductor chip 2 includes a semiconductor layer 21 having a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction), and a photoelectric conversion cell 22A provided in the semiconductor layer 21 and partitioned by a pixel isolation region 31 serving as a first separation region extending in the thickness direction (Z direction) of the semiconductor layer 21. The photoelectric conversion cell 22A is provided for each pixel 3. That is, each of the plurality of pixels 3 includes a photoelectric conversion cell 22A. The semiconductor layer 21 is made of, for example, single crystal silicon.

[0046] Further, the semiconductor chip 2 further includes a color filter 51 and a microlens (on-chip lens) 52 sequentially stacked from the second surface S2 side of the semiconductor layer 21 on the second surface S2 side. Also, although not shown, the semiconductor chip 2 further includes a multilayer wiring layer including an insulating layer and a wiring layer provided on the first surface S1 side of the semiconductor layer 21.

[0047] The color filter 51 and the microlens 52 are each provided for each pixel 3 (photoelectric conversion cell 22A). The color filter 51 separates the incident light incident from the light incident surface side of the semiconductor chip 2 by color. The microlens 52 condenses the irradiated light and efficiently makes the condensed light incident on the pixel 3 (photoelectric conversion cell 22A). Also, one color filter 51 and microlens 52 are provided so as to cover both a first photoelectric conversion region 23L and a second photoelectric conversion region 23R described later.

[0048] Here, the first surface S1 of the semiconductor layer 21 may also be referred to as the element formation surface or the main surface, and the second surface S2 side may be referred to as the light incident surface or the back surface. In the solid-state imaging device 1A of this first embodiment, the light incident from the second surface (light incident surface, back surface) S2 side of the semiconductor layer 21 is photoelectrically converted by the photoelectric conversion unit 25 (photoelectric conversion element PD1) of the photoelectric conversion cell 22A provided in the semiconductor layer 21.

[0049] <photoelectric conversion cell> As shown in FIGS. 4 to 7, the photoelectric conversion cell 22A includes a first photoelectric conversion region 23L and a second photoelectric conversion region 23R that are arranged adjacent to each other in the X direction in plan view on the semiconductor layer 21. Each of the first photoelectric conversion region 23L and the second photoelectric conversion region 23R has a photoelectric conversion unit 25 and transfer transistors TR1 and TR2. Further, the photoelectric conversion cell 22A further includes an in-pixel separation region 32 as a second separation region that is arranged between the first photoelectric conversion region 23L and the second photoelectric conversion region 23R in plan view and extends in the thickness direction (Z direction) of the semiconductor layer 21.

[0050] Further, the photoelectric conversion cell 22A is partitioned by an element isolation region (surface isolation region) 33 as a third separation region in the surface layer portion on the first surface S1 side of the semiconductor layer 21, and further includes an island-shaped element formation region (active region) 21a provided with a pixel transistor Qt. Further, in the first photoelectric conversion region 23L, the photoelectric conversion cell 22A includes an island-shaped element formation region 21b1 that is partitioned by the element isolation region 33 in the surface layer portion on the first surface S1 side of the semiconductor layer 21 and is provided with the above-described transfer transistor TR1, and in the second photoelectric conversion region 23R, the photoelectric conversion cell 22A includes an island-shaped element formation region 21b2 that is partitioned by the element isolation region 33 in the surface layer portion on the first surface S1 side of the semiconductor layer 21 and is provided with the above-described transfer transistor TR2. Further, the photoelectric conversion cell 22A further includes an island-shaped power supply region 21z that is partitioned by the element isolation region 33 in the surface layer portion on the first surface S1 side of the semiconductor layer 21.

[0051] The photoelectric conversion cell 22A further includes charge holding regions FD1 and FD2 provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21. The photoelectric conversion cell 22A further includes a p-type (first conductivity type) semiconductor region 24 provided across each of the element formation regions 21a, 21b1, and 21b2, the first photoelectric conversion region 23L, and the second photoelectric conversion region 23R, and a p-type contact region 48 provided in the p-type semiconductor region 24.

[0052] As shown in FIG. 4, the photoelectric conversion cell 22A has a rectangular planar pattern having four sides. Although not shown in detail, the photoelectric conversion cell 22A is repeatedly arranged for each three pixels via a pixel isolation region 31 in each of the X direction and the Y direction in plan view.

[0053] <Pixel isolation region> As shown in FIGS. 4 to 7, the pixel isolation region 31 extends from the second surface S2 side to the first surface S1 side of the semiconductor layer 21, and electrically and optically separates between adjacent three pixels and between the photoelectric conversion cells 22A in a two-dimensional plane. The pixel isolation region 31 is, for example, but not limited to, a trench isolation structure in which an insulating film is embedded in a groove extending from the second surface S2 to the first surface S1 side of the semiconductor layer 21 and integrated with the element isolation region 33 on the first surface S1 side of the semiconductor layer 21.

[0054] As shown in FIG. 4, the pixel isolation region 31 corresponding to one photoelectric conversion cell 22A (pixel 3) has an annular planar pattern (ring-shaped planar pattern) with a square planar shape in plan view. And the pixel isolation region 31 corresponding to the pixel region 2A in which a plurality of pixels 3 (photoelectric conversion cells 22A) are arranged has a composite planar pattern having a lattice-shaped planar pattern in the annular planar pattern with a square shape. That is, the pixel isolation region 31 separates the semiconductor layer 21 for each photoelectric conversion cell 22A (pixel 3). And the photoelectric conversion cell 22A is surrounded by two pixel isolation regions 31 extending in the arrangement direction (X direction) in which the first and second photoelectric conversion regions 23L and 23R are arranged, and two pixel isolation regions 31 extending in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first and second photoelectric conversion regions 23L and 23R. In other words, the photoelectric conversion cell 22A is surrounded by two pixel isolation regions 31 located on opposite sides in the arrangement direction of the first and second photoelectric conversion regions 23L and 23R, and two pixel isolation regions 31 located on opposite sides in a direction (Y direction) orthogonal to the arrangement direction (X direction) of the first and second photoelectric conversion regions 23L and 23R.

[0055] Here, in the pixel isolation region 31 partitioning the photoelectric conversion cell 22A, the two pixel isolation regions 31 extending in the X direction with the photoelectric conversion cell 22A interposed therebetween may be referred to as pixel isolation regions 31a and 31b. Also, the two pixel isolation regions 31 extending in the Y direction with the photoelectric conversion cell 22A interposed therebetween may be referred to as pixel isolation regions 31c and 31d.

[0056] <Intra-pixel isolation region> As shown in FIGS. 4 to 7, the intra-pixel isolation region 32 protrudes inward (toward the photoelectric conversion cell 22A) from the middle part of each of the two pixel isolation regions 31a and 31b extending in the X direction with the photoelectric conversion cell 22A interposed therebetween in plan view, and is spaced apart from each other. That is, the photoelectric conversion cell 22A is selectively partitioned by two intra-pixel isolation regions 32 protruding inward from the middle part of each of the two pixel isolation regions 31a and 31b extending in the X direction, where the first photoelectric conversion region 23L and the second photoelectric conversion region 23Lb adjacent to each other in the X direction are located.

[0057] The two in-pixel isolation regions 32 are not limited thereto, and similar to the pixel isolation region 31, for example, an insulating film is embedded in a groove extending from the second surface S2 of the semiconductor layer 21 toward the first surface S1 side, and the trench isolation structure is integrated with the element isolation region 33 on the first surface S1 side of the semiconductor layer 21.

[0058] <Element isolation region> As shown in FIGS. 4 to 7, the element isolation region 33 is provided over the first photoelectric conversion region 23L and the second photoelectric conversion region 23R in the surface layer portion on the first surface S1 side of the semiconductor layer 21. Further, the element isolation region 33 is provided over a plurality of photoelectric conversion cells 22A. And the element isolation region 33 overlaps with each of the pixel isolation region 31 and the in-pixel isolation region 32 in plan view. And the element isolation region 33 is in contact with and integrated with each of the pixel isolation region 31 and the in-pixel isolation region 32 in the depth direction of the semiconductor layer 21. The element isolation region 33 is not limited thereto, and for example, has a STI (Shallow Trench Isolation) structure in which an insulating film is embedded in a shallow groove recessed in the depth direction from the first surface S1 of the semiconductor layer 21.

[0059] <Photoelectric conversion part> As shown in FIGS. 5 to 7, the photoelectric conversion parts 25 of each of the first and second photoelectric conversion regions 23L, 23R are spaced apart from the first surface S1 of the semiconductor layer 21 in the thickness direction (Z direction) and are provided biased toward the second surface S2 side. Further, as shown in FIGS. 4 and 5, both end portions in the Y direction of the photoelectric conversion parts 25 of each of the first and second photoelectric conversion regions 23L, 23R are partitioned by the in-pixel isolation region 32 and the p-type semiconductor region 24. Also, as shown in FIGS. 6 and 7, the photoelectric conversion parts 25 of each of the first and second photoelectric conversion regions 23L, 23R are integrated between the two in-pixel isolation regions 32. And each photoelectric conversion part 25 includes an n-type (second conductivity type) semiconductor region 26 and constitutes the above-described photoelectric conversion elements PD1, PD2.

[0060] <p-type semiconductor region> As shown in FIGS. 4 to 7, the p-type semiconductor region 24 is provided for each photoelectric conversion cell 22A, and is electrically separated from the p-type semiconductor regions 24 of adjacent photoelectric conversion cells 22A by the pixel isolation region 31 and the element isolation region 33.

[0061] As described above, the p-type semiconductor region 24 is provided across each of the element formation regions 21a, 21b1, 21b2, the first photoelectric conversion region 23L, and the second photoelectric conversion region 23R. Specifically, as shown in FIGS. 5 to 7, the p-type semiconductor region 24 is provided in the surface layer portion of the first surface S1 of the semiconductor layer 21 including the element formation regions 21a, 21b1, 21b2, and the power supply region 21z. Further, as shown in FIGS. 6 and 7, the p-type semiconductor region 24 crosses between the two intra-pixel isolation regions 32 and is provided across each of the first and second photoelectric conversion regions 23L and 23R. Further, the p-type semiconductor region 24 is provided between each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R and the first surface S1 of the semiconductor layer 21. And the p-type semiconductor region 24 is also provided between each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R and the pixel isolation region 31 and the intra-pixel isolation region 32. The p-type semiconductor region 24 provided between each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R and each of the pixel isolation region 31 and the intra-pixel isolation region 32 is provided across from the first surface S1 side to the second surface S2 side of the semiconductor layer 21. That is, the upper surface on the element isolation region 33 side and the side surface on the pixel isolation region 31 side of each photoelectric conversion portion 25 are covered with the p-type semiconductor region 24. And each photoelectric conversion portion 25 is separated from the pixel isolation region 31, the intra-pixel isolation region 32, and the element isolation region 33 via the p-type semiconductor region 24. The p-type semiconductor region 24 is composed of one semiconductor region or a plurality of semiconductor regions. The p-type semiconductor region 24 forms a pn junction with the n-type semiconductor region 26 of the photoelectric conversion portion 25 for each photoelectric conversion cell 22A.

[0062] <Element formation regions 21b1 and 21b2> As shown in FIG. 4, each of the element formation regions 21b1 and 21b2 is arranged adjacent to each other in the X direction in a plan view. And each of the element formation regions 21b1 and 21b2 is arranged on the other pixel isolation region 31 side of the two pixel isolation regions 31 that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween, rather than the element formation region 21a.

[0063] As shown in FIG. 5, the element formation region 21b1 overlaps with the photoelectric conversion unit 25 in the first photoelectric conversion region 23L. The element formation region 21b2 overlaps with the photoelectric conversion unit 25 in the second photoelectric conversion region 23R. And as shown in FIGS. 4 and 5, a transfer transistor TR1 and a charge holding region FD1 are provided in the element formation region 21b1. Similarly, a transfer transistor TR2 and a charge holding region FD2 are also provided in the element formation region 21b2.

[0064] <Charge holding region> As shown in FIG. 5, each of the two charge holding regions FD1 and FD2 is provided on the first surface S1 side of the semiconductor layer 21 and overlaps with the photoelectric conversion unit 25 via the p-type semiconductor region 24. And as shown in FIG. 4, the charge holding region FD1 is arranged on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween in the first photoelectric conversion region 23L, and the intra-pixel isolation region 32 that protrudes inward from the middle part of this other pixel isolation region 31b. Also, in the charge holding region FD2, in the first photoelectric conversion region 23R, similar to the charge holding region FD1, it is arranged on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31 that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween, and the intra-pixel isolation region 32 that protrudes inward from the middle part of this other pixel isolation region 31b. The charge storage regions FD1 and FD2 are composed of n-type semiconductor regions having a higher impurity concentration than the n-type semiconductor region 26.

[0065] <Transfer transistor> As shown in FIG. 5, each of the transfer transistors TR1 and TR2 includes a gate groove portion 41 provided on the first surface S1 side of the semiconductor layer 21, a gate insulating film 42 provided along the side walls and the bottom wall in the gate groove portion 41, and a gate electrode 43 provided in the gate groove portion 41 via the gate insulating film 42. Further, the transfer transistors TR1 and TR2 include a channel formation region composed of a p-type semiconductor region 24 arranged side by side via the gate insulating film 42 on the side walls of the gate electrode 43, a photoelectric conversion portion 25 functioning as a source region, and charge holding regions FD1 and FD2 functioning as drain regions.

[0066] As shown in FIG. 5, the gate electrode 43 includes a first portion (vertical gate electrode portion) provided in the gate groove portion 41 via the gate insulating film 42, and a second portion formed integrally with the first portion and provided outside the gate groove portion 41. The gate insulating film 42 is composed of, for example, a silicon oxide film. The gate electrode 43 is composed of, for example, a polycrystalline silicon film into which impurities for reducing the resistance value are introduced.

[0067] As shown in FIG. 5, in the transfer transistors TR1 and TR2, the charge holding regions FD1 and FD2 functioning as drain regions and the photoelectric conversion portion 25 functioning as a source region are arranged along the depth direction of the semiconductor layer 21 via the p-type semiconductor region 24 of the channel formation region. That is, the transfer transistors TR1 and TR2 of this first embodiment have a vertical structure in which the source region and the drain region are arranged in the depth direction of the semiconductor layer 21. The transfer transistors TR1 and TR2 having this vertical structure are useful for miniaturization of the photoelectric conversion cell 22A (pixel 3).

[0068] As shown in FIG. 4, the transfer transistor TR1 of the first photoelectric conversion region 23L is disposed on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween in plan view, and one pixel isolation region 31c of the two pixel isolation regions 31c and 31d that extend in the Y direction with the photoelectric conversion cell 22A interposed therebetween. And the transfer transistor TR2 of the second photoelectric conversion region 23R is disposed on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween in plan view, and the other pixel isolation region 31d of the two pixel isolation regions 31c and 31d that extend in the Y direction with the photoelectric conversion cell 22A interposed therebetween.

[0069] <Element formation region 21a> As shown in FIG. 4, the element formation region 21a is disposed closer to one pixel isolation region 31a of the two pixel isolation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22A interposed therebetween than the element formation regions 21b1 and 21b2. And the element formation region 21a extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R in plan view.

[0070] As shown in FIGS. 4 and 7, the element formation region 21a includes a first portion 21a1 that traverses in the X direction between the two intra-pixel isolation regions 32 in plan view, and a pair of second portions 21a2 that extend from each of one end side and the other end side in the X direction of the first portion 21a1 toward the transfer transistor TR side of the first portion 21a1, in other words, the side opposite to the element isolation regions 21b1 and 21b2 of the first portion 21a1. That is, the element formation region 21a of this first embodiment includes, but is not limited to, two bent portions in plan view, and has an inverted U-shaped planar pattern in which the side of the element formation regions 21b1 and 21b2, in other words, one pixel isolation region 31a side of the two pixel isolation regions 31a and 31b that extend in the X direction is open.

[0071] As shown in FIGS. 4 and 7, two pixel transistors Qt are provided in the element formation region 21a. One of the two pixel transistors Qt is disposed at one of the two corners of the element formation region 21a. The other of the two pixel transistors Qt is disposed at the other corner of the two corners of the element formation region 21a. In other words, one pixel transistor Qt is disposed across the first portion 21a1 and one second portion 21a2 of the element formation region 21a. Also, the other pixel transistor Qt is disposed across the first portion 21a1 and the other second portion 21a2 of the element formation region 21a. That is, the photoelectric conversion cell 22A is provided with pixel transistors Qt in each of the first and second photoelectric conversion regions 23L, 23L.

[0072] As shown in FIGS. 4 and 7, each of the two pixel transistors Qt includes a gate insulating film 44 provided on the element formation region 21a on the first surface S1 side of the semiconductor layer 21, and a gate electrode 45 provided on the element formation region 21a via the gate insulating film 44. Also, each of the two pixel transistors Qt further includes a channel formation region in which a channel (conductive path) is formed in a p-type semiconductor region 24 directly under the gate electrode 45, and a pair of main electrode regions 46 and 47 which are provided in the p-type semiconductor region 24 so as to be separated from each other in the channel length direction (gate length direction) with the channel formation region therebetween and which function as a source region and a drain region. Each of the two pixel transistors Q controls the channel formed in the channel formation region by a gate voltage applied to the gate electrode 45.

[0073] As shown in FIGS. 4 and 7, the two pixel transistors Qt share one main electrode region 46 of each. That is, the two pixel transistors Qt are mounted on the element formation region 21a in a series connection sharing one main electrode region 46 of each.

[0074] One of the main electrode regions 46 shared by the two pixel transistors Qt is formed in the first portion 21a1 of the element formation region 21a in self-alignment with the gate electrode 45 of each of the two pixel transistors Qt, and includes a semiconductor region having a higher impurity concentration than the n-type semiconductor region 26 of the photoelectric conversion unit 25. The other main electrode region 47 included in one of the two pixel transistors Qt (on the side of the first photoelectric conversion region 23L) is formed in one second portion 21a2 of the element formation region 21a in self-alignment with the gate electrode 45 of this one pixel transistor Qt, and includes a semiconductor region having a higher impurity concentration than the n-type semiconductor region 26 of the photoelectric conversion unit 25. The other main electrode region 47 included in the other of the two pixel transistors Qt (on the side of the second photoelectric conversion region 23L) is formed in the other second portion 21a2 of the element formation region 21a in self-alignment with the gate electrode 45 of the other pixel transistor Q, and includes a semiconductor region having a higher impurity concentration than the n-type semiconductor region 26 of the photoelectric conversion unit 25.

[0075] <Power supply region> As shown in FIGS. 4 and 6, the power supply region 21z is disposed between the element formation regions 21b1 and 21b2 in a plan view. Further, the power supply region 21z is disposed between the two pixel internal separation regions 32 in a plan view. And a p-type contact region 48 is provided in the power supply region 21z. That is, the p-type contact region 48 is disposed between the two pixel internal separation regions 32 in a plan view and is shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R.

[0076] The p-type contact region 48 includes a p-type semiconductor region (impurity region) having a higher impurity concentration than the p-type semiconductor region 24. A reference potential is applied to this p-type contact region 48 as a power supply potential. Then, the p-type semiconductor region 24 is fixed at the reference potential via the p-type contact region 48. In this first embodiment, for example, a Vss potential of 0 V is applied as the reference potential. That is, the p-type contact region 48 is shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R. And in each of the first and second photoelectric conversion regions 23L and 23R, the p-type semiconductor region 24 has a reference potential applied thereto via the p-type contact region and is fixed at the reference potential.

[0077] <Flow of signal charges between the first photoelectric conversion region and the second photoelectric conversion region> As shown in FIGS. 6 and 7, each of the p-type semiconductor region 24 and the n-type semiconductor region 26 extends across each of the first photoelectric conversion region 23L and the second photoelectric conversion region 23L and crosses between the two intra-pixel separation regions 32 in plan view. And the space between the two intra-pixel separation regions 32 functions as an overflow path.

[0078] A first potential barrier can be formed between the two intra-pixel separation regions 32. When the transfer transistor TR1 of the first photoelectric conversion region 23L does not transfer signal charges from the photoelectric conversion unit 25 to the charge holding region FD1, a second potential barrier higher than the first potential barrier can be formed. Also, when the transfer transistor TR2 of the second photoelectric conversion region 23R does not transfer signal charges from the photoelectric conversion unit 25 to the charge holding region FD2, a second potential barrier higher than the first potential barrier can be formed.

[0079] Each photoelectric conversion unit 25 of each of the first and second photoelectric conversion regions 23L and 23R can independently accumulate signal charges up to the height of the first potential barrier. And when the amount of the accumulated signal charges exceeds the height of the first potential barrier, the signal charges flow from one of the photoelectric conversion units 25 of each of the first and second photoelectric conversion regions 23L and 23R to the other via the overflow path between the two intra-pixel separation regions 32.

[0080] <Main effects of the first embodiment> Next, the main effects of this first embodiment will be described. As shown in FIG. 4, in the solid-state imaging device 1A according to this first embodiment, since the element formation region 21a partitioned by the element isolation region 33 extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, it is possible to utilize the region between the two pixel inner isolation regions 32 in a plan view as the arrangement region of the pixel transistor Qt. As a result, it becomes possible to increase the degree of freedom in arranging the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22. In addition, since the degree of freedom in arranging the active elements within the photoelectric conversion cell 22 can be increased, it becomes possible to miniaturize the pixel 3 including the photoelectric conversion cell 22.

[0081] Also, as shown in FIG. 4, in the solid-state imaging device 1A according to this first embodiment, since the p-type contact region 48 shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R is arranged between the two pixel inner isolation regions 32 in a plan view, compared with the case where the contact region 48 is individually arranged in each of the first and second photoelectric conversion regions 23L and 23R, the degree of freedom in arranging the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 can be increased.

[0082] In addition, since the solid-state imaging device 1A according to this first embodiment employs a combination of both the arrangement of the element formation region 21a and the arrangement of the contact region 48, compared with the case where only one of the arrangement of the element formation region 21a and the arrangement of the contact region 48 is employed, it becomes possible to further increase the degree of freedom in arranging the active elements and to further miniaturize the pixel 3 including the photoelectric conversion cell 22.

[0083] In addition, in the solid-state imaging device 1A according to the first embodiment, one main electrode region 46 of the pixel transistor Qt disposed in the first photoelectric conversion region 23L and one main electrode region 46 of the pixel transistor Qt disposed in the second photoelectric conversion region 23R are shared between two pixel internal separation regions 32 in a plan view. Therefore, compared with the case where one main electrode region 46 of the pixel transistor Qt disposed in the first photoelectric conversion region 23L and one main electrode region 46 of the pixel transistor Qt disposed in the second photoelectric conversion region 23R are provided separately, the freedom of arranging active elements in the photoelectric conversion cell 22A can be further increased.

[0084] In addition, without increasing the planar size of the photoelectric conversion cell 22A (pixel 3), the gate area (gate length Lg × gate width Wg) of the pixel transistor Qt can be increased, and noise reduction can be achieved while suppressing an increase in the planar size of the pixel 3 including the photoelectric conversion cell 22A.

[0085] 〔Second Embodiment〕 The solid-state imaging device according to the second embodiment includes a photoelectric conversion cell 22B shown in FIG. 8 instead of the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment. The photoelectric conversion cell 22B shown in FIG. 8 of the second embodiment basically has the same configuration as the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment, but the planar pattern is different.

[0086] That is, as described above, the photoelectric conversion cell 22A of the first embodiment shown in FIG. 4 has a planar pattern including element formation regions 21a, 21b1, and 21b2 partitioned by the element isolation region 33, and one power supply region 21z partitioned by the element isolation region 33. Pixel transistors Qt are provided at each of one end side (the first photoelectric conversion region 23L side) and the other end side (the second photoelectric conversion region 23R side) of the element formation region 21a, and transfer transistors TR1, TR2 and charge holding regions FD1, FD2 are provided in each of the element formation regions 21b1 and 21b2. The power supply region 21z is disposed between the two intra-pixel isolation regions 32 in plan view, and a contact region 48 shared by the first and second photoelectric conversion regions 23L and 23R is provided in this power supply region 21z.

[0087] In contrast, as shown in FIG. 8, the photoelectric conversion cell 22B of the second embodiment has a planar pattern including one element formation region 21c partitioned by the element isolation region 33 and extending across the first and second photoelectric conversion regions 23L and 23R, and two power supply regions 21z partitioned by the element isolation region 33 and disposed in each of the first and second photoelectric conversion regions 23L and 23R. Transfer transistors TR1, TR2 and charge holding regions FD1, FD2 of each of the first and second photoelectric conversion regions 23L and 23R, and two pixel transistors Qt are provided in this one element formation region 21c. P-type contact regions 48 are provided in each of the two power supply regions 21z.

[0088] As shown in FIG. 8, the element formation region 21c extends across the first and second photoelectric conversion regions 23L and 23R, and includes a first portion 21c1 that crosses between the two pixel internal separation regions 32 in plan view, and a pair of second portions 21c2 that protrude from one end side and the other end side in the X direction of the first portion 21c1 toward one of the two pixel separation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22B interposed therebetween (the side of the pixel separation region 31a). Further, the element formation region 21c further includes a pair of third portions 21c3 that protrude from one end side and the other end side in the X direction of the first portion 21c1 toward the other of the two pixel separation regions 31 that extend in the X direction with the photoelectric conversion cell 22B interposed therebetween (the side of the pixel separation region 31b). The pair of second portions 21c2 are arranged on both sides of the pixel internal separation region 32 on one side (the side of the pixel separation region 31a) among the two pixel internal separation regions 32 in plan view. The pair of third portions 21c3 are arranged on both sides of the pixel internal separation region 32 on the other side (the side of the pixel separation region 31b) among the two pixel internal separation regions 32 in plan view. That is, the element formation region 21c of this second embodiment has an H-shaped planar pattern in which the element formation regions 21a, 21b1, and 21b2 of the first embodiment shown in FIG. 4 are integrated when viewed from a different perspective.

[0089] Although not shown in detail, the element formation region 21c is provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21, similarly to the element formation regions 21a and 21b1, 21b2 of the first embodiment shown in FIGS. 5 to 7, and overlaps with each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R via the p-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21.

[0090] As shown in FIG. 8, in the two power supply regions 21z, one power supply region 21z (the side of the first photoelectric conversion region 23L) is arranged between one of the pair of second portions 21c2 of the element formation region 21c (the second portion 21c2 on the side of the first photoelectric conversion region 23L) and the pixel separation region 31 (31a). The other power supply region 21z (the side of the second photoelectric conversion region 23R) is arranged between the other of the pair of second portions 21c2 of the element formation region 21c (the second portion 21c2 on the side of the second photoelectric conversion region 23R) and the pixel separation region 31 (31a).

[0091] In the two pixel transistors Qt, one of the pixel transistors Qt (on the side of the first photoelectric conversion region 23L) is arranged across the first portion 21c1 and one of the second portions 21c2 of the element formation region 21c. The other pixel transistor Qt (on the side of the second photoelectric conversion region 23R) is arranged across the first portion 21c1 and the other second portion 21c2 of the element formation region 21c.

[0092] In the two charge holding regions FD1 and FD2, one of the charge holding regions FD1 (on the side of the first photoelectric conversion region 23L) is arranged at the tip of one of the third portions 21c3 of the element formation region 21c. The other charge holding region FD2 (on the side of the second photoelectric conversion region 23R) is arranged at the tip of the other third portion 21c3 of the element formation region 21c.

[0093] In the two transfer transistors TR1 and TR2, one of the transfer transistors TR1 (on the side of the first photoelectric conversion region 23L) is arranged across the first portion 21c1 and one of the third portions 21c3 of the element formation region 21c. The other pixel transistor Qt2 (on the side of the second photoelectric conversion region 23R) is arranged across the first portion 21c1 and the other third portion 21c3 of the element formation region 21c.

[0094] Also in the photoelectric conversion cell 22B of this second embodiment, the element formation region 21c extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the two pixel internal separation regions 32 in plan view. Therefore, also in the solid-state imaging device according to this second embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.

[0095] Further, since the transfer transistors TR1 and TR2 and the charge holding regions FD1 and FD2 are not separated by the element isolation region 33, in other words, since the element isolation region 33 is not provided between the transfer transistors TR1 and TR2 and the charge holding regions FD1 and FD2, the transfer of signal charges by the transfer transistors TR1 and TR2 becomes easier.

[0096] Further, in the photoelectric conversion cell 22B of this second embodiment, the transfer transistor TR1 and the charge holding region FD1 of the first photoelectric conversion region 23L and the transfer transistor TR2 and the charge holding region FD2 of the second photoelectric conversion region 23R are arranged in one element formation region 21c partitioned by the element isolation region 33. Therefore, compared with the photoelectric conversion cell 22A of the above-described first embodiment, the degree of freedom in arranging active elements in the photoelectric conversion cell 22A can be further increased.

[0097] Note that, also in the photoelectric conversion cell 22B of this second embodiment, the portion between the two intra-pixel isolation regions 32 functions as an overflow path.

[0098] Also, in the photoelectric conversion cell 22B of this second embodiment, similar to the photoelectric conversion cell 22A of the above-described first embodiment, it includes a p-type semiconductor region 24, a photoelectric conversion section 25, and an n-type semiconductor region 26 shown in FIGS. 4 to 7.

[0099] 〔Third Embodiment〕 The solid-state imaging device according to this third embodiment includes a photoelectric conversion cell 22C shown in FIG. 9 instead of the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment. The photoelectric conversion cell 22C of the third embodiment shown in FIG. 9 basically has the same configuration as the photoelectric conversion cell 22A of the first embodiment, but the planar pattern is different.

[0100] That is, as shown in FIG. 9, in the two second portions 21a2 of the element formation region 21a partitioned by the element isolation region 33 in the photoelectric conversion cell 22C according to this third embodiment, the length in the Y direction of one second portion 21a2 is shorter than the length in the Y direction of the other second portion 21a2. And, in a plan view, a power supply region 21z partitioned by the element isolation region 33 is provided between this one second portion 21a2 and one pixel isolation region 31a of the two pixel isolation regions 31 extending in the X direction with the photoelectric conversion cell 22C interposed therebetween. And a p-type contact region 48 is provided in this power supply region 21z.

[0101] In addition, in the photoelectric conversion cell 22C according to this third embodiment, each of the two element formation regions 21b1 and 21b2 has a rectangular planar pattern. In the first photoelectric conversion region 23L, a charge holding region FD1 is provided on the pixel isolation region 31b side of the element formation region 21b1, and a transfer transistor TR1 is provided on the pixel isolation region 31c side of the element formation region 21b1. In the second photoelectric conversion region 23R, a charge holding region FD2 is provided on the pixel isolation region 31b side of the element formation region 21b2, and a transfer transistor TR2 is provided on the pixel isolation region 31d side of the element formation region 21b2.

[0102] Also in the photoelectric conversion cell 22C according to this third embodiment, the element formation region 21a extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the two intra-pixel isolation regions 32 in a plan view. Therefore, also in the solid-state imaging device according to this third embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.

[0103] In addition, in the photoelectric conversion cell 22C according to this third embodiment, a p-type contact region 48 is provided only in the first photoelectric conversion region 23L. For this reason, the gate area (gate length Lg × gate width Wg) of the pixel transistor Qt in the second photoelectric conversion region 23R can be made larger than the gate area of the pixel transistor Qt in the first photoelectric conversion region 23L, and it becomes possible to reduce noise. The reduction of noise in this pixel transistor Qt is particularly useful when the pixel transistor Qt having a larger gate area is used as the amplification transistor included in the readout circuit.

[0104] Note that also in the photoelectric conversion cell 22C of this third embodiment, the region between the two intra-pixel isolation regions 32 functions as an overflow path.

[0105] In addition, also in the photoelectric conversion cell 22C of this third embodiment, similar to the photoelectric conversion cell 22A of the above-described first embodiment, it includes a p-type semiconductor region 24, a photoelectric conversion section 25, and an n-type semiconductor region 26 shown in FIGS. 4 to 7.

[0106] Also, in this third embodiment, the case where the length in the Y direction of the second portion 21a2 on the side of the first photoelectric conversion region 23L is shorter than the length in the Y direction of the second portion 21a2 on the side of the second photoelectric conversion region 23R in the pair of second portions 21a2 of the element formation region 21a has been described. However, the present technology is not limited to this third embodiment. For example, in the pair of second portions 21a2 of the element formation region 21a, the length in the Y direction of the second portion 21a2 on the side of the second photoelectric conversion region 23R may be shorter than the length in the Y direction of the second portion 21a2 on the side of the first photoelectric conversion region 23L. In this case, the power supply region 21z and the contact region 48 are arranged between the second portion 21a2 having the shorter length in the Y direction in plan view and the pixel isolation region 31a. In short, the length in the Y direction of either one of the pair of second portions 21a2 of the element formation region 21a is made shorter than the length in the Y direction of the other second portion 21a2, and the contact region 48 shared by the first and second photoelectric conversion regions 23L and 23R is arranged between the second portion 21a2 having the shorter length in the Y direction and the pixel isolation region 31a.

[0107] 〔Fourth Embodiment〕 The solid-state imaging device according to this fourth embodiment includes a photoelectric conversion cell 22D shown in FIG. 10 instead of the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment. The photoelectric conversion cell 22D of the fourth embodiment shown in FIG. 10 basically has the same configuration as the photoelectric conversion cell 22A of the first embodiment shown in FIG. 4, and the planar pattern and the configuration of the in-pixel isolation region are different.

[0108] That is, as shown in FIG. 10, the photoelectric conversion cell 22D of this fourth embodiment is partitioned by the element isolation region 33 and has an element formation region 21d and 21e disposed across the first and second photoelectric conversion regions 23L and 23R, and two power supply regions 21z partitioned by the element isolation region 33 and disposed in each of the first and second photoelectric conversion regions 23L and 23R, forming a planar pattern. Two pixel transistors Qt are provided in the element formation region 21d. Two transfer transistors TR1 and TR2 and one charge holding region FD are provided in the element formation region 21e. P-type contact regions 48 are provided in each of the two power supply regions 21z.

[0109] Also, as shown in FIG. 10, the photoelectric conversion cell 22D of this fourth embodiment includes a pixel internal separation region 34 instead of the pixel internal separation region 32 of the first embodiment shown in FIG. 4 as a second separation region disposed between the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and extending in the thickness direction of the semiconductor layer 21.

[0110] As shown in FIG. 10, the pixel internal separation region 34 is disposed between the first photoelectric conversion region 23L and the second photoelectric conversion region 23R in a plan view and is separated from each of the two pixel separation regions 31a and 31b extending in the X direction with the photoelectric conversion cell 22D interposed therebetween. That is, in the photoelectric conversion cell 22D of this fourth embodiment, the first photoelectric conversion region 23L and the second photoelectric conversion region 23Lb adjacent to each other in the X direction are selectively partitioned by the pixel internal separation region 34 separated from each of the two pixel separation regions 31a and 31b extending in the X direction.

[0111] Although not shown in detail, the pixel internal separation region 34, referring to FIGS. 5 to 7 of the first embodiment described above, is similar to the pixel internal separation region 32 of the first embodiment. For example, an insulating film is embedded in a groove extending from the second surface S2 of the semiconductor layer 21 toward the first surface S1 side, and has a trench separation structure integrated with the element isolation region 33 on the first surface S1 side of the semiconductor layer 21.

[0112] As shown in FIG. 10, the element formation region 21d is disposed on one of the two pixel isolation regions 31a and 31b that extend in the X direction across the photoelectric conversion cell 22D in plan view, on the side of the pixel isolation region 31a, rather than the element formation region 21e. And the element formation region 21e is disposed on the side of the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b that extend in the X direction across the photoelectric conversion cell 22D in plan view, rather than the element formation region 21d. Although not shown in detail, each of the element formation regions 21d and 21e is provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21, similar to the element formation regions 21a and 21b1, 21b2 of the first embodiment shown in FIGS. 5 to 7, and in the thickness direction (Z direction) of the semiconductor layer 21, it overlaps with each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R via the p-type semiconductor region 24.

[0113] As shown in FIG. 10, the element formation region 21d extends in the X direction across the first and second photoelectric conversion regions 23L and 23R, and includes a first portion 21d1 that crosses between the in-pixel isolation region 34 and one of the two pixel isolation regions 31a and 31b that extend in the X direction in plan view, and a pair of second portions 21d2 that protrude from each of the one end side and the other end side in the X direction of the first portion 21d1 to the side opposite to the one pixel isolation region 31a side, in other words, to the element formation region 21e side. And each of the pair of second portions 21d2 is disposed via the element isolation region 33 on both sides of the in-pixel isolation region 34 in plan view. That is, the element formation region 21d has a U-shaped planar pattern in plan view with the side of the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b that extend in the X direction, in other words, the element formation region 21e side, open.

[0114] As shown in FIG. 10, two pixel transistors Qt are provided in the element formation region 21d. One of the two pixel transistors Qt is disposed at one of the two corners of the element formation region 21d. The other of the two pixel transistors Qt is disposed at the other corner of the two corners of the element formation region 21d. In other words, one pixel transistor Qt is disposed across the first portion 21d1 and one second portion 21d2 of the element formation region 21d. Further, the other pixel transistor Qt is disposed across the first portion 21d1 and the other second portion 21d2 of the element formation region 21d. That is, also in the photoelectric conversion cell 22A of this fourth embodiment, pixel transistors Qt are provided in each of the first and second photoelectric conversion regions 23L and 23L.

[0115] As shown in FIG. 10, the element formation region 21e extends across each of the first and second photoelectric conversion regions 23L and 23R, and in a plan view, a first portion 21e1 that crosses between the in-pixel separation region 34 and the other pixel separation region 31b of the two pixel separation regions 31a and 31b that extend in the X direction with the photoelectric conversion cell 22D interposed therebetween, and from each of one end side and the other end side in the X direction of this first portion 21e1, a pair of second portions 21e2 that protrude to the side opposite to the other pixel separation region 21b, in other words, to the element formation region 21d side. And each of the pair of second portions 21e2 is disposed via element separation regions 33 on both sides of the in-pixel separation region 34 in a plan view. That is, the element formation region 21e has an inverted U-shaped planar pattern in which the side of one pixel separation region 31 (31a) of the two pixel separation regions 31 that extend in the X direction, in other words, the side on the element formation region 21d side, is open in a plan view. And the pair of second portions 21e2 of the element formation region 21e are adjacent to the pair of second portions 21d2 of the element formation region 21d via the element separation regions 33 in a plan view.

[0116] As shown in FIG. 10, in the element formation region 21e, two transfer transistors Qt and one charge holding region FD are provided. Of the two transfer transistors Qt, one transfer transistor Qt is disposed in the first photoelectric conversion region 23L, and the other transfer transistor Qt is disposed in the second photoelectric conversion region 23R.

[0117] One of the transfer transistors Qt (in the first photoelectric conversion region 23L) is disposed on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b extending in the X direction with the photoelectric conversion cell 22D therebetween and one of the pixel isolation regions 31c and 31d extending in the Y direction with the photoelectric conversion cell 22D therebetween. And between this corner and one transfer transistor Qt, one of the two power supply regions 21z is disposed. And a p-type contact region 48 is provided in this one power supply region 21z.

[0118] The other transfer transistor Qt (in the second photoelectric conversion region 23R) is disposed on the corner side formed by the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b extending in the X direction with the photoelectric conversion cell 22D therebetween and the other pixel isolation region 31d of the two pixel isolation regions 31c and 31d extending in the Y direction with the photoelectric conversion cell 22D therebetween. And between this corner and the other transfer transistor Qt, the other power supply region 21z of the two power supply regions is disposed. And a p-type contact region 48 is provided in this other power supply region 21z.

[0119] Although not shown in detail, in the photoelectric conversion cell 22D of this fourth embodiment as well, similar to the photoelectric conversion cell 22A of the first embodiment shown in FIGS. 4 to 7, a p-type semiconductor region 24 is provided across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R. And, the p-type semiconductor region of this fourth embodiment, unlike the p-type semiconductor region 24 of the above-described first embodiment, crosses between each of the two pixel isolation regions 31a and 31b extending in the X direction across the photoelectric conversion cell 22D and the in-pixel isolation region 34. And, the contact region (p-type semiconductor region) 48 of each of the two power supply regions 21z is provided in the p-type semiconductor region 24 on the first surface S1 side of the semiconductor layer.

[0120] As shown in FIG. 10, the n-type charge holding region FD is in the first portion 21e1 of the element formation region 21e, and is provided between the other pixel isolation region 31b of the two pixel isolation regions 31a and 31b extending in the X direction across the photoelectric conversion cell 22 and the in-pixel isolation region 34. This n-type charge holding region FD is shared by each of the first and second photoelectric conversion regions 23L and 23R. And, this charge holding region FD functions as the drain region of the transfer transistors TR1 and TR2 of each of the first and second photoelectric conversion regions 23L and 23R, and holds the signal charges transferred from each of the photoelectric conversion units 25 (see FIG. 5 of the first embodiment) through the respective transfer transistors TR1 and TR2. And, in the photoelectric conversion cell 22D of this fourth embodiment, the space between each of the two pixel isolation regions 31 (31a, 31b) extending in the X direction and the in-pixel isolation region 34 functions as an overflow path.

[0121] Similar to the photoelectric conversion cell 22A of the first embodiment described above, in the photoelectric conversion cell 22D of this fourth embodiment, the element formation region 21d extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the pixel isolation region 31 (31a, 31b) and the in-pixel isolation region 34 in plan view. Therefore, also in the solid-state imaging device according to this fourth embodiment, the same effects as those of the solid-state imaging device 1A according to the first embodiment described above can be obtained.

[0122] Further, the photoelectric conversion cell 22D of this fourth embodiment shares one n-type charge holding region FD between the first photoelectric conversion region 23L and the second photoelectric conversion region 23R. And this n-type charge holding region FD is arranged between the pixel separation region 31(31b) and the in-pixel separation region 34 in plan view. Therefore, the photoelectric conversion cell 22D of this fourth embodiment can increase the degree of freedom in arranging active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 as compared with the case where an n-type charge accumulation region FD is arranged in each of the first and second photoelectric conversion regions 23L and 23R.

[0123] Also, since the photoelectric conversion cell 22D of this fourth embodiment employs a combination of the arrangement of the element formation region 21d and the arrangement of the charge holding region FD, the degree of freedom in arranging the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 can be further increased as compared with the case where either one of the arrangement of the element formation region 21d and the arrangement of the charge holding region FD is adopted.

[0124] Note that in the photoelectric conversion cell 22D of this fourth embodiment, the region between the in-pixel separation region 34 and the pixel separation region 31(31a, 31b) functions as an overflow path.

[0125] Also, in the photoelectric conversion cell 22D of this fourth embodiment as well, similar to the photoelectric conversion cell 22A of the first embodiment described above, it includes a p-type semiconductor region 24, a photoelectric conversion section 25, and an n-type semiconductor region 26 shown in FIGS. 4 to 7.

[0126] 〔Fifth Embodiment〕 The solid-state imaging device according to this fifth embodiment basically has the same configuration as the solid-state imaging device according to the fourth embodiment described above, but the planar pattern of the photoelectric conversion cell is different.

[0127] That is, the solid-state imaging device according to the fifth embodiment includes a photoelectric conversion cell 22E shown in FIG. 11 instead of the photoelectric conversion cell 22D shown in FIG. 10 of the fourth embodiment described above. The photoelectric conversion cell 22E shown in FIG. 10 of this fifth embodiment basically has the same configuration as the photoelectric conversion cell 22D shown in FIG. 10 of the fourth embodiment described above, but the planar pattern is different.

[0128] That is, as shown in FIG. 11, the photoelectric conversion cell 22E of this fifth embodiment has a planar pattern including two element formation regions 21f partitioned by an element isolation region 33 and arranged separately in each of the first and second photoelectric conversion regions 23L and 23R, and an element formation region 21e partitioned by the element isolation region 33 and arranged across each of the first and second photoelectric conversion regions 23L and 23R. Further, the photoelectric conversion cell 22E of this fifth embodiment has a planar pattern including a power supply region 21z arranged between one of the two pixel isolation regions 31 (31a, 31b) extending in the X direction with the photoelectric conversion cell 22E interposed therebetween and the in-pixel isolation region 34. Pixel transistors Qt are provided in each of the two element formation regions 21f. A p-type contact region (p-type semiconductor region) 48 is provided in the power supply region 21z.

[0129] As shown in FIG. 11, each of the two element formation regions 21f extends in the Y direction in a plan view and is arranged adjacent to each other with the in-pixel isolation region 34 and the power supply region 21z interposed therebetween. The pixel transistors Qt are provided in each of the two element formation regions 21f with the source region and the drain region arranged in the Y direction.

[0130] As shown in FIG. 11, the element formation region 21e of this fifth embodiment has a slightly different planar pattern from the element formation region 21e of the above-described fourth embodiment shown in FIG. 10. Similar to the element formation region 21e shown in FIG. 10, it includes a first portion 21e1 and a pair of second portions 21e2. Also, in the element formation region 21e of this fifth embodiment, two transfer transistors TR1 and TR2 and one charge holding region FD are provided in the same arrangement as in the element formation region 21e of the fourth embodiment shown in FIG. 10.

[0131] As shown in FIG. 11, different from the contact region 48 shown in FIG. 10 of the above-described fourth embodiment, the contact region 48 of this fifth embodiment is disposed between one of the two pixel isolation regions 31 (31a, 31b) extending in the X direction with the photoelectric conversion cell 22E interposed therebetween in plan view and the in-pixel isolation region 34, and is shared by the first and second photoelectric conversion regions 23L and 23R.

[0132] Although not shown in detail, each of the element formation regions 21f and 21e is provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21, similar to the element formation regions 21a and 21b1, 21b2 of the first embodiment shown in FIGS. 5 to 7, and overlaps with each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R via a p-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21.

[0133] In the above-described fourth embodiment, as shown in FIG. 11, a power supply region 21z and a p-type contact region 48 are respectively disposed on the corner side formed by the pixel isolation region 31b and the pixel isolation region 31c and on the corner side formed by the pixel isolation region 31b and the pixel isolation region 31d in plan view. In contrast, in this fifth embodiment, the power supply region 21z and the contact region 48 are not disposed on each corner side, and the power supply region 21z and the contact region 48 shared by the first and second photoelectric conversion regions 23L and 23R are disposed between the in-pixel isolation region 34 and the pixel isolation region 31a.

[0134] The photoelectric conversion cell 22E according to this fifth embodiment, similar to the above-described fourth embodiment, arranges the n-type charge holding region FD shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R between the pixel separation region 31(31b) and the in-pixel separation region 34 in plan view. Therefore, compared with the case where an n-type charge accumulation region FD is arranged in each of the first and second photoelectric conversion regions 23L and 23R, the degree of freedom in arranging the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 can be increased.

[0135] Further, in the photoelectric conversion cell 22E of this fifth embodiment, the p-type contact region 48 shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R is arranged between the pixel separation region 31(31a) and the in-pixel separation region 34 in plan view. Therefore, compared with the case where a p-type contact region 48 is arranged in each of the first and second photoelectric conversion regions 23L and 23R, the degree of freedom in arranging the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 can be increased.

[0136] Moreover, since the photoelectric conversion cell 22E of this fifth embodiment employs a combination of both the arrangement of the n-type charge holding region FD and the arrangement of the p-type contact region 48, compared with the case of adopting either one of the arrangement of the n-type charge holding region FD and the arrangement of the p-type contact region 48, the freedom in arranging within the photoelectric conversion cell 22 of the active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 can be further increased.

[0137] Note that also in the photoelectric conversion cell 22E of this fifth embodiment, the region between the in-pixel separation region 34 and the pixel separation regions 31a and 31b functions as an overflow path.

[0138] Further, also in the photoelectric conversion cell 22E of this fifth embodiment, similar to the photoelectric conversion cell 22A of the above-described first embodiment, it includes the p-type semiconductor region 24, the photoelectric conversion section 25, and the n-type semiconductor region 26 shown in FIGS. 4 to 7.

[0139] 〔Embodiment 6〕 The solid-state imaging device according to this sixth embodiment includes a photoelectric conversion cell 22F shown in FIG. 12 instead of the photoelectric conversion cell 2D of the fourth embodiment shown in FIG. 10. The photoelectric conversion cell 22F of the sixth embodiment shown in FIG. 12 basically has the same configuration as the photoelectric conversion cell 22D according to the fourth embodiment shown in FIG. 10, but has a different planar pattern.

[0140] That is, the photoelectric conversion cell 22D of the fourth embodiment shown in FIG. 10 has a planar pattern in which a power supply region 21z and a p-type contact region 48 are arranged at each of the two corner portions on the pixel separation region 31 (31b) side in a plan view.

[0141] On the other hand, as shown in FIG. 12, in the photoelectric conversion cell 22F of this sixth embodiment, power supply regions 21z partitioned by element separation regions 33 are provided in each of the first and second photoelectric conversion regions 23L and 23R with the in-pixel separation region 34 interposed therebetween in a plan view. And a p-type contact region 48 is provided in each of these two power supply regions 21z.

[0142] Of the two p-type contact regions 48, one p-type contact region 48 (on the first photoelectric conversion region 23L side) is disposed between one second portion 21d2 of the element formation region 21d and one second portion 21e2 of the element formation region 21e in the first photoelectric conversion region 23L in a plan view. Also, the other p-type contact region 48 (on the second photoelectric conversion region 23R side) is disposed between the other second portion 21d2 of the element formation region 21d and the other second portion 21e2 of the element formation region 21e in the second photoelectric conversion region 23R in a plan view.

[0143] Similar to the above-described fourth embodiment, in the photoelectric conversion cell 22F of this sixth embodiment, the element formation region 21d extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and crosses between the pixel separation region 31 (31a, 31b) and the in-pixel separation region 34 in a plan view.

[0144] Also, similar to the fourth embodiment described above, in the photoelectric conversion cell 22F of this sixth embodiment, the n-type charge holding region FD shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R is disposed between the pixel isolation region 31(31b) and the in-pixel isolation region 34 in plan view.

[0145] And also in the photoelectric conversion cell 22F of this sixth embodiment, both the arrangement of the element formation region 21d and the arrangement of the charge holding region FD are adopted in combination.

[0146] Therefore, also in the photoelectric conversion cell 22F of this sixth embodiment, the same effects as those of the photoelectric conversion cell 22D of the fourth embodiment described above can be obtained.

[0147] Note that also in the photoelectric conversion cell 22F of this sixth embodiment, the region between the in-pixel isolation region 34 and the pixel isolation region 31(31a, 31b) functions as an overflow path.

[0148] Also, similar to the photoelectric conversion cell 22A of the first embodiment described above, the photoelectric conversion cell 22F of this sixth embodiment includes a p-type semiconductor region 24, a photoelectric conversion section 25, and an n-type semiconductor region 26 shown in FIGS. 4 to 7.

[0149] 〔Seventh Embodiment〕 The solid-state imaging device according to this seventh embodiment includes a photoelectric conversion cell 22G shown in FIG. 13 instead of the photoelectric conversion cell 22F of the sixth embodiment shown in FIG. 12. The photoelectric conversion cell 22G of the seventh embodiment shown in FIG. 13 basically has the same configuration as the photoelectric conversion cell 22F of the sixth embodiment shown in FIG. 12, but the planar pattern is different.

[0150] That is, as shown in FIG. 13, in the photoelectric conversion cell 22G according to the seventh embodiment, in a pair of second portions 21d2 of the element formation region 21d partitioned by the element isolation region 33, the length in the Y direction of the second portion 21a2 on the other side (the second photoelectric conversion region 23R side) is longer than the length in the Y direction of the second portion 21a2 on one side (the first photoelectric conversion region 23L side). And in plan view, a power supply region 21z partitioned by the element isolation region 33 is provided between one second portion 21a2 and one of the pair of second portions 21e2 of the element formation region 21e. And a p-type contact region 48 is provided in this power supply region 21z.

[0151] Further, in the photoelectric conversion cell 22G according to the seventh embodiment, the gate area of the pixel transistor Qt disposed at the corner on the second photoelectric conversion region 23R side of the element formation region 22d is larger than the gate area of the pixel transistor Qt disposed at the corner on the first photoelectric conversion region 23L side of the element formation region 22d.

[0152] Also in the photoelectric conversion cell 22G according to the seventh embodiment, the element formation region 21d extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and in plan view, it crosses between the pixel isolation region 31(31a) and the intra-pixel isolation region 34. Therefore, also in the photoelectric conversion cell 22G of this seventh embodiment, the same effects as those of the photoelectric conversion cell 22F of the above-described sixth embodiment can be obtained.

[0153] 〔Eighth Embodiment〕 The solid-state imaging device according to this eighth embodiment includes the photoelectric conversion cell 22H shown in FIG. 14. The photoelectric conversion cell 22H of this eighth embodiment basically has the same configuration as the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment, but the planar pattern is different. That is, as shown in FIG. 14, the photoelectric conversion cell 22H of this eighth embodiment includes two element formation regions 21b1 and 21b2 and one power supply region 21z shown in FIG. 4, and further includes two element formation regions 21f shown in FIG. 11 instead of the element formation region 21a shown in FIG. 4. And a p-type contact region 48 is provided in the power supply region 21z. That is, the photoelectric conversion cell 22H of this eighth embodiment includes five semiconductor regions partitioned by the element isolation region 33. Specifically, the five semiconductor regions include two p-type semiconductor regions 24 and 24, two pairs of main electrode regions (n-type semiconductor regions) 46 and 47, and one p-type contact region (p-type semiconductor region) 48. In other words, the five semiconductor regions include a first semiconductor region (p-type semiconductor region 24) provided with a first transfer transistor (transfer transistor TR1) and a second semiconductor region (p-type semiconductor region 24) provided with a second transfer transistor (transfer transistor TR2). Further, the five semiconductor regions include a third semiconductor region (a pair of main electrode regions (n-type semiconductor regions) 46 and 47) provided with a first pixel transistor (pixel transistor Qt) other than the first and second transfer transistors (transfer transistors TR1 and TR2), a fourth semiconductor region (a pair of main electrode regions (n-type semiconductor regions) 46 and 47) provided with a second pixel transistor (pixel transistor Qt) other than the first and second transfer transistors (transfer transistors TR1 and TR2), and a p-type semiconductor region (p-type contact region 48).

[0154] As shown in FIG. 14, the power supply region 21z and the contact region 48 of this eighth embodiment are arranged between two intra-pixel isolation regions 32 in a plan view, and the length in the Y direction is longer than that of the power supply region 21z and the p-type contact region 48 of the first embodiment shown in FIG. 4. The two element formation regions 21f of this eighth embodiment are individually arranged in the first and second photoelectric conversion regions 23L and 23R adjacent to each other in the X direction with the power supply region 21z, the contact region 48, and the intra-pixel isolation region 32 on the pixel isolation region 31a side interposed therebetween. Further, the two element formation regions 21b1 and 21b2 of this eighth embodiment are individually arranged in the first and second photoelectric conversion regions 23L and 23R adjacent to each other in the X direction with the power supply region 21z, the contact region 48, and the intra-pixel isolation region 32 on the pixel isolation region 31b side interposed therebetween. Also in the photoelectric conversion cell 22H of this eighth embodiment, similarly to the first embodiment described above, since the p-type contact region 48 shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R is disposed between the two pixel internal separation regions 32 in plan view, the degree of freedom in arranging active elements including the pixel transistor Qt and the transfer transistors TR1 and TR2 within the photoelectric conversion cell 22 can be increased as compared with the case where the contact region 48 is separately disposed in each of the first and second photoelectric conversion regions 23L and 23R.

[0155] Note that when the solid-state imaging device according to this eighth embodiment is described from a different perspective (way of viewing), with reference to FIGS. 14 and 5 to 7, it includes the following configuration. That is, the solid-state imaging device according to this eighth embodiment includes a trench including a first pixel (pixel 3) provided in a semiconductor layer 21 as a semiconductor substrate, and a first region (a pixel separation region 31 having a quadrangular shape in plan view) that separates the first pixel from another pixel 3 adjacent to the first pixel in plan view, and a second region (a pixel internal separation region 32 within the pixel) where the photoelectric conversion unit 25 provided in the first pixel is blocked in plan view. Here, the trench extends in the thickness direction of the semiconductor layer 21 shown in FIGS. 5 to 7 and includes a configuration that penetrates across the first surface S1 and the second surface S2 of the semiconductor layer 21, and a configuration that extends in the thickness direction of the semiconductor layer 21 and is separated from at least one of the first surface S1 and the second surface S2 of the semiconductor layer 21. In this eighth embodiment, the trench is not limited to this, but for example, penetrates the semiconductor layer 21. In plan view, the second region has a first portion (one pixel internal separation region 32) between a first floating diffusion region (charge holding region FD1) provided in the first pixel (pixel 3) and a second floating diffusion region (charge holding region FD2). Also, in plan view, the second region has a second portion (the other pixel internal separation region 32) between a first transistor (one pixel transistor Qt) and a second transistor (the other pixel transistor Qt) provided in the first pixel (pixel 3). And a first portion of the second region (one intra-pixel isolation region 32) in plan view, and a second portion of the second region (a p-type contact region 48 is provided between the intra-pixel isolation region 32). In plan view, the first portion of the second region (one intra-pixel isolation region 32), the contact region 48, and the second portion of the second region (the other intra-pixel isolation region 32) are arranged in this order along the Y direction (the first direction). One main electrode region (the first contact) 46 of the first transistor (one pixel transistor Qt), the gate electrode 45, and the other main electrode region (the second contact) 47 are arranged in this order along the Y direction (the first direction). One main electrode region (the third contact) 46 of the second transistor (the other pixel transistor Qt), the gate electrode 45, and the other main electrode region (the fourth contact) 47 are arranged in this order along the Y direction (the first direction). The contact region 48 is provided at the center of the pixel 3 and is composed of a p-type semiconductor region (impurity region).

[0156] When changing the expression (viewpoint) further, the solid-state imaging device according to this eighth embodiment has a first pixel (pixel 3) provided on a semiconductor substrate and a separation region that separates the first pixel and other pixels 3 adjacent to each other in plan view. The separation region includes a first portion (pixel separation region 31a) and a second portion (pixel separation region 31b) located on opposite sides of each other in the Y direction in plan view, a third portion (pixel separation region 31a) and a fourth portion (pixel separation region 31b) located on opposite sides of each other in the X direction, and a fifth portion (one intra-pixel isolation region 32) and a sixth portion (the other intra-pixel isolation region 32) provided between the first portion (pixel separation region 31a) and the second portion (pixel separation region 31b) in plan view. The first portion (pixel separation region 31a) and the second portion (pixel separation region 31b) face each other, and the third portion (pixel separation region 31c) and the fourth portion (pixel separation region 31d) face each other. And in plan view, the first pixel (pixel 3) is surrounded by the first to fourth portions (pixel separation regions 31a to 31d) of the separation region. And a p-type contact region 48 is provided between the fifth portion (one intra-pixel isolation region 32) and the sixth portion (the other intra-pixel isolation region 32) in plan view. And the fifth portion (one intra-pixel isolation region 32) is in contact with the first portion (pixel isolation region 31a), and the sixth portion (the other intra-pixel isolation region 32) is in contact with the second portion (pixel isolation region 31b). The angle formed by the first portion (pixel isolation region 31a) and the fifth portion (one intra-pixel isolation region 32) in plan view is perpendicular, and the angle formed by the second portion (pixel isolation region 31b) and the sixth portion (the other intra-pixel isolation region 32) in plan view is also perpendicular. In other words, in plan view, the fifth portion (one intra-pixel isolation region 32) protrudes perpendicularly to the first portion (pixel isolation region 31a), and the sixth portion (the other intra-pixel isolation region 32) protrudes perpendicularly to the second portion (pixel isolation region 31a). These fifth portion (one intra-pixel isolation region 32) and sixth portion (the other intra-pixel isolation region 32) function as "protrusions" or "convex portions" and can be expressed as "protrusions" or "convex portions". In plan view, the fifth portion (one intra-pixel isolation region 32), the contact region 48, and the sixth portion (the other intra-pixel isolation region 32) are arranged in this order along the Y direction (the first direction). The first contact (main electrode region 4646) of the first transistor (one pixel transistor Qt), the gate electrode 45, and the second contact (main electrode region 47) are arranged in this order along the Y direction (the first direction). In plan view, the third contact (main electrode region 46) of the second transistor (the other pixel transistor Qt), the gate electrode 45, and the fourth contact (main electrode region 47) are arranged in this order along the Y direction (the first direction). The contact region 48 is provided at the center of pixel 3 and is composed of a p-type semiconductor region (impurity region).

[0157] 〔Embodiment 9〕 The solid-state imaging device according to this ninth embodiment includes a photoelectric conversion cell 22I shown in FIG. 15 instead of the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment. The photoelectric conversion cell 22I of the ninth embodiment shown in FIG. 15 basically has the same configuration as the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment, but the planar pattern is different.

[0158] That is, as shown in FIG. 15, the photoelectric conversion cell 22I of this ninth embodiment includes two element formation regions 21b1 and 21b2 shown in FIG. 4 and two power supply regions 21z shown in FIG. 8 of the above-described second embodiment instead of the power supply region 21z of the first embodiment shown in FIG. 4. Further, the photoelectric conversion cell 22I of this ninth embodiment includes an element formation region 21g partitioned by an element isolation region 33 as shown in FIG. 15 instead of the element formation region 21a shown in FIG. 4. And a p-type contact region 48 is provided in each of the two power supply regions 21z.

[0159] As shown in FIG. 15, the two element formation regions 21b1 and 21b2 of this ninth embodiment are arranged adjacent to each other in the X direction with the in-pixel isolation region 32 on the pixel isolation region 31b side interposed therebetween, and are individually arranged in the first and second photoelectric conversion regions 23L and 23R, similarly to the above-described first embodiment. Further, the two power supply regions 21z of this ninth embodiment are arranged adjacent to each other in the X direction with the in-pixel isolation region 32 on the pixel isolation region 31a side interposed therebetween, and are individually arranged in the first and second photoelectric conversion regions 23L and 23R, similarly to the above-described second embodiment.

[0160] As shown in FIG. 15, the element formation region 21g is arranged in a plan view between the element formation region 21b1 of the first photoelectric conversion region 23L and the power supply region 21z, between the two in-pixel isolation regions 32, and between the element formation region 21b1 of the second photoelectric conversion region 22R and the power supply region 21z. And one pixel transistor Qt is provided in the element formation region 21g. The pixel transistor Qt has a gate electrode 45 crossing the two in-pixel isolation regions 32 in a plan view, one main electrode region 47 provided on the first photoelectric conversion region 23L side of the element formation region 21g, and the other main electrode region 47 provided on the second photoelectric conversion region 23R side of the element formation region 21g.

[0161] In the photoelectric conversion cell 22I of the ninth embodiment as well, similar to the photoelectric conversion cell 22A of the first embodiment, the element formation region 21g extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and crosses between the in-pixel separation regions 32 in plan view. Therefore, also in the solid-state imaging device according to this ninth embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described first embodiment can be obtained.

[0162] 〔Tenth Embodiment〕 The solid-state imaging device according to this tenth embodiment includes a photoelectric conversion cell 22J shown in FIG. 16 instead of the photoelectric conversion cell 22F shown in FIG. 12 of the sixth embodiment described above. The photoelectric conversion cell 22J of the tenth embodiment shown in FIG. 16 basically has the same configuration as the photoelectric conversion cell 22F of the sixth embodiment shown in FIG. 12, but the planar pattern is different.

[0163] That is, as shown in FIG. 16, the photoelectric conversion cell 22J of this tenth embodiment includes the element formation regions 21e and the two power supply regions 21z of the sixth embodiment shown in FIG. 12, and the element formation region 21g of the ninth embodiment shown in FIG. 15 instead of the element formation region 21d of the sixth embodiment shown in FIG. 12. The length in the Y direction of the pair of second portions 21e2 of the element formation region 21e of this tenth embodiment is longer than the length in the Y direction of the pair of second portions 21e2 of the element formation region 21e of the sixth embodiment. The two power supply regions 21z of this tenth embodiment are arranged closer to the pixel separation region 31a side than the two power supply regions 21z of the sixth embodiment in plan view. The element formation region 21g is arranged between the in-pixel separation region 34 and one of the two pixel separation regions 31 (31a) extending in the X direction.

[0164] The photoelectric conversion cell 22J of this tenth embodiment is similar to the sixth embodiment described above in that the element formation region 21g extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and crosses between the pixel separation region 31 (31a) and the in-pixel separation region 34 in plan view. Further, similar to the above-described sixth embodiment, the photoelectric conversion cell 22J of this tenth embodiment arranges the n-type charge holding region FD shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R between the pixel isolation region 31b and the in-pixel isolation region 34 in plan view. Also, in the photoelectric conversion cell 22J of this tenth embodiment, both the arrangement of the element formation region 21g and the arrangement of the charge holding region FD are adopted in combination. Therefore, also in the photoelectric conversion cell 22J of this tenth embodiment, the same effects as those of the photoelectric conversion cell 22F of the above-described sixth embodiment can be obtained.

[0165] 〔Eleventh Embodiment〕 The solid-state imaging device according to this eleventh embodiment includes a photoelectric conversion cell 22K shown in FIG. 17 instead of the photoelectric conversion cell 22G shown in FIG. 13 of the above-described seventh embodiment. The photoelectric conversion cell 22K of the eleventh embodiment shown in FIG. 17 basically has the same configuration as the photoelectric conversion cell 22G of the seventh embodiment shown in FIG. 13, but the planar pattern is different.

[0166] That is, as shown in FIG. 17, the photoelectric conversion cell 22K of this eleventh embodiment includes the element formation region 21e and the power supply region 21z of the seventh embodiment shown in FIG. 13, and instead of the element formation region 21d of the seventh embodiment shown in FIG. 13, an element formation region 21h partitioned by the element isolation region 33. And one pixel transistor Qt is provided in the element formation region 21h. And a p-type contact region 48 is provided in the power supply region 21z.

[0167] As shown in FIG. 17, the element formation region 21h of this 11th embodiment extends across the first and second photoelectric conversion regions 23L and 23R, and crosses between the pixel isolation region 31 (31a) and the in-pixel isolation region 34. The element formation region 21h includes a first portion 21h1 that crosses between the pixel isolation region 31a and the in-pixel isolation region 34 in plan view, and a second portion 21h2 that extends from either one of the one end side and the other end side of the first portion 21h1 toward the side opposite to the pixel isolation region 31a side, in other words, toward the element formation region 21e side. In this 11th embodiment, the second portion 21h2 extends from the other end side (the second photoelectric conversion region 23R side) of the first portion 21h1 toward the element formation region 21e side.

[0168] Although not shown in detail, the element formation region 21h is provided in the surface layer portion on the first surface S1 side of the semiconductor layer 21, similar to the element formation regions 21a and 21b1, 21b2 of the first embodiment shown in FIGS. 5 to 7, and overlaps with each photoelectric conversion portion 25 of the first and second photoelectric conversion regions 23L and 23R through the p-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21.

[0169] As shown in FIG. 17, in the pixel transistor Qt, the gate electrode 45 crosses between the pixel isolation region 31a and the in-pixel isolation region 34, one main electrode region 47 is provided on the first photoelectric conversion region 23L side of the element formation region 21h, and the other main electrode region 47 is provided on the second photoelectric conversion region 23R side of the element formation region 21h.

[0170] Similar to the above-described 7th embodiment, in the photoelectric conversion cell 22K of this 11th embodiment, the element formation region 21h extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the pixel isolation region 31 (31a) and the in-pixel isolation region 34 in plan view. Also, similar to the above-described 7th embodiment, in the photoelectric conversion cell 22K of this 11th embodiment, the n-type charge holding region FD shared by the first photoelectric conversion region 23L and the second photoelectric conversion region 23R is disposed between the pixel isolation region 31 (31b) and the in-pixel isolation region 34 in plan view. Also, in the photoelectric conversion cell 22K of the 11th embodiment, both the arrangement of the element formation region 21h and the arrangement of the charge holding region FD are adopted in combination. Therefore, also in the photoelectric conversion cell 22K of the 11th embodiment, the same effects as those of the photoelectric conversion cell 22G of the 7th embodiment described above can be obtained.

[0171] 〔12th Embodiment〕 The solid-state imaging device according to this 12th embodiment includes a photoelectric conversion cell 22L shown in FIG. 18. The photoelectric conversion cell 22L of the 12th embodiment shown in FIG. 18 basically has the same configuration as the photoelectric conversion cell 22G shown in FIG. 13 of the 7th embodiment described above, and the number of pixel transistors Qt provided in the element formation region 22d is different.

[0172] That is, the photoelectric conversion cell 22G shown in FIG. 13 of the 7th embodiment described above is provided with two pixel transistors Qt in the element formation region 21d. On the other hand, as shown in FIG. 18, in the photoelectric conversion cell 22L of this 12th embodiment, a pixel transistor Qt is arranged at one of the two corner portions of the element formation region 21d. In this 12th embodiment, the pixel transistor Qt is arranged at the corner portion on the second photoelectric conversion region 23R side of the element formation region 21d.

[0173] Also in the photoelectric conversion cell 22L of this 12th embodiment, the same effects as those of the photoelectric conversion cell 22G of the 7th embodiment described above can be obtained.

[0174] 〔13th Embodiment〕 In this 13th embodiment, a solid-state imaging device in which a readout circuit is provided for each pixel block (pixel unit) including four pixels will be described.

[0175] The solid-state imaging device 1B according to this 13th embodiment includes a pixel block (pixel unit) 61B and a readout circuit 15B shown in FIG. 19. As shown in FIGS. 19 and 20, the pixel block 61B includes a plurality of pixels 3. In this 13th embodiment, the pixel block 61B includes, but is not limited to, for example, four pixels 3 (3a, 3b, 3c, 3d) arranged in a 2×2 array of two each in the X and Y directions in plan view. FIGS. 19 and 20 mainly illustrate one pixel block 61B, but the pixel blocks 61B are repeatedly arranged in the X and Y directions respectively.

[0176] Among the four pixels 3 (3a, 3b, 3c, 3d), the pixel 3a includes the photoelectric conversion cell 22M1 shown in FIG. 21A. The pixel 3b includes the photoelectric conversion cell 22M2 shown in FIG. 21B. The pixel 3c includes the photoelectric conversion cell 22M3 shown in FIG. 21C. The pixel 3d includes the photoelectric conversion cell 22M4 shown in FIG. 22D. Each of the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4 basically has the same configuration as the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment, but the arrangement of the power supply region 21z is different. Further, in the photoelectric conversion cell 22M1, one reset transistor RST is arranged as the pixel transistor Qt in the element formation region 21a, and in each of the photoelectric conversion cells 22M2, 22M3, and 22M4, an amplification transistor AMP and a selection transistor SEL are arranged as the pixel transistor Qt in the element formation region 21a in the same manner as the photoelectric conversion cell 22A shown in FIG. 4 of the above-described first embodiment. That is, the photoelectric conversion cell 22M1 includes the reset transistor RST as an active element, and each of the photoelectric conversion cells 22M2, 22M3, and 22M4 includes the amplification transistor AMP and the selection transistor SEL as active elements. And these transistors (AMP, SEL, RST) have the same configuration as the pixel transistor Qt shown in FIG. 7 of the above-described first embodiment.

[0177] As shown in FIGS. 21A to 21D, in each of the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4, power supply regions 21z are arranged on the element formation regions 21b1 and 21b2 sides in plan view and on both corner sides. And a p-type contact region 48 is provided in each power supply region 21z. That is, in each of the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4, a power supply region 21z and a contact region 48 are arranged in each of the first photoelectric conversion region 23L and the second photoelectric conversion region 23R.

[0178] As shown in FIG. 21A, the photoelectric conversion cell 22M1 of the pixel 3a has, but is not limited to, for example, a reset transistor RST (Qt) arranged on the second photoelectric conversion region 23R side, and the arrangement of the pixel transistor is omitted on the first photoelectric conversion region 23L side. As shown in FIG. 22B, the photoelectric conversion cell 22M2 of the pixel 3b has, but is not limited to, for example, an amplification transistor AMP arranged on the first photoelectric conversion region 23L side, and a selection transistor SEL arranged on the second photoelectric conversion region 23R side. As shown in FIG. 22C, the photoelectric conversion cell 22M3 of the pixel 3c has, but is not limited to, for example, an amplification transistor AMP arranged on the first photoelectric conversion region 23L side, and a selection transistor SEL arranged on the second photoelectric conversion region 23R side. As shown in FIG. 22D, the photoelectric conversion cell 22M4 of the pixel 3d has, but is not limited to, for example, a selection transistor SEL arranged on the first photoelectric conversion region 23L side, and an amplification transistor AMP arranged on the second photoelectric conversion region 23R side.

[0179] That is, in the photoelectric conversion cells 22M2 and 22M3 and the photoelectric conversion cell 22M4, the amplification transistor AMP and the selection transistor SEL arranged in the first and second photoelectric conversion regions 23L and 23R are reversed.

[0180] <Orientation of the photoelectric conversion cell> As shown in FIG. 20, the photoelectric conversion cell 22M1 of pixel 3a and the photoelectric conversion cell 22M2 of pixel 3b are arranged such that the second photoelectric conversion region 23R of pixel 3a and the first photoelectric conversion region 23L of pixel 3b are adjacent to each other in the X direction. That is, the reset transistor RST of pixel 3a and the amplification transistor AMP of pixel 3b are adjacent to each other in the X direction. Also, as shown in FIG. 20, the photoelectric conversion cell 22M3 of pixel 3c and the photoelectric conversion cell 22M4 of pixel 3d are arranged such that the first photoelectric conversion region 23L of pixel 3c and the second photoelectric conversion region 23R of pixel 3d are adjacent to each other in the X direction. That is, the amplification transistor AMP of pixel 3c and the amplification transistor AMP of pixel 3d are adjacent to each other in the X direction. Further, the photoelectric conversion cell 22M1 of pixel 3a and the photoelectric conversion cell 22M3 of pixel 3c are arranged such that the first photoelectric conversion region 23L of pixel 3a and the second photoelectric conversion region 23R of pixel 3c are adjacent to each other in the Y direction, and the second photoelectric conversion region 23R of pixel 3a and the first photoelectric conversion region 23L of pixel 3c are adjacent to each other. That is, as shown in FIG. 23, the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3a and the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3c are adjacent to each other in the Y direction. Also, as shown in FIG. 20, the photoelectric conversion cell 22M2 of pixel 3b and the photoelectric conversion cell 22M4 of pixel 3d are arranged such that the first photoelectric conversion region 23L of pixel 3b and the second photoelectric conversion region 23R of pixel 3d are adjacent to each other in the Y direction, and the second photoelectric conversion 23R of pixel 3a and the first photoelectric conversion region 23L of pixel 3c are adjacent to each other. That is, as shown in FIG. 23, the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3b and the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3d are adjacent to each other in the Y direction via the pixel isolation region 31.

[0181] <Readout Circuit> As shown in FIG. 19, the input stage of the readout circuit 15B is connected to the charge holding regions FD1 and FD2 of each of the four pixels 3a, 3b, 3c, and 3d via the conductive path 63. The readout circuit 15B reads the signal charges held in the charge holding regions FD1 and FD2 of each of the four pixels 3a, 3b, 3c, and 3d, and outputs a pixel signal based on the signal charges. The readout circuit 15B is shared by the four pixels 3a, 3b, 3c, and 3d (eight photoelectric conversion regions) and provided for each pixel block 61B.

[0182] The readout circuit 15B includes, but is not limited to, a reset transistor RST and three amplification stage cells Pc1, Pc2, and Pc3. Each of the three amplification stage cells Pc1, Pc2, and Pc3 includes an amplification transistor AMP and a selection transistor SEL connected in series.

[0183] The readout circuit 15B is composed of pixel transistors Qt included in the circuit block 62B shown in FIG. 20. The circuit block 62B includes, but is not limited to, a reset transistor TST, an amplification transistor AMP, and a selection transistor SEL arranged in the pixels 3a and 3b of one pixel block 61B, and two amplification transistors AMP and two selection transistors SEL arranged in the pixels 3c and 3d of the other pixel block 61B in two pixel blocks 61B arranged adjacent to each other in the Y direction. That is, the circuit block 62B is arranged across two pixel blocks 61B adjacent to each other in the Y direction.

[0184] Among the three amplification stage cells Pc1, Pc2, and Pc3 shown in FIG. 19, one amplification stage cell Pc1 includes, for example, as shown in FIGS. 19 and 21B, an amplification transistor AMP and a selection transistor SEL that share and are arranged in the element formation region 21a of the pixel 3b of one pixel block 61B with one main electrode region 46. And the remaining two amplification stage cells Pc2 and Pc3 include, as shown in FIGS. 19, 21C, and 21D, an amplification transistor AMP and a selection transistor SEL that share and are arranged in each of the pixels 3c and 3d of the other pixel block 61B with one main electrode region 46.

[0185] In the readout circuit 15B of this 13th embodiment, as shown in FIG. 19, for each of the amplification transistors AMP of the three amplification stage cells Pc1, Pc1, and Pc3, the source region is electrically connected to the drain region of each selection transistor SEL, and the drain region is electrically connected to the power supply line VDD and the drain region of the reset transistor RST. And the gate electrodes of the amplification transistors AMP of each of the three amplification stage cells Pc1, Pc1, and Pc3 are electrically connected to the charge holding regions FD1 and FD2 of the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4 of each of the four pixels 3a, 3b, 3c, and d3, and the source region of the reset transistor RST, respectively. Also, for each of the selection transistors SEL of the three amplification stage cells Pc1, Pc1, and Pc3, the source region of each is electrically connected to the vertical signal line 11 (VSL), and the gate electrodes of each are electrically connected to each other. That is, in pixel block (pixel unit) 61B, the charge holding regions FD1 and FD2 of each of the four pixels 3 (3a, 3b, 3c, 3d) are electrically connected to each other. And in pixel block 61B, the eight charge holding regions FD1 and FD2 are electrically connected to each other. And each of the eight charge holding regions FD1 and FD2 is electrically connected to the gate electrode of the amplification transistor AMP (first amplification transistor) of the amplification stage cell Pc1. And each of the eight charge holding regions FD1 and FD2 is electrically connected to the gate electrodes of the amplification transistors AMP (first amplification transistor) of the amplification stage cell Pc1, the amplification transistor AMP (second amplification transistor) of the amplification stage cell Pc2, and the amplification transistor AMP (third amplification transistor) of the amplification stage cell Pc3.

[0186] <Connection state> Next, the connection state of pixel block 51B will be described with reference to FIGS. 22 to 24. FIGS. 23 and 24 are enlarged views of a part of FIG. 22, and in the following description, FIGS. 23 and 24 will be mainly used for the description.

[0187] As shown in FIG. 23, wiring 63f1 is electrically connected to the charge holding region FD1 of the first photoelectric conversion region 23L of pixel 3a and the charge holding region FD2 of the second photoelectric conversion region 23R of pixel 3c. Also, wiring 63f2 is electrically connected to the charge holding region FD2 of the second photoelectric conversion region 23R of pixel 3a and the charge holding region FD1 of the first photoelectric conversion region 23L of pixel 3c. And in the first and second photoelectric conversion regions 23L and 23R of each of pixel 3a and pixel 3c, wiring 63g is electrically connected to the gate electrodes 43 of the respective transfer transistors TR1 and TR2 individually.

[0188] Further, a wiring 63f3 is electrically connected to a charge holding region FD1 of a first photoelectric conversion region 23L of a pixel 3b and a charge holding region FD2 of a second photoelectric conversion region 23R of a pixel 3d. Also, a wiring 63f4 is electrically connected to a charge holding region FD2 of a second photoelectric conversion region 23R of a pixel 3b and a charge holding region FD1 of a first photoelectric conversion region 23L of a pixel 3d. Then, in each of the first and second photoelectric conversion regions 23L and 23R of the pixels 3c and 3d, wirings 63g are individually and electrically connected to gate electrodes 43 of the respective transfer transistors TR1 and TR2.

[0189] Then, these wirings 63f1, 63f2, 63f3, 63f4 and the respective wirings 63g are provided in parallel, in other words, side by side, in, for example, the first metal wiring layer of the multilayer wiring layer. And the wirings 63f1, 63f2, 63f3, 63f4 and the respective wirings 63g are covered with an interlayer insulating film. For this reason, in the pixels 3a to 3d, the capacitance between each gate electrode 43 of the transfer transistors TR1 and TR2 and the charge holding regions FD1 and FD2 is increased, and the charge holding regions FD1 and FD2 can be boosted in voltage.

[0190] As shown in FIG. 23, a wiring 63vs1 is electrically connected to each contact region 48 of a second photoelectric conversion region 23R of a pixel 3a and a first photoelectric conversion region 23L of a pixel 3c. Also, a wiring 63vs2 is electrically connected to each contact region 48 of a first photoelectric conversion region 23L of a pixel 3b and a first photoelectric conversion region 23L of a pixel 3d. Then, these wirings 63vs1 and 63vs2 extend in the Y direction and are arranged side by side in, for example, the first metal wiring layer of the multilayer wiring layer in the X direction. And they are integrated at an intersection of a pixel isolation region 31 extending in the X direction and a pixel isolation region 31 extending in the Y direction in a plan view. And the wirings 63vs1 and 63vs2 are covered with an interlayer insulating film. And, for example, 0V is applied to the wirings 63vs1 and 63vs2 as a first reference potential.

[0191] As shown in FIG. 23, wiring 63vs1 and 63vs2 are arranged between the charge holding regions FD1 and FD2 of one pixel 3a and the charge holding regions FD1 and FD2 of the other pixel 3b in pixels 3a and 3b adjacent to each other in the X direction in a plan view. Also, wiring 63vs1 and 63vs2 are arranged between the charge holding regions FD1 and FD2 of one pixel 3c and the charge holding regions FD1 and FD2 of the other pixel 3d in pixels 3c and 3d adjacent to each other in the X direction in a plan view. Therefore, it is possible to shield between the charge holding regions FD1 and FD2 of one pixel 3a and 3c adjacent to each other in the X direction and the charge holding regions FD1 and FD2 of the other pixel 3b and 3d with the wiring 63vs1 and 63vs2.

[0192] As shown in FIG. 24, in two pixel blocks 61B adjacent to each other in the Y direction, wiring 63s1 is electrically connected to the gate electrode 45 of the selection transistor SEL of pixel 3c of the other pixel block 61B within one circuit block 62B. Also, wiring 63s2 is electrically connected to the gate electrode 45 of the selection transistor SEL of each of pixel 3d of the other pixel block 61B and pixel 3b of one pixel block 61B. Also, wiring 63a is electrically connected to the gate electrode 45 of each of the three amplification transistors AMP. And the wiring 63s1, the wiring 63s2, and the wiring 63a are provided, for example, in the first metal wiring layer of a multilayer wiring layer and extend in the Y direction.

[0193] As shown in FIG. 24, the wiring 63a is arranged between the wiring 63s1 and the wiring 63s2 in a plan view. In other words, the wiring 63s1 and the wiring 63s2 are arranged so as to sandwich the wiring 63a in a plan view. Therefore, it is possible to reduce the signal interference between the charge holding regions FD1 and FD2 of each of pixels 3a and 3c and the charge holding regions FD1 and FD2 of each of pixels 3b and 3d.

[0194] As shown in FIG. 24, the wiring 63a includes, in plan view, a trunk portion 63a1 extending in the Y direction between the pixel 3a and the pixel 3b, a trunk portion 63a2 extending from the trunk portion 63a1 toward the pixel 3a side and electrically connected to the main electrode region 47 of the reset transistor RST of the pixel 3a, and a trunk portion 63a3 extending from the trunk portion 63a1 toward the pixel 3c side and electrically connected to the gate electrode 45 of the amplification transistor AMP of the pixel 3c. Then, as shown in FIG. 23, the wiring 63a is integrated with the wirings 63f2 and 63f3. That is, the wiring 63a is included in the conductive path 63 shown in FIG. 19, is electrically connected to the charge holding regions FD1 and FD2 of each of the four pixels 3a, 3b, 3c, and 3d, and is further electrically connected to the gate electrodes of the amplification transistors AMP of each of the three amplification stage cells Pc1, Pc2, and Pc3 of the readout circuit 15B, and the source region of the reset transistor RST.

[0195] On the other hand, as shown in FIG. 24, the wiring 63s1 includes, in plan view, a trunk portion 63s extending in the Y direction across the pixel 3a and the pixel 3c 11 and a trunk portion 63s 11 extending between the two trunk portions 63a2 and 63a3 of the wiring 63a toward the pixel 3b and the pixel 3d sides from the trunk portion 63s. 12 In this way, since the wiring 63s1 (trunk portion 63s 12 ) extends between the wiring 63a (two trunk portions 63a2), parasitic capacitances are added to each of the wiring 63a and the booster wiring 63s, so that the capacitance between the selection transistor SEL and the amplification transistor AMP is increased, and the charge holding regions FD1 and FD2 can be boosted.

[0196] Also in the solid-state imaging device 1B according to the 13th embodiment, the element formation regions 21a of the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4 extend across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and cross between the two pixel internal separation regions 32 in plan view. Therefore, also in the solid-state imaging device 1B according to the 13th embodiment, the same effects as those of the solid-state imaging device 1A according to the first embodiment described above can be obtained.

[0197] 〔Embodiment 14〕 The solid-state imaging device 1C according to the 14th embodiment of the present technology basically has the same configuration as the solid-state imaging device 1B according to the 13th embodiment described above, and the following configuration is different.

[0198] That is, the solid-state imaging device 1C according to the 14th embodiment of the present technology includes a readout circuit 15C, a pixel block (pixel unit) 61C, and a circuit block 62C shown in FIG. 25 instead of the readout circuit 15B, the pixel block 61B, and the circuit block 62B shown in FIG. 19 of the 13th embodiment described above.

[0199] As shown in FIGS. 25 and 26, the pixel block 61C of this 14th embodiment has a pixel 3a including a photoelectric conversion cell 22M5. The photoelectric conversion cell 22M5 basically has the same configuration as the photoelectric conversion cell 22M2 of the pixel 3b, and the pixel transistors arranged in the element formation region 21a are different. That is, as shown in FIG. 27, the photoelectric conversion cell 22M5 has a switching transistor FDG arranged as a pixel transistor Qt on the side of the first photoelectric conversion region 23L and a reset transistor RST arranged as a pixel transistor Qt on the side of the second photoelectric conversion region 23R.

[0200] As shown in FIG. 26, the photoelectric conversion cell 22M5 of the pixel 3a and the photoelectric conversion cell 22M2 of the pixel 3c are arranged such that the second photoelectric conversion region 23R of the pixel 3a and the first photoelectric conversion region 23L of the pixel 3b are adjacent to each other in the X direction. Also, the photoelectric conversion cell 22M5 of the pixel 3a and the photoelectric conversion cell 22M2 of the pixel 3c are arranged such that the first photoelectric conversion region 23L of the pixel 3a and the second photoelectric conversion region 23R of the pixel 3c are adjacent to each other in the Y direction, and the second photoelectric conversion 23R of the pixel 3a and the first photoelectric conversion region 23L of the pixel 3c are adjacent to each other. As shown in FIG. 25, the input stage of the readout circuit 15C is connected to the charge holding regions FD1 and FD2 of each of the four pixels 3a, 3b, 3c, and 3d via the conductive path 63. The readout circuit 15C reads the signal charges held in the charge holding regions FD1 and FD2 of each of the four pixels 3a, 3b, 3c, and 3d and outputs a pixel signal based on the signal charges. The readout circuit 15C is shared by the four pixels 3a, 3b, 3c, and 3d and provided for each pixel block 61C.

[0201] The readout circuit 15C includes, but is not limited to, a switching transistor FDG and a reset transistor RST, and three amplification stage cells Pc1, Pc2, and Pc3. Each of the three amplification stage cells Pc1, Pc2, and Pc3 includes an amplification transistor AMP and a selection transistor SEL connected in series.

[0202] The readout circuit 15C is composed of transistors included in the circuit block 62C shown in FIG. 26. The circuit block 62C includes, but is not limited to, switching transistors FDG, reset transistors RST, amplification transistors AMP, and selection transistors SEL arranged in pixels 3a and 3b of one pixel block 61C, and two amplification transistors AMP and two selection transistors SEL arranged in pixels 3c and 3d of the other pixel block 61C, in two pixel blocks 61C arranged adjacent to each other in the Y direction. That is, the circuit block 62C is arranged across two pixel blocks 61C adjacent to each other in the Y direction. Of the three amplification stage cells Pc1, Pc2, and Pc3, one amplification stage cell Pc1 includes an amplification transistor AMP and a selection transistor SEL arranged in series in pixel 3b of one pixel block 61C, and the remaining two amplification stage cells Pc2 and Pc3 include amplification transistors AMP and selection transistors SEL arranged in series in each of pixels 3c and 3d of the other pixel block 61C.

[0203] As shown in FIG. 25, the switching transistor FDG has its source region electrically connected to the charge holding regions FD1 and FD2 of each of the photoelectric conversion cells 22M2 to 22M4 and 22M5, and is also electrically connected to the gate electrodes of the amplification transistors AMP of each of the amplification stage cells Pc1 to Pc3. And the switching transistor FDG has its drain region electrically connected to the source region of the reset transistor RST. And the gate electrode of the switching transistor FDG is electrically connected to the switching transistor drive line among the pixel drive lines 10, as will be described with reference to FIG. 2. The switching transistor FDG controls the charge holding by the charge holding regions FD1 and FD2, in other words, the charge holding by the conductive path 63, and adjusts the voltage amplification factor according to the potential amplified by the amplification transistor AMP. That is, each of the eight charge holding regions DF1 and FD2 of the pixel block 61C is electrically connected to the switching transistor FDG, and is electrically connected to the reset transistor RST via this switching transistor FDG. As shown in FIG. 25, a capacitor Ce is connected to the connection node portion between the switching transistor FDG and the reset transistor RST. This capacitor Ce includes a capacitor formed by a capacitive element as a passive element and a wiring capacitance formed by adjacent wirings.

[0204] Also in the solid-state imaging device 1C according to this 14th embodiment, the element formation regions 21a of each of the photoelectric conversion cells 22M2 to 22M5 extend over the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and cross between the two pixel internal separation regions 32 (see FIG. 22) in plan view. Therefore, also in the solid-state imaging device 1C according to this 14th embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described 1st embodiment can be obtained.

[0205] 〔15th Embodiment〕 The solid-state imaging device 1D according to the 15th embodiment of the present technology basically has the same configuration as the solid-state imaging device 1B according to the above-described 13th embodiment, and the following configurations are different.

[0206] That is, as shown in FIGS. 28 and 29, in the solid-state imaging device 1D according to the 15th embodiment, the connection forms of the wirings 63f1, 63f2, 63f3, and 63f4 are different. Other configurations are the same as those of the first embodiment described above.

[0207] Among the four pixels 3a, 3b, 3c, and 3d in the 2×2 array shown in FIGS. 28 and 29, in the pixels 3a and 3c facing each other in the Y direction, the first photoelectric conversion region 23L of the pixel 3a and the first photoelectric conversion region 23R of the pixel 3c are obliquely facing in plan view. Then, as shown in FIG. 29, the wiring 63f1 electrically connects the charge holding region FD1 of the first photoelectric conversion region 23L of the pixel 3a and the charge holding region FD1 of the first photoelectric conversion region 23L of the pixel 3c. Further, the wiring 63f2 electrically connects the charge holding region FD2 of the second photoelectric conversion region 23R of the pixel 3a and the charge holding region FD2 of the second photoelectric conversion region 23R of the pixel 3c. And the wiring 63f1 and the wiring 63f2 cross in an X shape in the two-dimensional plane and are electrically connected to the charge holding regions FD1 and FD2 of each of the pixels 3a and 3c.

[0208] Among the four pixels 3a, 3b, 3c, and 3d in the 2×2 array shown in FIGS. 28 and 29, in the pixels 3b and 3d facing each other in the Y direction, the first photoelectric conversion region 23L of the pixel 3b and the first photoelectric conversion region 23R of the pixel 3d are obliquely facing in plan view. Then, as shown in FIG. 29, the wiring 63f3 electrically connects the charge holding region FD1 of the first photoelectric conversion region 23L of the pixel 3b and the charge holding region FD1 of the first photoelectric conversion region 23L of the pixel 3d. Further, the wiring 63f4 electrically connects the charge holding region FD2 of the second photoelectric conversion region 23R of the pixel 3a and the charge holding region FD2 of the second photoelectric conversion region 23R of the pixel 3d. And the wiring 63f3 and the wiring 63f4 cross in an X shape in the two-dimensional plane and are electrically connected to the charge holding regions FD1 and FT2 of each of the pixels 3b and 3d.

[0209] In this way, by crossing wiring 63f1 and wiring 63f2, the charge holding regions FD1 and FD2 of each of the pixels 3a and 3c adjacent to each other in the Y direction can be electrically connected with the shortest wiring length, and the parasitic capacitance between the transfer transistors TR1 and TR2 and the charge holding regions FD1 and FD2 can be reduced. Also, by crossing wiring 63f3 and wiring 63f4, the charge holding regions FD1 and FD2 of each of the pixels 3b and 3d adjacent to each other in the Y direction can be electrically connected with the shortest wiring length, and the parasitic capacitance between the transfer transistors TR1 and TR2 and the charge holding regions FD1 and FD2 can be reduced. Thereby, it becomes possible to increase the photoelectric conversion efficiency.

[0210] In this embodiment, the case where the pixel 3a includes the photoelectric conversion cell 22M1 shown in FIG. 21A has been described. However, the technique of crossing the wirings 63f1 and 63f3 and the wirings 63f2 and 63f4 can also be applied when the pixel 3a includes the photoelectric conversion cell 22M2 shown in FIG. 21B as in the above-described 14th embodiment.

[0211] 〔16th Embodiment〕 The solid-state imaging device 1E according to the 16th embodiment of the present technology basically has the same configuration as the solid-state imaging device 1C according to the above-described 14th embodiment, and the configurations of the pixel block and the readout circuit are different.

[0212] That is, the solid-state imaging device 1E according to this 16th embodiment includes a pixel block 61E, a readout circuit 15E, and a circuit block 62E shown in FIGS. 30 and 31 instead of the pixel block 61C, the readout circuit 15C, and the circuit block 62C shown in FIG. 25 of the above-described 14th embodiment.

[0213] As shown in FIG. 31, the pixel block 61E of this 16th embodiment includes three pixels 3 (3e, 3f, 3g) arranged along the Y direction. Although one pixel block 61E is illustrated in FIG. 31, the pixel block 61E is repeatedly arranged in each of the X direction and the Y direction in the pixel region 2A as described with reference to FIG. 2.

[0214] As shown in FIG. 31, pixel 3e includes a photoelectric conversion cell 22N1, pixel 3f includes a photoelectric conversion cell 22N2, and pixel 3g includes a photoelectric conversion cell 22N3. Each of these photoelectric conversion cells 22N1, 22N2, and 22N3 basically has the same configuration as the photoelectric conversion cell 22M5 shown in FIG. 27 of the above-described 14th embodiment, but the type and arrangement direction of the pixel transistors arranged in the element formation region 21a are different.

[0215] As shown in FIG. 31, the photoelectric conversion cell 22N1 of pixel 3e includes, as pixel transistors, an amplification transistor AMP arranged on the first photoelectric conversion region 23L side of the element formation region 21a and a selection transistor SEL arranged on the second photoelectric conversion region 23R side of the element formation region 21a.

[0216] As shown in FIG. 31, the photoelectric conversion cell 22N2 of pixel 3f includes, as pixel transistors, a selection transistor SEL arranged on the first photoelectric conversion region 23L side of the element formation region 21a and an amplification transistor AMP arranged on the second photoelectric conversion region 23R side of the element formation region 21a.

[0217] As shown in FIG. 31, the photoelectric conversion cell 22N3 of pixel 3g includes, as pixel transistors, a switching transistor FDG arranged on the first photoelectric conversion region 23L side of the element formation region 21a and a reset transistor RST arranged on the second photoelectric conversion region 23R side of the element formation region 21a.

[0218] The photoelectric conversion cell 22N1 of pixel 3e and the photoelectric conversion cell 22N2 of pixel 3f are arranged in a direction in which the amplification transistors AMP and the selection transistors SEL face each other in a plan view in the Y direction.

[0219] The photoelectric conversion cell 22N2 of pixel 3f and the photoelectric conversion cell 22N3 of pixel 3g are such that in the Y direction, the first photoelectric conversion region 23L of pixel 3f and the second photoelectric conversion region 23R of pixel 3g are adjacent to each other, and the second photoelectric conversion 23R of pixel 3f and the first photoelectric conversion region 23L of pixel 3g are adjacent to each other. That is, the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3f and the charge holding regions FD1, FD2 and the two contact regions 48 of pixel 3g are adjacent to each other in the Y direction.

[0220] <Readout circuit> As shown in FIG. 30, the input stage of the readout circuit 15E is connected to the charge holding regions FD1, FD2 of each of the three pixels 3e, 3f, 3g via the conductive path 63. The readout circuit 15E reads the signal charges held in the charge holding regions FD1, FD2 of each of the three pixels 3e, 3f, 3g and outputs a pixel signal based on the signal charges. The readout circuit 15E is shared by the three pixels 3e, 3f, 3g (six photoelectric conversion regions) and is provided for each pixel block 61E.

[0221] The readout circuit 15E includes, but is not limited to, a switching transistor FDG, a reset transistor RST, and two amplification stage cells Pc1 and Pc2. This readout circuit 15E basically has the same configuration as the readout circuit 15C shown in FIG. 25 of the above-described 14th embodiment, except that the number of amplification stage cells is different.

[0222] The readout circuit 15E is composed of pixel transistors included in the circuit block 62E shown in FIG. 31. Different from the circuit block 62C shown in FIG. 26 of the above-described 14th embodiment, the circuit block 62E includes a switching transistor FDG, a reset transistor RST, two amplification transistors AMP, and two selection transistors SEL arranged in the pixels 3e, 3f, 3g within one pixel block 61E.

[0223] <Connection state> Next, the connection state of the pixel block will be described with reference to FIG. 32. As shown in FIG. 32, wiring 63f5 is electrically connected to the two charge holding regions FD1 and FD2 of the photoelectric conversion cell 22N2 of pixel 3f and the two charge holding regions FD1 and FD2 of the photoelectric conversion cell 22N3 of pixel 3g. Also, wiring 63f6 is electrically connected to the two charge holding regions FD1 and FD2 of the photoelectric conversion cell 22N2 of pixel 3e. Each of this wiring 63f5 and wiring 63f6 is provided, for example, in the first metal wiring layer of the multilayer wiring layer and is covered with an interlayer insulating film.

[0224] Wiring 63f5 and wiring 63f6 are electrically connected via 64f provided, for example, in the second metal wiring layer of the multilayer wiring layer. In the fine pixel 3, since the width of the two-dimensional plane of the shared region is narrow and it is difficult to route the wiring, it is preferable to electrically connect the spaced-apart wiring 64f5 and wiring 64f6 in the Y direction using the second-layer wiring 64f.

[0225] As shown in FIG. 32, in pixel block 61E, wiring 63g1, wiring 63g2, and boosting wiring 63s are arranged. Wiring 63g1 is electrically connected to the gate electrode 45 of the amplification transistor AMP of pixel 3e. Wiring 63g2 is electrically connected to the gate electrode 45 of the amplification transistor AMP of pixel 3f. Although not shown in detail, the boosting wiring 63s is electrically connected to wiring 63f5 and wiring 63f6. And wiring 63g1, wiring 63g2, and boosting wiring 63s are provided, for example, running parallel in the first metal wiring layer of the multilayer wiring layer. And these wiring 63g1, wiring 63g2, and boosting wiring 63s are covered with an interlayer insulating film. For this reason, the capacitance added to the conductive path 63 shown in FIG. 30 increases, and boosting of the charge holding regions FD1 and FD2 becomes possible.

[0226] As shown in FIG. 32, in this embodiment as well, wirings 63vs1 and 63vs2 are provided. Although not shown in detail, these wirings 63vs1 and 63vs2 are arranged between the charge holding regions FD1 and FD2 of one pixel block 61E and the charge holding regions FD1 and FD2 of the other pixel block 61E in the pixel block pair 61E adjacent to each other in the X direction. Therefore, between the pixel blocks 61E adjacent to each other in the X direction, the charge holding regions FD1 and FD2 of one pixel block 61E and the charge holding regions FD1 and FD2 of the other pixel block 61E can be shielded by the wirings 63vs1 and 63vs2.

[0227] Also in the solid-state imaging device 1E according to this 16th embodiment, the element formation regions 21a of the photoelectric conversion cells 22N1, 22N2, and 22N3 each extend across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R and cross between the two pixel internal separation regions 32 in plan view. Therefore, also in the solid-state imaging device 1E according to this 16th embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described 1st embodiment can be obtained.

[0228] 〔17th Embodiment〕 The solid-state imaging device 1F according to the 17th embodiment of the present technology basically has the same configuration as that of the above-described 13th embodiment, and the configuration of the photoelectric conversion cell of the pixel is different.

[0229] That is, the solid-state imaging device 1F according to this 17th embodiment includes a pixel block 61F shown in FIG. 33 instead of the pixel block 61B shown in FIG. 20.

[0230] The pixel block 62F includes, for example, four pixels 3 (3a1, 3b1, 3c1, 3d1) arranged in a 2×2 array of two each in the X direction and the Y direction in plan view. Although mainly one pixel block 61F is shown in FIG. 33, the pixel blocks 61F are repeatedly arranged in the X direction and the Y direction.

[0231] As shown in FIG. 33, among the four pixels 3 (3a1, 3b1, 3c1, 3d1), pixel 3a1 includes a photoelectric conversion cell 22P1. Pixel 3b1 includes a photoelectric conversion cell 22P2. Pixel 3c includes a photoelectric conversion cell 22P3. Pixel 3d includes a photoelectric conversion cell 22P4. Each of the photoelectric conversion cells 22P1, 22P2, 22P3, and 22P4 basically has the same configuration as the photoelectric conversion cell 22F shown in FIG. 12 of the above-described sixth embodiment, but the type and arrangement direction of the pixel transistors arranged in the element formation region 21d are different. Other configurations are the same as those of the above-described thirteenth embodiment.

[0232] As shown in FIG. 33, the photoelectric conversion cell 22P1 of pixel 3a1 includes an amplification transistor AMP arranged on the second photoelectric conversion region 23R side of the element formation region 21d as a pixel transistor, and no pixel transistor is arranged on the first photoelectric conversion region 23L side of the element formation region 21d.

[0233] As shown in FIG. 33, the photoelectric conversion cell 22P2 of pixel 3b2 includes an amplification transistor AMP arranged on the first photoelectric conversion region 23L side of the element formation region 21d and a selection transistor SEL arranged on the second photoelectric conversion region 23R side of the element formation region 21d as pixel transistors.

[0234] As shown in FIG. 33, the photoelectric conversion cell 22P3 of pixel 3c1 includes an amplification transistor AMP arranged on the first photoelectric conversion region 23L side of the element formation region 21d and a selection transistor SEL arranged on the second photoelectric conversion region 23R side of the element formation region 21d as pixel transistors.

[0235] As shown in FIG. 33, the photoelectric conversion cell 22P4 of pixel 3d1 includes a selection transistor SEL arranged on the first photoelectric conversion region 23L side of the element formation region 21d and an amplification transistor AMP arranged on the second photoelectric conversion region 23R side of the element formation region 21d as pixel transistors.

[0236] As shown in FIG. 33, the photoelectric conversion cell 22P1 of pixel 3a1 and the photoelectric conversion cell 22P2 of pixel 3b1 are arranged such that in the X direction, the second photoelectric conversion region 23R of pixel 3a1 and the first photoelectric conversion region 23L of pixel 3b1 are adjacent to each other. That is, the reset transistor RST of pixel 3a1 and the amplification transistor AMP of pixel 3b1 are adjacent to each other in the X direction. Also, as shown in FIG. 33, the photoelectric conversion cell 22P3 of pixel 3c1 and the photoelectric conversion cell 22P4 of pixel 3d1 are arranged such that in the X direction, the first photoelectric conversion region 23L of pixel 3c1 and the second photoelectric conversion region 23R of pixel 3d1 are adjacent to each other. That is, the amplification transistor AMP of pixel 3c1 and the amplification transistor AMP of pixel 3d1 are adjacent to each other in the X direction. Also, the photoelectric conversion cell 22P1 of pixel 3a1 and the photoelectric conversion cell 22P3 of pixel 3c1 are arranged such that in the Y direction, the first photoelectric conversion region 23L of pixel 3a1 and the second photoelectric conversion region 23R of pixel 3c1 are adjacent to each other, and the second photoelectric conversion 23R of pixel 3a1 and the first photoelectric conversion region 23L of pixel 3c1 are adjacent to each other. That is, as shown in FIG. 33, the charge holding region FD of pixel 3a1 and the charge holding region FD of pixel 3c1 are adjacent to each other in the Y direction. Also, as shown in FIG. 33, the photoelectric conversion cell 22P2 of pixel 3b1 and the photoelectric conversion cell 22P4 of pixel 3d1 are arranged such that in the Y direction, the first photoelectric conversion region 23L of pixel 3b1 and the second photoelectric conversion region 23R of pixel 3d1 are adjacent to each other, and the second photoelectric conversion 23R of pixel 3a1 and the first photoelectric conversion region 23L of pixel 3c1 are adjacent to each other. That is, as shown in FIG. 33, the charge holding region FD of pixel 3b1 and the charge holding region FD of pixel 3d1 are adjacent to each other in the Y direction via the pixel separation region 31, respectively.

[0237] Also in the solid-state imaging device 1F according to the 17th embodiment, each element formation region 21d of the photoelectric conversion cells 22P1, 22P2, 22P3, 22P4 extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the pixel separation region 31 and the in-pixel separation region 32 in a plan view. Therefore, also in the solid-state imaging device 1F according to the 17th embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described 1st embodiment can be obtained.

[0238] 〔18th Embodiment〕 The solid-state imaging device 1G according to the 18th embodiment of the present technology basically has the same configuration as the solid-state imaging device 1E according to the above-described 16th embodiment, and the configuration of the photoelectric conversion cells of the pixels is different.

[0239] That is, the solid-state imaging device 1G according to the 18th embodiment includes a pixel block 61G shown in FIG. 34 instead of the pixel block 61E shown in FIG. 31.

[0240] As shown in FIG. 34, the pixel block 61G of the 18th embodiment includes three pixels 3 (3e1, 3f1, 3g1) arranged along the Y direction. Although one pixel block 61G is illustrated in FIG. 34, the pixel block 61G is repeatedly arranged in each of the X direction and the Y direction in the pixel region 2A, as described with reference to FIG. 2.

[0241] As shown in FIG. 34, the pixel 3e1 includes a photoelectric conversion cell 22Q1, the pixel 3f1 includes a photoelectric conversion cell 22Q2, and the pixel 3g1 includes a photoelectric conversion cell 22Q3. Each of these photoelectric conversion cells 22Q1, 22Q2, 22Q3 basically has the same configuration as the photoelectric conversion cell 22F shown in FIG. 12 of the above-described 6th embodiment, but the type and arrangement direction of the pixel transistors arranged in the element formation region 21d are different.

[0242] As shown in FIG. 34, the photoelectric conversion cell 22Q1 of pixel 3e1 includes, as pixel transistors, an amplification transistor AMP disposed on the first photoelectric conversion region 23L side of the element formation region 21d and a selection transistor SEL disposed on the second photoelectric conversion region 23R side of the element formation region 21a.

[0243] As shown in FIG. 31, the photoelectric conversion cell 22Q2 of pixel 3f1 includes, as pixel transistors, a selection transistor SEL disposed on the first photoelectric conversion region 23L side of the element formation region 21d and an amplification transistor AMP disposed on the second photoelectric conversion region 23R side of the element formation region 21d.

[0244] As shown in FIG. 31, the photoelectric conversion cell 22Q3 of pixel 3g1 includes, as pixel transistors, a switching transistor FDG disposed on the first photoelectric conversion region 23L side of the element formation region 21d and a reset transistor RST disposed on the second photoelectric conversion region 23R side of the element formation region 21d.

[0245] The photoelectric conversion cell 22Q1 of pixel 3e1 and the photoelectric conversion cell 22Q2 of pixel 3f1 are arranged in a direction in which the amplification transistors AMP and the selection transistors SEL face each other in a plan view in the Y direction.

[0246] The photoelectric conversion cell 22Q2 of pixel 3f1 and the photoelectric conversion cell 22Q3 of pixel 3g1 are such that in the Y direction, the first photoelectric conversion region 23L of pixel 3f1 and the second photoelectric conversion region 23R of pixel 3g1 are adjacent to each other, and the second photoelectric conversion 23R of pixel 3f1 and the first photoelectric conversion region 23L of pixel 3g1 are adjacent to each other. That is, the charge holding regions FD and the two transfer transistors TR1, TR2 of pixel 3f1 and the charge holding regions FD and the two transfer transistors TR1, TR2 of pixel 3g1 are adjacent to each other in the Y direction.

[0247] Also in the solid-state imaging device 1G according to the 18th embodiment, each element formation region 21d of the photoelectric conversion cells 22Q1, 22Q2, 22Q3, and 22Q4 extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the pixel separation region 31 and the in-pixel separation region 32 in a plan view. Therefore, also in the solid-state imaging device 1G according to the 18th embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described 1st embodiment can be obtained.

[0248] 〔19th Embodiment〕 The solid-state imaging device 1H according to the 19th embodiment of the present technology basically has the same configuration as the solid-state imaging device 1B according to the above-described 13th embodiment, and the following configuration is different. That is, the solid-state imaging device 1H according to the 19th embodiment of the present technology includes a pixel block 61H and a circuit block 62H shown in FIGS. 35 and 36 instead of the pixel block 61B and the circuit block 62B shown in FIGS. 19 and 20 of the above-described 13th embodiment. Further, as shown in FIGS. 36 to 39, the solid-state imaging device 1H according to the 19th embodiment of the present technology includes relay wirings 71, conductive pads 72, relay wirings 73, and conductive pads 74.

[0249] As shown in FIG. 35, the pixel block 61H includes a plurality of pixels 3. In this 19th embodiment, the pixel block 61H includes, but is not limited to, for example, four pixels 3 (3a2, 3b2, 3c2, 3d2) arranged in a 2×2 array of two in each of the X direction and the Y direction in a plan view. Although mainly one pixel block 61H is illustrated in FIG. 36, the pixel blocks 61H are repeatedly arranged in each of the X direction and the Y direction.

[0250] As shown in FIGS. 36 to 39, among the four pixels 3 (3a2, 3b2, 3c2, 3d2), pixel 3a2 includes a photoelectric conversion cell 22R1. Pixel 3b2 includes a photoelectric conversion cell 22R2. Pixel 3c2 includes a photoelectric conversion cell 22R3. Pixel 3d2 includes a photoelectric conversion cell 22R4. Each of these photoelectric conversion cells 22R1, 22R2, 22R3, and 22R4 basically has the same configuration as the photoelectric conversion cells 22M1, 22M2, 22M3, and 22M4 shown in FIGS. 21A to 21D of the above-described 13th embodiment, with different planar patterns of the element formation regions 21b1, 21b2, and different arrangements of the transfer transistors TR1, TR2, the charge holding regions FD1, FD2, and the power supply region 21z.

[0251] As shown in FIGS. 36, 37, and 39, each of the photoelectric conversion cells 22R1, 22R2, 22R3, and 22R4 has a power supply region 21z disposed on both sides of the pixel internal separation region 32 on the element formation region 21a side in plan view. And a p-type contact region 48 is provided in each power supply region 21z. That is, in each of the photoelectric conversion cells 22R1, 22R2, 22R3, and 22R4, a power supply region 21z and a contact region 48 are disposed in each of the first photoelectric conversion region 23L and the second photoelectric conversion region 23R.

[0252] Also, as shown in FIGS. 36 and 38, in each of the photoelectric conversion cells 22R1, 22R2, 22R3, and 22R4, charge holding regions FD1, FD2 are disposed between the gate electrodes 43 of the transfer transistors TR1, TR2 and the pixel internal separation region 32 in plan view.

[0253] Also, as shown in FIGS. 36 and 38, the transfer transistors TR1 and TR2 of each of the photoelectric conversion cells 22R1 and 22R3 are arranged adjacent to each other (facing each other) so as to sandwich the pixel isolation region 31 between the photoelectric conversion cell 22R1 and the photoelectric conversion cell 22R3 in plan view. Similarly, also in the transfer transistors TR1 and TR2 of each of the photoelectric conversion cells 22R2 and 22R4, they are arranged adjacent to each other (facing each other) so as to sandwich the pixel isolation region 31 between the photoelectric conversion cell 22R2 and the photoelectric conversion cell 22R4 in plan view.

[0254] As shown in FIG. 37, the photoelectric conversion cell 22R1 of the pixel 3a2 has, but is not limited to, for example, a selection transistor SEL (Qt) arranged on the second photoelectric conversion region 23R side, and the arrangement of the pixel transistor is omitted on the first photoelectric conversion region 23L side. As shown in FIG. 37, the photoelectric conversion cell 22R2 of the pixel 3b2 has, but is not limited to, for example, an amplification transistor AMP arranged on the first photoelectric conversion region 23L side, and a selection transistor SEL arranged on the second photoelectric conversion region 23R side. As shown in FIG. 39, the photoelectric conversion cell 22R3 of the pixel 3c2 has, but is not limited to, for example, an amplification transistor AMP arranged on the first photoelectric conversion region 23L side, and a selection transistor SEL arranged on the second photoelectric conversion region 23R side. As shown in FIG. 39, the photoelectric conversion cell 22R4 of the pixel 3d2 has, but is not limited to, for example, a selection transistor SEL arranged on the first photoelectric conversion region 23L side, and an amplification transistor AMP arranged on the second photoelectric conversion region 23R side.

[0255] <Orientation of the photoelectric conversion cell> As shown in FIGS. 36 and 37, the photoelectric conversion cell 22R1 of the pixel 3a2 and the photoelectric conversion cell 22R2 of the pixel 3b2 are arranged such that the second photoelectric conversion region 23R of the pixel 3a2 and the first photoelectric conversion region 23L of the pixel 3b2 are adjacent to each other in the X direction. That is, the reset transistor RST of the pixel 3a2 and the amplification transistor AMP of the pixel 3b2 are adjacent to each other in the X direction. Also, as shown in FIGS. 36 and 39, the photoelectric conversion cell 22R3 of pixel 3c2 and the photoelectric conversion cell 22R4 of pixel 3d2 are such that in the X direction, the first photoelectric conversion region 23L of pixel 3c2 and the second photoelectric conversion region 23R of pixel 3d2 are adjacent to each other. That is, the amplification transistor AMP of pixel 3c2 and the amplification transistor AMP of pixel 3d2 are adjacent to each other in the X direction. Also, as shown in FIGS. 36 and 38, the photoelectric conversion cell 22R1 of pixel 3a2 and the photoelectric conversion cell 22R3 of pixel 3c2 are such that in the Y direction, the first photoelectric conversion region 23L of pixel 3a2 and the second photoelectric conversion region 23R of pixel 3c2 are adjacent to each other, and the second photoelectric conversion 23R of pixel 3a2 and the first photoelectric conversion region 23L of pixel 3c2 are adjacent to each other. That is, as shown in FIG. 38, the charge holding regions FD1, FD2 of pixel 3a2 and the charge holding regions FD1, FD2 of pixel 3c2 are adjacent to each other in the Y direction with the pixel separation region 31 therebetween in plan view. Also, as shown in FIGS. 36 and 38, the photoelectric conversion cell 22R2 of pixel 3b2 and the photoelectric conversion cell 22R4 of pixel 3d2 are such that in the Y direction, the first photoelectric conversion region 23L of pixel 3b2 and the second photoelectric conversion region 23R of pixel 3d2 are adjacent to each other, and the second photoelectric conversion 23R of pixel 3a2 and the first photoelectric conversion region 23L of pixel 3c2 are adjacent to each other. That is, as shown in FIG. 38, the charge holding regions FD1, FD2 of pixel 3b2 and the charge holding regions FD1, FD2 of pixel 3d2 are adjacent to each other in the Y direction with the pixel separation region 31 therebetween in plan view.

[0256] Although not shown in detail, referring to FIGS. 37 and 39, in two pixel blocks 61H arranged in the Y direction, the power supply regions 21z of the pixels 3a2 adjacent to each other in the Y direction and the power supply region 21z of the pixel 3c2 are adjacent to each other via the pixel separation region 31 in plan view. Further, in two pixel blocks 61H arranged in the Y direction, the power supply regions 21z of the pixels 3b2 adjacent to each other in the Y direction and the power supply region 21z of the pixel 3d2 are adjacent to each other via the pixel separation region 31 in plan view. FIGS. 37 and 39 illustrate a state in which the power supply regions 21z are arranged at each of the four corners surrounding the intersection where the pixel separation region 31 and the in-pixel separation region 32 intersect. And a p-type contact region 48 is provided in each of these four power supply regions 21z. That is, four contact regions 48 are arranged so as to surround the intersection of the pixel separation region 31 and the in-pixel separation region 32.

[0257] <Readout circuit> As shown in FIG. 35, the input stage of the readout circuit 15B is connected to the charge holding regions FD1 and FD2 of each of the four pixels 3a2, 3b2, 3c2, and 3d2 via the conductive path 63. The readout circuit 15B reads the signal charges held in the charge holding regions FD1 and FD2 of each of the four pixels 3a2, 3b2, 3c2, and 3d2 and outputs a pixel signal based on the signal charges. The readout circuit 15B is shared by the four pixels 3a2, 3b2, 3c2, and 3d2 (eight photoelectric conversion regions) and is provided for each pixel block 61H.

[0258] The readout circuit 15B has the same configuration as the readout circuit 15B shown in FIG. 19 of the above-described 13th embodiment. The readout circuit 15B of this 19th embodiment is composed of pixel transistors included in the circuit block 62E shown in FIG. 35. Different from the circuit block 62B shown in FIG. 20 of the above-described 13th embodiment, the circuit block 62H includes a switching transistor FDG, a reset transistor RST, two amplification transistors AMP, and two selection transistors SEL arranged in the pixels 3a2, 3b2, 3c2, and 3d2 within one pixel block 61H.

[0259] As shown in FIGS. 40 and 41, although not limited thereto, the pixel isolation region 31 of this 19th embodiment penetrates the element isolation region 33 in the thickness direction (Z direction) of the semiconductor layer 21, which is different from the pixel isolation region 31 shown in FIGS. 5 to 7 of the above-described 1st embodiment. Further, although not limited thereto, the pixel isolation region 31 of this 19th embodiment has a three-layer structure in which both sides of a conductive film extending in the depth direction of the semiconductor layer 21 are sandwiched by insulating films. Although not shown, in the in-pixel isolation region 32 of this 19th embodiment as well, the element isolation region 33 penetrates in the thickness direction of the semiconductor layer 21. In the in-pixel isolation region 32 of this 19th embodiment as well, although not limited thereto, it may have a three-layer structure in which both sides of a conductive film extending in the depth direction of the semiconductor layer 21 are sandwiched by insulating films.

[0260] As shown in FIGS. 40 and 41, also in this embodiment, the element formation regions 21a, 21b2, and the power supply region 21z overlap with the photoelectric conversion unit 25 via the p-type semiconductor region 24 in plan view. Further, although not shown, also in the element formation region 21b1, it overlaps with the photoelectric conversion unit 25 via the p-type semiconductor region 24 in plan view.

[0261] <Relay wiring, Conductive pad> As shown in FIG. 37, the relay wiring 71 includes two conductive pads 71a and 71b, and a connecting portion 71c that connects the two conductive pads 71a and 71b. The conductive pad 71a is connected to one end side of the connecting portion, and the conductive pad 71b is connected to the other end side of the connecting portion 71c. This relay wiring 71 overlaps with the pixel isolation region 31 in plan view and extends along the X direction.

[0262] As shown in FIG. 37, the conductive pad 71a is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation region 21a side of the photoelectric conversion cell 22R1 (pixel 3a2) in a plan view. The conductive pad 71a straddles the in-pixel separation region 32 in the X direction and overlaps with two p-type contact regions 48 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. Further, the conductive pad 71a straddles the in-pixel separation region 32 adjacent to the in-pixel separation region 32 of the photoelectric conversion cell 22R1 to a photoelectric conversion cell on the side opposite to the photoelectric conversion cell 22R1 side of the pixel separation region 31 (the photoelectric conversion cell 22R3 of another pixel block adjacent in the Y direction), and overlaps with two p-type contact regions 48 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. That is, the conductive pad 71a straddles the separation region including the pixel separation region 31 and the in-pixel separation region 32 in each of the X direction and the Y direction, overlaps with a plurality of p-type contact regions 48 disposed on both sides of the separation region, and is electrically and mechanically connected. In this embodiment, the conductive pad 71a is electrically and mechanically connected to each of the four contact regions 48 disposed so as to surround the intersection where the pixel separation region 31 extending in the X direction and the in-pixel separation region 32 extending in the Y direction intersect, straddling the pixel separation region 31 and the in-pixel separation region 32.

[0263] As shown in FIG. 42A, the conductive pad 71a has a body portion 71a1 located in the pixel separation region 31, and a head portion 71a2 that protrudes from the body portion 71a1 to the outside of the pixel separation region 31 and is wider than the body portion 71a1. The body portion 71a1 is in contact with the side wall of the contact region 48 and is electrically and mechanically connected. The head portion 71a2 is in contact with the upper surface (surface layer surface) of the contact region 48 and is electrically and mechanically connected. That is, the conductive pad 71a is configured in a shape having the body portion 71a1 and the head portion 71a2 wider than the body portion 71a1, and by disposing the body portion 71a1 in the pixel separation region 31 so that the body portion 71a1 and the head portion 71a2 are in contact with the contact region 48, the contact area between the contact region 48 and the conductive pad 71a is increased.

[0264] As shown in FIG. 37, the connecting portion 71c extends across the pixel separation region 31 over the pixels 3a2 and 3b2. As shown in FIG. 42B, the connecting portion 71c extends across the inside and outside of the pixel separation region 31 in the thickness direction of the semiconductor layer 21. And, the width of the portion of the connecting portion 71c located inside the pixel separation region 31 is smaller than the width of the pixel separation region 31, and is insulated and separated from the semiconductor of the semiconductor layer 21 by the insulating film of the pixel separation region 31.

[0265] As shown in FIG. 37, the conductive pad 71b is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation region 21a side of the photoelectric conversion cell 22R2 (pixel 3a2) in a plan view. And, the conductive pad 71b straddles the in-pixel separation region 32 in the X direction and overlaps with two p-type contact regions 48 disposed on both sides of this in-pixel separation region 32, and is electrically and mechanically connected. Further, the conductive pad 71b straddles the in-pixel separation region 32 adjacent to the in-pixel separation region 32 of the photoelectric conversion cell 22R2 to the photoelectric conversion cell (the photoelectric conversion cell 22R4 of another pixel block adjacent in the Y direction) on the side opposite to the photoelectric conversion cell 22R2 side of the pixel separation region 31, and overlaps with two p-type contact regions 48 disposed on both sides of this in-pixel separation region 32, and is electrically and mechanically connected. That is, the conductive pad 71b straddles the separation region including the pixel separation region 31 and the in-pixel separation region 32 in each of the X direction and the Y direction, overlaps with a plurality of p-type contact regions 48 disposed on both sides of this separation region, and is electrically and mechanically connected. In this embodiment, the conductive pad 71b is electrically and mechanically connected across the pixel separation region 31 and the in-pixel separation region 32 to each of the four contact regions 48 disposed so as to surround the intersection portion where the pixel separation region 31 extending in the X direction and the in-pixel separation region 32 extending in the Y direction intersect.

[0266] As shown in FIG. 42C, the conductive pad 71b has a body portion 71b1 located within the pixel isolation region 31, and a head portion 71b2 that protrudes from the body portion 71b1 to the outside of the pixel isolation region 31 and is wider than the body portion 71b1. The body portion 71b1 is in contact with the sidewall of the contact region 48 and is electrically and mechanically connected. The head portion 71b2 is in contact with the upper surface (surface layer) of the contact region 48 and is electrically and mechanically connected. That is, also in the conductive pad 71b, similar to the above-described conductive pad 71a, by arranging the body portion 71b1 within the pixel isolation region 31 so that the body portion 71b1 and the head portion 71b2 are in contact with the contact region 48, the contact area between the contact region 48 and the conductive pad 71b becomes larger.

[0267] Although not shown, at least one of the conductive pads 71a and 71b of the relay wiring 71 is electrically connected to the wiring on the interlayer insulating film via a contact electrode embedded in the upper interlayer insulating film. And a first reference potential is applied to this wiring as a power supply potential. Then, the first reference potential is supplied from this wiring to the relay wiring 71 via a conductive plug, and a plurality of contact regions 48 (p-type semiconductor regions) connected to each of the conductive pads 71a and 71b of the relay wiring 71 are fixed in potential to the first reference potential. As the first reference potential, for example, a VSS potential of 0V is applied.

[0268] As shown in FIG. 37, the conductive pad 72 is electrically and mechanically connected to semiconductor regions disposed on both sides of the pixel isolation region 31 across the pixel isolation region 31 between the photoelectric conversion cell 22R1 of the pixel 3a2 and the photoelectric conversion cell 22R2 of the pixel 3b2 in the X direction. Specifically, the conductive pad 72 overlaps with the main electrode region 47 of the reset transistor RST disposed on the photoelectric conversion cell 22R1 side of the pixel isolation region 31 and the main electrode region 47 of the amplification transistor AMP disposed on the photoelectric conversion cell 22R2 side of the pixel isolation region 31, and is electrically and mechanically connected.

[0269] As shown in FIG. 42D, the conductive pad 72 has a body portion 72a located within the pixel isolation region 31 and a head portion 72b that protrudes from the body portion 72a to the outside of the pixel isolation region 31 and is wider than the body portion 72a. The body portion 72a is in contact with the side wall of the main electrode region 47 (n-type semiconductor region) and is electrically and mechanically connected. The head portion 72b is in contact with the upper surface (surface layer) of the main electrode region 47 and is electrically and mechanically connected. That is, also in the case of the conductive pad 72, similar to the above-described conductive pad 71a, by arranging the body portion 72a within the pixel isolation region 31 such that the body portion 72a and the head portion 72b are in contact with the main electrode region 47, the contact area between the main electrode region 47 and the conductive pad 72 is increased.

[0270] Although not shown in the figure, the conductive pad 72 is electrically connected to the wiring on the interlayer insulating film via a contact electrode embedded in the upper interlayer insulating film. A second reference potential different from the first reference potential is applied to this wiring as the power supply potential. Then, the second reference potential is supplied from this wiring to the conductive pad 72 via a conductive plug, and a plurality of main electrode regions 47 (n-type semiconductor regions) connected to the conductive pad 72 are fixed in potential to the second reference potential. As the second reference potential, for example, a VDD potential of 3.0 V is applied.

[0271] As shown in FIG. 38, the relay wiring 73 includes two conductive pads 73a and 73b and a connecting portion 73c that connects the two conductive pads 73a and 73b. The conductive pad 73a is connected to one end side of the connecting portion 73c, and the conductive pad 73b is connected to the other end side of the connecting portion 73c. The conductive pad 73a and the conductive pad 73b are electrically and mechanically connected via the connecting portion. This relay wiring 73 overlaps the pixel isolation region 31 in plan view and extends along the X direction.

[0272] As shown in FIG. 38, the conductive pad 73a is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation region 21b1, 21b2 side of the photoelectric conversion cell 22R1 (pixel 3a2) in plan view. The conductive pad 73a straddles the in-pixel separation region 32 in the X direction and overlaps with two n-type charge holding regions FD1, FD2 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. Further, the conductive pad 73a is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation region 21b1, 21b2 side of the photoelectric conversion cell 22R3 (pixel 3c2) in plan view. The conductive pad 73a straddles the in-pixel separation region 32 in the X direction and overlaps with two n-type charge holding regions FD1, FD2 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. That is, the conductive pad 73a straddles the separation region including the pixel separation region 31 and the in-pixel separation region 32 in the X direction and the Y direction, respectively, and overlaps with a plurality of n-type charge holding regions FD1, FD2 disposed on both sides of the separation region, and is electrically and mechanically connected. In this embodiment, the conductive pad 73a is electrically and mechanically connected across the pixel separation region 31 and the in-pixel separation region 32 to each of the four charge holding regions FD1, FD2 disposed so as to surround the intersection where the pixel separation region 31 extending in the X direction and the in-pixel separation region 32 extending in the Y direction intersect.

[0273] As shown in FIG. 43A, the conductive pad 73a has a body portion 73a1 located in the pixel separation region 31, and a head portion 73a2 that protrudes from the body portion 73a1 to the outside of the pixel separation region 31 and is wider than the body portion 73a1. The body portion 73a1 is in contact with the side walls of the charge holding regions FD1, FD2 and is electrically and mechanically connected. The head portion 73a2 is in contact with the upper surface (surface layer) of the charge holding regions FD1, FD2 and is electrically and mechanically connected. That is, also in this conductive pad 73a, by disposing the body portion 73a1 in the pixel separation region 31 so that the body portion 73a1 and the head portion 73a2 are in contact with the charge holding regions FD1, FD2, the contact area between the charge holding regions FD1, FD2 and the conductive pad 73a becomes large, similar to the above-described conductive pad 71a.

[0274] As shown in FIG. 38, the connecting portion 73c extends across the pixel separation region 31 over the pixels 3a2 and 3c2 and the pixels 3b2 and 3d2. As shown in FIG. 43B, the connecting portion 73c extends across the inside and outside of the pixel separation region 31 in the thickness direction of the semiconductor layer 21. And, the width of the portion of the connecting portion 73c located inside the pixel separation region 31 is smaller than the width of the pixel separation region 31, and the semiconductor layer 21 is insulated and separated from the semiconductor by the insulating film of the pixel separation region 31.

[0275] As shown in FIG. 38, the conductive pad 73b is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation regions 21b1 and 21b2 sides of the photoelectric conversion cell 22R2 (pixel 3b2) in plan view. And, the conductive pad 73b straddles the in-pixel separation region 32 in the X direction and overlaps with two n-type charge holding regions FD1 and FD2 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. Further, the conductive pad 73b is disposed at a portion where the pixel separation region 31 and the in-pixel separation region 32 intersect on the element formation regions 21b1 and 21b2 sides of the photoelectric conversion cell 22R4 (pixel 3d2) in plan view. And, the conductive pad 73b straddles the in-pixel separation region 32 in the X direction and overlaps with two n-type charge holding regions FD1 and FD2 disposed on both sides of the in-pixel separation region 32, and is electrically and mechanically connected. That is, the conductive pad 73b straddles the separation region including the pixel separation region 31 and the in-pixel separation region 32 in the X direction and the Y direction respectively, and overlaps with a plurality of n-type charge holding regions FD1 and FD2 disposed on both sides of the separation region, and is electrically and mechanically connected. In this embodiment, the conductive pad 73b is electrically and mechanically connected across the pixel separation region 31 and the in-pixel separation region 32 to each of the four charge holding regions FD1 and FD2 disposed so as to surround the intersection portion where the pixel separation region 31 extending in the X direction and the in-pixel separation region 32 extending in the Y direction intersect.

[0276] As shown in FIG. 43C, the conductive pad 73b has a body portion 73b1 located within the pixel isolation region 31, and a head portion 73b2 that protrudes from the body portion 73b1 to the outside of the pixel isolation region 31 and is wider than the body portion 73b1. The body portion 73b1 is in contact with the sidewalls of the charge holding regions FD1 and FD2 and is electrically and mechanically connected. The head portion 73b2 is in contact with the upper surfaces (surface layers) of the charge holding regions FD1 and FD2 and is electrically and mechanically connected. That is, also in the case of the conductive pad 73b, similar to the above-described conductive pad 71a, by disposing the body portion 73b1 within the pixel isolation region 31 such that the body portion 73b1 and the head portion 73b2 are in contact with the charge holding regions FD1 and FD2, the contact area between the charge holding regions FD1 and FD2 and the conductive pad 73b is increased.

[0277] Although not shown in the figure, at least one of the conductive pads 73a and 73b is electrically connected to a wiring on the interlayer insulating film via a contact electrode embedded in the upper interlayer insulating film. And this contact electrode, the wiring, and the relay wiring 73 are included in the conductive path 63 shown in FIG. 35. And a plurality of charge holding regions FD1 and FD2 connected to each of the conductive pads 73a and 73b of the relay wiring are electrically connected to the readout circuit 15 shown in FIG. 35 via the conductive path 63 including the relay wiring 73, the contact electrode, and the wiring.

[0278] Each of the relay wiring 71, the conductive pad 72, the relay wiring 73, and the conductive pad 74 is, but not limited to, for example, composed of a polycrystalline silicon film into which impurities for reducing the resistance value are introduced.

[0279] As shown in FIG. 39, the conductive pad 74 straddles the pixel separation region 31 between the photoelectric conversion cell 22R3 of pixel 3c2 and the photoelectric conversion cell 22R4 of pixel 3d2 in the X direction, and is electrically and mechanically connected to the semiconductor regions disposed on both sides of this pixel separation region 31. Specifically, the conductive pad 74 overlaps with the main electrode region 47 of the amplification transistor AMP disposed on the photoelectric conversion cell 22R3 side of the pixel separation region 31 and the main electrode region 47 of the amplification transistor AMP disposed on the photoelectric conversion cell 22R4 side of the pixel separation region 31, and is electrically and mechanically connected.

[0280] Although not shown, the conductive pad 74 has the same configuration as the above-described conductive pad 72. And, similar to the conductive pad 72, the second reference potential is supplied to the conductive pad 72 from the upper layer wiring via the contact electrode (conductive plug), and a plurality of main electrode regions 47 (n-type semiconductor regions) connected to the conductive pad 72 are fixed in potential to the second reference potential. Also in the conductive pad 74, similar to the above-described conductive pad 72, the contact area between the main electrode region 47 and the conductive pad 72 becomes large.

[0281] As shown in FIG. 39, the amplification transistor AMP of the photoelectric conversion cell 22R3 (pixel 3c2) and the amplification transistor AMP of the photoelectric conversion cell 224 (pixel 3d2) share the gate electrode 45a disposed across the pixel separation region 31 between the photoelectric conversion cell 22R3 and the photoelectric conversion cell 224 in the X direction and extending across the photoelectric conversion cell 22R3 and the photoelectric conversion cell 224.

[0282] As shown in FIG. 44, the gate electrode 45a has a body portion 45a1 adjacent to the p-type semiconductor region 24 via the gate insulating film 44 within the pixel separation region 31, and a head portion 45a2 that protrudes from this body portion 45b1 to the outside of the pixel separation region 31, is adjacent to the p-type semiconductor region 24 via the gate insulating film 44, and is wider than the body portion 45a1.

[0283] <Main Effects of the 19th Embodiment> Next, the main effects of this 19th embodiment will be described. Also in the solid-state imaging device 1H according to this 19th embodiment, each element formation region 21a of the photoelectric conversion cells 22R1, 22R2, 22R3, 22R4 extends across the first photoelectric conversion region 23L and the second photoelectric conversion region 23R, and crosses between the two pixel internal separation regions 32 in a plan view. Therefore, also in the solid-state imaging device 1H according to this 19th embodiment, the same effects as those of the solid-state imaging device 1A according to the above-described 19th embodiment can be obtained.

[0284] Further, in the solid-state imaging device 1H according to this embodiment, the conductive pads 71a, 71b straddle a separation region including the pixel separation region 31 and the pixel internal separation region 32 in each of the X direction and the Y direction, and are connected to a plurality of p-type contact regions (p-type semiconductor regions) 48 arranged on both sides of this separation region. In this case, by connecting one contact electrode to the conductive pads 71a, 71b, a potential can be supplied to the plurality of contact regions 48 connected to the conductive pads 71a, 71b. As a result, compared with the case where a contact electrode is connected to each of the plurality of contact regions 48, it is not necessary to consider the misalignment between the contact region 48 and the contact electrode for each contact region 48. Therefore, it is possible to reduce the planar size (occupied area) of the contact region 48, and it is possible to increase the degree of freedom in arranging active elements including the pixel transistors Qt (AMP, SEL, RST) and the transfer transistors TR1, TR2 within the photoelectric conversion cells 22R1, 22R2, 22R3, 22R4 (pixels 3a2, 3b2, 3c2, 3d2). Also, since the degree of freedom in arranging the active elements within the photoelectric conversion cells 22R1, R2, R3, R4 can be increased, it is possible to miniaturize the pixels 3a2, 3b2, 3c2, 3d2 including the photoelectric conversion cells 22R1, R2, R3, R4.

[0285] Further, the conductive pad 71a is arranged such that the body portion 71a1 and the head portion 71a2 are in contact with the contact region 48 by disposing the body portion 71a1 within the pixel isolation region 31. As a result, the contact area between the contact electrode 48 and the conductive pad 71a increases. Therefore, the contact resistance between the contact electrode and the conductive pad 71a can be reduced, and it becomes possible to reduce the planar size of the contact region while ensuring the contact resistance between the contact electrode and the conductive pad 71a. Similarly, in the case of the conductive pad 71b, it is also possible to reduce the planar size of the contact region 48 while ensuring the contact resistance between the contact electrode and the conductive pad 71b.

[0286] Also, the conductive pad 71a and the conductive pad 71b are electrically connected via a connecting portion. Therefore, by connecting a contact electrode to either one of the conductive pad 71a and the conductive pad 71b, it is possible to supply a potential to a plurality of contact regions connected to the conductive pad 71a and to supply a potential to a plurality of conductive pads connected to the conductive pad 71b. As a result, the degree of freedom in routing the wiring in the upper wiring layer is increased.

[0287] Further, the conductive pad 72 straddles the pixel isolation region 31 in the Y direction between the photoelectric conversion cells 22R1 of the pixel 3a2 and the photoelectric conversion cells 22R2 of the pixel 3b2 and is connected to the main electrode regions (semiconductor regions) 47 disposed on both sides of the pixel isolation region 31. Therefore, also in this conductive pad 72, compared with the case where a contact electrode is connected to each main electrode region 47, it is not necessary to consider the misalignment between the main electrode region 47 and the contact electrode for each main electrode region 47. Thus, it becomes possible to reduce the planar size (occupied area) of the main electrode region 47, and it becomes possible to increase the degree of freedom in arranging the photoelectric conversion cells 22R1, R2, R3, R4 (pixels 3a2, 3b2, 3c2, 3d2) of the active elements including the pixel transistors Qt (AMP, SEL, RST) and the transfer transistors TR1, TR2.

[0288] This conductive pad 72 also has a shape having a body portion 72a and a wide head portion 72b, similar to the above-described conductive pads 71a and 71b. Therefore, by disposing the body portion 72a within the pixel isolation region 31 so that the body portion 72a and the head portion 72b come into contact with the main electrode region 47, the contact area between the main electrode region 47 and the conductive pad 72 is increased. For this reason, the contact resistance between the main electrode region 47 and the conductive pad 72 can be reduced, and it becomes possible to reduce the planar size of the main electrode region 47 while ensuring the contact resistance between the main electrode region 47 and the conductive pad 72.

[0289] Also, the conductive pads 73a and 73b are connected to a plurality of charge holding regions (n-type semiconductor regions) FD1 and FD2 disposed on both sides of this isolation region, straddling the isolation region including the pixel isolation region 31 and the in-pixel isolation region 32 in the X direction and the Y direction, respectively. Therefore, also in these conductive pads 73a and 73b, similar to the above-described conductive pads 71a and 71b, compared with the case where a contact electrode is connected for each of the plurality of charge holding regions FD1 and FD2, it is not necessary to consider the misalignment between the charge holding regions FD1 and FD2 and the contact electrodes for each of the charge holding regions FD1 and FD2. Thus, it becomes possible to reduce the planar size (occupied area) of the charge holding regions FD1 and FD2, and it becomes possible to increase the degree of freedom in arranging the active elements including the pixel transistors Qt (AMP, SEL, RST) and the transfer transistors TR1 and TR2 within the photoelectric conversion cells 22R1, R2, R3, and R4 (pixels 3a2, 3b2, 3c2, and 3d2). Further, since the degree of freedom in arranging the active elements within the photoelectric conversion cells 22R1, R2, R3, and R4 can be increased, it becomes possible to miniaturize the pixels 3a2, 3b2, 3c2, and 3d2 including the photoelectric conversion cells 22R1, R2, R3, and R4.

[0290] Also in this conductive pad 73a, since it has a shape having a body portion 73a1 and a wide head portion 73a2 similar to the above-described conductive pads 71a and 71b, by arranging the body portion 73a1 within the pixel isolation region 31 so that the body portion 73a1 and the head portion 73a2 come into contact with the charge holding regions FD1 and FD2, the contact area between the charge holding regions FD1 and FD2 and the conductive pad 73a increases. For this reason, the contact resistance between the charge holding regions FD1 and FD2 and the conductive pad 73a can be reduced, and it becomes possible to reduce the planar size of the charge holding regions FD1 and FD2 while ensuring the contact resistance between the contact electrode and the conductive pad 73a. Similarly, also in the conductive pad 73b, it becomes possible to reduce the planar size of the contact region 48 while ensuring the contact resistance between the charge holding regions FD1 and FD2 and the conductive pad 73a.

[0291] Further, the conductive pad 73a and the conductive pad 73b are electrically connected via a connecting portion 73c. Therefore, by connecting a contact electrode to either one of the conductive pad 73a and the conductive pad 73b, it is possible to supply a potential to the plurality of charge holding regions FD1 and FD2 connected to the conductive pad 73a, and it is also possible to supply a potential to the plurality of charge holding regions FD1 and FD2 connected to the conductive pad 73b. As a result, the degree of freedom in routing in the upper wiring layer increases.

[0292] Also, the amplification transistor AMP of the photoelectric conversion cell 22R3 (pixel 3c2) and the amplification transistor AMP of the photoelectric conversion cell 224 (pixel 3d2) share a gate electrode 45a across the pixel isolation region 31 in the X direction. Therefore, a contact electrode can be connected to the gate electrode 45a on the pixel isolation region 31, and the degree of freedom in routing in the upper wiring layer increases.

[0293] In addition, since the gate electrode 45a has a shape having a trunk portion 72a and a wide head portion 72b, by arranging the trunk portion 72a within the pixel isolation region 31 so that the trunk portion 72a and the head portion 72b face the p-type semiconductor region via the gate insulating film, the gate width Wg of the amplification transistor AMP can be increased, and noise reduction can be achieved without increasing the planar size of the amplification transistor AMP.

[0294] In addition, by combining the arrangement of the element formation region 21a and the connection form of any of the conductive pads 71a, 71b, 72, 73a, and 73b, it becomes possible to further increase the degree of freedom in arranging active elements and to further miniaturize the pixel 3 including the photoelectric conversion cell.

[0295] In addition, by increasing the degree of freedom in arranging active elements within the photoelectric conversion cell, the volume of the photoelectric conversion portion can be increased at the planar size of the same pixel 3, and the saturation signal amount Qs can be improved.

[0296] In the above-described Embodiment 19, the photoelectric conversion cell 22R1 of the pixel 3a2 omits the arrangement of the pixel transistors on the first photoelectric conversion region 23L side. However, in order to ensure the layout symmetry, as shown in FIG. 45 of the modified example, a dummy gate electrode 45b may be provided on the first photoelectric conversion region 23L side of the photoelectric conversion cell 22R1.

[0297] In addition, a switching transistor may be arranged on the first photoelectric conversion region 23L side of the photoelectric conversion cell 22R1 according to the element configuration of the readout circuit.

[0298] 〔Embodiment 20〕 In this 20th embodiment, the connection state between the wiring of the first-layer wiring layer and the conductive pad will be described. FIG. 46 is a view showing two pixel blocks 61H shown in FIG. 36 arranged in the X direction. Among the two pixel blocks 61H, a relay wiring 73 is provided in one pixel block 61H1, while in the other pixel block 51H2, conductive pads 73a and 73b are provided independently instead of the relay wiring 73.

[0299] As shown in FIG. 46, wirings 77, 78, and 79 are routed through the two pixel blocks 61H1 and 61H2. As shown in FIG. 47, the wiring 77 is provided in the first wiring layer on the interlayer insulating film 75. Although not shown, similarly, the wirings 78 and 79 are also provided in the wiring layer of the first layer.

[0300] As shown in FIG. 46, the wiring 77 extends along the Y direction on the pixel isolation region 31 between the pixel block 61H1 and the pixel block 61H2. Further, the wiring 77 extends along the X direction on the pixel isolation region 31 that extends in the X direction with the two pixel blocks 61H (61H1, 61H2) interposed therebetween.

[0301] Then, as shown in FIG. 47, the wiring 77 is electrically and mechanically connected to the conductive pad 71b via a contact electrode (conductive plug) 76 embedded in the interlayer insulating film 75 on the pixel isolation region 31. Also, although not shown in detail, the wiring 77 is electrically connected to the conductive pad 71b via a contact electrode 76 embedded in the interlayer insulating film 75 on the pixel isolation region 31. The contact electrode 76 is preferably connected to the conductive pad 71b at a position where at least a part of the contact electrode 76 overlaps with the pixel isolation region 31 in a plane. In this way, by connecting the wiring 77 to the conductive pad 71b via the contact electrode 76 on the pixel isolation region 31 that was originally a dead space, the degree of freedom in routing the wiring is increased.

[0302] As shown in FIG. 46, the wiring 78 is disposed in one pixel block 61H1. The wiring 78 traverses the conductive pad 73b in the Y direction in a plan view and extends over two photoelectric conversion cells 22R2 and 22R4 arranged in the Y direction (on pixels 3b2 and 3d2). Although not shown in detail, the wiring 78 is electrically connected to the conductive pad 73b via the contact electrode 76 on the pixel isolation region 31, similar to the conductive pad 71b. Then, the wiring 78 bends from one end on the side of the photoelectric conversion cell 22R2 in the portion extending in the Y direction toward the photoelectric conversion cell 22R1 side and extends over the gate electrode 45 of the amplification transistor AMP in the photoelectric conversion cell 22R2. Although not shown in detail, the wiring 78 is electrically connected to the gate electrode 45 of the amplification transistor AMP disposed in the photoelectric conversion cell 22R2 via the contact electrode. Further, the wiring 78 bends from the other end on the side of the photoelectric conversion cell 22R4 in the portion extending in the Y direction toward the photoelectric conversion cell 22R3 side and extends over the gate electrode 45 of the amplification transistor AMP in the photoelectric conversion cell 22R4. Although not shown in detail, the wiring 78 is electrically connected to the gate electrode 45 of the amplification transistor AMP disposed in the photoelectric conversion cell 22R4 via the contact electrode.

[0303] By connecting the wiring 78 to the conductive pad 73b via the contact electrode on the pixel isolation region 31, which was originally a dead space, the degree of freedom in routing the wiring 78 is increased.

[0304] As shown in FIG. 46, the wiring 79 is disposed in the other pixel block 61H2. The wiring 79 crosses the pad 73b in the Y direction in plan view and extends over two photoelectric conversion cells 22R2 and 22R4 arranged in the Y direction (on pixels 3b2 and 3d2). Although not shown in detail, the wiring 79 is electrically and mechanically connected to the pad 73b via the contact electrode 76 on the pixel isolation region 31, similar to the conductive pad 71b. Then, the wiring 79 bends from one end on the side of the photoelectric conversion cell 22R2 in the portion extending in the Y direction toward the photoelectric conversion cell 22R1 side, and extends over the gate electrode 45 of the amplification transistor AMP in the photoelectric conversion cell 22R2. Although not shown in detail, the wiring 79 is electrically connected to the gate electrode 45 of the amplification transistor AMP disposed in the photoelectric conversion cell 22R2 via a contact electrode. Also, the wiring 79 bends from the other end on the side of the photoelectric conversion cell 22R4 in the portion extending in the Y direction toward the photoelectric conversion cell 22R3 side, and extends over the gate electrodes 45 of the amplification transistors AMP of each of the photoelectric conversion cells 22R4 and 22R3. Although not shown in detail, the wiring 79 is electrically connected to the gate electrodes 45 of the amplification transistors AMP disposed in each of the photoelectric conversion cells 22R4 and 22R3 via contact electrodes, respectively.

[0305] Also, the wiring 79 bends from one end on the side of the photoelectric conversion cell 22R3 in the portion extending over the photoelectric conversion cells 22R3 and 22R4 toward the photoelectric conversion cell 22R1 side, and terminates on the conductive pad 73a. Although not shown in detail, the wiring 79 is electrically connected to the conductive pad 73a via the contact electrode 76 on the pixel isolation region 31, similar to the conductive pad 71b.

[0306] In this way, by connecting the wiring 79 to the conductive pad 73b via the contact electrode on the pixel isolation region 31, which was originally a dead space, and connecting the wiring 79 to the conductive pad 73a via the contact electrode on the pixel isolation region 31, the degree of freedom in routing the wiring 79 is increased.

[0307] 〔21st Embodiment〕 The solid-state imaging device 1J according to the 21st embodiment of the present technology includes a pixel block 61J and a readout circuit 15J shown in FIGS. 48 and 49. As shown in FIG. 49, the pixel block 61J includes a plurality of pixels 3. In this 21st embodiment, the pixel block 61J includes, but is not limited to, for example, four pixels 3 (3a3, 3b3, 3c3, 3d3) arranged in a 2×2 array of two in each of the X direction and the Y direction in a plan view. Although mainly one pixel block 61J is illustrated in FIG. 49, the pixel blocks 61J are repeatedly arranged in each of the X direction and the Y direction.

[0308] As shown in FIG. 48, each of the four pixels 3a3, 3b3, 3c3, 3d3 includes a photoelectric conversion cell 22S. The photoelectric conversion cell 22S includes a photoelectric conversion element PD, a charge holding region (Floating Diffusion) FD that holds (accumulates) the signal charge photoelectrically converted by this photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charge photoelectrically converted by this photoelectric conversion element PD to the charge holding region FD. The photoelectric conversion cell 22S of this embodiment has one photoelectric conversion region 22S, which is different from the photoelectric conversion cell 22A of the first embodiment described above.

[0309] The photoelectric conversion element PD generates a signal charge according to the amount of received light. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground). As the photoelectric conversion element PD, for example, a photodiode is used.

[0310] The drain region of the transfer transistor TR is electrically connected to the charge accumulation region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line among the pixel drive lines 10 (see FIG. 2). The charge accumulation region FD temporarily accumulates and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0311] As shown in FIG. 48, the input stage of the readout circuit 15J is connected to the charge holding region FD of each of the four pixels 3a3, 3b3, 3c3, and 3d3. The readout circuit 15J reads the signal charges held in the charge holding regions FD of the four pixels 3a3, 3b3, 3c3, and 3d3 and outputs a pixel signal based on the signal charges. The readout circuit 15J is shared by the four pixels 3a3, 3b3, 3c3, and 3d3 (four photoelectric conversion cells 22S) included in one pixel block 61J and is provided for each pixel block 61J.

[0312] The readout circuit 15J includes, but is not limited to, a switching transistor FDG, a reset transistor RST, and one amplification stage cell Pc1. This readout circuit 15J basically has the same configuration as the readout circuit 15C shown in FIG. 25 of the above-described 14th embodiment, and the number of amplification stage cells is different.

[0313] The readout circuit 15J is composed of pixel transistors included in the circuit block 62J shown in FIG. 50. Different from the circuit block 62C shown in FIG. 25 of the above-described 14th embodiment, the circuit block 62J includes a switching transistor FDG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL provided for each pixel block 61J. These pixel transistors (FDG, RST, AMP, SEL) are provided in a semiconductor layer 140 laminated via an insulating layer 130 on a semiconductor layer 101 having a photoelectric conversion element PD and a transfer transistor TR, which will be described in detail later.

[0314] ≪Specific Configuration of Solid-State Imaging Device≫ Next, the specific configuration of the solid-state imaging device 1J of this embodiment will be described. As shown in FIG. 52, the solid-state imaging device 1J includes a semiconductor layer 101 having a first surface S1 and a second surface S2 located on opposite sides in the thickness direction, and a photoelectric conversion cell 22S provided by being partitioned by a separation region 110 in the semiconductor layer 101. The solid-state imaging device 1J also includes a semiconductor layer 140 laminated via an insulating layer 1300 on the first surface S1 side of the semiconductor layer 101. The solid-state imaging device 1J also includes, on the second surface S2 side of the semiconductor layer 101, a planarization film 161, a light-shielding film 162, a color filter 163, and a microlens 164 laminated in sequence from the second surface S2 side.

[0315] The planarization film 161 is provided on the second surface S2 side of the semiconductor layer 101 so as to cover the second surface S2 of the semiconductor layer 101, and planarizes the second surface S2 side of the semiconductor layer 101. The light-shielding film 162 has a lattice-shaped planar pattern in a plan view so as to partition adjacent pixels 3. The color filter 163 and the microlens 164 are each provided for each pixel 3. The color filter 163 separates incident light incident from the light incident surface side of the semiconductor layer 101 by color. The microlens 164 condenses the irradiation light and efficiently makes the condensed light enter the pixel 3.

[0316] Here, the first surface S1 of the semiconductor layer 101 may also be referred to as an element formation surface or a main surface, and the second surface S2 side may be referred to as a light incident surface or a back surface. The solid-state imaging device 1J of this embodiment photoelectrically converts light incident from the second surface (light incident surface, back surface) S2 side of the semiconductor layer 101 with a photoelectric conversion unit 103 (photoelectric conversion element PD) provided in the semiconductor layer 101. The semiconductor layer 101 is composed of, for example, a p-type semiconductor substrate made of single crystal silicon.

[0317] <Separation region> As shown in FIG. 52, the separation region 110 extends from the first surface S1 side to the second surface S2 side of the semiconductor layer 101, and electrically and optically separates between adjacent pixels 3 in a two-dimensional plane. The separation region 110 is not limited to this, but for example, has a trench separation structure in which an insulating film is embedded in a groove extending from the first surface S1 to the second surface S2 side of the semiconductor layer 101. In this embodiment, the separation region 110 is not limited to this, but for example, extends across the first surface S1 and the second surface S2 of the semiconductor layer 101.

[0318] As shown in FIG. 49, the separation region 110 corresponding to one pixel 3 (one photoelectric conversion cell 22S) has an annular planar pattern (ring-shaped planar pattern) with a square planar shape in plan view. And the separation regions 110 corresponding to the four pixels 3 (3a3, 3b3, 3c3, 3d3) of the pixel block 61J have a composite planar pattern having a lattice-shaped planar pattern in the annular planar pattern with a square shape surrounding the four pixels 3 in plan view.

[0319] As shown in FIG. 52, the photoelectric conversion cells 22S are provided for each pixel 3. In FIG. 52, among the four pixels 3a3, 3b3, 3c3, 3d3 included in one pixel block 61J shown in FIG. 49, two pixels 3a3, 3b3 are illustrated. As shown in FIG. 52, the photoelectric conversion cell 22S has a p-type semiconductor region 102. Also, the photoelectric conversion cell 22S has a transfer transistor TR, a charge holding region FD, and a contact region 121 on the first surface S1 side of the semiconductor layer 101, and has a photoelectric conversion portion 103 on the second surface S2 side of the semiconductor layer 101. Further, the photoelectric conversion cell 22S has a p-type semiconductor region 105 and a pinning film 106.

[0320] <Photoelectric conversion portion> The photoelectric conversion portion 103 is surrounded by the p-type semiconductor region 102. The photoelectric conversion portion 103 includes an n-type semiconductor region 104. And this photoelectric conversion portion 103 constitutes the above-described photoelectric conversion element PD.

[0321] <p-type semiconductor region> As shown in FIG. 52, the p-type semiconductor region 102 is provided between the photoelectric conversion portion 103 and the first surface S1 of the semiconductor layer 101, and between the photoelectric conversion portion 103 and the second surface S2 of the semiconductor layer 101, respectively. Also, the p-type semiconductor region 102 is provided between the photoelectric conversion portion 103 and the separation region 110.

[0322] <Transfer transistor> As shown in FIG. 52, the transfer transistor TR includes a gate electrode 124 provided on the first surface S1 side of the semiconductor layer 101 via a gate insulating film, a channel formation region in which a channel is formed in a p-type semiconductor region 102 directly under the gate electrode 124, a photoelectric conversion unit 103 functioning as a source region, and a charge holding region FD functioning as a drain region. The gate insulating film is made of, for example, a silicon oxide film. The gate electrode 124 is made of, for example, a polycrystalline silicon film into which impurities for reducing the resistance value are introduced. The transfer transistor TR is a field effect transistor and is composed of, for example, a MOSFET. The transfer transistor TR may be composed of a MISFET.

[0323] As shown in FIG. 49, each transfer transistor TR of the four photoelectric conversion cells 22S (pixels 3a3, 3b3, 3c3, 3d3) included in the pixel block 61J is disposed offset from the center of each photoelectric conversion cell 22S (pixels 3a3, 3b3, 3c3, 3d3) toward the corner in a plan view. And each transfer transistor TR of these four photoelectric conversion cells 22S is disposed offset toward the central side surrounded by the four photoelectric conversion cells 22S (four pixels 3a3, 3b3, 3c3, 3d3) in a 2×2 array. That is, the gate electrodes 124 of the transfer transistors TR of each of the four pixels 3 (four pixels 3a3, 3b3, 3c3, 3d3) are adjacent to each other in each of the X direction and the Y direction.

[0324] <Charge holding region> As shown in FIG. 52, the charge holding region FD is provided in the p-type semiconductor region 102 on the first surface S1 side of the semiconductor layer 101 and is separated from the photoelectric conversion unit 103 via the p-type semiconductor region 102. The charge holding region FD is composed of, for example, an n-type semiconductor region having a higher impurity concentration than the photoelectric conversion unit 103. The charge holding region FD holds charges and reduces the ohmic contact resistance with a conductive pad 122 described later.

[0325] As shown in FIG. 51, the charge holding region FD is provided in contact with a first intersection portion 111a located at the center of a pixel block 61J having four pixels 3 (four photoelectric conversion cells 22S) as one unit among the intersection portions where the separation region 110 extending in the X direction and the separation region 110 extending in the Y direction intersect. That is, the charge holding regions FD of each of the four pixels 3 included in the pixel block 61J are arranged so as to surround the first intersection portion 111a and are adjacent to each other via the separation region 110 in plan view.

[0326] <Contact region> As shown in FIG. 52, the p-type contact region 121 is provided in the p-type semiconductor region 102 on the first surface S1 side of the semiconductor layer 101 and is electrically connected to the p-type semiconductor region 102. The contact region 121 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type semiconductor region 102, and reduces the ohmic contact resistance with the conductive pad 123 described later.

[0327] As shown in FIG. 51, the p-type contact region 121 is provided in contact with a second intersection portion 111b located at a corner of a pixel block 61J having four pixels 3 (four photoelectric conversion cells 22S) as one unit among the intersection portions where the separation region 110 extending in the X direction and the separation region 110 extending in the Y direction intersect. That is, the contact regions 121 of each of the four pixels 3 included in the pixel block 61J are arranged so as to surround the second intersection portion 111b and are adjacent to each other via the separation region 110 in plan view.

[0328] As shown in FIGS. 49 and 52, in pixel block 61J, the conductive pads 122 described above are electrically and mechanically connected to the charge holding regions FD of each of the four photoelectric conversion cells 22S arranged via the first intersection portion 111a of the separation region 110 across the first intersection portion 111a of the separation region 110. Further, at the corner of the pixel block 61J, the conductive pads 123 described above are electrically and mechanically connected to the contact regions 121 of each of the four photoelectric conversion cells 22S arranged via the second intersection portion 111b of the separation region 110 across the second intersection portion 111b of the separation region 110. Each of the conductive pads 122 and 123 is composed of, for example, a polycrystalline silicon film into which impurities for reducing the resistance value are introduced.

[0329] As shown in FIG. 51, the separation region 110 includes a first portion 110a in contact with the charge holding region FD in plan view and a second portion 110b in contact with the contact region 121, and the width W2 of the second portion 110b is narrower than the width W1 of the first portion 110a. The first portion 110a of the separation region 110 is configured to be longer than the portion in contact with the charge holding region FD in plan view and protrudes in the extending direction from the portion in contact with the charge holding region FD. The ratio of the first portion 110a to the second portion 110b of the separation region 110 is larger for the second portion 110b in a circulating planar pattern surrounding one photoelectric conversion cell 22S.

[0330] As shown in FIG. 53, the first portion 110a of the separation region 110 includes a head (surface portion) 110a1 provided on the first surface S1 side of the semiconductor layer 101 and a body portion (deep layer portion) 110a2 that is provided in contact with the head 110a1 at a position deeper than the head 110a1 in the thickness direction (Z direction) of the semiconductor layer 101 and has a narrower width than the head 110a1. The head 110a1 is longer, that is, deeper than the charge holding region FD in the depth direction of the semiconductor layer 101.

[0331] As shown in FIG. 52, the p-type semiconductor region 105 extends along the sidewall of the separation region 110 in the depth direction of the semiconductor layer 101 and is in contact with the p-type semiconductor region 102. In the first portion 110a of the separation region 110, the p-type semiconductor region 105 extends from the stepped portion between the head portion 110a1 and the body portion 110a2 toward the second surface S2 side of the semiconductor layer 101. In the second portion 110b, the p-type semiconductor region 105 is in contact with the contact region 121 and extends from the contact region 121 toward the second surface S2 side of the semiconductor layer 101. That is, the p-type semiconductor region 105 extends in the depth direction of the semiconductor layer 101 adjacent to each of the body portion 110a2 of the first portion 110a and the second portion 110b. This p-type semiconductor region 105 surrounds the periphery of the photoelectric conversion portion 103 in plan view and functions as a pinning layer for controlling the generation of dark current. The p-type semiconductor region 105 has a higher impurity concentration than the p-type semiconductor region 102 and a lower impurity concentration than the p-type contact region 121.

[0332] As shown in FIGS. 52 and 53, the pinning film 106 is interposed between the separation region 110 and the p-type semiconductor region and the p-type contact region to control the generation of dark current. As the pinning film 106, for example, hafnium oxide (HfO2), tantalum oxide (Ta2O5), or the like can be used. In this embodiment, the pinning film 106 is provided. However, when the pinning film 106 is not provided, the p-type semiconductor region 105 extends in the thickness direction of the semiconductor layer 101 in contact with each of the body portion 110a2 of the first portion 110a and the second portion 110b of the separation region 110.

[0333] As shown in FIG. 52, the insulating layer 130 covers the conductive pads 122 and 123 and the gate electrode 124 of the transfer transistor TR. The insulating layer 130 is composed of, for example, a silicon oxide (SiO) film, a silicon nitride (SiN) film, or a silicon carbonitride (SiON) film, or a laminated film formed by laminating two or more of these films.

[0334] As shown in FIG. 52, the semiconductor layer 140 includes island-shaped element formation regions 142a and 142b made of semiconductor, an insulating film 143 provided so as to fill the space between the element formation region 142a and the element formation region 142b, and insulating films 141 provided on the insulating layer 130 side of each of the element formation regions 142a and 142b. The element formation regions 142a and 142b are provided for each pixel block 61J.

[0335] As shown in FIGS. 50 and 52, in the element formation region 142a, an amplification transistor AMP and a selection transistor SEL are arranged in series connection. In the element formation region 142b, a switching transistor FDG and a reset transistor RST are arranged in series connection. In the amplification transistor AMP and the selection transistor SEL, one of a pair of main electrode regions that function as a source region and a drain region is shared. Also, in the switching transistor FDG and the reset transistor RST, one of a pair of main electrode regions that function as a source region and a drain region is shared. In FIG. 50, gate electrodes 145a, 145s, 145f, and 145r of the amplification transistor AMP, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST are shown. In FIG. 52, gate electrodes 145a and 145r of the amplification transistor AMP and the reset transistor RST are shown.

[0336] As shown in FIG. 52, the semiconductor layer 140 is covered with an insulating layer 146. A contact electrode 147a embedded in a connection hole reaching from the surface of the insulating layer 146 to the surface of the conductive pad 122 is electrically and mechanically connected to the conductive pad 122. A contact electrode 147b embedded in a connection hole reaching from the surface of the insulating layer 146 to the surface of the conductive pad 123 is electrically and mechanically connected to the conductive pad 123. A contact electrode 147a embedded in a connection hole reaching from the surface of the insulating layer 146 to the surface of the conductive pad 122 is electrically and mechanically connected to the gate electrode 124 of the transfer transistor TR.

[0337] As shown in FIG. 52, a contact electrode embedded in a connection hole reaching the gate electrode 145a from the surface of the insulating layer 146 is connected to the gate electrode 145a of the amplification transistor AMP. A contact electrode 147e embedded in a connection hole reaching the gate electrode 145r from the surface of the insulating layer 146 is connected to the gate electrode 145r of the reset transistor RST. Although not shown, similarly, contact electrodes embedded in connection holes reaching the gate electrodes of the selection transistor SEL and the switching transistor FDG from the surface of the insulating layer 146 are also connected.

[0338] A reference potential is applied to the contact electrode 147b as a power supply potential. Then, the p-type semiconductor region 102 of each pixel 3 is fixed at the reference potential via the contact electrode 147b, the conductive pad 123, and the contact region 121. In this first embodiment, for example, a Vss potential of 0 V is applied as the reference potential.

[0339] <Effect of the 21st Embodiment> The solid-state imaging device 1J of this 21st embodiment has a separation region 110 including a first portion 110a in contact with the charge holding region in plan view and a second portion 110b in contact with the contact region 121 and having a width W2 narrower than the width W1 of the first portion 110a. Thereby, while suppressing dark current, the area of the photoelectric conversion unit 103 (photoelectric conversion element PD) can be maximized. Also, compared with the case where the photoelectric conversion cell 22S is surrounded by the first portion, the planar area of the photoelectric conversion cell 22S increases by an amount corresponding to the length of the second portion in plan view, so that the degree of freedom in arranging active elements including the transfer transistor TR within the photoelectric conversion cell 22S can be increased.

[0340] In this embodiment, a solid-state imaging device 1J in which a photoelectric conversion cell, a transfer transistor, and a pixel transistor constituting a readout circuit are provided in different semiconductor layers is described. However, as in the above-described embodiment, in a solid-state imaging device in which a photoelectric conversion cell, a transfer transistor, and a pixel transistor are provided in one semiconductor layer, since active elements are densely packed, it is particularly effective to make the width of a second portion including contact with a contact region narrower than that of a first portion including contact with a charge holding region as in this embodiment.

[0341] Also, the volume of the photoelectric conversion portion can be increased at the same planar size, and the saturation signal amount can be improved. Also, the contact area between the conductive pad 123 and the contact region 121 becomes large, and the resistance of the conductive path using the conductive pad 123 can be reduced. Also, in the first portion 110a of the separation region 110, in the thickness direction of the semiconductor layer 101, the width of the body portion 110a2 is made narrower than the width of the head portion 110a1 including contact with the charge holding region FD. Therefore, compared with the case where the separation region is configured in the thickness direction of the semiconductor layer by the width of the head portion 110a1, the volume of the photoelectric conversion portion 103 can be increased, and the saturation signal amount Qs can be further improved.

[0342] 〔22nd Embodiment〕 As shown in FIG. 54, in the solid-state imaging device 1K according to this 22nd embodiment, the photoelectric conversion cell 22T included in the pixel 3 is partitioned into two regions by an in-pixel separation region. And the photoelectric conversion cell 22T is partitioned by a separation region 110 having a first portion and a second portion, similarly to the photoelectric conversion cell 22S shown in FIG. 51 of the above-described 21st embodiment. Also in the solid-state imaging device 1K of this 2nd embodiment, the same effects as those of the above-described 21st embodiment can be obtained.

[0343] 〔23rd Embodiment〕 ≪Application Examples to Electronic Devices≫ This technology (the technology according to the present disclosure) can be applied to various electronic devices such as imaging devices such as digital still cameras and digital video cameras, mobile phones equipped with an imaging function, or other devices equipped with an imaging function.

[0344] FIG. 55 is a diagram showing a schematic configuration of an electronic device (e.g., a camera) according to the 23rd embodiment of the present technology. As shown in FIG. 55, the electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. This electronic device 200 shows an embodiment in the case where the solid-state imaging devices 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1H, 1J according to the 1st to 22nd embodiments of the present technology are used in an electronic device (e.g., a camera) as the solid-state imaging device 201.

[0345] The optical lens 202 forms an image of subject image light (incident light 206) on the imaging surface of the solid-state imaging device 201. As a result, signal charges are accumulated in the solid-state imaging device 201 over a certain period. The shutter device 203 controls the light irradiation period and the light shielding period to the solid-state imaging device 201. The drive circuit 204 supplies a drive signal for controlling the transfer operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203. Signal transfer of the solid-state imaging device 201 is performed by the drive signal (timing signal) supplied from the drive circuit 204. The signal processing circuit 205 performs various signal processes on the signal (pixel signal) output from the solid-state imaging device 201. The video signal on which the signal process has been performed is stored in a storage medium such as a memory or output to a monitor.

[0346] With such a configuration, in the electronic device 200 of the 23rd embodiment, in the solid-state imaging device 201, since light reflection in the light shielding film and the insulating film in contact with the air layer is suppressed by the light reflection suppression unit, smear can be suppressed and image quality can be improved.

[0347] Note that the electronic device 200 to which the solid-state imaging devices 1A to 1J can be applied is not limited to a camera, and can also be applied to other electronic devices. For example, it may be applied to an imaging device such as a camera module for mobile devices such as mobile phones and tablet terminals.

[0348] In addition, this technology can be applied to all optical detection devices including, in addition to the solid-state imaging device as the above-described image sensor, a distance measurement sensor called a ToF (Time of Flight) sensor that measures distance. The distance measurement sensor emits irradiation light toward an object, detects the reflected light that is reflected by the surface of the object and returns, and calculates the distance to the object based on the flight time from when the irradiation light is emitted until the reflected light is received. As the structure of the element isolation region of this distance measurement sensor, the structure of the above-described element isolation region can be adopted.

[0349] 〔Modification Example of the 14th Embodiment〕 As shown in FIG. 45, in the modification example of the above-described 19th embodiment, a dummy gate electrode 45b is provided in the element formation region 21a of the pixel 3a2. Needless to say, the technique of providing this dummy gate electrode 45b, that is, the dummy transistor, can also be applied to the above-described 14th embodiment shown in FIGS. 25 to 27.

[0350] For example, as a first modification example of the above-described 14th embodiment, as shown in FIG. 56, a dummy transistor DMT is provided in the element formation region 21a of the pixel 3c instead of the selection transistor SEL in FIG. 26, and two dummy transistors DMT are provided in the element formation region 21a of the pixel 3b instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26.

[0351] Further, as a second modification of the above-described 14th embodiment, as shown in FIG. 57, two dummy transistors DMT may be provided in the element formation region 21a of the pixel 3c instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26, and two dummy transistors DMT may be provided in the element formation region 21a of the pixel 3b instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26.

[0352] Further, as a third modification of the above-described 14th embodiment, as shown in FIG. 58, a dummy transistor DMT may be provided in the element formation region 21a of the pixel 3c instead of the amplification transistor AMP in FIG. 26, and two dummy transistors DMT may be provided in the element formation region 21a of the pixel 3b instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26.

[0353] Further, as a fourth modification of the above-described 14th embodiment, as shown in FIG. 59, two dummy transistors DMT may be provided in the element formation region 21a of the pixel 3d instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26, and two dummy transistors DMT may be provided in the element formation region 21a of the pixel 3b instead of the amplification transistor AMP and the selection transistor SEL in FIG. 26.

[0354] That is, the circuit block 62C may have a dummy transistor DMT as a pixel transistor. The number of dummy transistors DMT is not limited to the first to fourth modifications of the 14th embodiment, and the circuit block 62C only needs to include at least one amplification transistor AMP, one selection transistor SEL, one reset transistor RST, and one switching transistor FDG.

[0355] Note that the dummy transistor DMT can also be applied in the above-described 13th embodiment. Further, it goes without saying that the solid-state imaging device according to the first to fourth modifications of the 14th embodiment can also be applied to the electronic device according to the above-described 23rd embodiment.

[0356] Note that the present technology may also be configured as follows. (1) A semiconductor layer having a first surface and a second surface located on opposite sides in the thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first separation region extending in the thickness direction of the semiconductor layer. The photoelectric conversion cell includes a first photoelectric conversion region and a second photoelectric conversion region, each of which is provided adjacent to each other in plan view in the semiconductor layer and each of which has a photoelectric conversion unit and a transfer transistor, a second separation region disposed between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in the thickness direction of the semiconductor layer, and an element formation region partitioned by a third separation region and provided on the first surface side of the semiconductor layer, and provided with a pixel transistor. The element formation region extends across the first and second photoelectric conversion regions in plan view, and is a photodetection device. (2) The photoelectric conversion cell is configured with a rectangular planar pattern, the second separation region is provided so as to protrude inward from each of the two first separation regions located on opposite sides across the photoelectric conversion cell in plan view, and the element formation region crosses between the two second separation regions in plan view, and is the photodetection device according to (1) above. (3) The element formation region includes a first portion crossing between the two second separation regions, and a pair of second portions extending from each of one end side and the other end side of the first portion to the side opposite to the transfer transistor side of the first portion, and is the photodetection device according to (1) or (2) above. (4) The photoelectric conversion cell further includes a first conductivity type semiconductor region provided in the semiconductor layer across each of the element formation region, the first and second photoelectric conversion regions, and a first conductivity type contact region provided in the first semiconductor region. The contact region is disposed between the two second separation regions in a plan view, and the photodetection device according to any one of (1) to (3) above. (5) The transfer transistors of each of the first and second photoelectric conversion regions are provided in the element formation region, and the photodetection device according to any one of (1) to (4) above. (6) A semiconductor region of a first conductivity type provided in the semiconductor layer across the element formation region, the first and second photoelectric conversion regions; A contact region of a first conductivity type provided in the first semiconductor region, and further includes: The contact region is disposed between at least one of the pair of second portions and the first separation region in a plan view, and the photodetection device according to any one of (1) to (5) above. (7) The pixel transistor is provided in each of the first and second photoelectric conversion regions, and the photodetection device according to any one of (1) to (6) above. (8) Each of the first separation region and the second separation region is integrated with the third separation region, and the photodetection device according to any one of (1) to (7) above. (9) A semiconductor layer having a first surface and a second surface located on opposite sides in the thickness direction; A photoelectric conversion cell provided in the semiconductor layer and partitioned by a first separation region extending in the thickness direction of the semiconductor layer; The photoelectric conversion cell is A first photoelectric conversion region and a second photoelectric conversion region each provided adjacent to each other in a plan view on the semiconductor layer and each having a photoelectric conversion unit and a transfer transistor; A second separation region provided between the first photoelectric conversion region and the second photoelectric conversion in a plan view and extending in the thickness direction of the semiconductor layer; An element formation region partitioned by a third separation region on the first surface side of the semiconductor layer and provided with a pixel transistor; A charge holding region provided on the first surface side of the semiconductor layer, A semiconductor region of a first conductivity type provided in the semiconductor layer across the element formation region, the first photoelectric conversion region, and the second photoelectric conversion region, A contact region of the first conductivity type provided in the semiconductor region, and At least one of the charge holding region and the contact region is shared by the first and second photoelectric conversion regions and is disposed between the first photoelectric conversion region and the second photoelectric conversion region in a plan view, a photodetector. (10) The photoelectric conversion cell has a rectangular planar pattern in a plan view, The second separation region is provided separately from each of the two first separation regions located on opposite sides of the photoelectric conversion cell in a plan view, the photodetector according to (9) above. (11) The charge holding region is disposed between one of the two first separation regions and the second separation region in a plan view, The contact region is disposed between the other of the two first separation regions and the second separation region in a plan view, the photodetector according to (9) or (10) above. (12) The element formation region and the pixel transistor are provided individually for each of the first and second photoelectric conversion regions, the photodetector according to any one of (9) to (11) above. (13) The charge holding region is provided between one of the two first separation regions and the second separation region, The element formation region crosses between the other of the two first separation regions and the second separation region in a plan view and extends across the first and second photoelectric conversion regions, the photodetector according to any one of (9) to (12). (14) The element formation region is A first portion crossing between the other first separation region and the second separation region, A pair of second portions extending from each of one end side and the other end side of the first portion to the side opposite to the other first separation region side of the first portion; The photodetection device according to the above (10), including . (15) The photodetection device according to any one of the above (9) to (14), wherein the pixel transistor is provided in each of the first and second photoelectric conversion regions. (16) A semiconductor layer having a plurality of photoelectric conversion cells arranged adjacent to each other via a separation region in a plan view, and each provided with a photoelectric conversion unit and a transfer transistor; Semiconductor regions respectively provided on the separation region side of each of the plurality of photoelectric conversion cells in a plan view; A conductive pad partially embedded in the separation region and connected to the semiconductor region of each of the plurality of photoelectric conversion cells across the separation region in a plan view; A photodetection device comprising the above. (17) The conductive pad includes a body portion located in the separation region, and a head portion protruding from the body portion to the outside of the element isolation region and wider than the body portion. The photodetection device according to the above (16), wherein the semiconductor region is connected to each of the body portion and the head portion. (18) The photodetection device according to the above (16) or (17), wherein the semiconductor region is any one of a charge holding region, a first contact region to which a first reference potential is applied, and a second contact region to which a second reference potential different from the first reference potential is applied. (19) The photodetection device according to claim 15 of any one of the above (16) to (18), further comprising a relay wiring including two of the conductive pads and a connecting portion connecting the two conductive pads. (20) The photodetection device according to any one of the above (16) to (19), wherein each of the plurality of photoelectric conversion cells further has a pixel transistor sharing a gate electrode disposed in each of the photoelectric conversion cells across the separation region. (21) The gate electrode has a body portion adjacent to the semiconductor layer via a gate insulating film within the isolation region, and a head portion that protrudes from the body portion to the outside of the isolation region, is adjacent to the semiconductor layer via the gate insulating film, and is wider than the body portion, of the photodetector according to (20) above. (22) A semiconductor layer having a first surface and a second surface positioned on opposite sides in the thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by an element isolation region, The photoelectric conversion cell has a transfer transistor, a charge holding region, and a contact region on the first surface side of the semiconductor layer, and a photoelectric conversion portion on the second surface side, The isolation region has a first portion in contact with the charge holding region in plan view, and a second portion in contact with the contact region and narrower than the first portion, of the photodetector. (23) In the photodetector according to (22) above, the ratio of the first portion to the second portion of the isolation region in plan view is such that the second portion is larger. (24) The first portion of the isolation region includes a surface portion provided on the first surface side of the semiconductor layer, and a deep layer portion provided in contact with the surface portion at a position deeper than the surface portion in the thickness direction of the semiconductor layer and narrower than the surface portion, of the photodetector according to (22) or (23) above. (25) The photoelectric conversion portion includes a first semiconductor region, The photoelectric conversion cell further has a second semiconductor region that extends in the thickness direction of the semiconductor layer adjacent to each of the deep layer portion of the first portion and the second portion, and has a conductivity type opposite to that of the first semiconductor region, of the photodetector according to any one of (22) to (24) above. (26) The photoelectric conversion cell further has a pinning film between each of the deep layer portion of the first portion and the second portion and the second semiconductor region, of the photodetector according to any one of (22) to (25) above. (27) A pixel unit having four pixels, each pixel having two photoelectric conversion regions, two transfer transistors, and two charge holding regions, A photodetection device in which the charge holding regions of each pixel in the pixel unit are electrically connected to each other. (28) The photodetection device according to (27) above, wherein the eight charge holding regions of the pixel unit are electrically connected. (29) The photodetection device according to (27) or (28) above, wherein the eight charge holding regions are connected to a first amplification transistor. (30) The photodetection device according to any one of (27) to (29) above, wherein the eight charge holding regions are connected to the first amplification transistor and a second amplification transistor. (31) The photodetection device according to any one of (27) to (30) above, wherein the eight charge holding regions are connected to a switching transistor and are connected to a reset transistor via the switching transistor. (32) The photodetection device according to (31) above, having a capacitor connected between the switching transistor and the reset transistor. (33) The four pixels in the pixel unit have a first pixel, a second pixel, a third pixel, and a fourth pixel, The first pixel includes first and second charge holding regions, The second pixel includes third and fourth charge holding regions, The third pixel includes fifth and sixth charge holding regions, The fourth pixel includes seventh and eighth charge holding regions, A first line connecting the first charge holding region and the fifth charge holding region and a second line connecting the second charge holding region and the sixth charge holding region are parallel, A third line connecting the first charge holding region and the second charge holding region and a fourth line connecting the fifth charge holding region and the sixth charge holding region are parallel, The photodetection device described in any one of (27) to (32) above. (34) Having a plurality of pixels provided two-dimensionally, A photodetection device having five semiconductor regions partitioned by an element isolation region within each pixel of the plurality of pixels. (35) The photodetection device according to (34) above, wherein two of the five semiconductor regions are regions where transfer transistors are provided. (36) The photodetection device according to (34) or (35) above, wherein two of the five semiconductor regions are regions where pixel transistors are provided. (37) The photodetection device according to (36) above, wherein the pixel transistor includes any one of a selection transistor, an amplification transistor, and a reset transistor. (38) The photodetection device according to any one of (35) to (37) above, wherein one of the five semiconductor regions is a p-type semiconductor region. (39) The photodetection device according to (38) above, wherein a reference potential is applied as a power supply potential to the p-type semiconductor region. (40) The photodetection device according to (39) above, wherein the reference potential is 0V. (41) Two of the five semiconductor regions are regions where pixel transistors are provided, The photodetection device according to (38) above, wherein the p-type semiconductor region is provided between the regions where the pixel transistors are provided. (42) The photodetection device according to any one of (34) to (41) above, wherein the element isolation region is STI. (43) Having a plurality of pixels provided two-dimensionally, Each pixel having five semiconductor regions partitioned by an element isolation region, The five semiconductor regions are, A first semiconductor region provided with a first transfer transistor, and a second semiconductor region provided with a second transfer transistor; a third semiconductor region provided with a first pixel transistor other than the first and second transfer transistors; a fourth semiconductor region provided with a second pixel transistor other than the first and second transfer transistors; a p-type semiconductor region; A photodetection device having the above. (44) The photodetection device according to (43) above, wherein the first or second pixel transistor is any one of a selection transistor, an amplification transistor, and a reset transistor. (45) The photodetection device according to (44) or (44) above, wherein a reference potential is applied to the p-type semiconductor region as a power supply potential. (46) The photodetection device according to (45) above, wherein the reference potential is 0V. (47) The photodetection device according to any one of (43) to (46) above, wherein the p-type semiconductor region is provided between the third semiconductor region and the fourth semiconductor region. (48) The photodetection device according to any one of (43) to (47) above, wherein the element isolation region is STI. (49) a first pixel provided on a semiconductor substrate; a trench including a first region that separates the first pixel from an adjacent pixel, and a second region in which a photoelectric conversion unit provided in the first pixel is blocked in a plan view. In a plan view, the second region has a first portion between a first floating diffusion region and a second floating diffusion region provided in the first pixel. In the plan view, the second region has a second portion between a first transistor and a second transistor provided in the first pixel. The photodetection device in which a contact region is provided between the first portion and the second portion in the plan view. (50) The light detection device according to (49) above, wherein the first part, the contact region, and the second part in the plan view are arranged in this order along a first direction. (51) The light detection device according to (50) above, wherein the first contact, the gate electrode, and the second contact of the first transistor are arranged in this order along the first direction. (52) The light detection device according to (51) above, wherein the third contact, the gate electrode, and the fourth contact of the second transistor are arranged in this order along the first direction. (53) The light detection device according to any one of (49) to (52) above, wherein the trench penetrates the semiconductor substrate. (54) The light detection device according to any one of (49) to (53) above, wherein the contact region is provided at the center of the first pixel. (55) The light detection device according to any one of (49) to (54) above, wherein the contact region is a p-type impurity region. (56) a first pixel provided on a semiconductor substrate; a separation region that separates the first pixel and a pixel adjacent to the first pixel; in the plan view, the first pixel is surrounded by first to fourth portions of the separation region; the separation region has fifth and sixth portions provided between the first portion and the third portion in the plan view; a contact region is provided between the fifth portion and the sixth portion in the plan view; the fifth portion is in contact with the first portion, and the sixth portion is in contact with the third portion, a light detection device. (57) The light detection device according to (56) above, wherein an angle formed by the first portion and the fifth portion is perpendicular. (58) The light detection device according to (56) or (57) above, wherein the first portion and the third portion face each other. (59) The photodetection device according to any one of (56) to (58) above, wherein, in the plan view, the fifth portion, the contact region, and the sixth portion are arranged along the first direction in this order. (60) The first pixel includes a first transistor and a second transistor provided on both sides of the sixth portion. The photodetection device according to (59) above, wherein the first contact, gate electrode, and second contact of the first transistor are arranged along the first direction in this order. (61) The photodetection device according to (60) above, wherein the third contact, gate electrode, and fourth contact of the second transistor are arranged along the first direction in this order. (62) The photodetection device according to any one of (56) to (61) above, wherein the trench penetrates the semiconductor substrate. (63) The photodetection device according to any one of (56) to (62) above, wherein the contact region is provided at the center of the first pixel. (64) The photodetection device according to any one of (56) to (63) above, wherein the contact region is a p-type impurity region. (65) An electronic device including the photodetection device according to any one of (1), (9), (16), (22), (27), (34), (43), (49), and (56), an optical lens that forms an image of object light on an imaging surface of the photodetection device, and a signal processing circuit that performs signal processing on a signal output from the photodetection device.

[0357] The scope of the present technology is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that bring about equivalent effects to those intended by the present technology. Further, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but can be defined by any desired combination of specific features among all the disclosed respective features.

Explanation of Reference Numerals

[0358] 1 Solid-state imaging device 2 Semiconductor chip 2A Pixel region 2B Peripheral region 3, 3a, 3b, 3c, 3d Pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 12 Horizontal signal line 13 Logic circuit 14 Bonding pad 15 Readout circuit 21 Semiconductor layer 21a, 21b1, 21b2, 21c, 21d Element formation region (active region) 21z Power supply region 22A, 22B, 22C, 22D, 22E, 22F, 22G, 22H, 22I, 22J, 22K, 22L, 22M1, 22M2, 22M3, 22M4, 22M5 Photoelectric conversion cell 23L First photoelectric conversion region 23R Second photoelectric conversion region 24 p-type semiconductor region 25 Photoelectric conversion section 26 n-type semiconductor region 31 Pixel isolation region (first isolation region) 32 Intra-pixel isolation region (second isolation region) 33 Element isolation region (third isolation region) 41 Gate trench 42 Gate insulating film 43 Gate electrode 44 Gate insulating film 45 Gate electrode 46, 47 Main electrode region 48 Contact region 51 Color filter 52 Microlens 71, 73 Relay wiring 71a, 72, 73a, 73b Conductive pad 71c, 73c Connection part AMP amplification transistor FD, FD1, FD2 charge holding region (floating diffusion) FDG switching transistor RST reset transistor SEL selection transistor TR1, TR2 transfer transistor

Claims

1. A plurality of pixels arranged two-dimensionally, Each pixel of the plurality of pixels is A photoelectric conversion cell partitioned by a pixel isolation region; a photoelectric conversion unit provided in the photoelectric conversion cell and performing photoelectric conversion on light incident on a light incident surface side of the photoelectric conversion cell; five semiconductor regions provided on an opposite side to the light incident surface side of the photoelectric conversion cell and partitioned by element isolation regions; The five semiconductor regions are: a first semiconductor region in which a first transfer transistor is provided; a second semiconductor region in which a second transfer transistor is provided; a third semiconductor region in which a first pixel transistor other than the first and second transfer transistors is provided; a fourth semiconductor region in which a second pixel transistor other than the first and second transfer transistors is provided; A p-type semiconductor region; having The photodetector, wherein the p-type semiconductor region is provided between the third semiconductor region and the fourth semiconductor region and between the first semiconductor region and the second semiconductor region.

2. The photodetection device according to claim 1 , wherein the first or second pixel transistor is any one of a selection transistor, an amplification transistor, and a reset transistor.

3. 2. The photodetector according to claim 1, wherein a reference potential is applied to the p-type semiconductor region as a power supply potential.

4. 4. The photodetection device of claim 3, wherein the reference potential is 0V.

5. The photodetector according to claim 1 , wherein the element isolation region is an STI region.

Images