Image sensor and image pickup device

Abstract

To provide an image pickup device and an image pickup element that removes noise line segments that occur when correlated double sampling of pixels is not performed in an image pickup element that calculates the signals of adjacent pixels.SOLUTION: An image pickup element has a first substrate 111 on which an arithmetic unit is provided that performs a third signal calculation on the basis of a first signal 18 based on the charge generated by a pixel 10 that photoelectrically converts light and a second signal for correcting the first signal 18, and a second substrate 112 on which a control unit is provided that controls the arithmetic unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an imaging element and an imaging device. [Background technology]

[0002] An image sensor that calculates signals from adjacent pixels is known (Patent Document 1). However, this image sensor does not perform correlated double sampling (CDS) before calculating the signals from the pixels, and therefore cannot remove noise signal components from each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2001-94888 Summary of the Invention

[0004] According to a first aspect of the present invention, an imaging device includes a first substrate on which first pixels having first photoelectric conversion units that convert light into electric charges are disposed, a second substrate that is a substrate stacked on the first substrate and on which a first storage unit that stores a first digital signal obtained by converting a first signal based on the electric charges converted by the first photoelectric conversion unit into a digital signal is disposed, and a substrate that is stacked on the first substrate and on which a first storage unit that stores a first digital signal read out from the first storage unit is disposed. a first correlated double sampling using a second digital signal obtained by converting a second signal read from the first pixel into a digital signal for removing noise contained in the first signal; and a third substrate on which a first processing unit that performs processing is disposed. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing a cross-sectional structure of an image sensor according to a first embodiment. [Figure 3] FIG. 1 is a block diagram showing the configuration of an imaging element according to a first embodiment. [Figure 4]FIG. 2 is a circuit diagram showing the configuration of a pixel according to the first embodiment. [Figure 5] FIG. 2 is a block diagram showing the detailed configuration of the imaging element according to the first embodiment. [Figure 6] 4 is a timing chart showing the operation of the imaging element according to the first embodiment. [Figure 7] FIG. 10 is a block diagram showing the details of the configuration of an imaging element according to Modification 1. DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) FIG. 1 is a block diagram showing the configuration of an imaging device according to a first embodiment. The imaging device 1 includes a photographing optical system 2, an imaging element 3, and a control unit 4. The imaging device 1 is, for example, a camera. The photographing optical system 2 forms a subject image on the imaging element 3. The imaging element 3 captures the subject image formed by the photographing optical system 2 and generates an image signal. The imaging element 3 is, for example, a CMOS image sensor. The control unit 4 outputs a control signal to the imaging element 3 for controlling the operation of the imaging element 3. The control unit 4 also functions as an image generation unit that performs various image processes on the image signal output from the imaging element 3 and generates image data. The photographing optical system 2 may be detachable from the imaging device 1.

[0007] FIG. 2 is a diagram showing a cross-sectional structure of an imaging element according to the first embodiment. The imaging element 3 shown in FIG. 2 is a back-illuminated imaging element. The imaging element 3 includes a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114. The first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are each formed of a semiconductor substrate or the like. The first substrate 111 is stacked on the second substrate 112, which is stacked on the third substrate 113, which is stacked on the fourth substrate 114. Incident light L, indicated by a hollow arrow, is incident in the positive direction of the Z axis. As shown by the coordinate axes, the left direction on the paper, which is perpendicular to the Z axis, is the positive X axis, and the front direction on the paper, which is perpendicular to the Z axis and the X axis, is the positive Y axis.

[0008] The imaging element 3 further has a microlens layer 101, a color filter layer 102, and a passivation layer 103. The passivation layer 103, the color filter layer 102, and the microlens layer 101 are sequentially stacked on a first substrate 111. The microlens layer 101 has a plurality of microlenses ML. The microlenses ML focus incident light onto a photoelectric conversion unit 12, which will be described later. The color filter layer 102 has a plurality of color filters F. The passivation layer 103 is made of a nitride film or an oxide film.

[0009] First substrate 111, second substrate 112, third substrate 113, and fourth substrate 114 each have a first surface 105a, 106a, 107a, or 108a on which gate electrodes and gate insulating films are provided, and a second surface 105b, 106b, 107b, or 108b different from the first surface. Various elements such as transistors are provided on first surfaces 105a, 106a, 107a, or 108a. Wiring layers 140, 141, 144, and 145 are stacked and provided on first surface 105a of first substrate 111, first surface 106a of second substrate 112, first surface 107a of third substrate 113, and first surface 108a of fourth substrate 114, respectively. Furthermore, inter-substrate connection layers 142, 143 are respectively stacked on second surface 106b of second substrate 112 and second surface 107b of third substrate 113. Wiring layers 140 to 145 are layers including a conductor film (metal film) and an insulating film, and each has a plurality of wires, vias, etc. arranged therein.

[0010] The elements on first surface 105a of first substrate 111 and the elements on first surface 106a of second substrate 112 are electrically connected by connecting portions 109 such as bumps or electrodes via wiring layers 140 and 141, and similarly, the elements on first surface 107a of third substrate 113 and the elements on first surface 108a of fourth substrate 114 are electrically connected by connecting portions 109 such as bumps or electrodes via wiring layers 144 and 145. Furthermore, second substrate 112 and third substrate 113 have through holes 120 that penetrate from the first surface to the second surface of the substrate, and a plurality of through electrodes 110 such as silicon through electrodes that are arranged from the first surface to the second surface via through holes 120. The through electrodes 110 of the second substrate 112 connect the circuits provided on the first surface 106a and the second surface 106b of the second substrate 112 to each other, and the through electrodes 110 of the third substrate 113 connect the circuits provided on the first surface 107a and the second surface 107b of the third substrate 113 to each other. The circuits provided on the second surface 106b of the second substrate 112 and the circuits provided on the second surface 107b of the third substrate 113 are electrically connected by connecting parts 109 such as bumps or electrodes via inter-substrate connecting layers 142 and 143.

[0011] FIG. 3 is a block diagram showing the configuration of an image sensor according to the first embodiment. The first substrate 111 has a plurality of pixels 10 arranged two-dimensionally and a comparison unit 40. The pixels 10 are arranged in the X-axis direction and the Y-axis direction shown in FIG. 2. The pixels 10 output a photoelectric conversion signal and a noise signal (described later) to the comparison unit 40. The comparison unit 40 is provided for each pixel 10 and is configured with a comparator circuit or the like. The comparison unit 40 compares each of the photoelectric conversion signal and the noise signal output from the pixel 10 with a reference signal and outputs the comparison result to the second substrate 112. The second substrate 112 has a plurality of memory units 50. The memory unit 50 is provided for each pixel 10 and is configured with a latch circuit or the like. The memory unit 50 stores, as a digital signal, a count value corresponding to the elapsed time since the comparison by the comparison unit 40 started, based on the comparison result by the comparison unit 40. The memory unit 50 stores a digital signal corresponding to the photoelectric conversion signal and a digital signal corresponding to the noise signal. The memory unit 50 also functions as an accumulation unit 50 that accumulates the photoelectric conversion signal and the noise signal (reset signal) that have been converted into digital signals. As will be described in detail later, the comparison unit 40 and the memory unit 50 constitute an integral AD conversion unit that converts the photoelectric conversion signal and the noise signal into digital signals. The digital signals stored in the memory unit 50 are output to the fourth board 114 via the third board 113.

[0012] The fourth substrate 114 has a plurality of ALUs (Arithmetic and Logic Units), i.e., arithmetic units 80. An arithmetic unit 80 is provided for each pixel 10, and performs signal processing such as correlated double sampling (CDS) by subtracting a digital signal of a photoelectric conversion signal from a digital signal of a noise signal, and calculations between signals generated for each pixel 10. The arithmetic units 80 are configured to include an adder circuit, a subtractor circuit, a flip-flop circuit, a shift circuit, and the like. The arithmetic units 80 are connected to each other via signal lines, switches SW, and the like.

[0013] The third substrate 113 has an ALU control unit 70 (hereinafter referred to as the control unit 70) that controls the arithmetic units 80. The control unit 70 is provided for each pixel 10 and outputs control signals to the arithmetic units 80, switches SW, and the like arranged on the fourth substrate 114 to control the content of the arithmetic operations performed by the arithmetic units 80. For example, the control unit 70 selects pixel signals by controlling the on-state of a predetermined switch SW, and the arithmetic units 80 corresponding to this control unit 70 perform arithmetic operations on the signals of the selected multiple pixels. Note that the first substrate 111 is also a pixel substrate 111 including multiple pixels 10 each having a photoelectric conversion unit 12 and a readout unit (output unit) described later, and the second substrate 112 is also an accumulation substrate 112 including an accumulation unit 50 (storage unit 50). The fourth substrate 114 is also an arithmetic substrate 114 including the arithmetic units 80.

[0014] In this embodiment, correlated double sampling is performed before performing calculations between signals from each pixel 10. Therefore, calculations between signals from any pixel 10 can be performed using signals from which noise signal components for each pixel 10 have been removed. Furthermore, the calculation units 80 and control units 70 are stacked on the corresponding pixels 10, respectively. This prevents a decrease in the aperture ratio of the pixels 10. Furthermore, the control unit 70 on the third substrate 113 controls the calculation unit 80 by supplying a control signal to the calculation unit 80 on the fourth substrate 114 from the Z-axis direction shown in FIG. 2. As a result, calculations can be performed on signals from any pixel 10 without increasing the chip area of ​​the image sensor 3.

[0015] 4 is a circuit diagram showing the configuration of a pixel of the image sensor according to the first embodiment. The pixel 10 has a photoelectric conversion unit 12, such as a photodiode (PD), and a readout unit 20. The photoelectric conversion unit 12 converts incident light into electric charges and accumulates the photoelectrically converted electric charges. The readout unit 20 has a transfer unit 13, a discharge unit 14, a floating diffusion (FD) 15, an amplifier unit 16, and a current source 17.

[0016] The transfer unit 13 is controlled by a signal Vtx and transfers the charges photoelectrically converted by the photoelectric conversion unit 12 to the floating diffusion 15. That is, the transfer unit 13 forms a charge transfer path between the photoelectric conversion unit 12 and the floating diffusion 15. The floating diffusion 15 holds (accumulates) the charges. The amplifier 16 amplifies a signal based on the charges held in the floating diffusion 15 and outputs it to a signal line 18. In the example shown in FIG. 4, the amplifier 16 is configured by a transistor M3 whose drain terminal, gate terminal, and source terminal are connected to a power supply VDD, the floating diffusion 15, and a current source 17, respectively.

[0017] The discharge unit (reset unit) 14 is controlled by a signal Vrst to discharge the charge in the floating diffusion 15 and reset the potential of the floating diffusion 15 to a reset potential (reference potential). The transfer unit 13 and the discharge unit 14 are configured by, for example, a transistor M1 and a transistor M2, respectively.

[0018] The readout unit 20 sequentially reads out to the signal line 18 a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 12 to the floating diffusion 15 by the transfer unit 13 and a signal (noise signal) when the potential of the floating diffusion 15 is reset to the reset potential. The readout unit 20 is an output unit 20 that generates and outputs a signal based on the charge accumulated in the floating diffusion 15, and outputs the photoelectric conversion signal and the noise signal to the signal line 18.

[0019] 5 is a block diagram showing the detailed configuration of the image sensor according to the first embodiment. The image sensor 3 includes a plurality of pixels 10, a calculation unit 100 provided for each pixel 10, a timing generator 200, a DA conversion unit 210, a global counter 220, a shift register 230, a VSCAN circuit (vertical scanning circuit) 240, an HSCAN circuit (horizontal scanning circuit) 250, a sense amplifier 300, a line memory 310, and an input / output unit 320. The calculation unit 100 includes an analog-to-digital conversion unit (AD conversion unit) 60, a control unit 70, a calculation unit 80, a storage unit 83, a demultiplexer 81, a demultiplexer 84, and a multiplexer 85. The AD conversion unit 60 includes a comparison unit 40, a storage unit 50, and a demultiplexer 53. The storage unit 50 also includes a signal storage unit 51 for storing digital signals corresponding to the photoelectric conversion signals, and a noise storage unit 52 for storing digital signals corresponding to the noise signals. The signal storage unit 51 and the noise storage unit 52 are each configured with a plurality of latch circuits corresponding to the number of bits of the signals to be stored. For example, the signal storage unit 51 and the noise storage unit 52 each include 12 latch circuits, and the digital signals stored in the signal storage unit 51 and the noise storage unit 52 are each 12-bit parallel signals.

[0020] The first layer of the image sensor 3, i.e., the first substrate 111, is provided with the pixels 10, the comparator 40, and part of the timing generator 200. The timing generator 200 is composed of multiple circuits, which are arranged on the first to fourth substrates 111 to 114. In FIG. 5, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are referred to as the first layer, the second layer, the third layer, and the fourth layer, respectively. The circuits that make up the timing generator 200 are arranged in the periphery of the area in which the pixels 10 and the arithmetic unit 100 are arranged. The second layer, i.e., the second substrate 112, is provided with the signal storage unit 51, the noise storage unit 52, the demultiplexer 53, the DA conversion unit 210, the global counter 220, the shift register 230, and part of the timing generator 200.

[0021] The third substrate 113 is provided with the control unit 70, the VSCAN circuit 240, the HSCAN circuit 250, and part of the timing generator 200. The fourth substrate 114 is provided with the arithmetic unit 80, the memory unit 83, the demultiplexer 81, the demultiplexer 84, the multiplexer 85, the sense amplifier 300, the line memory 310, and the input / output unit 320. The DA conversion unit 210, the global counter 220, the shift register 230, the VSCAN circuit 240, the HSCAN circuit 250, the sense amplifier 300, the line memory 310, and the input / output unit 320 are arranged on the periphery of the area where the arithmetic unit 100 is arranged on each substrate.

[0022] The timing generator 200, which includes a pulse generation circuit and other components, generates pulse signals and other signals based on register setting values ​​output from the control unit 4 of the imaging device 1 and outputs the signals to each pixel 10, the DA conversion unit 210, the global counter 220, the shift register 230, the VSCAN circuit 240, and the HSCAN circuit 250. The register setting values ​​are set, for example, according to the shutter speed (charge accumulation time of the photoelectric conversion unit), the ISO sensitivity, whether or not image correction is performed, and other factors. The DA conversion unit 210 generates a ramp signal whose signal level changes as a reference signal based on the pulse signal from the timing generator 200. The DA conversion unit 210 is also commonly connected to each comparison unit 40 provided for each pixel 10 and outputs the reference signal to each comparison unit 40. The global counter 220 generates a clock signal indicating a count value based on the pulse signal from the timing generator 200 and outputs the clock signal to the signal storage unit 51 and the noise storage unit 52. The shift register 230 generates a timing signal based on the pulse signal from the timing generator 200 and outputs the generated timing signal to the signal storage unit 51 and the noise storage unit 52 .

[0023] The VSCAN circuit 240 and HSCAN circuit 250 sequentially select each control unit 70 based on a signal from the timing generator 200, and output signals indicating the content of the calculation (arithmetic operation) to be performed by the calculation unit 80 and the pixel 10 to be calculated to each control unit 70. The sense amplifier 300 is connected to signal lines 122 to which each calculation unit 100 for each pixel 10 is connected, and amplifies and reads out the signal input to the signal line 122, thereby reading out the signal at high speed. The signal read out by the sense amplifier 300 is stored in the line memory 310. The input / output unit 320 performs signal processing on the signal output from the line memory 310, such as adjusting the signal bit width and adding a synchronization code, and outputs the signal as an image signal to the control unit 4 of the imaging device 1. The input / output unit 320 is configured with input / output circuits compatible with high-speed interfaces such as LVDS and SLVS, and transmits signals at high speed.

[0024] 6 is a timing chart showing an example of the operation of the image sensor according to the first embodiment. In FIG. 6, the horizontal axis represents time. During the period from time t1 to time t2, register settings are input to the timing generator 200 from the control unit 4 of the image sensor 1. During the period from time t2 to time t3, the timing generator 200 generates signals indicating the content of calculations, etc., of each arithmetic unit 80 based on the register setting values, and outputs these signals to the VSCAN circuit 240, the HSCAN circuit 250, etc. During the period from time t3 to time t4, the VSCAN circuit 240 and the HSCAN circuit 250 sequentially output the signals indicating the content of calculations, etc., generated by the timing generator 200 to each control unit 70 provided for each pixel 10.

[0025] During the period from time t10 to time t11, the noise signal of each pixel 10 is output to the comparison unit 40. The comparison unit 40 compares the noise signal read from the pixel 10 with a reference signal supplied by the DA conversion unit 210 and outputs the comparison result to the demultiplexer 53. The demultiplexer 53 outputs the comparison result by the comparison unit 40 to the noise storage unit 52. Based on the comparison result by the comparison unit 40 and the clock signal from the global counter 220, the noise storage unit 52 stores a count value corresponding to the elapsed time from when the comparison by the comparison unit 40 starts to when the comparison result is output as a digital signal corresponding to the noise signal.

[0026] During the period from time t11 to time t12, the photoelectric conversion signal of each pixel 10 is output to the comparison unit 40. The comparison unit 40 compares the photoelectric conversion signal with a reference signal and outputs the comparison result to the demultiplexer 53. The demultiplexer 53 outputs the comparison result by the comparison unit 40 to the signal storage unit 51. Based on the comparison result by the comparison unit 40 and the clock signal, the signal storage unit 51 stores a count value corresponding to the elapsed time from when the comparison by the comparison unit 40 starts to when the comparison result is output as a digital signal corresponding to the photoelectric conversion signal. Thus, in this embodiment, the signal storage unit 51 and the noise storage unit 52 each store a 12-bit digital signal.

[0027] Furthermore, during the period from time t11 to time t12, the noise storage unit 52 shifts the 12-bit digital signal stored in the noise storage unit 52 in time by one bit at a time based on the timing signal from the shift register 230, and sequentially outputs the shifted signal to the signal line 121 shown in FIG. 5. The serial signal output to the signal line 121 is input to the demultiplexer 81. The demultiplexer 81 outputs the serial signal from the noise storage unit 52 to the arithmetic unit 80. The arithmetic unit 80 sequentially stores digital signals corresponding to the noise signal in the storage unit 83. In this way, the storage unit 83 stores the 12-bit digital signal related to the noise signal.

[0028] The signal line 121 is a signal line connecting the memory unit 50 of the second substrate 112 and the demultiplexer 81 of the fourth substrate 114, and is a signal line using the through electrodes 110, bumps, etc. shown in FIG. 2. Generally, it is difficult to form a large number of through electrodes 110 at a narrow pitch, making it difficult to simultaneously transmit a large number of parallel signals from the second substrate 112 to the fourth substrate 114. In this embodiment, the parallel signals stored in the memory unit 50 of the second substrate 112 are converted into serial signals and output to the fourth substrate 114. This reduces the amount of wiring connecting the second substrate 112 and the fourth substrate 114, and enables digital signals for each pixel 10 to be output simultaneously. In addition, it is possible to prevent an increase in chip area due to the formation of a large number of through electrodes 110, etc.

[0029] During the period from time t12 to time t20, the signal storage unit 51 converts the digital signal corresponding to the photoelectric conversion signal stored in the signal storage unit 51 into a serial signal based on the timing signal from the shift register 230, and sequentially outputs the serial signal bit by bit to the demultiplexer 81 via the signal line 121. The demultiplexer 81 outputs the serial signal from the signal storage unit 51 to the arithmetic unit 80. Based on a control signal from the control unit 70, the arithmetic unit 80 causes the demultiplexer 84 to output the 12-bit digital signal corresponding to the noise signal stored in the storage unit 83 bit by bit. Based on the control signal from the control unit 70, the demultiplexer 84 outputs (feeds back) the digital signal corresponding to the noise signal to the arithmetic unit 80.

[0030] The arithmetic unit 80 generates a correction signal by subtracting a digital signal corresponding to the photoelectric conversion signal output bit by bit from the signal storage unit 51 from a digital signal corresponding to the noise signal output bit by bit from the storage unit 83. The arithmetic unit 80 sequentially stores the correction signals generated bit by bit in the storage unit 83. The arithmetic unit 80 performs subtraction multiple times according to the number of bits of the signal stored in the storage unit 50, and sequentially stores the correction signals resulting from the subtraction in the storage unit 83. In this embodiment, the signal storage unit 51 and the noise storage unit 52 constituting the storage unit 50 each store a 12-bit digital signal, so the subtraction process is performed 12 times. The storage unit 83 stores a digital signal corresponding to the 12-bit noise signal and a 12-bit correction signal. For this reason, the storage unit 83 is configured with 24 latch circuits, etc.

[0031] As described above, in this embodiment, digital CDS, which performs differential processing between the digital signal of the photoelectric conversion signal and the digital signal of the noise signal, is performed bit by bit in a time-division manner. Furthermore, a calculation unit 80 is provided for each pixel 10, and digital CDS is performed simultaneously for all pixels 10. Because the digital CDS calculation is performed bit by bit, it is possible to avoid arranging a large number of digital circuits, such as multi-bit (e.g., 12-bit) flip-flop circuits, on the fourth substrate 114. As a result, the number of circuits per pixel 10 can be reduced, preventing an increase in chip area.

[0032] During the period from time t30 to time t40, an operation is performed between correction signals for two pixels 10 respectively arranged in adjacent regions A and B in FIG. 5 . That is, the 12-bit correction signal for the pixel 10 in region A stored in the memory unit 83 of region A is input (feedback) bit by bit to the arithmetic unit 80 of region A via the demultiplexer 84. Similarly, the 12-bit correction signal for the pixel 10 in region B stored in the memory unit 83 of region B is input bit by bit to the arithmetic unit 80 of region A via the demultiplexer 84 of region B, the multiplexer 85 of region B, and the multiplexer 85 of region A, respectively. The arithmetic unit 80 of region A performs an operation on the 12-bit correction signal for region A and the 12-bit correction signal for region B input bit by bit. This will be described in detail below.

[0033] In the arithmetic section 100 arranged in region A, the arithmetic unit 80 in region A outputs the 12-bit correction signal for the pixel 10 in region A stored in the memory section 83 in region A to the demultiplexer 84 one bit at a time. The demultiplexer 84 in region A outputs (feeds back) the correction signal to the arithmetic unit 80 in region A. In the arithmetic section 100 arranged in region B, the arithmetic unit 80 in region B outputs the correction signal for the pixel 10 in region B stored in the memory section 83 in region B to the demultiplexer 84 one bit at a time. The demultiplexer 84 in region B outputs the correction signal to the multiplexer 85 in region B.

[0034] Signal lines 123 and 124, which are connected to the respective calculation units 100, are connected to each multiplexer 85 provided for each pixel 10. The signal lines 123 and 124 are, for example, two-dimensionally arranged in the row and column directions on the fourth substrate 114, and are connected to each calculation unit 100 for each pixel 10. The multiplexer 85 is controlled by the control unit 70 and selects a signal to be calculated by the calculation unit 80 from the correction signals input to the signal lines 123 and 124. The multiplexer 85 in region B outputs the correction signal for the pixel 10 in region B to the multiplexer 85 in region A via the signal line 123 shown in FIG. 5. The multiplexer 85 in region A outputs the correction signal for the pixel 10 in region B to the calculation unit 80 in region A via the signal line 124. The correction signals of the pixels 10 in the region A and the correction signals of the pixels 10 in the region B are input to the arithmetic unit 80 in the region A bit by bit.

[0035] The arithmetic unit 80 in area A performs an operation on the correction signal output bit by bit from the memory unit 83 in area A and the correction signal output bit by bit from the memory unit 83 in area B to generate a pixel signal. The arithmetic unit 80 sequentially stores the pixel signals generated bit by bit in the memory unit 83. The arithmetic unit 80 performs an operation multiple times according to the number of bits of the correction signal, and sequentially stores the pixel signals resulting from the operation in the memory unit 83. After the operation between the correction signals, the memory unit 83 stores a 12-bit correction signal and a 12-bit pixel signal.

[0036] As described above, in this embodiment, correlated double sampling is performed to generate correction signals before performing calculations between correction signals for each pixel 10. Therefore, calculations between correction signals for any pixel 10 can be performed using signals from which noise signal components for each pixel 10 have been removed. Furthermore, in this embodiment, calculations between correction signals generated for each pixel 10 are performed bit by bit. As a result, it is possible to avoid placing multi-bit digital circuits, such as multi-bit (e.g., 12-bit) arithmetic circuits or multi-bit (e.g., 12-bit) flip-flop circuits, on the fourth substrate 114, thereby preventing an increase in chip area. Because calculations between correction signals are performed bit by bit, the circuit area of ​​the calculation unit 80 can be reduced. Furthermore, the calculation unit 80 performs correlated double sampling and calculations between correction signals for each pixel 10. That is, the calculation unit 80 functions as both a correction unit that generates correction signals by subtracting digital signals and an inter-pixel calculation unit that performs calculations between correction signals generated for each pixel 10. Therefore, the chip area can be reduced compared to when the correction unit and the inter-pixel calculation unit are separately provided.

[0037] In this embodiment, a fourth substrate 114 is provided, separate from the third substrate 113 on which the control unit 70 is disposed. The arithmetic unit 80, multiplexer 85, and other components are disposed on the fourth substrate 114. Therefore, the signal lines 123 and 124 can be two-dimensionally arranged and commonly connected to the arithmetic units 100 of all pixels 10 without increasing the chip area. By outputting a control signal from the control unit 70 to control the arithmetic units 80 and multiplexer 85, etc., arithmetic operations can be performed between correction signals of any pixel 10. Arithmetic operations can be performed between adjacent pixels or between pixels disposed in distant regions. Furthermore, correction signals of other pixels 10 for which arithmetic operations are performed by the arithmetic unit 100 are directly transmitted via the signal lines 123 and 124 without passing through latches, registers, and the like. Because there is no delay time associated with passing through latches, registers, and the like, signals can be read out at high speed, enabling high-speed arithmetic operations between any pixels 10.

[0038] During the period from time t50 to time t60, the calculation unit 80 causes the demultiplexer 84 to output the pixel signals stored in the memory unit 83. The demultiplexer 84 outputs the pixel signals to the signal line 122. The sense amplifier 300 amplifies and reads out the pixel signals output to the signal line 122. Each calculation unit 100 provided for each pixel 10 sequentially outputs signals to the signal line 122, and the sense amplifier 300 sequentially reads out the signals output to the signal line 122.

[0039] During the period from time t70 to time t80, pixel signals read out by the sense amplifier 300 are sequentially stored in the line memory 310. The input / output unit 320 performs signal processing on the signals sequentially output from the line memory 310, and outputs the processed signals as image signals.

[0040] According to the above-described embodiment, the following effects can be obtained. (1) The image sensor 3 includes a plurality of pixels 10 each having a photoelectric conversion unit 12, and a calculation unit 100 provided for each pixel 10. The calculation unit 100 generates a correction signal based on a photoelectric conversion signal output from the pixel 10 and a noise signal output from the pixel 10, and performs calculations between the correction signals generated for each pixel 10. In this embodiment, the correction signal is generated by performing correlated double sampling before performing calculations between the signals of each pixel 10. Therefore, calculations between the signals of any pixel 10 can be performed using signals from which the noise signal components of each pixel 10 have been removed. (2) The calculation section 100 has an AD conversion section 60 that converts a photoelectric conversion signal into a first digital signal and a noise signal into a second digital signal, and a correction / inter-pixel calculation section (calculation unit 80) that generates a correction signal by subtracting the first digital signal from the second digital signal and performs calculations between the correction signals generated for each pixel 10. As a result, the area of ​​the peripheral circuitry for each pixel 10 can be reduced compared to when the correction section and the inter-pixel calculation section are provided separately, and the chip area can also be reduced.

[0041] (3) The photoelectric conversion unit 12 is disposed on the first substrate, and at least a part of the calculation unit 100 is disposed on the second substrate. This prevents the aperture ratio of the pixel 10 from decreasing. (4) The AD conversion unit 60 converts the photoelectric conversion signal into a first digital signal having a first number of bits, and converts the noise signal into a second digital signal having a second number of bits. This allows the photoelectric conversion signal and the noise signal to be converted into digital signals and stored in the storage unit 50. (5) The calculation unit 100 has a memory unit 83 that stores a second digital signal having a second number of bits. The calculation unit 100 performs subtraction on a bit-by-bit basis between the stored second digital signal and the first digital signal output from the AD conversion unit 60. In this embodiment, differential processing is performed on a bit-by-bit basis between the digital signal of the photoelectric conversion signal and the digital signal of the noise signal. This makes it possible to avoid providing a large number of flip-flop circuits, etc., for each pixel 10, and prevents an increase in chip area.

[0042] (6) The calculation unit 100 performs calculations for each bit between the correction signals generated for each pixel 10. This makes it possible to avoid providing a large number of arithmetic circuits, flip-flop circuits, etc. for inter-pixel calculations that perform calculations between the signals of each pixel 10, and prevents an increase in chip area. (7) The image sensor 3 further includes a plurality of signal lines (signal lines 123 and 124) to which a plurality of arithmetic units 100 are connected and through which correction signals are output from the arithmetic units 100. The arithmetic units 100 each have a first selection unit (multiplexer 85) that selects a correction signal for calculation by the arithmetic unit 100 from the correction signals output to the plurality of signal lines. In this embodiment, the control unit 70 controls the arithmetic units 80 and the multiplexer 85 to select and read out the correction signal for each pixel 10. This allows calculation to be performed between the correction signals of any pixel 10.

[0043] (8) The image sensor 3 includes a pixel substrate (first substrate 111) including a plurality of pixels 10, each having a photoelectric conversion unit 12 that photoelectrically converts incident light to generate an electric charge and an output unit 20 (readout unit 20) that generates and outputs a signal based on the electric charge, and an arithmetic unit (arithmetic unit 80) that is stacked on the pixel substrate and includes a calculation unit that generates a correction signal based on a reset signal obtained after resetting the electric charge of the output unit 20 and a photoelectric conversion signal based on the electric charge generated by the photoelectric conversion unit 12, and performs calculations between the correction signals generated for each pixel 10. This configuration allows calculations between signals for any pixel 10 to be performed using signals from which noise signal components for each pixel 10 have been removed. Furthermore, because the arithmetic units 80 are stacked on the corresponding pixels 10, a decrease in the aperture ratio of the pixels 10 can be prevented. (9) The image sensor 3 has a storage substrate (second substrate 112) including a storage section (storage section 50) that stores photoelectric conversion signals converted into digital signals and reset signals. The storage substrate is stacked between the pixel substrate and the arithmetic substrate. This prevents a decrease in the aperture ratio of the pixels 10.

[0044] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

[0045] (Variation 1) In the above-described embodiment, an example has been described in which the calculation unit 80 is used both as a correction unit that performs CDS processing and as an inter-pixel calculation unit that performs inter-pixel calculation. However, as shown in FIG. 7 , the correction unit 54 that performs CDS processing may be provided separately from the calculation unit 80. In this case, the calculation unit 80 functions as an inter-pixel calculation unit. The correction unit 54 generates a correction signal by subtracting a digital signal based on the photoelectrically converted signal output from the signal storage unit 51 from a digital signal based on the noise signal output from the noise storage unit 52, and outputs the correction signal to the calculation unit 80 via the demultiplexer 81.

[0046] (Variation 2) In the above-described embodiment, an example has been described in which pixel signals resulting from inter-pixel calculations are sequentially output to the sense amplifier 300 via the signal line 122. However, the calculation unit 100 may be configured to output the correction signals stored in the memory unit 83 as pixel signals to the sense amplifier 300 via the signal line 122. Furthermore, each of the digital signals corresponding to the photoelectric conversion signals stored in the signal memory unit 51 and the digital signals corresponding to the noise signals stored in the noise memory unit 52 may be output to the signal line 122 via the demultiplexer 81.

[0047] (Variation 3) In the above-described embodiment, an example has been described in which the CDS processing and inter-pixel calculations are performed in a time-division manner for each bit. However, the control unit 70 may control the calculation unit 80, etc., to perform calculations for each number of bits. For example, calculations may be performed for each two bits, or for each number of bits that is less than the number of bits of the digital signal stored in the noise storage unit 52.

[0048] (Variation 4) In the above-described embodiment, an example has been described in which digital CDS is performed before calculations are performed between signals of each pixel 10. However, analog CDS may also be performed before calculations are performed between signals of each pixel 10. For example, the AD conversion unit 60 performs differential processing between the photoelectric conversion signal and the noise signal, and converts the analog signal based on the difference between the signals into a digital signal. The storage unit 50 stores the digital signal from which the noise signal component has been removed for each pixel 10. The digital signals stored in the storage unit 50 are sequentially output to the calculation unit 80.

[0049] (Variation 5) In the above-described embodiment, an example has been described in which a photodiode is used as the photoelectric conversion unit 12. However, a photoelectric conversion film may be used as the photoelectric conversion unit 12.

[0050] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0051] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 2016-60001 (filed March 24, 2016) [Explanation of symbols]

[0052] 3 imaging element, 12 photoelectric conversion unit, 10 pixel, 40 comparison unit, 60 AD conversion unit, 100 calculation unit

Claims

1. a first substrate on which first pixels having first photoelectric conversion units that convert light into electric charges are arranged; a second substrate laminated on the first substrate, on which a first storage unit is disposed that stores a first digital signal obtained by converting a first signal based on the electric charge converted by the first photoelectric conversion unit into a digital signal; a third substrate laminated on the first substrate, on which a first calculation unit is disposed, the third substrate performing a first correlated double sampling process on the first digital signal read from the first storage unit by using a second digital signal obtained by converting a second signal read from the first pixel into a digital signal for removing noise contained in the first signal; An imaging element comprising:

2. 2. The imaging device according to claim 1, the first storage unit stores the second digital signal; the first calculation unit performs the first correlated double sampling process on the first digital signal read from the first storage unit by using the second digital signal read from the first storage unit; Image sensor.

3. 3. The imaging device according to claim 1, a first comparison unit for converting the first signal into the first digital signal is disposed on the first substrate; Image sensor.

4. 3. The imaging device according to claim 1, a first connection portion for electrically connecting the first substrate and the second substrate, the first connection portion having conductive members arranged to face each other in a direction in which the first substrate and the second substrate are stacked; a second connection portion for electrically connecting the second substrate and the third substrate, the second connection portion having a through electrode that penetrates the second substrate; An imaging element comprising:

5. 5. The imaging device according to claim 4, The through electrode outputs the first digital signal read from the first storage unit. Image sensor.

6. 6. The imaging device according to claim 4, a first comparison unit for converting the first signal into the first digital signal is disposed on the first substrate; Image sensor.

7. 7. The imaging device according to claim 6, the conductive member electrically connects the first comparing unit and the first storage unit; Image sensor.

8. The imaging device according to any one of claims 1 to 7, An imaging element including a fourth substrate, which is a substrate stacked on the first substrate and on which a first control unit that controls the first calculation unit is disposed.

9. 9. The imaging device according to claim 8, the fourth substrate is disposed between the second substrate and the third substrate in a direction in which the second substrate, the third substrate, and the fourth substrate are stacked; Image sensor.

10. 2. The imaging device according to claim 1, the first substrate is provided with second pixels each having a second photoelectric conversion unit arranged alongside the first photoelectric conversion unit in a column direction; a second storage unit is disposed on the second substrate and stores a third digital signal obtained by converting a third signal based on the charge converted by the second photoelectric conversion unit into a digital signal; a second calculation unit is disposed on the third substrate, the second calculation unit performing a second correlated double sampling process on the third digital signal read from the second storage unit, using a fourth digital signal obtained by converting a fourth signal read from the second pixel and used to remove noise contained in the third signal into a digital signal; Image sensor.

11. The imaging device according to claim 10, the first storage unit stores the second digital signal; the second storage unit stores the fourth digital signal; the first calculation unit performs the first correlated double sampling process on the first digital signal read from the first storage unit by using the second digital signal read from the first storage unit; the second calculation unit performs the second correlated double sampling process on the third digital signal read from the second storage unit by using the fourth digital signal read from the second storage unit. Image sensor.

12. 12. The imaging device according to claim 10, a first comparing unit for converting the first signal into the first digital signal and a second comparing unit for converting the third signal into the third digital signal are arranged on the first substrate; Image sensor.

13. 12. The imaging device according to claim 10, a first connection portion for electrically connecting the first substrate and the second substrate, the first connection portion having first conductive members arranged to face each other in a direction in which the first substrate and the second substrate are stacked; a second connection portion for electrically connecting the first substrate and the second substrate, the second connection portion having second conductive members arranged to face each other in the stacking direction of the first substrate and the second substrate; a third connection portion for electrically connecting the second substrate and the third substrate, the third connection portion having a first through electrode that penetrates the second substrate; a fourth connection portion for electrically connecting the second substrate and the third substrate, the fourth connection portion having a second through electrode that penetrates the second substrate; An imaging element comprising:

14. The imaging device according to claim 13, the first through-electrode outputs the first digital signal read from the first storage unit, the second through-electrode outputs the third digital signal read from the second storage unit; Image sensor.

15. 15. The imaging device according to claim 13, a first comparing unit for converting the first signal into the first digital signal and a second comparing unit for converting the third signal into the third digital signal are arranged on the first substrate; Image sensor.

16. The imaging device according to claim 15, the first conductive member electrically connects the first comparing unit and the first storage unit; the second conductive member electrically connects the second comparing unit and the second storage unit; Image sensor.

17. The imaging device according to any one of claims 10 to 16, An imaging element comprising a fourth substrate, which is a substrate stacked on the first substrate and on which a first control unit that controls the first calculation unit and a second control unit that controls the second calculation unit are arranged.

18. 18. The imaging device according to claim 17, the fourth substrate is disposed between the second substrate and the third substrate in a direction in which the second substrate, the third substrate, and the fourth substrate are stacked; Image sensor.

19. The imaging device according to any one of claims 10 to 18, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction. Image sensor.

20. The imaging device according to claim 10, a third pixel having a third photoelectric conversion unit arranged alongside the first photoelectric conversion unit in the row direction is arranged on the first substrate; a third storage unit is disposed on the second substrate and stores a fifth digital signal obtained by converting a fifth signal based on the charge converted by the third photoelectric conversion unit into a digital signal; a third calculation unit is disposed on the third substrate, the third calculation unit performing a third correlated double sampling process on the fifth digital signal read from the third storage unit, using a sixth digital signal obtained by converting a sixth signal, which is a signal read from the third pixel and is for removing noise contained in the fifth signal, into a digital signal; Image sensor.

21. 21. The imaging device according to claim 20, the first storage unit stores the second digital signal; the second storage unit stores the fourth digital signal; the third storage unit stores the sixth digital signal; the first calculation unit performs the first correlated double sampling process on the first digital signal read from the first storage unit by using the second digital signal read from the first storage unit; the second calculation unit performs the second correlated double sampling process on the third digital signal read from the second storage unit by using the fourth digital signal read from the second storage unit; the third calculation unit performs the third correlated double sampling process on the fifth digital signal read from the third storage unit by using the sixth digital signal read from the third storage unit. Image sensor.

22. 22. The imaging device according to claim 20, the first substrate has disposed thereon a first comparison unit for converting the first signal into the first digital signal, a second comparison unit for converting the third signal into the third digital signal, and a third comparison unit for converting the fifth signal into the fifth digital signal; Image sensor.

23. 22. The imaging device according to claim 20, a first connection portion for electrically connecting the first substrate and the second substrate, the first connection portion having first conductive members arranged to face each other in a direction in which the first substrate and the second substrate are stacked; a second connection portion for electrically connecting the first substrate and the second substrate, the second connection portion having second conductive members arranged to face each other in the stacking direction of the first substrate and the second substrate; a third connection portion for electrically connecting the first substrate and the second substrate, the third connection portion having third conductive members arranged to face each other in the stacking direction of the first substrate and the second substrate; a fourth connection portion that is a connection portion for electrically connecting the second substrate and the third substrate and has a first through electrode that penetrates the second substrate; a fifth connection portion that is a connection portion for electrically connecting the second substrate and the third substrate and has a second through electrode that penetrates the second substrate; a sixth connection portion that is a connection portion for electrically connecting the second substrate and the third substrate and has a third through-electrode that penetrates the second substrate; An imaging element comprising:

24. 24. The imaging device according to claim 23, the first through-electrode outputs the first digital signal read from the first storage unit, the second through-electrode outputs the third digital signal read from the second storage unit, the third through-electrode outputs the fifth digital signal read from the third storage unit; Image sensor.

25. 25. The imaging device according to claim 23 or 24, the first substrate has disposed thereon a first comparison unit for converting the first signal into the first digital signal, a second comparison unit for converting the third signal into the third digital signal, and a third comparison unit for converting the fifth signal into the fifth digital signal; Image sensor.

26. 26. The imaging device according to claim 25, the first conductive member electrically connects the first comparing unit and the first storage unit; the second conductive member electrically connects the second comparing unit and the second storage unit; the third conductive member electrically connects the third comparing unit and the third storage unit; Image sensor.

27. 27. The imaging device according to claim 20, An imaging element comprising a fourth substrate, which is a substrate stacked on the first substrate, and on which a first control unit that controls the first calculation unit, a second control unit that controls the second calculation unit, and a third control unit that controls the third calculation unit are arranged.

28. 28. The imaging device according to claim 27, the fourth substrate is disposed between the second substrate and the third substrate in a direction in which the second substrate, the third substrate, and the fourth substrate are stacked; Image sensor.

29. 29. The imaging device according to claim 20, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction, the third photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the row direction. Image sensor.

30. 2. The imaging device according to claim 1, the first substrate is provided with second pixels each having a second photoelectric conversion unit arranged alongside the first photoelectric conversion unit in the row direction; a second storage unit is disposed on the second substrate and stores a third digital signal obtained by converting a third signal based on the charge converted by the second photoelectric conversion unit into a digital signal; a second calculation unit is disposed on the third substrate, the second calculation unit performing a second correlated double sampling process on the third digital signal read from the second storage unit, using a fourth digital signal obtained by converting a fourth signal read from the second pixel and used to remove noise contained in the third signal into a digital signal; Image sensor.

31. 31. The imaging device according to claim 30, the first storage unit stores the second digital signal; the second storage unit stores the fourth digital signal; the first calculation unit performs the first correlated double sampling process on the first digital signal read from the first storage unit by using the second digital signal read from the first storage unit; the second calculation unit performs the second correlated double sampling process on the third digital signal read from the second storage unit by using the fourth digital signal read from the second storage unit. Image sensor.

32. 32. The imaging device according to claim 30 or 31, a first comparing unit for converting the first signal into the first digital signal and a second comparing unit for converting the third signal into the third digital signal are arranged on the first substrate; Image sensor.

33. 32. The imaging device according to claim 30 or 31, a first connection portion for electrically connecting the first substrate and the second substrate, the first connection portion having first conductive members arranged to face each other in a direction in which the first substrate and the second substrate are stacked; a second connection portion for electrically connecting the first substrate and the second substrate, the second connection portion having second conductive members arranged to face each other in the stacking direction of the first substrate and the second substrate; a third connection portion for electrically connecting the second substrate and the third substrate, the third connection portion having a first through electrode that penetrates the second substrate; a fourth connection portion for electrically connecting the second substrate and the third substrate, the fourth connection portion having a second through electrode that penetrates the second substrate; An imaging element comprising:

34. 34. The imaging device according to claim 33, the first through-electrode outputs the first digital signal read from the first storage unit, the second through-electrode outputs the third digital signal read from the second storage unit; Image sensor.

35. 35. The imaging device according to claim 33 or 34, a first comparing unit for converting the first signal into the first digital signal and a second comparing unit for converting the third signal into the third digital signal are arranged on the first substrate; Image sensor.

36. 36. The imaging device according to claim 35, the first conductive member electrically connects the first comparing unit and the first storage unit; the second conductive member electrically connects the second comparing unit and the second storage unit; Image sensor.

37. 37. The imaging device according to claim 30, An imaging element comprising a fourth substrate, which is a substrate stacked on the first substrate and on which a first control unit that controls the first calculation unit and a second control unit that controls the second calculation unit are arranged.

38. 38. The imaging device according to claim 37, the fourth substrate is disposed between the second substrate and the third substrate in a direction in which the second substrate, the third substrate, and the fourth substrate are stacked; Image sensor.

39. 39. The imaging device according to claim 30, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the row direction. Image sensor.

40. An imaging device comprising the imaging element according to any one of claims 1 to 39.

41. 41. The imaging device according to claim 40, a generation unit electrically connected to the imaging element and generating image data; An imaging device comprising:

42. 42. The imaging device according to claim 40 or claim 41, The imaging element receives light emitted from an optical system. Imaging device.

43. 43. The imaging device according to claim 42, an imaging device to which the optical system is attached;

Images