Chip integrated heat dissipation system and preparation method thereof

Abstract

The invention relates to a chip integrated heat dissipation system and a preparation method thereof, and belongs to the technical field of heat dissipation of semiconductor devices. The chip integrated heat dissipation system comprises a nano-diamond transition layer attached to a chip. A micro-column array supporting layer is arranged on one side, far away from the chip, of the nano-diamond transition layer; the micro-column array supporting layer is in contact with one surface of the diamond film, and the other surface of the diamond film is attached to the three-dimensional micro-channel heat dissipation layer. The invention also provides a preparation method of the chip integrated heat dissipation system. The chip integrated heat dissipation system provided by the invention has the advantage of efficient heat dissipation, and through the combination of the three-dimensional structure and the high heat conduction characteristic of diamond, the heat dissipation power density is remarkably improved, the junction temperature of the chip is reduced, and the heat dissipation requirement of a high-power device is met. The heat dissipation performance reliability is high, the thermal stress is eliminated through the gradient structure design, the interlayer binding force is improved, and the stable performance is still kept after multiple thermal cycles. And the preparation process is good in compatibility and convenient for large-scale production.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device heat dissipation, and in particular to a chip integrated heat dissipation system and a preparation method thereof. BACKGROUND

[0002] With the rapid development of semiconductor technology, the power density of electronic devices is constantly rising, and the heat dissipation problem has become a key factor restricting its performance and reliability. Traditional heat dissipation technology gradually exposes many limitations when dealing with high-power density chips. Traditional metal heat sinks, such as copper and aluminum, have been widely used in chip heat dissipation for a long time due to their good processing performance and relatively high thermal conductivity. However, its thermal conductivity is limited, and the thermal conductivity of copper is about 400 W / m·K. For 5G communication chips, GPUs and other high-power density chips, the heat flux density generated is more than 500 W / cm², and the traditional metal heat sink has been difficult to meet the heat dissipation demand. Ceramic materials such as aluminum nitride (AlN) and beryllium oxide (BeO) have good insulation and have been applied in some applications that require high insulation. However, its thermal conductivity is relatively low, generally between 200-300 W / m·K, which still has a big gap compared with the thermal conductivity of diamond, which is as high as 2000 W / m·K.

[0003] Although the existing diamond heat dissipation scheme utilizes the high thermal conductivity of diamond, it mostly uses physical bonding to combine diamond with chips. This method has the problem of high interfacial thermal resistance (ITR), which is usually as high as 20-50 K·cm 2 / W. At the same time, due to the mismatch of the thermal expansion coefficient (CTE) between the chip and the diamond, delamination may occur between the diamond layer and the chip in a high-temperature working environment, affecting the heat dissipation effect and the reliability of the device. SUMMARY

[0004] In view of the low heat dissipation efficiency of the existing chip heat dissipation device and the problem that it cannot meet the heat dissipation demand of high-power devices, the present application provides a chip integrated heat dissipation system and a preparation method thereof to solve the above problems. The present application provides a high-efficiency heat dissipation system composed of four functional layers, which constructs a multi-stage heat conduction path from the chip surface to the external environment through deep coupling of material properties and structural design, improves the heat dissipation efficiency of the heat dissipation device, and can meet the heat dissipation demand of high-power devices.

[0005] The technical scheme of the present application is as follows: In a first aspect, the present application provides a chip integrated heat dissipation system, which comprises a nanodiamond transition layer attached to a chip; the nanodiamond transition layer is provided with a microcolumn array support layer on the side away from the chip; the microcolumn array support layer is in contact with one face of a diamond film, and the other face of the diamond film is attached to a three-dimensional microchannel heat dissipation layer.

[0006] In this invention, a nanocrystalline diamond transition layer is directly bonded to the chip's heat-generating surface. It is formed using a nanocrystalline diamond thin film material, uniformly grown via chemical vapor deposition (CVD). Its core function lies in bridging the physical and thermal properties of the chip and the subsequent heat dissipation layer. On one hand, it acts as a "buffer layer," alleviating interfacial stress caused by lattice mismatch between the chip and diamond, avoiding the delamination failure problem commonly found in traditional direct bonding. On the other hand, it acts as a "nucleation layer," providing a highly active surface for the subsequent growth of diamond structures and enhancing interlayer bonding. The porous microstructure of the nanocrystalline diamond can also effectively capture interfacial defects, further reducing interfacial thermal resistance and forming the first efficient channel for heat transfer from the chip to the outside.

[0007] Furthermore, the micropillar array support layer is composed of multiple regularly arranged micropillar structures.

[0008] Furthermore, the main body of the micropillar structure is made of silicon-based material, and the surface is uniformly covered with a single-crystal diamond coating to form a "silicon pillar-diamond" composite heat-conducting unit.

[0009] In this invention, a regularly arranged micropillar structure is constructed on the side of the nanodiamond transition layer away from the chip using micro-nano fabrication technology. The micropillars are distributed in three dimensions, significantly overcoming the heat dissipation area limitations of traditional planar structures and forming a dense network of heat conduction nodes. The single-crystal diamond coating utilizes its extremely high intrinsic thermal conductivity (far exceeding that of ordinary metals and ceramics) to rapidly conduct heat from local hot spots on the chip to the tops of the micropillars, and then achieves lateral heat diffusion through the gaps between the pillars, laying the foundation for efficient heat exchange in the subsequent three-dimensional flow channels.

[0010] Furthermore, the three-dimensional microchannel heat dissipation layer adopts a serpentine or spiral microchannel structure, with the main material being a high thermal conductivity metal (such as copper), and the inner wall is coated with a polycrystalline diamond film using atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques.

[0011] In this invention, a three-dimensional microchannel heat dissipation layer is integrated on the outside of the micropillar array. The three-dimensional curved design of the microchannels extends the contact path between the coolant and the wall surface. Combined with the ultra-smooth surface (roughness ≤ nanometer level) of the inner wall diamond film, fluid resistance is significantly reduced and the convective heat transfer coefficient is improved. The polycrystalline diamond film has both high thermal conductivity and chemical stability, ensuring rapid heat transfer to the coolant while protecting the metal channels from corrosion. It is suitable for efficient heat dissipation media such as two-phase flow and phase change cooling.

[0012] Furthermore, the space between the chip and the nanodiamond transition layer, and between the micropillar array support layer and the three-dimensional microchannel heat dissipation layer, is filled with a highly thermally conductive nanocomposite slurry.

[0013] In this invention, a highly thermally conductive nanocomposite slurry is filled in key interfacial gaps such as the transition layer between the chip and the nanodiamond, the micropillar array support layer, and the three-dimensional microfluidic heat dissipation layer. This slurry, with one-dimensional / two-dimensional thermally conductive fillers such as silver nanowires and graphene as its core, forms a cross-scale thermally conductive network, breaking through the thermal conductivity bottleneck of traditional silicone grease-based materials, achieving an exponential reduction in interlayer thermal resistance, and ensuring bottleneck-free heat transfer between heterogeneous material interfaces.

[0014] Furthermore, a support base is provided at the bottom of the three-dimensional microchannel heat dissipation layer.

[0015] Secondly, the present invention provides a method for fabricating the above-mentioned chip-integrated heat dissipation system, comprising the following steps: (1) A nanodiamond transition layer is prepared on the heating surface of the chip by chemical vapor deposition; wherein the reaction gases are CH4 and H2; The nanodiamond transition layer (NCD) is grown on the chip surface via chemical vapor deposition (CVD). Its porous microstructure provides highly active nucleation sites for the subsequent single-crystal diamond (SCD) coating on the micropillars. The micropillar array uses silicon-based materials, and single-crystal diamond coatings (with crystal orientation deviation ≤5°) are directionally grown on the surface of the micropillars using seed-assisted CVD technology. This allows the single-crystal diamond (SCD) coating and the nanodiamond (NCD) transition layer to form a chemical metallurgical bond, rather than a simple physical stacking, ensuring interfacial adhesion.

[0016] (2) Photolithography defines a circular pattern. The micropillars are formed into a vertical silicon pillar array (height-to-diameter ratio ≥ 10:1) through photolithography and reactive ion etching (RIE). The silicon substrate is then etched to a depth of 100 μm to form a vertical micropillar array. A nanodiamond transition layer is directly embedded at the bottom of the micropillar array. The nanoscale roughness (Ra≤10nm) of the transition layer and the pillar structure of the micropillars form a mechanical interlock, increasing the contact area and strengthening the interface fixation. Then, using seed-assisted chemical vapor deposition, CH4 and H2 are introduced to form a directionally grown single-crystal diamond coating on the surface of the micropillars. (3) Electroforming method is used to prepare serpentine copper microchannels with a flow channel curvature radius ≥200 μm to avoid fluid dead zones; then titanium layer is deposited by atomic layer deposition (ALD), and then polycrystalline diamond (PCD) film is grown on the inner wall of copper microchannel by hot filament chemical vapor deposition (CVD) with a surface roughness Ra≤15 nm to enhance corrosion resistance. (4) Low-temperature bonding and encapsulation: Through surface activated bonding (SAB), the single crystal diamond (SCD) coating of the micropillar is directly bonded to the copper flow channel under certain temperature and pressure, with no void defects at the interface and a bonding strength ≥80 MPa; finally, fluid encapsulation is performed: micro pumps and flow sensors are integrated at both ends of the micro channel to form a closed-loop cooling system with a coolant filling rate ≥95%.

[0017] Furthermore, before implementing step (1), the chip is pre-treated. First, the chip surface is activated: the back of the silicon chip is cleaned with Ar plasma to remove the oxide layer and reduce the roughness to Ra≤10nm; then, a chromium (Cr) layer is deposited on the chip surface by magnetron sputtering as an anchoring layer for diamond growth to improve the interface bonding force.

[0018] Furthermore, in step (2), the volume ratio of CH4 to H2 is CH4 / H2 = 5%, the total flow rate is 500 sccm, the chamber pressure is 15 kPa, the substrate temperature is 600 ℃, the growth time is 90 minutes, and the resulting single-crystal diamond coating has a grain density ≥10. 10 / cm 2 Crystal orientation deviation ≤ 5°.

[0019] The beneficial effects of this invention are as follows: The chip-integrated heat dissipation system provided by this invention utilizes an innovative and collaborative mechanism, offering the following advantages: (1) Gradient thermal conduction and thermal stress regulation A three-layer material gradient design—nanocrystalline diamond (flexible buffer) → single-crystal diamond (directional thermal conduction) → polycrystalline diamond (uniform diffusion)—is employed to construct a progressive transition system for the coefficient of thermal expansion (CTE). The nanocrystalline diamond layer, with its high interfacial tolerance due to its nanoscale grains, absorbs the CTE difference between the chip and the diamond system (silicon chip CTE approximately 2.6 ppm / K, diamond approximately 1.0 ppm / K), reducing interfacial thermal stress by over 80%. The single-crystal diamond micropillars utilize their uniform crystal orientation to form a "high-speed thermal conduction channel" along the pillar axis, directionally dissipating concentrated heat from the chip. The inner wall of the polycrystalline diamond channel, through the isotropic thermal conductivity of its polycrystalline structure, uniformly diffuses concentrated heat across the entire channel surface, preventing localized overheating. This synergistic effect of the three materials solves the compatibility problem between heterogeneous materials and constructs an efficient thermal conduction path from the chip's micro-area to the macroscopic channel.

[0020] (2) Three-dimensional microstructure synergistic heat dissipation mechanism The micropillar array and the three-dimensional flow channel form a multi-level heat dissipation network of "point-surface-volume": Micropillar array: The micron-scale columnar structure increases the effective heat dissipation area of ​​the chip surface by 5-8 times. The single-crystal diamond coating on the surface of each micropillar acts as a "micro thermally conductive antenna" to directly capture the heat in the hot spot area of ​​the chip and achieve rapid longitudinal heat conduction through the high aspect ratio (≥5:1) of the pillar.

[0021] Three-dimensional flow channel: A serpentine microchannel layout surrounds the micropillar array, forming a "surrounding" coolant flow field. The coolant (such as the fluorinated Novec 7100) makes full contact with the tips of the micropillars during flow, efficiently removing heat through convection and phase change heat transfer (designed for two-phase flow). A diamond film on the inner wall of the microchannel further reduces wall thermal resistance, increasing the heat dissipation power density by more than three times compared to traditional planar flow channels, exceeding 1000 W / cm². 2 bottleneck.

[0022] (3) Innovation in low-temperature bonding and integration processes Surface activated bonding (SAB) technology achieves high-strength metallurgical bonding between layers in a low-temperature chip bonding environment of 150 ℃~200 ℃, avoiding the thermal damage to the chip caused by traditional high-temperature bonding. This process removes the interface oxide layer through plasma pretreatment, achieving atomic diffusion bonding at the nanoscale. The bonding strength is increased by 50% compared to traditional solder bonding, and the interface thermal resistance can be controlled within 5 K·cm. 2 Below / W. Meanwhile, the integrated design of the flow channels and micropillars adopts a "molding first, then bonding" strategy to ensure the geometric accuracy and fluid sealing of the three-dimensional structure, achieving seamless connection between the microchannels and the chip heat dissipation unit.

[0023] In summary, the chip-integrated heat dissipation system provided by this invention possesses the advantages of high-efficiency heat dissipation. By combining a three-dimensional structure with the high thermal conductivity of diamond, it significantly improves heat dissipation power density, reduces chip junction temperature, and meets the heat dissipation requirements of high-power devices. It also exhibits high reliability in heat dissipation performance; the gradient structure design eliminates thermal stress and enhances interlayer bonding, maintaining stable performance even after multiple thermal cycles. Furthermore, it demonstrates good process compatibility, as the fabrication process is compatible with existing semiconductor manufacturing processes, facilitating large-scale production and reducing manufacturing costs. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the overall structure of the chip integrated heat dissipation system of the present invention.

[0026] Figure 2 This is a flowchart illustrating the fabrication process of the chip-integrated heat dissipation system of this invention.

[0027] In the figure, 1-chip, 2-micropillar array support layer, 3-nano diamond transition layer, 4-diamond film, 5-three-dimensional microchannel heat dissipation layer, 6-support base. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0029] To address the problem of low heat dissipation efficiency in chip heat dissipation devices, which fails to meet the heat dissipation requirements of high-power devices, this invention provides a chip-integrated heat dissipation system and its fabrication method. Referring to... Figure 1 The chip-integrated heat dissipation system includes a nanodiamond transition layer 3 bonded to chip 1; a micropillar array support layer 2 is provided on the side of the nanodiamond transition layer 3 away from the chip; the micropillar array support layer 2 is in contact with one side of a diamond film 4, and the other side of the diamond film 4 is bonded to a three-dimensional microfluidic heat dissipation layer 5. The nanodiamond transition layer 3 is directly bonded to the heat-generating surface of chip 1 and is formed by uniform growth of nanocrystalline diamond film material through chemical vapor deposition (CVD). Its core function is to bridge the physical and thermal properties of chip 1 and the subsequent heat dissipation layer. On the one hand, it acts as a "buffer layer" to alleviate the interfacial stress caused by lattice mismatch between the chip and diamond, avoiding the delamination failure problem commonly found in traditional direct bonding; on the other hand, it acts as a "nucleation layer" to provide a highly active surface for the subsequent growth of diamond structures, enhancing the interlayer bonding force. The porous microstructure of nanocrystalline diamond can also effectively capture interface defects, further reducing interfacial thermal resistance and forming the first efficient channel for heat transfer from the chip to the outside.

[0030] In some preferred embodiments, the micropillar array support layer 2 is composed of multiple regularly arranged micropillar structures. The main body of the micropillar structure is a silicon-based material, with a uniform single-crystal diamond coating on the surface, forming a "silicon pillar-diamond" composite thermally conductive unit. On the side of the nanodiamond transition layer away from the chip, a regularly arranged micropillar structure is constructed using micro-nano fabrication technology. The micropillars are distributed in three dimensions, significantly breaking through the heat dissipation area limitations of traditional planar structures and forming a dense network of heat conduction nodes. The single-crystal diamond coating utilizes its extremely high intrinsic thermal conductivity to rapidly conduct heat from local hot spots on the chip to the top of the micropillars, and then achieves lateral heat diffusion through the gaps between the pillars, laying the foundation for efficient heat exchange in the subsequent three-dimensional flow channels.

[0031] In some preferred embodiments, the three-dimensional microchannel heat dissipation layer 5 adopts a serpentine or spiral microchannel structure, with the main material being high thermal conductivity copper. The inner wall is coated with a polycrystalline diamond film using atomic layer deposition (ALD) and chemical vapor deposition (CVD) techniques. The three-dimensional microchannel heat dissipation layer is integrated on the outside of the micropillar array. The three-dimensional curved design of the microchannels extends the contact path between the coolant and the wall surface. Combined with the ultra-smooth surface of the inner wall diamond film (roughness ≤ nanometer level), this significantly reduces fluid resistance and improves the convective heat transfer coefficient. The polycrystalline diamond film possesses both high thermal conductivity and chemical stability, ensuring rapid heat transfer to the coolant while protecting the metal channels from corrosion, making it suitable for efficient heat dissipation media such as two-phase flow and phase change cooling.

[0032] In some preferred embodiments, a highly thermally conductive nanocomposite slurry is filled between the chip 1 and the nanodiamond transition layer 3, and between the micropillar array support layer 2 and the three-dimensional microfluidic heat dissipation layer 5. The highly thermally conductive nanocomposite slurry uses one-dimensional / two-dimensional thermally conductive fillers such as silver nanowires and graphene as its core to form a cross-scale thermally conductive network, breaking through the thermal conductivity bottleneck of traditional silicone grease-based materials, achieving an exponential reduction in interlayer thermal resistance, and ensuring bottleneck-free heat transfer between heterogeneous material interfaces.

[0033] In some preferred embodiments, the bottom of the three-dimensional microchannel heat dissipation layer 5 is provided with a support base 6.

[0034] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to specific implementation methods. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0035] Example 1 A method for fabricating a chip-integrated heat dissipation system includes the following steps: 1. Substrate and Material Selection (1) Chip: Select a 50 mm × 50 mm × 0.5 mm silicon (Si) chip with high-density power units integrated on the back side. The target heat flux density is 800 W / cm².

[0036] (2) Nanocrystalline diamond transition layer material: nanocrystalline diamond (NCD) with a grain size of 50~100 nm, grown by plasma-enhanced chemical vapor deposition (PECVD).

[0037] (3) Micropillar array support layer material: monocrystalline silicon with a 2 μm monocrystalline diamond (SCD) coating grown on the surface.

[0038] (4) Microchannel material: electrolytic copper (purity ≥99.99%), with a 1 μm polycrystalline diamond (PCD) film coated on the inner wall.

[0039] (5) High thermal conductivity nanocomposite slurry: Silver nanowires (50 nm in diameter and 10-20 μm in length) and graphene (5-10 μm in diameter) mixed slurry in a volume ratio of 3:2, dispersed in a polyimide matrix.

[0040] 2. Preparation process (1) Chip pretreatment (surface activation) (a) Cleaning: The chip was placed in acetone and ethanol for ultrasonic cleaning for 15 minutes each to remove surface oil; then transferred to deionized water for ultrasonic cleaning for 30 minutes to remove ionic impurities.

[0041] (b) Roughening: Ar plasma treatment (power 150W, pressure 10Pa, time 10 minutes) is used to form a nanoscale uneven structure (roughness Ra≤5nm) on the back of the chip to enhance the interfacial bonding force.

[0042] (c) Nucleation layer deposition: A 10 nm chromium (Cr) layer was deposited on the back of the chip by magnetron sputtering at a sputtering power of 200 W, an argon flow rate of 50 sccm, and a deposition time of 10 minutes.

[0043] (2) Growth of nanodiamond transition layer (a) Equipment: Microwave plasma CVD (MPCVD) system with a reaction chamber volume of 50 L.

[0044] (b) Process parameters: Reaction gas: CH4 / H2=5% (volume ratio), total flow rate 500 sccm; Chamber pressure: 15kPa; Substrate temperature: 600 ℃; Growth time: 90 minutes.

[0045] (3) Results: A uniform 200 nm nanodiamond (NCD) layer was formed, and the Raman spectrum showed a depth of 1332 cm⁻¹. -1 The characteristic peaks of strong diamond are present, while the intensity of impurity peaks is <5%.

[0046] (3) Fabrication of micropillar array support layer and single crystal diamond coating (a) Micropillar etching: Photolithography: Coating with SU-8 photoresist (2 μm thick), exposure wavelength 365 nm, development time 60 seconds, forming a circular pattern with a diameter of 10 μm and a spacing of 50 μm.

[0047] Etching: Reactive ion etching (RIE), gas SF6 / O2=8:2, power 200 W, etching rate 1 μm / min, depth 100 μm, forming a vertical silicon micropillar array with a height-to-diameter ratio of 10:1.

[0048] (b) Single-crystal diamond growth: Seed crystal pretreatment: Coat the surface of the micropillar with a 5 nm diamond seed crystal solution (concentration 1 mg / ml) and dry at 120 ℃ for 30 minutes.

[0049] Secondary CVD: CH4 (1.5%) / H2 was introduced, pressure 10 kPa, temperature 850 ℃, growth rate 5 μm / h, duration 0.4 hours, forming a 2 μm thick single crystal diamond (SCD) coating. X-ray diffraction (XRD) showed that the (111) crystal orientation was dominant and the full width at half maximum (FWHM) was <0.5°.

[0050] (4) Fabrication of three-dimensional microchannel heat dissipation layer (a) Electroforming of copper: Mold preparation: SU-8 photoresist was used to prepare a serpentine flow channel mold (width 50 μm, depth 200 μm, radius of curvature 300 μm).

[0051] Electroforming solution: copper sulfate solution (concentration 200 g / L, sulfuric acid concentration 50 g / L), current density 2 A / dm³ 2 Electroforming time is 6 hours to form a copper microfluidic substrate.

[0052] (b) Inner wall coating treatment: Atomic layer (ALD) deposition of titanium layer: at a temperature of 150 °C, titanium tetrachloride (TiCl4) and water vapor are alternately introduced, and a 5 nm adhesion layer is formed after 200 cycles.

[0053] Hot-filament CVD growth of polycrystalline diamond: filament temperature 2000 ℃, CH4 / H2=3%, pressure 5 kPa, growth time 2 hours, forming a 1 μm uniform PCD film with surface roughness Ra≤10 nm.

[0054] (5) Interlayer bonding and encapsulation (a) Low-temperature bonding: Surface activation: The copper substrate of the three-dimensional microchannel heat dissipation layer and the micropillar array support layer are treated with Ar plasma (power 100 W, time 5 minutes) to remove the surface oxide layer.

[0055] Bonding process: Vacuum bonding at 150 ℃ and 5 MPa pressure (equipment: hot press bonding machine), bonding time 30 minutes, interface was ultrasonically scanned and no void defects were found.

[0056] (b) High thermal conductivity nanocomposite slurry filling: Silver nanowire-graphene slurry was uniformly coated in the gap between the chip and the nanodiamond transition layer (thickness 50 μm), cured at 100 ℃ for 1 hour, and the thermal conductivity test value was 620 W / m·K.

[0057] (c) Fluid encapsulation: Micro connectors are welded to both ends of the three-dimensional microchannel and connected to the coolant circulation system (pump flow rate 50ml / min, coolant is Novec7100).

[0058] Example 2 The performance of the chip-integrated heat dissipation system prepared in Example 1 was tested, as follows: By applying a corresponding heat flux density using a thermal resistance tester, the thermal resistance of the integrated heat dissipation system prepared in Example 1 of this invention is compared with that of a traditional copper heat sink.

[0059] Traditional copper radiators refer to heat dissipation structures that use copper as the main body and rely on physical contact for heat conduction. They typically consist of a copper base with copper or aluminum fins. Copper's high thermal conductivity (400 W / m·K) allows for rapid heat absorption, while copper or aluminum's high heat dissipation efficiency (226 W / m·K) accelerates heat dissipation. The copper-aluminum joint relies on physical welding, resulting in high interfacial thermal resistance.

[0060] Traditional copper heat sink testing conditions are: 100 W constant heat load, ambient temperature 20.6 ℃, and chip contact area 1 cm². 2 The interface is filled with silicone grease.

[0061] The integrated heat dissipation system prepared in Example 1 of this invention was tested under the following conditions: 100 W heat load, ambient temperature 20.6℃, and chip contact area 1 cm². 2 It employs a nanodiamond transition layer and surface activation bonding technology.

[0062] Actual test results: (1) Traditional copper radiators: Junction temperature rise: ΔT = 37.4 ℃ (i.e., junction temperature TJ = 20.6 ℃ + 37.4 ℃ = 58 ℃).

[0063] Effect of interfacial thermal resistance: Silicone grease filling increases interfacial thermal resistance by 20-50 K·cm 2 / W (Actual thermal resistance 20-50 K / W ÷ 1cm) 2 =20-50 K / W), directly contributing about 10~15 ℃ temperature rise.

[0064] Limitations: The planar structure has low heat dissipation efficiency, relies solely on two-dimensional expansion, and the actual hot spot temperature of the chip may exceed 80℃.

[0065] Thermal cycling test: -40℃~120℃, after 1000 cycles, the interfacial thermal resistance changed by 5.2%, the total system thermal resistance changed by 5.5%, the oxide layer of the copper and aluminum fins thickened, and the thermal conductivity decreased.

[0066] (2) Integrated heat dissipation system prepared in Example 1 Junction temperature rise: ΔT = 15 ℃ (i.e. junction temperature TJ ≤ 35.6 ℃), which is about 60% lower than the traditional scheme.

[0067] Advantages in interfacial thermal resistance: The interfacial thermal resistance of the nanodiamond transition layer is ≤5 K·cm. 2 / W (Actual thermal resistance ≤ 5K / W ÷ 1cm) 2 =5 K / W), contributing a temperature rise of ≤2.5 ℃.

[0068] Technological breakthrough: The three-dimensional micro-pillar array and serpentine flow channel design increase the heat dissipation area by 5-8 times, and the hot spot temperature uniformity error is <±2 ℃.

[0069] Thermal cycling test: -40 ℃~120 ℃, after 1000 cycles, the interface thermal resistance changed by 2.8%, and the total system thermal resistance changed by 1.3% (due to the partial offsetting of changes by the cooperation of multiple structures), and there was no delamination or cracking in the structure.

[0070] As can be clearly seen from the above embodiments, the present invention achieves a reliable combination of different chips such as silicon and silicon carbide with a diamond heat dissipation layer through a nano-diamond transition layer. The size of the micropillars and the shape of the flow channels can be customized according to the heat dissipation characteristics of the chip, adapting to different heat dissipation requirements such as point heat sources and surface heat sources. It constructs a complete heat dissipation chain of "chip micro-area heat collection - three-dimensional structure heat transfer - fluid medium heat diffusion". The optimization of the entire chain from material interface to system architecture breaks through the key technical bottleneck of heat dissipation of high-power devices, and provides key technical support for the reliable operation of high-density integrated circuits.

[0071] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A chip-integrated heat dissipation system, characterized in that, It includes a nanodiamond transition layer that is bonded to the chip; a micropillar array support layer is provided on the side of the nanodiamond transition layer away from the chip; the micropillar array support layer is in contact with one side of the diamond film, and the other side of the diamond film is bonded to a three-dimensional microchannel heat dissipation layer.

2. The chip integrated heat dissipation system as described in claim 1, characterized in that, The micropillar array support layer consists of multiple regularly arranged micropillar structures.

3. The chip integrated heat dissipation system as described in claim 1, characterized in that, The micropillar structure is mainly made of silicon-based material, and its surface is uniformly covered with a single-crystal diamond coating.

4. The chip integrated heat dissipation system as described in claim 1, characterized in that, The three-dimensional microchannel heat dissipation layer adopts a serpentine or spiral microchannel structure, with the main material being a high thermal conductivity metal, and the inner wall being coated with a polycrystalline diamond film using atomic layer deposition and chemical vapor deposition techniques.

5. The chip integrated heat dissipation system as described in claim 4, characterized in that, The high thermal conductivity metal is copper.

6. The chip integrated heat dissipation system as described in claim 1, characterized in that, The space between the chip and the nanodiamond transition layer, and between the micropillar array support layer and the three-dimensional microchannel heat dissipation layer, is filled with a highly thermally conductive nanocomposite slurry.

7. The chip integrated heat dissipation system as described in claim 1, characterized in that, The bottom of the three-dimensional microchannel heat dissipation layer is provided with a support base.

8. A method for fabricating a chip-integrated heat dissipation system as described in claim 1, characterized in that, Includes the following steps: (1) A nanodiamond transition layer is prepared on the heating surface of the chip by chemical vapor deposition; The reacting gases are CH4 and H2; (2) Photolithography defines a circular pattern, reactive ion etching the silicon substrate to a depth of 100 μm to form a vertical micropillar array; then, using seed-assisted chemical vapor deposition technology, CH4 and H2 are introduced to form a directionally grown single-crystal diamond coating on the surface of the micropillars. (3) Electroforming method is used to prepare serpentine copper microchannels with a flow channel curvature radius ≥200 μm to avoid fluid dead zones; then titanium layer is deposited by atomic layer deposition, and then polycrystalline diamond film is grown by hot filament chemical vapor deposition with a surface roughness Ra≤15nm. (4) Low-temperature bonding and encapsulation: Through surface activation bonding, the diamond layer and the copper flow channel are directly bonded under certain temperature and pressure, with no void defects at the interface and a bonding strength ≥80 MPa; finally, fluid encapsulation is performed: micro pumps and flow sensors are integrated at both ends of the micro channel to form a closed-loop cooling system with a coolant filling rate ≥95%.

9. The preparation method according to claim 8, characterized in that, Before implementing step (1), the chip is pre-treated. First, the chip surface is activated: the back of the silicon chip is cleaned with Ar plasma to remove the oxide layer and reduce the roughness to Ra≤10nm; then, a chromium layer is deposited on the chip surface by magnetron sputtering as an anchoring layer for diamond growth to improve the interface bonding force.

10. The preparation method according to claim 8, characterized in that, In step (2), the volume ratio of CH4 to H2 is CH4 / H2 = 5%, the total flow rate is 500 sccm, the chamber pressure is 15 kPa, the substrate temperature is 600 ℃, the growth time is 90 minutes, and the resulting single-crystal diamond coating has a grain density ≥10. 10 / cm 2 Crystal orientation deviation ≤ 5°.

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