Electrostatic chuck with improved temperature control

Abstract

Embodiments of the present disclosure provide an electrostatic chuck for securing a substrate during processing. Some embodiments of the present disclosure provide methods and apparatus for increased temperature control across the radial profile of a substrate. Some embodiments of the present disclosure provide methods and apparatus for providing control of hydrogen concentration in a film being processed during a high-density plasma (HDP) process.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to an apparatus for fixing a substrate during processing. Specifically, embodiments of the present disclosure relate to an apparatus and method for fixing a substrate during a high density plasma (HDP) process.

Background Art

[0002] Negative-bias temperature instability (NBTI) is a major reliability issue in metal-oxide-semiconductor field-effect transistors (MOSFETs). NBTI manifests as an increase in the threshold voltage of the MOSFET and, as a result, a decrease in drain current and transconductance. Generally, a more stable dynamic random access memory (DRAM) refresh rate and NBTI performance are preferred to provide an improved device yield.

[0003] Gate-induced drain leakage (GIDL) is a leakage current that occurs due to a high electric field between the gate and the drain. GIDL occurs when the MOSFET is biased in the accumulation region and when the drain bias is much lower than the breakdown voltage.

[0004] Gate-induced drain leakage is an undesirable short-channel effect that occurs at a higher drain bias when the transistor is in an overdriven off state. GIDL is a result of the deep depletion region formed at the drain at a high off bias (negative for NFETs and positive for PFETs). The depletion region causes a band bend that enables conductive-band-to-band tunneling, which creates an excess current. GIDL can be detrimental to integrated circuits, specifically non-volatile memory circuits such as flash EEPROMs.

[0005] Higher temperatures at the edge of the substrate during the MOSFET formation process lead to lower hydrogen concentration (H%) in the processed layer of the substrate. Conversely, lower temperatures result in higher H% for the processed film and higher wet etching rate (WER).

[0006] In particular, the adjustability or control of the substrate temperature, especially at the edge, is also limited by the design of the electrostatic chuck (ESC). Current designs limit the maximum gas pressure edge cooling channels between the wafer and the ESC before gas leakage becomes a problem. This design capacity limits the available parameters between the inner and outer channels for adjusting the temperature and H% at the edge of the wafer.

[0007] Therefore, there is a need in the art for an apparatus that enables increased adjustability of the temperature and H% of the film processed by HDP at the edge of the wafer. SUMMARY OF THE INVENTION

[0008] One or more embodiments of the present disclosure are directed to an electrostatic chuck comprising a top surface, a bottom surface, and a controller. The top surface comprises a central region with a plurality of substrate support mesas, an inner channel (IC) having an IC width that surrounds the central region, an inner band (IB) having an IB width that surrounds the inner channel, an outer channel (OC) having an OC width that surrounds the inner band, and an outer band (OB) having an OB width that surrounds the outer channel. The controller is configured to control the temperature across the entire area of the wafer fixed to the top surface of the electrostatic chuck during processing.

[0009] Additional embodiments of the present disclosure are directed to an electrostatic chuck having a top surface and a bottom surface. The top surface includes a central region having a plurality of substrate support mesas, an inner channel (IC) having an IC width that surrounds the central region, an inner band (IB) having an IB width that surrounds the inner channel, an outer channel (OC) having an OC width that surrounds the inner band, and an outer band (OB) having an OB width that surrounds the outer channel. The electrostatic chuck is configured to provide an H% with a range (R / 2) divided by 2 of about 2% or less across the entire area of the wafer during processing.

[0010] Further embodiments of the present disclosure are directed to a method of modifying an electrostatic chuck to improve temperature control across the entire area of a wafer surface fixed to the top surface of the electrostatic chuck. The method includes reducing the surface roughness of the top surface of the electrostatic chuck, changing the shape of the plurality of substrate support mesas, reducing the contact area for the plurality of substrate support mesas, increasing the width of the inner band of the electrostatic chuck, increasing the width of the outer band of the electrostatic chuck, increasing the pressure in the outer channel, and reducing the pressure in the inner channel, and includes one or more of these.

[0011] So that the manner in which the features of the present disclosure have been described above can be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be made by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure, and therefore the present disclosure should not be considered limited with respect to the scope of the present disclosure, as it may admit other equally effective embodiments.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

[0013] Before describing various exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps to be discussed in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] As used herein and in the appended claims, the term "substrate" refers to the surface on which a process acts, or a portion of the surface. Also, it will be understood by those skilled in the art that a reference to a substrate may, in some cases, refer only to a portion of the substrate, unless the context clearly dictates otherwise. Additionally, a reference to a deposition on a substrate may mean both the bare substrate and the substrate on which one or more films or features have been deposited or formed thereon.

[0015] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during the manufacturing process. For example, the substrate surface on which processing can be performed may include materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, aluminum gallium arsenide, aluminum gallium nitride, glass, sapphire, etc., as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, without limitation, semiconductor wafers. The substrate may be subjected to a pretreatment process to perform polishing, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or firing on the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include the lower layer as indicated by the context. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] One or more embodiments of the present disclosure are directed to electrostatic chucks. Some embodiments of the present disclosure advantageously provide an electrostatic chuck configured to adjust the concentration of hydrogen (H%) across the surface of a wafer fixed to the electrostatic chuck. Some embodiments of the present disclosure advantageously provide an electrostatic chuck with a variability range (range divided by 2; R / 2) in H% of about 2% or less.

[0017] Many variability plots yield an average value of the measurements across the wafer in addition to the standard variability and range of values present on the wafer. The range of variability may be expressed as the range of the average value + / -. Since the range of variability extends both above and below the average value, the range of variability is sometimes simply expressed as R / 2, i.e., the variability from the average value in only one direction.

[0018] Referring to FIGS. 1 and 2, one or more embodiments of the present disclosure are directed to an electrostatic chuck 100. FIG. 1 illustrates a parallel projection view of the electrostatic chuck 100 according to one or more embodiments. FIG. 2 illustrates a partial cross-sectional view of the electrostatic chuck 100 according to one or more embodiments. The illustrated electrostatic chuck 100 generally has a disk-shaped body 101 including an upper coating layer 101A and a lower body 101B. The upper coating layer 101A has a top surface 102 and a bottom surface 104 that define the thickness T of the upper coating layer 101A. The upper coating layer 101A is in contact with the lower body 101B such that the top surface of the lower body is adjacent to the bottom surface 104 of the upper coating layer 101A. The lower body 101B has a bottom surface 105. The thickness of the body 101 including the upper coating layer 101A and the lower body 101B is in the range of about 1.5 inches to about 2.5 inches. In some embodiments, the thickness of the body 101 is about 2 inches. ESC The upper coating layer 101A has a top surface 102 and a bottom surface 104 that define the thickness T of the upper coating layer 101A. The upper coating layer 101A is in contact with the lower body 101B such that the top surface of the lower body is adjacent to the bottom surface 104 of the upper coating layer 101A. The lower body 101B has a bottom surface 105. The thickness of the body 101 including the upper coating layer 101A and the lower body 101B is in the range of about 1.5 inches to about 2.5 inches. In some embodiments, the thickness of the body 101 is about 2 inches.

[0019] In some embodiments, the thickness T of the upper coating layer 101A ESC is in the range of about 7 mils to about 15 mils, or about 8 mils to about 12 mils. In some embodiments, the thickness T of the upper coating layer 101A ESC is about 10 mils.

[0020] An outer peripheral edge 106 forms the outer boundary of the body 101. The top surface 102 is configured to support a substrate during processing.

[0021] The top surface 102 of the electrostatic chuck 100 includes a central region 110, an inner channel 120, an inner band 130, an outer channel 140, and an outer band 150. The central region 110, also referred to as the field of the electrostatic chuck 100, is adjacent to the inner channel 120 at its outer peripheral edge. The intersection 114 of the inner wall 121 of the inner channel 120 with the top surface 112 is the outer peripheral edge of the central region 110.

[0022] The diameter of the central region 110 relative to the total diameter of the upper coating layer 101A can vary. The diameter of the central region 110 is measured from the intersection 114 of the inner wall 121 of the inner channel 120 with the top surface 112 of the central region 110 passing through the center of the body 101. In some embodiments, the ratio of the diameter of the central region 110 to the diameter of the body 101 is in the range of 80% to 95%, or in the range of 85% to 95%, or in the range of 85% to 92%, or in the range of 86% to 90%.

[0023] The inner channel 120 adjacent to the central region 110 has a width W IC and extends over a depth D IC within the upper coating layer 101A of the electrostatic chuck 100. The width W IC is measured as the distance between the inner wall 121 and the outer wall 123 of the inner channel 120. The depth D IC is measured from the top surface 102 of the upper coating layer 101A to the bottom surface 122 of the inner channel 120. The thickness T IC of the upper coating layer 101A in the inner channel 120 is measured from the bottom surface 122 of the inner channel 120 to the bottom surface 104 of the upper coating layer 101A. In the embodiment illustrated in FIG. 2, the depth of the inner channel 120 close to the inner wall 121 is smaller than the depth D IC of the inner channel. The depth D IF close to the field of the central region 110 is shallower in this embodiment due to the top surface 112 being lower than the supporting surface which is the top surface 102.

[0024] The width W IC of the inner channel 120 is, according to some embodiments, in the range of 0.5 mm to 5 mm, or in the range of 1 mm to 5 mm, or in the range of 1.5 mm to 5 mm, or in the range of 2 mm to 5 mm, or in the range of 2 mm to 4.5 mm.

[0025] The depth D ICAccording to one or more embodiments, it is 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm or less. In some embodiments, the depth D of the inner channel 120 IC is in the range of 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60% of the thickness T of the upper coating layer 101A ESC .

[0026] The inner channel 120 is separated from the outer channel 140 by an inner band 130. The inner band 130 has a top surface 132 that is substantially coplanar with the top surface 102 of the upper coating layer 101A. When used in this way, the term "substantially coplanar" means that the major plane formed by the top surface 102 of the upper coating layer 101A is within ±0.025 mm of the major plane formed by the top surface 132 of the inner band 130.

[0027] The width W of the inner band 130 IB can be varied to change the spacing between the inner channel 120 and the outer channel 140. A standard electrostatic chuck may have an IB width of from about 2 mm to about 3 mm, more specifically from about 2.3 mm to about 2.7 mm. In some embodiments, the width W of the inner band IB (IB width) is increased by a proportion in the range of about 50% to about 60%, about 90% to about 110%, or about 50% to about 110%. In some embodiments, the IB width is increased by an amount in the range of about 1.2 mm to about 1.6 mm, about 2.0 mm to about 3.0 mm, or about 1.2 mm to about 3.0 mm.

[0028] The outer channel 140 adjacent to the inner band 130 has a width W OC and extends across a depth D within the upper coating layer 101A of the electrostatic chuck 100. The width W OC is measured as the distance between the inner wall 141 and the outer wall 143 of the outer channel 140. The depth D OC OC ​is measured from the top surface 102 of the upper coating layer 101A to the bottom surface 142 of the outer channel 140. The thickness T of the upper coating layer 101A in the outer channel 140 OC is measured from the bottom surface 142 of the outer channel 140 to the bottom surface 104 of the upper coating layer 101A.

[0029] The width W of the outer channel 140 OC According to some embodiments, is in the range of 0.5 mm to 10 mm, or 1 mm to 8 mm, or 2 mm to 6 mm, or 2.5 mm to 5.5 mm.

[0030] The depth D of the outer channel 140 OC According to one or more embodiments, is 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm or less. In some embodiments, the depth D of the outer channel 140 OC is the thickness T of the upper coating layer 101A ESC is in the range of 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60% of.

[0031] The outer band 150 is the region of the electrostatic chuck 100 between the outer wall 143 of the outer channel 140 and the outer peripheral edge 106 of the body 101. The width W of the outer band 150, which in some embodiments is in the range of 2 mm to 5.5 mm, 2.2 mm to 5.2 mm, 3.5 mm to 4 mm, 4 mm to 4.5 mm, 4.75 mm to 5.25 mm OB . A standard electrostatic chuck has an outer band width W of from about 1.7 mm to about 2.7 mm, more specifically from about 2.0 mm to about 2.4 mm OBIt may have an (OB width). In some embodiments, the OB width is increased by a proportion in the range of about 45% to about 55%, in the range of about 65% to about 70%, in the range of about 45% to about 70%, in the range of about 90% to about 110%, in the range of about 110% to about 150%, in the range of about 120% to about 140%, or in the range of about 45% to about 150%. In some embodiments, the OB width is increased by an amount in the range of about 1.3 mm to about 1.7 mm, in the range of about 2.8 mm to about 3.1 mm, or in the range of about 1.3 mm to about 3.1 mm.

[0032] In the embodiments illustrated in FIGS. 1 and 2, the central region 110 includes a plurality of substrate support mesas 115. The substrate support mesa 115 extends from the top surface 112 of the central region 110 to the top surface 116 of the substrate support mesa 115. In some embodiments, the top surfaces 116 of the plurality of substrate support mesas 115 are substantially in the same plane as each other. In some embodiments, the top surface 116 of the substrate support mesa 115 is substantially in the same plane as the top surface 102 of the upper coating layer 101A. The height of the substrate support mesa 115 depends on the height difference between the top surface 112 of the central region 110 and the top surface 102 of the upper coating layer 101A.

[0033] The substrate support mesa 115 may be of any suitable shape. A rectangular mesa is shown in FIG. 1, but those skilled in the art will recognize that this is for illustrative purposes only and that the present disclosure is not limited to rectangular or square mesas. In some embodiments, the substrate support mesa 115 has a shape selected from one or more of a square, rectangle, circle, oval, triangle, polygon (e.g., pentagon, hexagon, etc.), star, diamond, trapezoid, cross, flower, semi - circle, or crescent.

[0034] Figure 3 illustrates a partial cross-sectional view of an electrostatic chuck 100 according to one or more embodiments of the present disclosure. The illustrated electrostatic chuck 100 includes a substrate 250 shown on a top surface 102. In some embodiments, the substrate 250 is in contact with a substrate support mesa 115, an inner band 130, and an outer band 150. The substrate support mesa 115 is shown hatched differently from a body 101 of the electrostatic chuck 100, but those skilled in the art will recognize that this is for illustrative purposes only. In some embodiments, the substrate support mesa 115 is made of the same material as the remainder of the electrostatic chuck 100. The hatching is provided to easily distinguish the contact areas.

[0035] The electrostatic chuck 100 further includes a controller 160. In some embodiments, the controller 160 is coupled to the electrostatic chuck 100. In some embodiments, the controller 160 is coupled to one or more of an inner channel 120 or an outer channel 140. In some embodiments, there are two or more controllers 160 connected to individual channels, and a primary control processor is coupled to each of the separate processors to control the electrostatic chuck 100.

[0036] The controller 160 may be any form of general-purpose computer processor, microcontroller, microprocessor, or the like that can be used in an industrial environment to control various channels and sub-processors.

[0037] The controller 160 may have a processor 162, a memory 164 coupled to the processor 162, an output device 166 coupled to the processor 162, and a support circuit 168 for communication between different electronic components. The memory 164 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0038] The memory 164 of the processor 162 or the computer-readable medium may be one or more of readily available memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. The memory 164 may hold an instruction set operable by the processor 162 to control the parameters and components of the electrostatic chuck 100.

[0039] The support circuit 168 is coupled to the processor 162 to support the processor 162 in a conventional manner. The circuit may include, for example, cache, power supply, clock circuit, input / output circuitry, subsystems, and the like.

[0040] The process may generally be stored in memory as a software routine that, when executed by the processor 162, causes the process of the present disclosure to be performed on the electrostatic chuck. The software routine may further be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may further be performed in hardware. As such, the process may be implemented in the form of software and executed using a computer system, may be implemented in the form of hardware, such as an application specific integrated circuit or other type of hardware implementation, or may be implemented as a combination of software and hardware. The software routine, when executed by the processor, converts a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation such that the process is performed.

[0041] In some embodiments, the controller 160 has one or more configurations for executing individual processes or sub - processes to carry out the method. The controller 160 can be connected to intermediate components and configured to operate those intermediate components to carry out the functions of the method. For example, the controller 160 can be connected to and configured to control one or more of a gas valve, a heater, a mass flow controller, and others.

[0042] The controller 160 of some embodiments has one or more configurations selected from a configuration for chucking and / or de - chucking a substrate on an electrostatic chuck, a configuration for monitoring the concentration of hydrogen across the wafer, a configuration for monitoring the surface temperature across the wafer, a configuration for controlling the pressure in the inner channel, or a configuration for controlling the pressure in the outer channel.

[0043] As discussed above, current electrostatic chuck designs limit the maximum gas pressure in the outer cooling channel before leakage becomes a problem. Thus, the present disclosure identifies various ways to modify the current electrostatic chuck to enable better control of temperature, and thus hydrogen (H) concentration, across the wafer.

[0044] One or more embodiments of the present disclosure advantageously provide an electrostatic chuck with improved outer zone cooling. Some embodiments provide an electrostatic chuck with an improved cooling fluid leak rate. Some embodiments provide an ESC with improved cooling at the ESC / wafer edge that results in a higher radial adjustment range of hydrogen percentage, an ESC with an improved wet etching rate (WER), and / or an ESC that minimizes or eliminates gate - induced drain leakage.

[0045] In some embodiments, the cooling fluid includes one or more of helium, neon, argon, krypton, or xenon. In some embodiments, the cooling fluid consists essentially of helium.

[0046] The current ESC design is capable of having a pressure of about 20 torr in each of the inner and outer channels. A conventional ESC with pressures of 4 torr and 10 torr in the inner and outer channels respectively has been observed to result in a hydrogen non-uniformity of about 8.7%. The inventors have surprisingly found that a pressure ratio of 6:14 torr in the inner channel:outer channel results in a hydrogen non-uniformity of 0.5%. Without being bound by any particular theory of operation, GIDL is thought to be eliminated or minimized by varying the inner and outer channel backside pressures. Some embodiments advantageously result in a hydrogen percent non-uniformity of less than about 5%, 4%, 3%, or 2% for a process at 315 °C. Some embodiments result in improved wafer cooling efficiency. Some embodiments allow for a higher outer channel set point, a lower inner channel set point, and a higher outer:inner channel ratio for process tuning. Some embodiments reduce the ESC / substrate helium leak rate. Some embodiments result in improved substrate temperature control.

[0047] One embodiment of the present disclosure enables an electrostatic chuck with reduced surface roughness. Without being bound by theory, reducing the surface roughness of the top surface of the electrostatic chuck enables more efficient heat transfer between the substrate support mesa and the wafer. Further, reducing the surface roughness of the top surface of the electrostatic chuck results in a larger surface area and a stronger chucking force in the inner and outer bands, thereby reducing gas leakage from the inner and / or outer channels.

[0048] In some embodiments, the surface roughness of one or more of the plurality of substrate support mesas 115, the inner band 130, or the outer band 150 is reduced relative to a standard electrostatic chuck. In some embodiments, the surface roughness is reduced by soft polishing one or more of the plurality of substrate support mesas 115, the inner band 130, or the outer band 150. In some embodiments, the surface roughness of the outer band is reduced by an amount in the range of about 70% to about 90% relative to a standard electrostatic chuck.

[0049] For example, a standard electrostatic chuck may have a surface roughness in the range of about 25 Ra to about 40 Ra. In some embodiments, the surface roughness of the outer band is reduced to about 25 Ra or less, about 20 Ra or less, about 15 Ra or less, about 10 Ra or less, or about 7 Ra or less. In some embodiments, the surface roughness is reduced to about 6 Ra. In some embodiments, the surface roughness is in the range of about 10 Ra to about 25 Ra, or about 15 Ra to about 20 Ra. In some embodiments, the surface roughness is measured by a surface profilometer.

[0050] Another embodiment of the present disclosure enables an electrostatic chuck with reduced substrate support mesas. In some embodiments, the number of substrate support mesas is reduced. In some embodiments, the contact area of the substrate support mesas is reduced. In some embodiments, the percentage of the central region covered by the substrate support mesas is reduced. In some embodiments, the ratio between the perimeter and the area of each substrate support mesa is reduced.

[0051] Without being bound by theory, each of the modifications proposed above is thought to reduce conductive heat transfer through the substrate support mesas. Convective heat transfer will still occur, but relatively, a larger amount of heat transfer is expected to occur through the inner and outer bands, in which case that heat transfer can be more readily controlled using the inner and outer channels.

[0052] For example, a standard electrostatic chuck may have a square substrate support mesa, in which case each mesa has a contact area of about 11 mm 2 or more. In terms of the number of mesas on a standard electrostatic chuck, the contact coverage may be about 12% or more, or about 15% or more of the total area of the top surface of the electrostatic chuck.

[0053] In some embodiments, the substrate support mesa is circular in shape. In some embodiments, each mesa has a contact point that is about 10 mm 2 or less. In some embodiments, depending on the number of mesas, the contact coverage is about 10% or less, about 7% or less, or about 5% or less of the total area of the electrostatic chuck.

[0054] Further embodiments of the present disclosure enable an electrostatic chuck with a wider inner band and / or outer band. Without being bound by theory, the wider inner band and / or outer band are thought to enable increased heat transfer between the electrostatic chuck and the wafer. Also, the wider outer band is thought to help prevent leakage of the cooling gas from the outer channel. Additionally, the wider inner band is thought to allow for greater pressure fluctuations between the inner channel and the outer channel.

[0055] Additional embodiments of the present disclosure enable an electrostatic chuck with increased pressure in the outer channel and / or decreased pressure in the inner channel. Without being bound by theory, the increased pressure difference between the outer channel and the inner channel is thought to provide better control over the temperature uniformity of the wafer. Also, the physical modifications to the standard electrostatic chuck outlined in the present disclosure are thought to allow for a greater pressure difference.

[0056] In some embodiments, the maximum pressure of the coolant in the inner channel and the outer channel is about 20 Torr. In some embodiments, the minimum pressure in the inner channel and the outer channel is about 2 Torr.

[0057] In some embodiments, the pressure in the inner channel (IC pressure) is lower than the pressure in the outer channel (OC pressure). In some embodiments, the IC pressure is about 6 Torr or less, about 5.5 Torr or less, or about 5 Torr or less. In some embodiments, the OC pressure is about 14 Torr or more, about 15 Torr or more, about 17 Torr or more, or about 19 Torr or more.

[0058] The difference between the IC pressure and the OC pressure of about 8 Torr or more, about 10 Torr or more, about 12 Torr or more, or about 14 Torr or more in some embodiments. In some embodiments, the ratio of the OC pressure to the IC pressure is about 2.5 or more, about 3 or more, about 4 or more, or about 4 or more. In some embodiments, the ratio of the OC pressure to the IC pressure is in the range of about 2.5 to about 4, in the range of about 3 to about 4, or in the range of about 3.5 to about 4.

[0059] Without being bound by theory, various embodiments of the present disclosure improve the control of the temperature of the wafer (temperature uniformity) across the entire area of the wafer. The temperature is thought to be correlated with the concentration of hydrogen (H%) in the film produced by a high density plasma (HDP) deposition process. The increased H% is also correlated with the wet etching rate (WER) and the wet etching rate ratio (WERR) of the deposited film.

[0060] If the improved temperature control of some embodiments enables an increased temperature uniformity across the entire surface of the wafer during the HDP process, some embodiments of the present disclosure also enable an increased H% uniformity and an increased WERR uniformity across the entire area of the wafer. In some embodiments, the electrostatic chuck is configured to have an H% with a range (R / 2) of about 2% or less, about 1% or less, or about 0.5% or less across the entire area of the wafer.

[0061] Examples Five electrostatic chuck samples with a diameter of approximately 300 mm were prepared with different dimensions and characteristics as shown in Table 1. Unless otherwise specified, all dimensions are normalized with respect to Sample 1. TIFF0007696989000001.tif83170

[0062] The evaluation of the average temperature of the wafer during processing was performed for Samples 1 - 4 at various set points for IC pressure and OC pressure. The temperature was measured at a wavelength of approximately 1 μm with an infrared optical thermometer. The temperature was measured on the back side of the wafer through a small hole in the central region of the electrostatic chuck. The thermometer was unable to measure temperatures below 193°C. Temperatures of 193°C (or lower) are presented as "low" in Tables 2A - 2D.

[0063] The data is grouped by IC pressure in Tables 2A - 2D. In some examples, higher OC pressures could not be maintained due to leakage. These situations are noted by dashes. TIFF0007696989000002.tif74170TIFF0007696989000003.tif74170TIFF0007696989000004.tif73170TIFF0007696989000005.tif75170

[0064] To vary the pressure in the inner and outer channels, SiO2 samples were prepared on each of the electrostatic chuck samples using the HDP method. The substrate temperature was set to 315°C, but the temperature variation across the entire substrate surface was evident due to inner and outer channel cooling.

[0065] The prepared SiO2 film was evaluated for the wet etching rate across the entire surface of the wafer and standardized to form a radial profile for each sample. To evaluate the wet etching rate, the oxide film thickness on the surface of the wafer was measured both before and after the wafer was immersed for a controlled time in a 1% HF solution. A summary of the results for Samples 1 - 4 is provided in Table 3. All pressures are provided in Torr units. For each combination of IC pressure and OC pressure, the average wet etching rate across the entire wafer is normalized to 1. The standard deviation and R / 2 listed as 1Sig / R / 2 are provided as indicators of the dispersion of the wet etching rate across the entire wafer. For Samples 1 - 3, the higher OC pressures could not be maintained due to leakage. These situations are noted by dashes. TIFF0007696989000006.tif94170

[0066] References throughout this specification to "one embodiment", "an embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in an embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067] Although the disclosure herein has been described with reference to individual embodiments, those of ordinary skill in the art will understand that the described embodiments are merely illustrative with respect to the principles and applications of the disclosure. It will be apparent to those of ordinary skill in the art that various modifications and variations can be made to the methods and apparatuses of the disclosure without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that fall within the scope of the appended claims and the equivalents of those claims.

Claims

1. An electrostatic chuck, having a top surface and a bottom surface, the top surface having a total area, and the top surface being a central region including a plurality of substrate support mesas, the plurality of substrate support mesas extending from the top surface of the central region and having a coverage of contact area, central region, an inner channel (IC) having an IC width surrounding the central region, an inner band (IB) having an IB width surrounding the inner channel, wherein the depth of the inner channel from the top surface of the central region to the bottom surface of the IC is shallower than the depth from the top surface of the IB to the bottom surface of the IC, inner band (IB), an outer channel (OC) having an OC width surrounding the inner band, wherein the depth of the outer channel from the top surface of the electrostatic chuck is deeper than the depth from the top surface of the central region to the bottom surface of the IC, outer channel (OC), and an outer band (OB) having an OB width surrounding the outer channel comprising a top surface and a bottom surface, and a controller configured to control the temperature over the entire area of a wafer fixed to the top surface of the electrostatic chuck during processing An electrostatic chuck comprising.

2. The electrostatic chuck according to claim 1, wherein the maximum pressure of the coolant in the IC and the OC is about 20 Torr.

3. The electrostatic chuck according to claim 1, wherein the pressure (IC pressure) in the inner channel is lower than the pressure (OC pressure) in the outer channel.

4. The electrostatic chuck according to claim 3, wherein the difference between the IC pressure and the OC pressure is 8 Torr or more.

5. The electrostatic chuck according to claim 3, wherein the OC pressure is 14 Torr or more.

6. The electrostatic chuck according to claim 3, wherein a ratio of the OC pressure to the IC pressure is in a range of about 2.5 to about 4.

7. The electrostatic chuck according to claim 1, wherein the electrostatic chuck is configured to have a hydrogen concentration H% over an entire surface of the wafer fixed to the electrostatic chuck during processing, and the hydrogen concentration H% has a variability range R / 2 divided by 2 of about 2% or less over the entire wafer during processing.

8. The electrostatic chuck according to claim 7, wherein the R / 2 is 0.5% or less over the entire surface of the wafer.

9. The electrostatic chuck according to claim 1, wherein a coverage of the contact area of the plurality of substrate support mesas is 10% or less of a total area of a top surface of the electrostatic chuck.

10. The electrostatic chuck according to claim 9, wherein the coverage of the contact area of the plurality of substrate support mesas is less than 7% of the total area of the top surface of the electrostatic chuck.

11. The electrostatic chuck according to claim 7, wherein the plurality of substrate support mesas are circular in shape.

12. The electrostatic chuck according to claim 7, wherein the coverage of the contact area of the plurality of substrate support mesas is less than 5% of the total area of the top surface of the electrostatic chuck.

13. The electrostatic chuck according to claim 11, wherein an area of the plurality of substrate support mesas is less than about 10% of the total area of the top surface of the electrostatic chuck.

14. The electrostatic chuck according to claim 1, wherein the OC width is in a range of 2 mm to 6 mm.

15. The electrostatic chuck according to claim 7, wherein the OB width is in a range of 3.5 mm to 4 mm.

16. The electrostatic chuck according to claim 7, wherein the OB width is increased by a ratio in a range of about 110% to about 150% with respect to a standard electrostatic chuck.

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