Hydrogenation and nitridation treatments for changing the effective oxide thickness of the film

Abstract

To provide a method for enabling the formation of a metal gate structure with a reduced effective oxide thickness compared to a similar structure formed by conventional methods.SOLUTION: A metal gate structure 1000 is depicted as a simple film stack formed on a semiconductor substrate 1001, and comprises an interfacial oxide layer 1002, a high dielectric constant dielectric layer 1003, an interfacial layer 1409, a capping layer 1404, and an exposed surface 1401 of the capping layer. In the metal gate structure, a plasma nitridization process is performed and then a plasma hydrogenation process or a single-step plasma hydrogenation and nitridization process is performed thereby removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack.SELECTED DRAWING: Figure 14C

Description

Technical Field

[0001]

[0001] The embodiments described herein generally relate to methods and apparatuses for processing semiconductor substrates, and more specifically, to hydrogenation and nitridation processes for changing the effective oxide thickness of a film.

Background Art

[0002]

[0002] In integrated circuits, smaller transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), are highly desirable. First, smaller transistors enable more transistors to be formed within a given chip area, thereby reducing the chip size. Second, smaller transistors can generally switch faster than larger transistors, thereby improving chip performance.

[0003]

[0003] One approach for shrinking the size of MOSFETs is scaling. In scaling, important device dimensions such as the length of the transistor, the width of the transistor, and the thickness of the oxide (or dielectric) are proportionally reduced. In this approach, the transistor channel resistance does not change as the transistor size is reduced, but as the size is reduced, the gate capacitance and RC delay of the transistor proportionally decrease.

[0004]

[0004] However, in order to reduce the MOSFET to the size required by future technology nodes, while the reduction of the dielectric thickness in the MOSFET is extremely important, there are also significant trade - offs. Specifically, with the linear reduction of the thickness of the conventional oxide / nitride oxide dielectric layer of the MOSFET, gate leakage increases rapidly, resulting in an increase in power consumption. Furthermore, the thickness of the dielectric layer is now only a few atomic layers, and concerns about reliability are increasing. Therefore, any means that can reduce the oxide thickness or the effective oxide thickness (EOT) in the transistor without rapidly increasing the gate leakage is highly desirable. This application addresses such needs and other needs.

Summary of the Invention

[0005]

[0005] Embodiments described herein generally relate to sequential hydrogenation and nitridation processes for reducing interfacial and bulk O atoms in conductive structures within semiconductor devices. In one embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a high - dielectric - constant dielectric layer on a semiconductor substrate and depositing a capping layer on the high - dielectric - constant dielectric layer to form a portion of the structure, wherein the deposited capping layer includes an exposed surface, and exposing the exposed surface to plasma - excited hydrogen species and plasma - excited nitrogen species. A portion of the substrate includes the capping layer and the high - dielectric - constant dielectric.

[0006]

[0006] In one embodiment, a method of forming a structure within a semiconductor device includes depositing a high - dielectric - constant dielectric layer on a semiconductor substrate and depositing a metal nitride layer on the high - dielectric - constant dielectric layer to form a portion of the structure, wherein the portion includes the metal nitride layer and the high - dielectric - constant dielectric layer and has a first effective oxide thickness, and the deposited metal nitride layer has an exposed surface, and exposing the exposed surface to non - oxidizing plasma - excited hydrogen species and then plasma - excited nitrogen species in sequence to reduce the first effective oxide thickness to a second effective oxide thickness.

[0007]

[0007] In another embodiment, a method of forming a structure within a semiconductor device includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a metal nitride layer on the high-k dielectric layer, sequentially exposing an exposed surface to plasma-excited hydrogen species and then plasma-excited nitrogen species, sequentially exposing the exposed surface to plasma-excited hydrogen species and then plasma-excited nitrogen species again, exposing the exposed surface to air, and performing a thermal annealing process on the high-k dielectric layer and the metal nitride layer at a specific time and a specific temperature after exposing the exposed surface to air.

[0008]

[0008] In another embodiment, a method of forming a structure within a semiconductor device includes depositing a high-k dielectric layer on a semiconductor substrate, and depositing a metal nitride layer on the high-k dielectric layer to form a part of the structure, where the part includes the metal nitride layer and the high-k dielectric layer and has a first effective oxide thickness, and the deposited metal nitride layer has an exposed surface, and reducing the first effective oxide thickness to a second effective oxide thickness by continuously exposing the exposed surface to non-oxidizing plasma-excited hydrogen species and then plasma-excited nitrogen species.

[0009]

[0009] In another embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a capping layer on the high-k dielectric layer, exposing an exposed surface of the capping layer to plasma-excited hydrogen species and plasma-excited nitrogen species, exposing the exposed surface to air, and performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specific time and a specific temperature.

[0010]

[0010] In another embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a high-k dielectric layer on a semiconductor substrate and depositing a capping layer on the high-k dielectric layer to form a part of the structure, wherein the deposited capping layer includes an exposed surface, and exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species, wherein the plasma-excited hydrogen species includes ammonia and the plasma-excited nitrogen species includes nitrogen gas (N2). A part of the structure includes the capping layer and the high-k dielectric.

[0011]

[0011] In another embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a metal nitride capping layer on a high-k dielectric layer formed on a surface of a substrate and exposing an exposed surface of the deposited metal nitride capping layer to a plasma including a first gas including hydrogen-containing species and a second gas including nitrogen-containing species, wherein the hydrogen-containing species in the first gas includes nitrogen.

[0012]

[0012] In another embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a high-k dielectric layer on a semiconductor substrate, depositing a capping layer on the high-k dielectric layer, exposing an exposed surface of the capping layer to plasma-excited hydrogen species and plasma-excited nitrogen species, exposing the exposed surface to air, and performing a thermal annealing process on the high-k dielectric layer and the capping layer at a specific time and a specific temperature.

[0013]

[0013] In another embodiment, a method of forming a structure within a semiconductor device is provided. The method includes depositing a high-k dielectric layer on a semiconductor substrate and depositing a capping layer on the high-k dielectric layer to form a portion of the structure, the portion including the capping layer and the high-k dielectric layer, the deposited capping layer having an exposed surface, depositing the capping layer, and exposing the exposed surface to plasma-excited hydrogen species and plasma-excited nitrogen species, the plasma-excited hydrogen species including ammonia and the plasma-excited nitrogen species including nitrogen gas (N2).

[0014]

[0014] To better understand the above-described features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that since the present disclosure may admit other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of this disclosure and should not be considered as limiting the scope of the present disclosure.

Brief Description of the Drawings

[0015]

Figure 1

Figures 2A-2E

Figure 3

Figure 4

Figure 5

Figure 6

Figures 7A-7E

Figure 8

Figure 9

Figure 10

Figure 11

Figures 12A-12J

Figure 13

Figures 14A-14J

DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0024] For ease of understanding, where possible, the same reference numbers have been used to denote the same elements common to the figures. The elements and features of one embodiment are considered to be beneficially incorporated into other embodiments without further description.

[0017]

[0025] The embodiments described in this specification generally relate to methods and apparatuses for nitriding layers in structures within semiconductor devices formed on a substrate. A single-step plasma hydrogenation and nitridation process can be performed on a metal layer or a stack of metal layers (e.g., a metal layer that is thermally annealed prior to the deposition of a metal capping layer) included in a conductive structure. In various embodiments, the single-step plasma hydrogenation and nitridation process can be performed before, after, or both before and after a thermal annealing process. In each embodiment, the electrical resistance in the conductive structure is reduced by the advantageous increase in the nitrogen atom concentration in the conductive structure. One such conductive structure is shown in FIG. 1.

[0018] Conductive structure with reduced interfacial and bulk oxygen

[0026] FIG. 1 shows a cross-sectional view of a conductive structure 100, or a contact structure, formed on a semiconductor substrate 110 as part of a semiconductor device, according to an embodiment of the present disclosure. The conductive structure 100 can be any part of a semiconductor device configured to conduct current and thus benefits from a reduction in electrical resistance. In the embodiment shown in FIG. 1, the conductive structure 100 is illustrated as a contact structure for providing electrical contact to a source or drain structure 101, and is shown in a state after the conductive structure 100 is formed and a planarization process such as chemical mechanical polishing (CMP) is completed on the semiconductor substrate 110. For example, the conductive structure 100 can be a contact structure for a field effect transistor (FET).

[0019]

[0027] The conductive structure 100 is disposed within a contact well 109, which is a cavity formed in an insulating material 120, i.e., within an opening. The insulating material 120, alternatively referred to as shallow trench isolation (STI), may include one or more dielectric materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), or a plurality of layers thereof. The insulating material 120 can be formed by high-density plasma (HDP), flowable chemical vapor deposition (FCVD), tetraethyl orthosilicate (TEOS), etc. The conductive structure 100 may include a stack of multiple metal layers (e.g., a first metal layer 102, a metal nitride layer 103, and at least a conductive portion disposed on the first metal layer 102 and the metal nitride layer 103). The conductive portion may include a capping layer 104 and / or a conductive layer 106.

[0020]

[0028] The source or drain structure 101 can be formed from a semiconductor substrate 110 or from a different semiconductor material deposited on the semiconductor substrate 110. In the latter case, the different semiconductor material may include silicon-germanium, III-V compound semiconductor materials, etc. For example, in some embodiments, an epitaxial process may be performed to grow the source or drain structure 101.

[0021]

[0029] The first metal layer 102 is formed on the source or drain structure 101. The first metal layer 102 includes one or more metals selected to form a silicon compound 105 at the interface with the source or drain structure 101 after appropriate thermal annealing. For example, in some embodiments, the first metal layer 102 contains titanium (Ti) or is entirely composed of Ti and may have a thickness of from about 40 Å to about 50 Å. The metal nitride layer 103 is formed on the first metal layer 102, contains a metal nitride, and functions, for example, as a diffusion barrier layer within the conductive structure 100. In some embodiments, the metal nitride layer 103 includes titanium nitride (TiN), tantalum nitride (TaN), and / or tungsten nitride (W3N2) and may have a thickness of from about 10 Å to 20 Å. The capping layer 104 is typically formed on the metal nitride layer 103 after the thermal annealing process in which the silicon compound 105 is formed within the conductive structure 100 and includes one or more metals. In some embodiments, the conductive structure 100 may include a separately formed conductive layer 106 (which may include a metal such as cobalt, copper, ruthenium, nickel, tungsten, aluminum, or other useful metals, or alloys thereof). In some embodiments, the capping layer 104 contains Co and may have a thickness of from about 10 Å to 20 Å. In other embodiments, the capping layer 104 includes a metal (e.g., cobalt) that completely fills the remaining portion of the contact well 109.

[0022]

[0030] As described above, the presence of O atoms in the first metal layer 102 and / or the metal nitride layer 103 has an adverse effect on the effective conductivity of the conductive structure 100. First, the oxide in any metal layer increases the bulk conductivity of the formed metal layer. Second, the interfacial oxide, i.e., the metal oxide formed at the interface between the metal nitride layer 103 and the capping layer 104, results in poor adhesion between the metal nitride layer 103 and the capping layer 104, and potentially creates voids that significantly reduce the effective cross-sectional area of the conductive structure 100. Unfortunately, a low concentration of O atoms is generally always present to some extent in the bulk portion of the metal layer of the conductive structure 100. Furthermore, in many cases, a higher concentration of oxide can be formed on the metal surface exposed to air during the manufacturing process. According to an embodiment of the present disclosure, the presence of bulk and interfacial O atoms in the conductive structure 100 can be reduced through continuous hydrogenation and plasma nitridation treatments. Physical models of how such continuous treatments reduce bulk and interfacial O atoms in the conductive structure 100 are shown in FIGS. 2A to 2E and FIGS. 3A to 3D.

[0023] Physical Model for Reducing Interfacial and Bulk Oxygen

[0031] FIGS. 2A to 2E are schematic views of the metal nitride layer 103 within the contact structure 100 at various stages of the manufacture of the contact structure 100 according to one embodiment of the present disclosure. It should be noted that FIGS. 2A to 2E show only one possible surface termination of the metal nitride layer 103 and represent only a typical TiN structure. In some embodiments, the metal nitride layer 103 may have any other possible surface termination or crystal structure associated with the TiN layer.

[0024]

[0032] In FIG. 2A, portion 200 of the metal nitride layer 103 is schematically shown immediately after the metal nitride layer 103 has been deposited on the first metal layer 102 and before portion 200 is exposed to air. Portion 200 includes surface 201 of portion 200 onto which the capping layer 104 will ultimately be deposited. As shown, portion 200 has an NaCl-type cubic structure and is mainly composed of Ti element and N atoms. Further, portion 200 includes low-concentration (cross-hatched) bulk O atoms 211 typically disposed in the bulk region of portion 200 below surface 201. The bulk O atoms 211 may be incorporated by contamination found in the processing environment during the deposition process used to form portion 200. Further, portion 200 generally includes vacancies 213. The vacancies 213 are sites within the crystal lattice of portion 200 where atoms are missing. The vacancies 213 are locations where further oxidation can occur within portion 200 when the nitride layer 103 is exposed to air. It should be noted that when the metal nitride layer 103 is formed by atomic layer deposition (ALD) processing, the vacancies 213 are relatively common due to the film nucleation and growth mechanisms found in ALD processing compared to conventional chemical vapor deposition (CVD) or physical vapor deposition (PVD) processing. Thus, one or more of the embodiments of the present disclosure may provide significant advantages when used with films formed by ALD processing rather than conventional PVD or CVD-type processing.

[0025]

[0033] FIG. 2B shows portion 200 after being removed from the processing system in which the metal nitride layer 103 was deposited. For example, the semiconductor substrate 110 on which portion 200 is formed can be exposed to air in preparation for a thermal annealing process. Typically, a conventional heat treatment chamber such as an annealing chamber is operated in a processing system different from the processing system used to form the first metal layer 102 and the metal nitride layer 103. The reasons include differences in cleanliness, thermal management control, and vacuum level requirements needed to form state-of-the-art device node applications. Thus, in FIG. 2B, portion 200 is shown in a state after being exposed to air. As shown, surface 201 is partially oxidized, and surface O atoms 212 occupy most or all of the vacancies 213 disposed on surface 201. In some cases, as a result of portion 200 being exposed to air, some of the vacancies 213 disposed within portion 200 are occupied by bulk O atoms 211.

[0026]

[0034] FIG. 2C shows portion 200 in a state after undergoing a thermal annealing process to form the silicon compound 105 as shown in FIG. 1. Some or all of the remaining vacancies 213 are filled with bulk O atoms 211 or surface O atoms 212. In some embodiments, bulk O atoms 211 can further replace some of the N atoms disposed within portion 200. Thus, the annealing process generally increases the number of both bulk O atoms 211 and surface O atoms 212 within portion 200. Even if the depth of the surface O atoms 212 on surface 201 is only one or two monolayers, the effect on the resistivity of the conductive structure 100 can be significant, especially for smaller device structures such as those associated with advanced device nodes (e.g., below the 65 nm technology node).

[0027]

[0035] In FIG. 2D, portion 200 is shown after being exposed to hydrogen atoms that react with bulk O atoms 211 and / or surface O atoms 212 included in portion 200, according to various embodiments of the present disclosure. In some embodiments, the bulk O atoms 211 and / or surface O atoms 212 react with hydrogen atoms from thermally dissociated hydrogen gas (H2) as part of a thermal hydrogenation process, while in other embodiments, the bulk O atoms 211 and / or surface O atoms 212 react with hydrogen atoms from a hydrogen-containing plasma as part of a plasma hydrogenation process.

[0028]

[0036] The thermal hydrogenation process can be carried out in a suitable rapid thermal processing chamber under specific processing conditions (including heating portion 200 to at least about 550° C. to about 650° C.). The plasma hydrogenation process can be performed in a suitable plasma processing chamber under specific processing conditions. Exemplary plasma processing chambers and plasma processing conditions are described below in connection with the plasma hydrogenation process, respectively. As shown, the hydrogenation process reduces or, alternatively, removes all or substantially all of the surface O atoms 212 from surface 201, leaving voids 213. Further, the plasma hydrogenation process can also remove some or all of the bulk O atoms 211 disposed below surface 201.

[0029]

[0037] In FIG. 2E, portion 200 in a state after being subjected to a plasma nitridation process, according to various embodiments of the present disclosure, is shown. The plasma nitridation process can be carried out in a suitable plasma processing chamber under specific processing conditions. Exemplary plasma processing chambers and plasma processing conditions are described below in connection with the plasma nitridation process, respectively. In some embodiments, the plasma nitridation process may be carried out in the same plasma processing chamber as the chamber in which the plasma hydrogenation process is performed. Further, no air break occurs between the plasma or thermal hydrogenation process and the plasma nitridation process. That is, portion 200 is not exposed to air after the plasma or thermal hydrogenation process and before the plasma nitridation process.

[0030]

[0038] As shown, by nitridation treatment, the pores 213 are filled with N atoms, and on the surface 201, almost no or no surface O atoms 212 are arranged. Therefore, the surface 201 may be saturated with N atoms, and as a result, even when the surface 201 is exposed to air again before the capping layer 104 is deposited, the subsequent oxidation of the surface 201 is significantly reduced or eliminated. Therefore, the adhesion between the surface 201 of the metal nitride layer 103 and the capping layer 104 is improved. In addition, some or all of the pores below the surface 201 can be filled with N atoms instead of bulk O atoms 211, and the conductivity of the metal nitride layer 103, the first metal layer 102, and the conductive structure 100 is further improved overall.

[0031]

[0039] FIG. 3 is a graph of an X-ray photoelectron spectroscopy (XPS) spectrum 310 for a TiN film deposited and thermally annealed before treatment and an XPS spectrum 320 for a TiN film deposited and thermally annealed in the same manner after treatment according to an embodiment of the present disclosure. This treatment includes a plasma or thermal hydrogenation treatment followed by a plasma nitridation treatment. The thermal annealing treatment is a rapid thermal treatment in a nitrogen gas (N2) or ammonium (NH3) environment at a temperature between about 550°C and 600°C. The plasma hydrogenation treatment is performed on a substrate pedestal in an inductively coupled plasma (ICP) chamber for about 30 seconds to about 200 seconds at a temperature between about 340°C and 500°C, a treatment pressure between about 10 mTorr and 150 mTorr, a plasma output between about 250 W and 2000 W, an H2 flow rate between about 5 sccm and 100 sccm, and an argon (Ar) flow rate between about 250 sccm and 2000 sccm. The plasma nitridation treatment can be performed on the substrate pedestal in the same ICP chamber for about 30 seconds to about 200 seconds at a temperature between about 350°C and 500°C, a treatment pressure between about 10 mTorr and 100 mTorr, a plasma power between about 250 W and 2000 W, an NH3 flow rate between about 5 sccm and 100 sccm, a nitrogen (N2) flow rate between about 300 sccm and 500 sccm, and an argon (Ar) flow rate between about 20 sccm and 500 sccm.

[0032]

[0040] As is well known in the art, the XPS spectrum of a TiN film can include multiple peaks, each indicating a different relative concentration of different titanium-containing materials. For example, the Ti-O peak at a binding energy of approximately 458.5 eV generally indicates the presence of a Ti-O bond, and thus the presence of O atoms in the titanium-containing material. The Ti-O-N peak at a binding energy of approximately 457 eV generally indicates the presence of a Ti-O-N bond, and thus the presence of N and O atoms in the titanium-containing material. The Ti-N peak at a binding energy of approximately 454.9 eV generally indicates the presence of a Ti-N bond, and thus the presence of nitrogen (N) atoms in the titanium-containing material.

[0033]

[0041] XPS spectrum 310 is associated with the Ti 2p shell of the deposited TiN film after the above-described thermal annealing treatment. XPS spectrum 320 is associated with the Ti 2p shell of the deposited and thermally annealed TiN film after the above-described plasma hydrogenation treatment followed by the above-described plasma nitridation treatment. As shown, the peaks indicating the presence of Ti-O bonds and the peaks indicating the presence of Ti-O-N bonds are significantly lower in XPS spectrum 320 than in XPS spectrum 310, clearly indicating a decrease in the presence of O atoms in the TiN film. Further, the peak indicating the presence of Ti-N bonds is significantly higher in XPS spectrum 320 than in XPS spectrum 310, clearly indicating an increase in the concentration of N atoms in the TiN film. Thus, by performing hydrogenation and nitridation treatments after the annealing treatment, the concentration of O atoms in the metal nitride film 103 can be significantly decreased, and the concentration of N atoms in the metal nitride film 103 can be significantly increased.

[0034]

[0042] Figures 2A through 2E, and FIG. 3, show the effects of sequential post-anneal hydrogenation and nitridation of the metal nitride layer 103. In some embodiments, prior to the thermal anneal treatment, subjecting portion 200 to a plasma or thermal hydrogenation treatment, followed by a plasma nitridation treatment, may have similar advantageous effects. Specifically, (as shown in FIG. 2E) the plasma nitridation treatment can cause surface 201 to be almost or completely saturated with N atoms, such that little or no oxidation occurs upon subsequent air exposure and thermal annealing of surface 201. As a result, the concentration of bulk O atoms 211 found in portion 200 and the concentration of surface O atoms 212 on surface 201 do not significantly increase.

[0035] Overview of a System for Sequential Hydrogenation and Nitridation

[0043] FIG. 4 is a schematic cross-sectional view of a plasma processing chamber 400 configured to implement one or more aspects of the present disclosure. Plasma processing chamber 400 may be any suitable plasma processing chamber, such as an inductively coupled plasma (ICP) processing chamber. As shown in FIG. 4, processing chamber 400 may include a chamber wall 406, a chamber lid 408, and a substrate support pedestal 404 disposed within chamber wall 406. Typically, chamber wall 406 is coupled to electrical ground 416. Chamber lid 408 may be composed of any suitable dielectric, such as quartz. In some embodiments, dielectric lid 408 may assume different shapes (e.g., dome shape). In some embodiments, chamber lid 408 may be coated with a ceramic coating, such as a yttrium-containing oxide, for protection from plasma species. In one embodiment, the ceramic coating is a high performance material (HPM) composed of the compound Y4Al2O9 and the solid solution Y 2-x Zr x O3 (Y2O3-ZrO2 solid solution). The ceramic coating may have a thickness in the range of about 100 microns to about 300 microns (e.g., about 200 microns).

[0036]

[0044] Above the chamber lid 408, a radio frequency (RF) antenna including at least one induction coil element 410 can be arranged (two coaxial coil elements are shown). In some embodiments, the induction coil element 410 can be arranged around at least a part of the chamber wall 406. As shown in the figure, one end of the induction coil element 410 can be connected to an RF power supply 414 via a first impedance matching network 412, and the other end can be connected to an electrical ground 417. The power supply 414 can typically generate up to 10 kilowatts (kW) at an adjustable frequency in the range of 2 to 160 MHz, and 13.56 MHz is a typical operating frequency. The RF power supplied to the induction coil element 410 may be pulsed (i.e., switched between an on state and an off state) at a frequency in the range of 1 to 100 kHz, or may be power cycled (i.e., the power input is varied from a high level to a low level).

[0037]

[0045] A shielding electrode 418 may be interposed between the induction coil element 410 of the RF antenna and the chamber lid 408. As shown in FIG. 4, the shielding electrode 418 may be connected to the electrical ground 419 alternately electrically, in a floating state, or via any suitable means for establishing and interrupting an electrical connection such as a switch 420.

[0038]

[0046] In some embodiments, a detector 422 can be attached to the chamber wall 406 to facilitate determination of when the gas mixture in the chamber 400 is excited into a plasma. The detector 422 can, for example, detect radiation emitted by the excitation gas or measure the intensity of one or more wavelengths of light associated with the generated plasma using optical emission spectroscopy (OES).

[0039]

[0047] The pedestal 404 can be coupled to a bias power supply 426 via a second impedance matching network 424. The bias power supply 426 can generally generate an RF signal having an adjustable frequency in the range of 2 to 160 MHz and a power between 0 and 10 kW, similar to the RF power supply 414. Optionally, the bias power supply 426 may be a direct current (DC) or pulsed DC source.

[0040]

[0048] In operation, a substrate 428, such as a semiconductor substrate, is disposed on the pedestal 404. To form a gas mixture 434, a process gas is supplied from a gas panel 430 through an inlet port 432. Typical process gases that can be used in one or more of the processes described herein are described below. The inlet port 432 can be coated with a ceramic coating such as HPM. By applying power from the RF power supply 414, the gas mixture 434 can energize the plasma 436 within the processing chamber 400. The pressure inside the chamber body 400 can be controlled using a throttle valve 438 and a vacuum pump 440. In some embodiments, the temperature of the chamber wall 406 can be controlled using a liquid-containing conduit (not shown). This liquid-containing conduit passes through the chamber wall 406 or a heating element (e.g., a heating cartridge or coil) embedded within the chamber wall 406, or is wrapped around the processing chamber 400 (e.g., a heating wrap or tape).

[0041]

[0049] The temperature of the substrate 428 can be controlled by stabilizing the temperature of the pedestal 404. In some embodiments, helium (He) gas from the gas source 442 can be supplied through the gas conduit 444 to a channel (not shown) formed in the pedestal surface below the substrate 428. The helium gas can facilitate heat transfer between the pedestal 404 and the substrate 428. During processing, the pedestal 404 can be heated to a steady-state temperature, and then the helium gas can facilitate uniform heating of the substrate 428. The pedestal may be heated by a heating element (not shown), such as a resistive heater embedded within the pedestal 404, or by a lamp generally directed towards the pedestal 404 or the substrate 428 when above them. Using such thermal control, the substrate 428 can be maintained at a temperature between about 20 and about 350 °C.

[0042]

[0050] To enable control of the components of the processing chamber 400 described herein, a controller 446 can be provided. The controller 446 generally includes a central processing unit (CPU) 448, a memory 450, and support circuitry 452 for the CPU 448. The controller 446 can interface with the RF power supply 414, the switch 420, the detector 422, and the bias power supply 426.

[0043]

[0051] The controller 446 may be any suitable form of general - purpose computer processor that can be used in an industrial setting to control various chambers and sub - processors. The memory 450 for the CPU 448 or other computer - readable media may be one or more of any readily available memory forms such as random - access memory (RAM), read - only memory (ROM), floppy disks, hard disks, or any other form of digital storage device, local or remote. To support the processor in a conventional manner, a support circuit 452 may be coupled to the CPU 448. These circuits may include caches, power supplies, clock circuits, input / output circuits, and subsystems, etc. In some embodiments, the techniques disclosed herein for energizing and maintaining a plasma may be stored in the memory 450 as software routines. Further, the software routines may be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 448.

[0044]

[0052] According to some embodiments of the present disclosure, before and / or after thermal annealing is performed on a substrate, a plasma nitridation process (hereinafter referred to as "continuous hydrogenation / nitridation process") is performed on the substrate following a thermal or plasma hydrogenation process. The continuous hydrogenation / nitridation process may include capacitively coupled plasma processing or inductively coupled plasma processing. In some embodiments, the plasma for the hydrogenation / nitridation process may be formed in a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma for the plasma processing may be formed in - situ, i.e., inside the processing chamber 400. Hydrogenation and nitridation can be performed in the same step (hereinafter referred to as "single - step plasma hydrogenation and nitridation process"). In some embodiments, the plasma for the single - step plasma hydrogenation and nitridation process may be formed in a remote plasma source outside the processing chamber 400, and in other embodiments, the plasma for the plasma processing may be formed in - situ, i.e., inside the processing chamber 400.

[0045]

[0053] In plasma hydrogenation treatment, plasma-excited H radicals and / or ions react with bulk O atoms 211 and / or surface O atoms 212 to generate vacancies 213. In the case of thermal hydrogenation treatment, dissociated H atoms react with bulk O atoms 211 and / or surface O atoms 212 to generate vacancies 213. In nitridation treatment, N radicals and / or ions occupy the vacancies 213.

[0046]

[0054] It should be noted that during plasma hydrogenation treatment, the processing environment in the processing chamber 400 generally contains a relatively low concentration of O atoms due to the presence of H atoms such as dissociated H atoms, H radicals, and / or H ions. Therefore, the processing environment in the processing chamber 400 during plasma hydrogenation treatment may contain a lower concentration of O atoms than the processing environment in the processing chamber 400 during nitridation treatment or the processing environment in the processing chamber during the deposition of the metal nitride layer. However, for both hydrogenation and nitridation, it is generally advantageous for the concentration of O atoms to be lower. Therefore, in some embodiments, the processing chamber can be conditioned by plasma treatment such as H2 treatment prior to plasma hydrogenation treatment and / or nitridation treatment to remove any traces of O species.

[0047]

[0055] When the metal nitride layer treated by the hydrogenation / nitridation treatment or the single-step plasma hydrogenation and nitridation treatment described in this specification is a thin film having a thickness of about 200 Å or less, the ICP treatment generally has a lower possibility of damaging the metal nitride layer during either hydrogenation or nitridation. Specifically, in the ICP treatment, the plasma sheath is typically smaller than that in a CCP chamber, and thus the ions moving through the plasma sheath typically have proportionally less energy (for example, energy on the order of several tens of eV, such as 10 to 20 eV). In contrast, the ions in a CCP chamber typically have energy on the order of several hundreds of eV (for example, >200 to 400 eV), and as a result, can cause significant damage to the metal nitride layer. Furthermore, the ICP treatment can remove more oxygen from the metal nitride layer than when using CCP or remote plasma treatment. This is due to the generally higher density of ions, radicals, and other plasma-excited species formed in and near the substrate in the ICP treatment chamber compared to the CCP and remote plasma sources used in other types of treatment chambers. In contrast, the concentration of radicals from CCP and remote plasma sources is relatively low.

[0048]

[0056] In embodiments where the plasma for plasma processing is formed in situ, the plasma can be formed via an induction coil element 410, a first impedance matching network 412, an RF power source 414, and in some embodiments, a second impedance matching network 424 and a bias power source 426. In these embodiments, plasma processing can include introducing one or more process gases selected to generate specific plasma species (i.e., ions, neutral atoms, and / or radicals) into the processing chamber 400. More specifically, in the case of plasma hydrogenation processing, one or more process gases are selected to generate plasma-excited hydrogen species, and in the case of plasma nitridation processing, one or more process gases are selected to generate plasma-excited nitrogen species. Thus, in the case of plasma hydrogenation processing, one or more process gases may include hydrogen (H2) and / or D2, and in the case of plasma nitridation processing, one or more process gases may include nitrogen (N2) or ammonia (NH3). Alternatively or additionally, plasma processing can include introducing one or more carriers and / or inert gases such as argon (Ar) into the processing chamber 400. In the case of single-step plasma hydrogenation and nitridation processing, one or more process gases can include hydrogen (H2), D2, nitrogen (N2), ammonia (NH3), or hydrazine (N2H4).

[0049]

[0057] In some embodiments, plasma hydrogenation processing mainly includes forming a plasma containing a process gas consisting essentially of hydrogen (H2) and forming reactive species supplied from the plasma. The formation of hydrogen-containing species using a plasma formed with H2 (e.g., inductively coupled plasma) results in significantly more hydrogen-containing radicals and ions than thermal hydrogenation processing using an H2-containing process gas, thereby improving the effectiveness of plasma hydrogenation processing and reducing unwanted reactions found when using impure hydrogen containing reactive gases. It should be noted.

[0050]

[0058] In some embodiments, one or more process gases are energized by an RF power source such as RF power source 414. The RF power can be pulsed with a duty cycle of 2% to 70% and can be in the range of about 100 W to about 2500 W. The RF power can also be a continuous wave in the range of about 100 W to about 2500 W. The process chamber can have a chamber pressure in the range of about 10 mTorr to about 200 mTorr during plasma processing, although the process temperature (e.g., the temperature of pedestal 404) can be in the range of 20°C to about 500°C.

[0051]

[0059] In an exemplary embodiment, the plasma hydrogenation process is carried out at a process temperature between about 400°C and about 500°C, a chamber pressure between about 5 mTorr and about 20 mTorr, an RF power between about 1000 W and about 2000 W, and a bias voltage between about 175 V and about 250 V, with an H2 flow between about 20 sccm and about 40 sccm and an Ar flow between about 400 sccm and about 500 sccm, over a period between about 50 seconds and about 300 seconds. Plasma-excited hydrogen species generated from the plasma inside process chamber 400 can reduce some or all of the oxides present on the exposed surface of the metal nitride layer (e.g., metal nitride layer 103) of the partially formed conductive structure (e.g., conductive structure 100). In some embodiments, the plasma-excited hydrogen species can also reduce some or all of the O atoms present in the bulk material of the metal nitride layer or other metal layers of the conductive structure, such as the first metal layer 102 of conductive structure 100. The reduction of such O atoms has been described above in connection with FIGS. 2D and 3B.

[0052]

[0060] In another exemplary embodiment, the plasma nitridation process is carried out at a processing temperature between about 400°C and about 500°C, a chamber pressure between about 5 mTorr and about 25 mTorr, an RF power between about 1000 W and about 2000 W, and a bias voltage between about 175 V and about 250 V, with an NH3 flow between about 20 sccm and about 40 sccm, an N2 flow between about 400 sccm and about 600 sccm, and an Ar flow between about 400 sccm and about 500 sccm, over a period between about 50 seconds and about 300 seconds. The plasma-excited nitrogen species generated from the plasma inside the processing chamber 400 can saturate the exposed surface of the metal nitride layer of the partially formed conductive structure (e.g., the surface 201 of the metal nitride layer 103). In some embodiments, the plasma-excited nitrogen species can also fill the pores present in the bulk material of the metal nitride layer or other metal layers of the conductive structure. Such nitridation has been described above in relation to FIGS. 2E and 3C.

[0053]

[0100] In some embodiments, the single-step plasma hydrogenation and nitridation process is carried out over a period between about 30 seconds and about 150 seconds, at a chamber pressure between about 10 mTorr and about 100 mTorr, a processing temperature (e.g., substrate pedestal temperature) between about 350°C and about 500°C, and an RF power between about 300 W and about 2000 W, with an NH3 flow rate between about 5 sccm and about 100 sccm, an N2 flow rate between about 50 sccm and about 1000 sccm, a helium (He) flow rate between about 1 and about 1000 sccm, and a substrate bias is applied at a frequency between about 2 MHz and about 160 MHz and a bias power between about 0 kW and about 10 kW.

[0054]

[0101] In some embodiments, the single-step plasma hydrogenation and nitridation process is carried out without applying substrate bias power over a period between about 85 seconds and about 95 seconds, with a chamber pressure between about 15 mTorr and about 25 mTorr, a processing temperature between about 350 °C and about 500 °C, and an RF power between about 300 W and about 1600 W, with an NH3 flow rate between about 10 sccm and about 40 sccm, an N2 flow rate between about 200 sccm and about 550 sccm, and an Ar flow rate between about 200 sccm and about 550 sccm.

[0055]

[0061] In embodiments where the plasma for plasma processing is formed remotely, the plasma can be formed via any technically feasible remote plasma source. In such embodiments, the plasma processing can include introducing one or more process gases selected to generate plasma-excited hydrogen species or plasma-excited nitrogen species into the remote plasma source. Alternatively or additionally, the remote plasma processing can include introducing one or more carriers and / or inert gases, such as argon (Ar), into the remote plasma source. The remotely generated plasma species then flow into the processing chamber 400 and process the metal nitride layer of the conductive structure formed on the substrate disposed within the processing chamber 400. As described above, depending on whether the plasma species are plasma-excited hydrogen species or plasma-excited nitrogen species, the interfacial and bulk O atoms in the metal nitride layer are reduced or the nitridation of the metal nitride layer is enhanced.

[0056]

[0062] In some embodiments, a thermal hydrogenation process can be used to expose the metal nitride layer to hydrogen atoms instead of a plasma hydrogenation process. In such embodiments, the thermal hydrogenation process is generally carried out at a high temperature (e.g., from about 500 °C to about 650 °C). At such a high temperature, H2 gas dissociates into individual atoms, which can then react with O atoms in the metal nitride layer 103 to form voids 213. Further, in such embodiments, the thermal hydrogenation process is generally carried out in a processing chamber different from the processing chamber 400. For example, in some embodiments, the thermal hydrogenation process is carried out in a rapid thermal processing chamber. In such embodiments, a salicidation process may be carried out simultaneously with the thermal hydrogenation process, thereby eliminating a subsequent annealing process.

[0057]

[0063] In embodiments where a thermal annealing process is utilized to expose the metal nitride layer to hydrogen atoms, the plasma nitridation process is carried out without air intrusion that exposes the metal nitride layer 103 to air. For example, in such embodiments, one chamber of a multi-chamber processing system may be configured to carry out the thermal hydrogenation process, and another chamber of the same multi-chamber processing system may be configured to carry out the plasma nitridation process. Thus, the substrate on which the metal nitride layer 103 is formed can be directly transferred to the plasma nitridation chamber after undergoing the thermal hydrogenation process without being exposed to air.

[0058]

[0064] FIG. 5 is a top view of a multi-chamber processing system 500 configured to implement one or more aspects of the present disclosure. The multi-chamber processing system 500 is configured to perform one or more manufacturing processes on individual substrates, such as silicon wafers, to form semiconductor devices. The multi-chamber processing system 500 includes a transfer chamber 506, a buffer chamber 508, single-wafer load locks 510 and 512, processing chambers 514, 516, 518, 520, 522, and 524, preheat chambers 523 and 525, and part or all of robots 526 and 528. The single-wafer load locks 510 and 512 include heating elements 513 and can be attached to the buffer chamber 508. The processing chambers 514, 516, 518, and 520 are attached to the transfer chamber 506. The processing chambers 522 and 524 are attached to the buffer chamber 508. The operation of the multi-chamber processing system 500 is controlled by a computer system 530. The computer system 530 can be any device or combination of devices configured to perform the operations of the present invention provided herein. Thus, the computer system 530 can be a controller or an array of controllers and / or a general-purpose computer configured with software that, when executed, performs the operations of the present invention. An example of a suitable multi-chamber processing system 500 is an Endura® RTM CL system manufactured by Applied Materials, Inc. of Santa Clara, Calif.

[0059]

[0065] Each of the processing chambers 514, 516, 518, 520, 522, and 524 can be configured to perform one or more processing steps in the manufacture of conductive structures (e.g., contact structures for field effect transistors (FETs)) within semiconductor devices. More specifically, the processing chambers 514, 516, 518, 520, 522, and 524 can include one or more metal deposition chambers, surface cleaning and preparation chambers, thermal annealing and / or thermal hydrogenation chambers, and plasma hydrogenation / nitridation chambers.

[0060]

[0066] For example, in the case of a contact structure including a Ti-TiN-Co stack formed on a silicon source or drain structure, in some embodiments, the multi-chamber processing system 500 may be configured to continuously perform several processing steps in the manufacturing process of such a conductive structure. In such embodiments, the processing chamber 514 may be configured to perform surface cleaning and preparation processing on the exposed surface of the silicon source or drain structure, the processing chamber 516 may be configured to continuously deposit Ti and TiN layers on the prepared silicon source or drain structure, the processing chambers 522 and / or 524 may be configured to form a silicon compound by performing rapid thermal processing (RTP) or other thermal annealing processing on the Ti / TiN layer and the source or drain structure, the processing chamber 518 may be configured to deposit a Co capping layer on the annealed Ti / TiN layer, and the processing chamber 520 may be configured to perform a hydrogenation process and then a nitridation process before or after the thermal annealing process. Therefore, in such embodiments, a complete contact structure can be formed without air intrusion into one or more layers of the contact structure and the resulting undesirable oxidation.

[0061]

[0067] In an alternative embodiment, not all processing steps for forming the complete contact structure are performed in a single multi-chamber processing system 500. For example, in some embodiments, the multi-chamber processing system 500 may include a metal deposition processing chamber, but the thermal annealing silicidation process may be performed in a different substrate processing system. In such an example, air intrusion occurs prior to the thermal annealing process. And it is known that such air intrusion can increase the presence of O atoms on the interfacial surface of the metal nitride layer and in the bulk material of the metal nitride layer of the contact structure. However, since the multi-chamber processing system 500 can be configured with both a metal deposition chamber and one or more plasma processing chambers, a continuous plasma (or thermal) hydrogenation / plasma nitridation process or a single-step plasma hydrogenation and nitridation process can be performed prior to air intrusion. Thus, after depositing the first metal layer 102 and the metal nitride layer 103, and before removing the substrate from the multi-chamber processing system 500 and exposing it to air, the multi-chamber processing system 500 can be configured to perform a continuous hydrogenation / nitridation process or a single-step plasma hydrogenation and nitridation process on the substrate. As described above, by nitriding the exposed surface of the metal nitride layer 103 prior to air intrusion, oxidation of the exposed surface during air intrusion and subsequent thermal annealing can be significantly reduced.

[0062]

[0068] In some embodiments, the multi-chamber processing system 500 may include one or more thermal annealing and plasma processing chambers. In such embodiments, a continuous hydrogenation and nitrogenation process or a single-step plasma hydrogenation and nitridation process can be performed after the thermal annealing process, thereby removing O atoms introduced by air intrusion prior to annealing and by the thermal annealing process itself. Typically, the thermal annealing process cannot maintain the desired low oxygen levels required for state-of-the-art device nodes due to the high temperatures that the processing components (e.g., seals, processing kit components, pumps, etc.) reach during the thermal process.

[0063]

[0069] Alternatively or additionally, a continuous hydrogenation / nitridation process or a single-step plasma hydrogenation and nitridation process may be performed before the thermal annealing process. Thus, in this embodiment, even if no air intrusion occurs after the deposition of the metal nitride layer 103 and before the thermal annealing process, the interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer can be reduced or eliminated before performing the thermal annealing process. Thus, in some configurations, the continuous hydrogenation and plasma nitridation process or the single-step plasma hydrogenation and nitridation process can be performed before the thermal annealing process and further before air intrusion occurs after the thermal annealing process.

[0064]

[0070] In some embodiments, the multi-chamber processing system 500 can include one or more metal deposition chambers configured to deposit the capping layer 104 and / or the conductive layer 106, and one or more plasma processing chambers configured to perform a continuous hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process. In this embodiment, a continuous hydrogenation and nitridation process or a single-step plasma hydrogenation and nitridation process can be performed before depositing the capping layer in the conductive structure, thereby removing the interfacial and bulk O atoms introduced by air intrusion and by the thermal annealing process for forming the silicon compound 105. It should be noted that no air intrusion occurs between the continuous hydrogenation and nitridation process and the deposition of the capping layer 104 and / or the conductive layer 106 in this embodiment. Thus, in this embodiment, if air intrusion occurs between the thermal annealing process and the deposition of the capping layer 104, the interfacial O atoms and O atoms present in the bulk portion of the metal nitride layer can be reduced or eliminated.

[0065] Reduction of Bulk and Interfacial Oxygen in the Contact Structure

[0071] FIG. 6 shows a flow diagram of a processing step for reducing bulk and interfacial oxygen in a contact structure according to some embodiments of the present disclosure. FIGS. 7A through 7E are schematic cross-sectional views of semiconductor devices corresponding to various stages of the process of FIG. 6 according to various embodiments of the present disclosure. FIGS. 7A through 7E show that a first metal layer 102, a metal nitride layer 103, and a capping layer 104 that fill cavity 109 are selectively deposited (e.g., as shown in FIG. 1, the layers are not conformally formed over cavity 109), but this is not intended to be a limitation of the scope of the disclosure described herein, and thus, the first metal layer 102, the metal nitride layer 103, and the capping layer 104 can be formed selectively or non-selectively, and one or more additional layers may be included.

[0066]

[0072] Prior to step 601, a cleaning process or other surface preparation process can be performed on the surface of the semiconductor substrate where a contact such as the exposed surface 701 of the source or drain structure 101 in FIG. 7A is to be formed. In some embodiments, a dry etching process can be performed to remove native oxide on the surface 701. For example, a remote plasma-assisted dry etching process such as conventional plasma etching or the SiCoNi™ etching process available from Applied Materials, Inc. located in Santa Clara, California can be performed. In the SiCoNi™ etching process, the surface of the semiconductor substrate where the contact is to be formed is exposed to H2, NF3, and / or NH3 plasma species (e.g., plasma-excited hydrogen and fluorine species). For example, in some embodiments, such a surface can experience simultaneous exposure to H2, NF3, and NH3 plasma. The SiCoNi™ etching process can be performed in a SiCoNi™ Preclean chamber. The SiCoNi™ Preclean chamber can be integrated into one of various multi-processing platforms including the Producer™ GT, Centura™ AP, and Endura platforms, all of which are available from Applied Materials.

[0067]

[0073] Method 600 begins at step 601. In step 601, as shown in FIG. 7B, a first metal layer 102 and a metal nitride layer 103 are deposited on a semiconductor substrate. For example, in some embodiments, a Ti layer is deposited first, followed by a TiN barrier layer. Such deposition can be performed using any suitable PVD, CVD, or ALD process. Thus, the deposition process may be a selective process or a non-selective deposition process. In a selective deposition process, the first metal layer 102 and the metal nitride layer 103 are deposited on the surface 701 but not on other surfaces of the semiconductor substrate 110. On the other hand, in a non-selective process, the first metal layer 102 and the metal nitride layer 103 can be deposited on all unmasked surfaces of the semiconductor substrate 110. In some embodiments, the deposition in step 601 is performed without air intrusion after the surface preparation process described above. That is, the semiconductor substrate is not exposed to air between the surface preparation process and the deposition in step 601. In such embodiments, the deposition in step 601 and the surface preparation process may be performed by different chambers of the same multi-chamber processing system (e.g., multi-chamber processing system 500), respectively.

[0068]

[0074] In step 603, a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. The thermal annealing process forms a silicon compound 105 as shown in FIG. 7C. For example, in some embodiments, a spike annealing process reaching a peak temperature between about 500°C and about 600°C can be performed in step 603. Alternatively, any other suitable annealing process can be performed instead to form a silicon compound 105 between the source or drain structure 101 and the first metal layer 102 deposited in step 601.

[0069]

[0075] In some embodiments, the chamber for performing step 603 may be configured as the chamber of the same multi-chamber processing system that performs the metal deposition of step 601. Thus, in this embodiment, the thermal annealing process of step 603 is performed without air intrusion after the metal deposition of step 601, thereby further reducing the interfacial O present on the surface 702 of the metal nitride layer 103. However, such a configuration of the multi-chamber processing system is not common for the reasons described above, and generally, air intrusion occurs between step 601 and step 603.

[0070]

[0076] In step 604, a continuous hydrogenation / plasma nitridation process is performed on the surface 702 of the metal nitride layer 103. That is, the surface 702 is exposed to hydrogen atoms and plasma-excited nitrogen species 703 as shown in FIG. 7D. In some embodiments, in step 604, a plasma hydrogenation process is then followed by a plasma nitridation process. In embodiments where the hydrogenation process is a plasma hydrogenation process, both the plasma hydrogenation process and the plasma nitridation process can be performed in the processing chamber 400 using the processing parameters described above in connection with FIG. 4. Alternatively, the plasma hydrogenation process may be performed in one of the processing chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500, while the plasma nitridation process may be performed in another chamber of the processing chambers 514, 516, 518, 520, 522, and 524.

[0071]

[0077] As described above, in some embodiments, the surface 702 of the metal nitride layer 103 is exposed to hydrogen atoms via a thermal hydrogenation process. In such embodiments, the thermal hydrogenation process of step 604 is performed in one of the processing chambers 514, 516, 518, 520, 522, and 524 of the multi-chamber processing system 500 (e.g., a rapid thermal processing chamber configured to use H2 gas as a processing gas). Further, in such embodiments, the plasma nitridation process is performed in another one of the processing chambers 514, 516, 518, 520, 522, and 524 (e.g., a processing chamber similar to the plasma processing chamber 400 of FIG. 4). Thus, even if the thermal hydrogenation process and the plasma nitridation process are performed in different processing chambers, air intrusion does not occur between these two processes.

[0072]

[0078] In step 605, as shown in FIG. 7E, the capping layer 104 is deposited on the annealed first metal layer 102 and the metal nitride layer 103. For example, in one embodiment, the metal capping layer is a Co layer or a layer of a cobalt-containing alloy. Since the interfacial O atoms that may be present on the surface 702 of the metal nitride layer 103 are removed during step 604, the adhesion between the capping layer 104 and the metal nitride layer 103 is improved over the adhesion of a contact structure formed by the prior art. Further, the removal of O atoms in the metal nitride layer 103 reduces the electrical resistivity of the conductive structure 100.

[0073]

[0079] In some embodiments, steps 604 and 605 are performed in the same multi-chamber processing system so that no air intrusion occurs after the successive hydrogenation and nitridation treatments of step 604. As a result, oxidation of the metal nitride layer 103 that may occur during exposure to the atmosphere is avoided. In other embodiments, the processing chamber for performing the successive hydrogenation and nitridation treatments of step 604 may be configured in a different multi-chamber processing system from the processing chamber for performing step 605. It should be noted that in such embodiments, the nitridation treatment of step 604 completely nitrides the surface of the metal nitride layer 103, thereby minimizing or otherwise preventing oxidation that may occur during air intrusion between steps 604 and 605.

[0074]

[0080] FIG. 8 shows a flow diagram of processing steps for reducing bulk and interfacial oxygen in a contact structure according to some embodiments of the present disclosure. Prior to step 801, a cleaning process or other surface preparation process can be performed as described above in connection with FIG. 7.

[0075]

[0081] Method 800 begins at step 801. In step 801, a metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101. Step 801 may be substantially similar to step 601 of method 600.

[0076]

[0082] In step 802, a continuous hydrogenation / plasma nitridation treatment is performed on the surface 702 of the metal nitride layer 103. That is, the surface 702 is exposed to hydrogen atoms and plasma-excited nitrogen species. Step 802 may be substantially similar to step 604 of method 600. However, note that unlike step 604, the continuous hydrogenation / plasma nitridation treatment of step 802 is performed before the thermal annealing treatment. Further, in some embodiments, step 802 is performed in a chamber (e.g., a rapid thermal processing chamber) configured as part of a multi-chamber processing system including a thermal annealing chamber for performing step 803. In such embodiments, the influence of O atoms in the first metal layer 102 and the metal nitride layer 103 deposited in step 801 is further reduced because such O atoms are removed before the annealing treatment of step 803.

[0077]

[0083] In step 803, a thermal annealing treatment is performed on the semiconductor substrate 110 including the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 803 may be substantially similar to step 603 of method 600. Alternatively, in embodiments where a thermal hydrogenation treatment is performed in step 802, the thermal annealing treatment may be performed in step 802 and step 803 may be skipped. For example, in some embodiments, the thermal annealing treatment for forming the silicon compound 105 is performed in the same processing chamber as the thermal hydrogenation treatment of step 802. In such embodiments, the thermal annealing treatment may be performed simultaneously with, immediately before, or immediately after the thermal hydrogenation treatment.

[0078]

[0084] At any step 804, plasma treatment is performed on the surface 702 of the metal nitride layer 103. Step 804 may be substantially similar to step 604 of method 600. Thus, in an embodiment of method 800 in which step 804 is performed, a continuous hydrogenation / nitridation treatment is performed before and after the thermal annealing treatment of step 803. In some embodiments, the continuous hydrogenation / nitridation treatment performed in step 804 is substantially the same as the plasma treatment performed in step 802. In other embodiments, the continuous hydrogenation / nitridation treatment of step 804 may be different from the continuous hydrogenation / nitridation treatment of step 802. For example, the treatment parameters of the continuous hydrogenation / nitridation treatment utilized in step 802 may be different from the treatment parameters of the continuous hydrogenation / nitridation utilized in step 804.

[0079]

[0085] In step 805, the capping layer 104 and / or the conductive layer 106 are deposited on the annealed first metal layer 102 and the metal nitride layer 103. Step 805 may be substantially similar to step 605 of method 600. Similarly, in some embodiments, steps 804 and 805 may be performed in the same multi-chamber processing system so that no air intrusion occurs after the plasma treatment of step 804. As a result, oxidation of the metal nitride layer 103 that may occur while exposed to air is avoided, and the adhesion between the capping layer 104 and the metal nitride layer 103 is improved over the adhesion of contact structures formed by the prior art.

[0080]

[0086] FIG. 9 shows a flow diagram of a processing step for reducing bulk and interfacial oxygen in a contact structure according to some embodiments of the present disclosure. Prior to step 901, a cleaning process or other surface preparation process may be performed as described above in connection with method 600. As shown, method 900 begins at step 901. In step 901, a first metal layer 102 and a metal nitride layer 103 are deposited on the source or drain structure 101. Step 901 may be substantially similar to step 601 of method 600. In step 902, a continuous hydrogenation / nitridation process is performed on the surface 702 of the metal nitride layer 103. Step 902 may be substantially similar to step 802 of method 800. In step 903, a thermal annealing process is performed on the semiconductor substrate 110 including the first metal layer 102, the metal nitride layer 103, and the source or drain structure 101. Step 903 may be substantially similar to step 603 of method 600. In step 905, a capping layer 104 is deposited on the annealed first metal layer 102 and metal nitride layer 103. Step 905 may be substantially similar to step 605 of method 600. Thus, in method 900, the continuous hydrogenation / nitridation process is performed before the thermal annealing process of step 903, but not after the thermal annealing process of step 903. The continuous hydrogenation / nitridation process generally includes a plasma or thermal hydrogenation process and a plasma nitridation process.

[0081]

[0087] Methods 600 and 800 are described for forming a contact structure on a substrate, but similarly, methods 600 and 800 may be utilized to form other conductive structures on a substrate. Thus, any conductive structure including a metal nitride layer can benefit from being formed by method 600 or 800.

[0082] Metal gate structure with reduced EOT

[0088] According to various embodiments of the present disclosure, a continuous hydrogenation and nitridation process is utilized in the manufacture of a high-k dielectric / metal gate stack to reduce the effective oxide thickness (EOT) of the stack. In this embodiment, the EOT of the stack decreases without a compromise (trade-off) associated with an increase in leakage or a flat-band voltage shift. Such an increase in leakage or a flat-band voltage shift is known to occur when the high-k dielectric layer in the stack simply decreases in thickness or is otherwise scaled down by conventional techniques. One such stack is shown in FIG. 10.

[0083]

[0089] FIG. 10 shows a cross-sectional view of a metal gate structure 1000 formed in accordance with an embodiment of the present disclosure. The metal gate structure 1000 is formed on a semiconductor substrate 1001 as part of a semiconductor device, such as a MOSFET or other FET. The metal gate structure 1000 is a stack of a plurality of material layers formed on the semiconductor substrate 1001 and includes, for example, an interface layer 1002 disposed on the semiconductor substrate 1001, a high-k dielectric layer 1003 disposed on the interface layer 1002, a metal nitride capping layer 1004 disposed on the high-k dielectric layer 1003, and a metal gate electrode layer 1005 disposed on the metal nitride capping layer 1004. In the embodiment shown in FIG. 10, the various layers of the metal gate structure 1000 are shown as a simple film stack formed on the semiconductor substrate 1001. In practice, the metal gate structure 1000 can be formed within a contact well or other cavity formed within an insulating material or a dielectric material similar to the insulating material 120 of FIG. 1. Thus, one or more of the interface layer 1002, the high-k dielectric layer 1003, the metal nitride capping layer 1004, and the metal gate electrode layer 1005 may be material layers conformally deposited within such a cavity.

[0084]

[0090] The semiconductor substrate 1001 may be any suitable semiconductor substrate on which the metal gate structure 1000 can be formed. Thus, the semiconductor substrate 1001 may be formed from any suitable semiconductor material (including, but not limited to, Si (silicon), Ge (germanium), silicon-germanium (Si-Ge), silicon-germanium-carbon (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and all other group III / V or II / VI compound semiconductors). Alternatively or additionally, the semiconductor substrate 1001 may be a layered semiconductor such as, for example, Si / Si-Ge, semiconductor-on-insulator (SOI), or silicon-germanium-on-insulator (SiGOI). Further, in some embodiments, the semiconductor substrate 1001 includes doped regions and / or undoped regions such as an n-doped region or a p-doped region proximate to the interfacial oxide layer 1002.

[0085]

[0091] The interfacial oxide layer 1002 is disposed on the semiconductor substrate 1001 between the semiconductor substrate 1001 and the high-k dielectric layer 1003 and is configured as an interfacial oxide layer suitable for use in the metal gate structure 1000. In embodiments where the semiconductor substrate 1001 includes a Si-containing material, the interfacial oxide layer 1002 may include silicon oxide (SiO X ), silicon oxynitride (SiNO, Si2NO, Si2N2O), and / or nitrided silicon oxide. In embodiments where the semiconductor substrate 1001 is other than a Si-containing semiconductor material, the interfacial oxide layer 1002 may include a semiconductor oxide, a semiconductor oxynitride, and / or a nitrided semiconducting oxide.

[0086]

[0092] The interface oxide layer 1002 can be formed by any suitable thermal or wet growth technique (e.g., oxidation or oxynitridation). For example, but not by way of limitation, the interface oxide layer 1002 may be formed by a wet chemical oxidation process. The wet chemical oxidation process includes treating the cleaned surface of the semiconductor substrate 1001 (e.g., an HF-finalized semiconductor surface) with a mixture of ammonium hydroxide, hydrogen peroxide, and water. Alternatively, the interface oxide layer 1002 may be formed by treating the HF-finalized semiconductor surface in an ozonated aqueous solution. Alternatively, the interface oxide layer 1002 may be formed by any suitable thermal oxidation technique.

[0087]

[0093] The thickness of the interface oxide layer 1002 is a function of the semiconductor device that the metal gate structure 1000 partially constitutes. In addition, the interface oxide layer 1002 is significantly thinner than the high-k dielectric layer 1003, the metal nitride capping layer 1004, and the metal gate electrode layer 1005. Typically, the interface oxide layer 1002 has a thickness of about 0.5 to 2.0 nm, but in some embodiments, the interface oxide layer 1002 may be thicker. In some embodiments, the heat treatment for device fabrication that occurs after the formation of the metal gate structure 1000 may further increase the thickness of the interface oxide layer 1002.

[0088]

[0094] The high-k dielectric layer 1003 may be a gate dielectric layer or other dielectric layer within the metal gate structure 1000 and includes a so-called "high-k dielectric" material. More specifically, the high-k dielectric layer 1003 includes one or more materials having a dielectric constant greater than that of SiO2 (e.g., a material having a dielectric constant of at least about 4.0, or ideally at least about 10.0). Further, the high-k dielectric material included in the high-k dielectric layer 1003 is suitable for use in an integrated circuit. Thus, the one or more high-k dielectric materials included in the high-k dielectric layer 1003, in addition to having a high dielectric constant, ideally also have the ability to prevent dopant diffusion, low electrical defects that can compromise breakdown performance, excellent thermal stability, and a high recrystallization temperature. Examples of high-k dielectric materials suitable for use in such a high-k dielectric layer 1003 include, but are not limited to, silicon nitride, silicon oxynitride, metal oxides, metal nitrides, metal oxynitrides, and / or metal silicates. In some embodiments, the high-k dielectric layer 1003 is hafnium oxide (Hf x O y ), zirconium oxide (ZrO2), hafnium silicate (Hf x Si 1ーx O y ), or other hafnium-based dielectrics, lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), yttrium oxide (Y2O3), hafnium silicate (Hf x Si 1ーx O y ), lanthanum oxide (La2O3), and / or one or more of these multilayer stacks.

[0089]

[0095] The high-k dielectric layer 1003 can be formed by any suitable deposition method including, for example, thermal growth processes such as oxidation, nitridation, or oxynitridation. Alternatively, the high-k dielectric layer 1003 may be formed by one or more deposition processes (including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition, and / or any combination thereof).

[0090]

[0096] The thickness 1003A of the high-k dielectric layer 1003 can vary depending on the dielectric material contained therein, the process used to form the high-k dielectric layer 1003, and the shape and operation of the semiconductor device in which the metal gate structure 1000 is included. In some embodiments, the thickness 1003A of the high-k dielectric layer 1003 is from about 1.0 nm to about 20 nm.

[0091]

[0097] The metal nitride capping layer 1004 is a metal layer disposed on the high-k dielectric layer 1003 and is typically configured as a conductive protection layer on the high-k dielectric layer 1003. Thus, in some embodiments, the metal nitride capping layer 1004 is configured to prevent unwanted oxidation of the semiconductor substrate 1001 and / or the high-k dielectric layer 1003. Further, in such embodiments, the metal nitride capping layer 1004 may be configured to allow oxygen to diffuse from the high-k dielectric layer 1003 during a thermal annealing process that occurs after deposition of the metal nitride capping layer 1004. In such embodiments, the metal nitride capping layer 1004 may be further configured to allow oxygen to diffuse from the interface layer 1009 formed between the high-k dielectric layer 1003 and the metal nitride capping layer 1004 during the thermal annealing process.

[0092]

[0098] In some embodiments, the metal nitride capping layer 1004 includes metal nitrides such as TiN, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), etc. It should be noted that in some embodiments, the deposition of the nitride capping layer 1004 on the high-k dielectric layer 1003 may result in the formation of an interface layer 1009 disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004. According to some embodiments, when the continuous plasma hydrogenation and nitridation processes described herein are applied to the exposed surface of the metal nitride capping layer 1004, the interface layer 1009 is continuously removed or its thickness is reduced.

[0093]

[0099] The metal nitride capping layer 1004 may be formed by any suitable deposition method including, but not limited to, PVD processing, CVD processing, PECVD processing, MOCVD processing, ALD deposition processing, reactive sputtering, chemical solution deposition, and / or any combination thereof.

[0094]

[0100] In some embodiments, the metal nitride capping layer 1004 is significantly thinner than the high-k dielectric layer 1003 and the metal gate electrode layer 1005. For example, in an embodiment of the metal gate structure 1000 where the high-k dielectric layer 1003 is an HfO2 layer having a thickness 1003A of about 20 nm to about 40 nm and the metal gate electrode layer 1005 is a TiN layer having a thickness of about 20 nm to about 40 nm, the metal nitride capping layer 1004 may have a thickness 1004A of about 5 nm to about 15 nm.

[0095]

[0101] In some embodiments, the thickness 1004A of the metal nitride capping layer 1004 is selected to facilitate the diffusion of oxygen atoms from the high-k dielectric layer 1003 and / or the interface layer 1009. Specifically, in this embodiment, the thickness 1004A is selected such that O atoms diffuse from the high-k dielectric layer 1003 and / or the interface layer 1009 during the thermal annealing process that occurs after the deposition of the metal nitride capping layer 1004. In this embodiment, the thickness 1004A is selected to be less than the diffusion length of O atoms passing through the metal nitride capping layer 1004 during the thermal annealing process. In one example, one such thermal annealing process is a spike annealing process performed on the metal gate structure 1000 at a peak temperature of about 700 to about 900 °C for 1 to 2 seconds.

[0096]

[0102] The metal gate electrode layer 1005 is a metal layer formed on the metal nitride capping layer 1004 and includes one or more deposited metal layers. In some embodiments, the metal gate electrode layer 1005 is configured as the gate electrode and / or the work function metal of the metal gate structure 1000. In this embodiment, the one or more metal layers included in the metal gate electrode layer 1005 are selected to have an integrated gate electrode work function value that facilitates the operation of the metal gate structure 1000 and the semiconductor device in which the metal gate structure 1000 is included. The metal gate electrode 1005 may be formed by any suitable deposition method including, but not limited to, CVD, PECVD, MOCVD, ALD, evaporation, reactive sputtering, chemical solution deposition, and / or any combination thereof.

[0097]

[0100] In some embodiments, the metal gate electrode layer 1005 is a p-metal gate material such as TiN. Alternatively, in some embodiments, the metal gate electrode layer 1005 is an n-metal gate. N-metals suitable for use in the metal gate electrode layer 1005 include titanium aluminum carbide (Ti x AlC).

[0098] Formation of a Metal Gate Structure with Reduced EOT

[0101] According to various embodiments, during the manufacture of the metal gate structure 1000, prior to the deposition of the metal gate electrode layer 1005, a continuous plasma hydrogenation and nitridation treatment is performed on the metal nitride capping layer 1004. In this embodiment, the EOT of the metal gate structure 1000 is reduced, but the leakage current of the metal gate structure 1000 increases to a lower extent than expected. Further, in this embodiment, the metal gate structure 1000 typically exhibits little or no flat band voltage shift associated with the reduced EOT.

[0099]

[0102] For example, in one embodiment of the metal gate structure 1000, the interfacial oxide layer 1002 has a thickness of about 1 to 2 nm, the high-k dielectric layer 1003 has a thickness 1003A of about 2 to 3 nm, and the metal nitride capping layer 1004 has a thickness 1004A of about 3 to 4 nm. In this embodiment, one measurable effect in treating the metal nitride capping layer 1004 using the continuous plasma hydrogenation and nitridation treatment described herein is that the measured EOT of the metal gate structure 1000 decreases by about 1 Å (i.e., from about 9 Å to about 8 Å). Another effect of such treatment of the metal nitride capping layer 1004 is that the leakage current (at a flat band voltage of -1V) increases by about 2.4 times (i.e., from about 0.268 A / cm 2 to about 0.658 A / cm 2 up to). In contrast, according to established scaling trends well-known in the art, if the EOT of the metal gate structure 1000 is instead reduced by conventional techniques (e.g., reducing the thickness 1003A by about 1 Å), the leakage current is expected to increase by about 10 times. Thus, it has been found that treating the metal nitride capping layer 1004 using the continuous plasma hydrogenation and nitridation treatment described herein has the effect of reducing the EOT of the metal gate structure 1000 at about one-fourth of the increased leakage current associated with simply reducing the thickness 1004A of the metal nitride capping layer 1004.

[0100]

[0103] Furthermore, even though the above-described reduction of EOT is achieved, when the metal gate structure 1000 is formed by continuous plasma hydrogenation and nitridation processes, it has been shown that the flat band voltage shift measured in the metal gate structure 1000 remains substantially constant. Therefore, by applying the continuous plasma hydrogenation and nitridation processes to the metal nitride capping layer 1004, it becomes possible to fabricate the metal gate structure 1000 with reduced EOT without causing a flat band voltage shift and the resulting impact on the device design.

[0101]

[0104] FIG. 11 shows a flowchart of processing steps for reducing EOT in a metal gate structure according to various embodiments of the present disclosure. FIGS. 12A through 12J are schematic cross-sectional views of semiconductor devices corresponding to various stages of the processing of FIG. 11 according to various embodiments of the present disclosure.

[0102]

[0105] Method 1100 starts at step 1101. At step 1101, as shown in FIG. 12A, a high-k dielectric layer 1003 is deposited on the interfacial oxide layer 1002. The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with FIG. 10.

[0103]

[0106] At step 1102, as shown in FIG. 12B, a metal nitride capping layer 1004 is deposited on the high-k dielectric layer 1003. The metal nitride capping layer 1004 may be formed via any suitable deposition method described above in connection with FIG. 10. In some embodiments, the deposition of the metal nitride capping layer 1004 results in the formation of an interfacial layer 1009. The interfacial layer 1009 is disposed at the interface between the high-k dielectric layer 1003 and the metal nitride capping layer 1004. In such embodiments, the interfacial layer 1009 generally includes voids (which may be similar to the voids 213 in FIG. 2A) and / or O atoms incorporated therein due to contamination present in the processing environment during the deposition process of step 1102.

[0104]

[0107] In optional step 1103, the exposed surface 1201 shown in FIG. 12B is exposed to air. For example, in some embodiments, the metal nitride capping layer 1004 is deposited in one processing system, such as the multi-chamber processing system 500 of FIG. 5, but the next processing step performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after deposition of the metal nitride layer 1004. In an embodiment where the metal nitride capping layer 1004 is deposited in one chamber of a multi-chamber processing system and step 1104 is performed in another one or two processing chambers of the same multi-chamber processing system, optional step 1103 is not performed.

[0105]

[0108] In embodiments where the metal nitride capping layer 1004 deposited in step 1102 is a sacrificial metal nitride layer that is later removed, method 1100 proceeds to step 1131. In embodiments where the metal nitride capping layer 1004 deposited in step 1102 is retained within the metal gate structure 1000, method 1100 proceeds to step 1104. In some embodiments, the sacrificial metal nitride layer can be removed using a subsequent wet or dry etching process that is selective for removal of the metal nitride capping layer 1004.

[0106]

[0109] In step 1104, as shown in FIG. 12C, a continuous plasma hydrogenation and nitridation process is performed on the surface 1201 of the metal nitride capping layer 1004. The plasma hydrogenation and nitridation process can be substantially similar to the plasma hydrogenation and nitridation process described above in connection with FIG. 4. Further, the plasma hydrogenation process includes non-oxidizing plasma-excited hydrogen species and does not include any oxidizing plasma-excited hydrogen species.

[0107]

[0110] In some embodiments, the plasma hydrogenation treatment of step 1104 is carried out with a chamber pressure between about 20 mTorr and about 100 mTorr, a treatment temperature (e.g., substrate pedestal temperature) between about 400 °C and about 500 °C, and an RF power between about 500 W and about 1500 W, for a period between about 30 seconds and about 150 seconds, with a flow rate of H2 between about 20 sccm and about 100 sccm, and a flow rate of Ar between about 900 sccm and about 980 sccm. In some embodiments, the flow rate of H2 is between about 1% and about 15% of the total process gas introduced into the chamber. In some embodiments, the plasma hydrogenation treatment of step 1104 is carried out with a chamber pressure between about 45 mTorr and about 55 mTorr, a treatment temperature between about 425 °C and about 475 °C, and an RF power between about 700 W and about 800 W, for a period between about 85 seconds and about 95 seconds, with a flow rate of H2 between about 45 sccm and about 55 sccm, and a flow rate of Ar between about 965 sccm and about 955 sccm.

[0108]

[0111] In some embodiments, the plasma nitridation treatment of step 1104 is carried out with a chamber pressure between about 10 mTorr and about 50 mTorr, a treatment temperature between about 400 °C and about 500 °C, and an RF power between about 500 W and about 1500 W, for a period between about 30 seconds and about 150 seconds, with a flow rate of NH3 between about 1% and about 10% of the total process gas flow rate, a flow rate of N2 between about 45% and about 55% of the total process gas flow rate, and a flow rate of Ar selected to be equal to the remainder of the process gas flow rate. In some embodiments, the plasma nitridation treatment of step 1104 is carried out with a chamber pressure between about 15 mTorr and about 25 mTorr, a treatment temperature between about 425 °C and about 475 °C, and an RF power between about 700 W and about 800 W, for a period between about 85 seconds and about 95 seconds, with a flow rate of NH3 between about 2% and about 3% of the total process gas flow rate, a flow rate of N2 between about 45% and about 55% of the total process gas flow rate, and a flow rate of Ar selected to be equal to the remainder of the process gas flow rate.

[0109]

[0112] In summary, in step 1104, the surface 1201 is exposed to plasma-excited hydrogen species generated by plasma hydrogenation treatment, and some or all of the oxides present on the surface 1201 are reduced. Further, in some embodiments, such plasma-excited hydrogen species can also reduce some or all of the oxygen (O) atoms present in the bulk material of the metal nitride capping layer 1004. Further, in step 1104, the surface 1201 is exposed to plasma-excited nitrogen species generated by plasma nitridation treatment, thereby saturating the surface 1201 with N atoms and, in some embodiments, filling the vacancies present in the bulk material of the metal nitride capping layer 1004 with N atoms. Thus, in some embodiments, the interface layer 1009 is removed or significantly reduced, as shown in FIG. 12D.

[0110]

[0113] In some embodiments, the plasma hydrogenation treatment of step 1104 is performed in the same processing chamber (e.g., the processing chamber 400 of FIG. 4) as the plasma nitridation treatment of step 1104. Alternatively, the plasma hydrogenation treatment of step 1104 is performed in a first processing chamber of a multi-chamber processing system, while the plasma nitridation treatment of step 1104 is performed in a second processing chamber of the same multi-chamber processing system. In either case, it should be noted that the surface 1201 is not exposed to air between the plasma hydrogenation treatment and the plasma nitridation treatment of step 1104. Thus, in any embodiment, the surface 1201 is not exposed to air after being exposed to plasma-excited hydrogen species and before being exposed to plasma-excited nitrogen species.

[0111]

[0114] In some embodiments, before performing plasma hydrogenation treatment in the processing chamber, for example, in order to reduce trace oxygen contamination in the processing chamber, an oxygen-free conditioning process is performed in the processing chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma without the substrate being placed and before the substrate is treated with the above-described plasma hydrogenation treatment. Such plasma treatment of the processing chamber before introducing the substrate into the chamber may be referred to as a plasma every wafer (PEW) treatment or a PEW process.

[0112]

[0115] In some embodiments, such PEW treatment includes introducing one or more non-oxygen-containing gases such as N2, NH3, Ar, H2, or any suitable combination thereof into the processing chamber and exciting one or more gases to form an oxygen-free plasma. Alternatively, the PEW treatment may include introducing plasma-containing radicals and / or ions of N, H, or NH3, or any suitable combination thereof into the processing chamber, and the plasma is formed in a remote plasma source outside the processing chamber. In one embodiment, NH3 gas, or a combination of NH3 gas and Ar gas, is introduced into the processing chamber. In another embodiment, H2 gas, or a combination of H2 gas and Ar gas, is introduced into the processing chamber. In yet another embodiment, N2 gas, or a combination of N2 gas and Ar gas, is introduced into the processing chamber.

[0113]

[0116] Typically, the plasma treatment of the processing chamber before introducing the substrate includes introducing or forming a hydrogen- and / or nitrogen-containing plasma in the processing chamber. In some embodiments, radicals (e.g., N * , NH * , and / or H * ) generated from the plasma in the processing chamber during the PEW treatment react with trace amounts of O atoms in the processing chamber.

[0114]

[0117] In some embodiments, during the PEW process, one or more gases introduced into the processing chamber are energized by an RF power source such as the RF power source 414 of FIG. 4. The RF power can be pulsed with a duty cycle of 2% to 70% and can be in the range of about 100 W to about 2500 W. The RF power can also be a continuous wave in the range of about 100 W to about 2500 W. In such embodiments, the PEW process of step 1104 is carried out at a chamber pressure of about 10 mTorr to about 200 mTorr, a processing temperature of about 400 °C to about 500 °C, and an RF power of about 250 W to about 750 W for a period of about 20 seconds to about 100 seconds, with an H2 flow rate of about 50 sccm to about 200 sccm and an O2 flow rate of about 450 sccm to about 550 sccm.

[0115]

[0118] In optional step 1105, the exposed surface 1201 is exposed to air. For example, in some embodiments, the continuous hydrogenation and nitridation processes described above are carried out in a certain processing system, but the next processing step carried out on the semiconductor substrate 1001 is carried out in a different processing system. Thus, in such an embodiment, the semiconductor substrate 1001 is exposed to air after the deposition of the metal nitride layer 1004. In embodiments where the continuous hydrogenation and nitridation processes are carried out in one chamber of a multi-chamber processing system and step 1106 is carried out in another processing chamber of the same multi-chamber processing system, optional step 1105 is not carried out.

[0116]

[0119] In embodiments where a sacrificial silicon-containing layer is subsequently deposited and removed as part of the formation of the metal gate structure 1000, method 1100 proceeds from step 1105 to step 1121. In embodiments where a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, method 1100 proceeds to step 1106. The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form a deposited layer.

[0117]

[0120] In step 1106, a thermal annealing process such as a post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the metal nitride capping layer 1004. For example, in some embodiments, a spike anneal process is performed in step 1106, reaching a peak temperature of about 600 to 900 °C. The post-cap anneal is performed on the partially formed metal gate structure 1000, smoothing the interface, repairing unsaturated bonds, and injecting thermal energy into the metal nitride capping layer.

[0118]

[0121] In step 1107, as shown in FIG. 12E, the metal gate electrode layer 1005 is deposited on the processed metal nitride capping layer 1004, thereby completing the formation of the metal gate structure 1000. The metal gate electrode 1005 can be formed by any suitable deposition method described above in connection with FIG. 10.

[0119]

[0122] In step 1121, as shown in FIG. 12F, the sacrificial silicon layer 1202 is deposited on the metal nitride capping layer 1004. Step 1121 is performed after the surface 1201 of the metal nitride capping layer 1004 has been treated by the continuous plasma hydrogenation and nitridation processes of step 1104 and the optional air exposure of step 1105.

[0120]

[0123] The sacrificial silicon layer 1202 may include any suitable silicon-containing material such as amorphous silicon and may be deposited using any suitable deposition process well known in the art such as CVD processing. The sacrificial silicon layer 1202 is deposited on the metal nitride capping layer 1004 and reduces the formation of oxides in the metal nitride capping layer 1004, the interface layer 1009 (if still present), and the high-k dielectric layer 1003 during subsequent thermal annealing processes (e.g., so-called post-cap anneal processes). In some embodiments, the post-cap anneal process includes a thermal anneal process in air. As a result, further oxidation of a very thin layer of the metal gate structure 1000 including the interface layer 1002, the high-k dielectric layer 1003, and the metal nitride capping layer 1004 may occur, thereby increasing the EOT of the metal gate structure 1000. However, the presence of the sacrificial silicon layer 1202 can shield the layers of the metal gate structure 1000 from O atoms in the air during the pre-cap anneal process. Further, the sacrificial silicon layer 1202 can react with and hold O atoms dissipated from the high-k dielectric layer 1003, the interface layer 1009 (if still present), and the metal nitride capping layer 1004 during the thermal annealing process. Thus, the sacrificial silicon layer 1202 minimizes or eliminates the possibility of unwanted oxidation of part of the metal gate structure 1000 during subsequent thermal annealing processes.

[0121]

[0124] In step 1122, a thermal annealing process such as a post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride capping layer 1004, and the sacrificial silicon layer 1202. The thermal annealing process of step 1122 may be substantially similar to the thermal annealing process of step 1106 described above.

[0122]

[0125] In step 1123, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process can be utilized in step 1123, including selective wet etching processes, plasma-based dry etching processes, chemical mechanical polishing processes, or any combination thereof. Next, method 1100 proceeds to step 1107. In step 1107, the final layer of the metal gate structure 1000 is deposited.

[0123]

[0126] In step 1131, as shown in FIG. 12G, a sacrificial silicon layer 1203 is deposited on the metal nitride capping layer 1004. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1131. However, it should be noted that in step 1131, the metal nitride capping layer 1004 has not been treated with continuous plasma hydrogenation and nitridation processes. As a result, the metal nitride capping layer 1004 may still include the interface layer 1009 as shown.

[0124]

[0127] In step 1132, a thermal annealing process such as a post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the metal nitride capping layer 1004, the interface layer 1009, and the sacrificial silicon layer 1203. The thermal annealing process of step 1132 may be substantially similar to the thermal annealing process of step 1106 described above.

[0125]

[0128] In step 1133, as shown in FIG. 12H, the sacrificial silicon layer 1203, the metal nitride capping layer 1004, and the interface layer 1009 are removed from the metal gate structure 1000. Any technically feasible removal process or combination of processes can be used in step 1123, including selective wet etching processes, plasma-based dry etching processes, chemical mechanical polishing processes, or any combination thereof. Next, method 1100 proceeds to step 1134.

[0126]

[0129] In step 1134, as shown in FIG. 12I, a final metal nitride capping layer 1204 is deposited on the high-k dielectric layer 1003. The final metal nitride capping layer 1204 may be substantially similar to the metal nitride capping layer 1004 and may also include the interface layer 1009.

[0127]

[0130] In optional step 1135, the exposed surface 1205 shown in FIG. 12I is exposed to air. For example, in some embodiments, the final metal nitride capping layer 1204 is deposited in a processing system, but the next processing step performed on the semiconductor substrate 1001, i.e., step 1136, is performed in a different processing system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after deposition of the final metal nitride layer 1204. In embodiments where the final metal nitride capping layer 1204 is deposited in one chamber of a multi-chamber processing system and step 1136 is performed in another one or two processing chambers of the same multi-chamber processing system, optional step 1135 is not performed.

[0128]

[0131] In step 1136, as shown in FIG. 12J, a continuous plasma hydrogenation and nitridation treatment is performed on the surface 1205 of the final metal nitride capping layer 1204. The continuous plasma hydrogenation and nitridation treatment performed in step 1136 may be substantially similar to the treatment used in step 1104. As a result, the interface layer 1009 can be removed or reduced during step 1136, thereby removing O atoms present in the final metal nitride capping layer 1204, the interface layer 1009, and in some embodiments, the high-k dielectric layer 1003. As a result, the EOT of the metal gate structure 1000 is reduced without reducing the thickness 1003A of the high-k dielectric layer 1003.

[0129]

[0132] After the continuous plasma hydrogenation and nitridation treatment is performed in step 1136, method 1100 proceeds to step 1107. In step 1107, the final layer of the metal gate structure 1000 is deposited. In embodiments where steps 1136 and 1107 are performed in different processing systems, the semiconductor substrate 1001 is necessarily exposed to air. However, since the plasma nitridation treatment in step 1136 can completely or almost completely nitride the exposed surface 1205 of the final metal nitride capping layer 1204, generally little or no oxidation occurs while it is exposed to air.

[0130] Single-step nitrogen-hydrogenation treatment

[0133] Method 1300 starts at step 1301. In step 1301, as shown in FIG. 14A, a high-k dielectric layer 1003 is deposited on the interfacial oxide layer 1002. The interfacial oxide layer 1002 can be deposited by any suitable method (e.g., chemical oxidation of the underlying semiconductor substrate 1001, thermal oxidation of the underlying substrate, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.). The high-k dielectric layer 1003 may be formed via any suitable deposition method described above in connection with FIG. 10. The high-k dielectric layer 1003 can include any high-k material that is oxidizable. According to one embodiment, the high-k dielectric layer 1003 includes silicon dioxide (SiO2) or hafnium oxide (HfO2).

[0131]

[0134] In step 1302, as shown in FIG. 14B, a capping layer 1404 is deposited on the high-k dielectric layer 1003. The capping layer 1404 may be formed by any suitable deposition method described above in connection with FIG. 10. The capping layer 1404 may include a metal nitride. The capping layer may include a metal nitride such as titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or titanium silicon nitride (TiSiN) according to one embodiment. In some embodiments, the deposition of the capping layer 1404 results in the formation of an interface layer 1409 disposed at the interface between the high-k dielectric layer 1003 and the capping layer 1404. In such embodiments, the interface layer 1409 generally includes defects such as pores (which may be similar to the pores 213 in FIG. 2A) and / or O atoms incorporated therein due to contamination present in the processing environment during the deposition process of step 1302. Due to electron hopping from defect to defect, the defects may allow undesirable charge transfer. Charge transfer may cause current leakage or dielectric breakdown, reducing the electrical reliability of the metal gate structure 1000.

[0132]

[0135] In optional step 1303, the exposed surface 1401 shown in FIG. 14B is exposed to air. For example, in some embodiments, the capping layer 1404 is deposited in one processing system such as the multi-chamber processing system 500 of FIG. 5, but the next processing step performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after the deposition of the capping layer 1404. In embodiments where the capping layer 1404 is deposited in one chamber of a multi-chamber processing system and step 1304 is performed in another one or two processing chambers of the same multi-chamber processing system, the optional step 1303 is not performed.

[0133]

[0136] In embodiments where the capping layer 1404 deposited in step 1302 is a sacrificial layer that is later removed, method 1400 proceeds to step 1331. In embodiments where the capping layer 1404 deposited in step 1302 is retained within the metal gate structure 1000, method 1300 proceeds to step 1304. In some embodiments, the sacrificial layer may be removed by use of a subsequent wet or dry etching process that is selective to the removal of the capping layer 1404.

[0134]

[0137] In step 1304, as shown in FIG. 14C, a single-step plasma hydrogenation and nitridation process is performed on the surface 1401 of the capping layer 1404. The single-step plasma hydrogenation and nitridation process includes exposing a workpiece such as the metal gate structure 1000 to a processing plasma that includes a nitrogen-containing gas and a hydrogen-containing gas. In some embodiments, the hydrogen-containing gas substantially includes both nitrogen and hydrogen-containing gases such as ammonia (NH3), hydrazine (N2H4), or hydrogen azide (HN3). In one example, the hydrogen-containing gas includes ammonia (NH3) and the nitrogen-containing gas includes (N2). According to one embodiment, the processing plasma may include a single gas (e.g., hydrazine (N2H4) or ammonia (NH3)) that includes both hydrogen and nitrogen. According to one embodiment, the processing plasma may include an additional neutral carrier gas (e.g., argon (Ar) or helium (He)). In one example, the processing gases included within the processing plasma substantially include ammonia (NH3), nitrogen (N2), and a neutral carrier gas such as argon (Ar) or helium (He). Further, during the single-step plasma hydrogenation and nitridation process of step 1304, a bias can be applied to the substrate by bias power supply 426. The bias power supply 426 is generally capable of generating an RF signal having an adjustable frequency in the range of about 2 MHz to about 160 MHz and a power between about 0 kW and about 10 kW, similar to the RF power supply 414. The bias power improves the conformality of the grown film by rearranging the deposited atoms.

[0135]

[0138] In some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 is carried out at a chamber pressure between about 10 mTorr and about 100 mTorr, a processing temperature (e.g., substrate pedestal temperature) between about 350 °C and about 500 °C, and an RF power between about 300 W and about 2000 W for a period between about 30 seconds and about 150 seconds, with an NH3 flow rate between about 5 sccm and about 100 sccm, an N2 flow rate between about 50 sccm and about 1000 sccm, and a helium (He) flow rate between about 1 and about 1000 sccm, and a frequency between about 2 MHz and about 160 MHz, and a bias power between about 0 kW and about 10 kW is applied.

[0136]

[0139] In some embodiments, the single-step plasma hydrogenation and nitridation process of step 1304 is carried out at a chamber pressure between about 15 mTorr and about 25 mTorr, a processing temperature between about 425 °C and about 475 °C, and an RF power between about 900 W and about 1100 W for a period between about 85 seconds and about 95 seconds, with an NH3 flow rate between about 15 sccm and about 35 sccm, an N2 flow rate between about 450 sccm and about 550 sccm, and an Ar flow rate between about 450 sccm and about 500 sccm, without applying substrate bias power.

[0137]

[0140] In summary, in step 1304, the surface 1401 is exposed to plasma-excited hydrogen and nitrogen species generated by plasma treatment, and some or all of the oxides present on the surface 1401 are converted to nitrides. Thus, in some embodiments, as shown in FIG. 14D, the increase in the thickness of the interface layer 1409 ceases or the increase in thickness is significantly reduced. The interface layer 1409 still remains, but no increase in the layer thickness occurs. The reduction or nitridation of the interface layer 1409 reduces the EOT and changes the work function of the metal gate structure 1000.

[0138]

[0141] In some embodiments, before performing the single-step plasma hydrogenation and nitridation treatment of step 1304, for example, in order to reduce trace oxygen contamination in the processing chamber, an oxygen-free conditioning process is performed in the processing chamber. In such embodiments, the processing chamber is treated with an oxygen-free plasma without the substrate being placed and before the substrate is treated with the above-described single-step plasma hydrogenation and nitridation treatment.

[0139]

[0142] In optional step 1305, the exposed surface 1401 is exposed to air. For example, in some embodiments, the single-step plasma hydrogenation and nitridation treatment of step 1304 is performed in a certain processing system, but the next processing step performed on the semiconductor substrate 1001 is performed in a different processing system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after the deposition of layer 1404. In embodiments where the single-step plasma hydrogenation and nitridation treatment of step 1304 is performed in one chamber of a multi-chamber processing system and step 1306 is performed in another processing chamber of the same multi-chamber processing system, optional step 1305 is not performed.

[0140]

[0143] In embodiments where a sacrificial silicon-containing layer is subsequently deposited and removed as part of the formation of the metal gate structure 1000, method 1300 proceeds from step 1305 to step 1321. In embodiments where a sacrificial silicon layer is not deposited when forming the metal gate structure 1000, method 1300 proceeds to step 1306. The sacrificial silicon-containing layer can be formed by using a CVD or ALD process that uses one or more silicon-containing precursor gases to form a deposited layer.

[0141]

[0144] In step 1306, a thermal annealing process such as post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, and the capping layer 1404. For example, in some embodiments, a spike anneal process is performed in step 1306, reaching a peak temperature of about 600 °C to about 900 °C. The post-cap anneal is performed on the partially formed metal gate structure 1000, smoothing the interface, repairing unsaturated bonds, and injecting thermal energy into the capping layer 1404.

[0142]

[0145] In step 1307, as shown in FIG. 14E, the metal gate electrode layer 1005 is deposited on the processed capping layer 1404, thereby completing the formation of the metal gate structure 1000. The metal gate electrode 1005 can be formed by any suitable deposition method described above in connection with FIG. 10.

[0143]

[0146] In step 1321, as shown in FIG. 14F, the sacrificial silicon layer 1202 is deposited on the capping layer 1404. Step 1321 is performed after the surface 1401 of the capping layer 1404 has been processed by the single-step plasma hydrogenation and nitridation treatment of step 1304 and the optional air exposure of step 1305.

[0144]

[0147] In step 1322, a thermal annealing process such as post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the capping layer 1404, and the sacrificial silicon layer 1202. The thermal annealing process of step 1322 can be substantially similar to the thermal annealing process of step 1306 described above.

[0145]

[0148] In step 1323, the sacrificial silicon layer 1202 is removed from the metal gate structure 1000. Any technically feasible removal process can be utilized in step 1323, including selective wet etching processes, plasma-based dry etching processes, chemical mechanical polishing processes, or any combination thereof. Next, method 1300 proceeds to step 1307. In step 1307, the final layer of the metal gate structure 1000 is deposited.

[0146]

[0149] In step 1331, as shown in FIG. 14G, the sacrificial silicon layer 1203 is deposited on the capping layer 1404. The sacrificial silicon layer 1203 may be substantially similar to the sacrificial silicon layer 1202 deposited in step 1331. However, it should be noted that in step 1331, the capping layer 1404 has not been treated by a single-step plasma hydrogenation and nitridation process. As a result, the capping layer 1404 may still include the interface layer 1409 as shown.

[0147]

[0150] In step 1332, a thermal annealing process such as a post-cap anneal is performed on the semiconductor substrate 1001, the interface layer 1002, the high-k dielectric layer 1003, the capping layer 1404, the interface layer 1409, and the sacrificial silicon layer 1203. The thermal annealing process of step 1332 may be substantially similar to the thermal annealing process of step 1306 described above.

[0148]

[0151] In step 1333, as shown in FIG. 14H, the sacrificial silicon layer 1203, the capping layer 1404, and the interface layer 1409 are removed from the metal gate structure 1000. Any technically feasible removal process or combination of processes can be used in step 1333, including selective wet etching processes, plasma-based dry etching processes, chemical mechanical polishing processes, or any combination thereof. Next, method 1300 proceeds to step 1334.

[0149]

[0152] In step 1334, as shown in FIG. 14I, a final capping layer 1404f is deposited on the high-k dielectric layer 1003. The final capping layer 1404f may be composed of the same material as the capping layer 1404, and the final capping layer may further include an interface layer 1409.

[0150]

[0153] In optional step 1335, the exposed surface 1405 shown in FIG. 14I is exposed to air. For example, in some embodiments, the final capping layer 1404f is deposited in a certain processing system, but the next processing step to be performed on the semiconductor substrate 1001, i.e., step 1336, is performed in a different processing system. Thus, in such embodiments, the semiconductor substrate 1001 is exposed to air after the deposition of the final capping layer 1404f. In embodiments where the final capping layer 1404f is deposited in one chamber of a multi-chamber processing system and step 1336 is performed in another one or two processing chambers of the same multi-chamber processing system, the optional step 1335 is not performed.

[0151]

[0154] In step 1336, as shown in FIG. 14J, a single-step plasma hydrogenation and nitridation treatment is performed on the surface 1405 of the final capping layer 1404. The single-step plasma hydrogenation and nitridation treatment performed in step 1336 may be substantially similar to the treatment utilized in step 1304. As a result, the thickness of the interface layer 1409 can be removed or reduced during step 1336, thereby removing O atoms present in the final capping layer 1404f, the interface layer 1009, and in some embodiments, the high-k dielectric layer 1003. As a result, the EOT of the metal gate structure 1000 is reduced without reducing the thickness 1003A of the high-k dielectric layer 1003.

[0152]

[0155] After the single-step plasma hydrogenation and nitridation treatment is performed in step 1336, method 1300 proceeds to step 1307. In step 1307, the final layer of the metal gate structure 1000 is deposited. In embodiments where steps 1336 and 1307 are performed in different processing systems, the semiconductor substrate 1001 is necessarily exposed to air. However, since the plasma nitridation treatment in step 1336 can completely or almost completely nitride the exposed surface 1405 of the final capping layer 1404f, generally little or no oxidation occurs while it is exposed to air.

[0153]

[0156] In the embodiments disclosed herein, either a continuous hydrogenation and nitridation treatment or a single-step hydrogenation and nitridation treatment can be utilized to form a metal gate structure with a reduced EOT compared to similar structures formed by conventional methods. A plasma hydrogenation treatment, followed by a plasma nitridation treatment, is performed on the metal nitride layer within the film stack. In some embodiments, O atoms disposed within the layers of the film stack are removed. In some embodiments, an increase in the thickness of the oxygen-containing interface layer disposed within the film stack is reduced or prevented. In some embodiments, N atoms are added to the layers of the film stack. As a result, the EOT of the metal gate structure decreases with little or no accompanying flat-band voltage shift. Further, the metal gate structure functions with an increase in leakage current that is approximately one-fourth of the increase in leakage current associated with similar metal gate structures formed by the prior art.

[0154]

[0157] The above description is directed to embodiments of the present disclosure, but other and additional embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure. The scope of the present disclosure is determined by the following claims.

Claims

1. 1. A method of forming a structure in a semiconductor device, comprising: depositing a metal nitride layer on a high-k dielectric layer formed on a semiconductor substrate disposed on a substrate support surface of a pedestal disposed in a first processing chamber of a cluster tool to form a portion of the structure; performing a single step plasma hydrogenation and nitridation process by exposing an exposed surface of the deposited metal nitride layer formed on the semiconductor substrate to non-oxidizing plasma excited hydrogen species and plasma excited nitrogen species while a bias is applied to the semiconductor substrate disposed on a substrate support surface of a pedestal disposed in a second process chamber of the cluster tool; The method includes:

2. 10. The method of claim 1, further comprising depositing a metal layer on the exposed surface of the metal nitride layer after exposing the exposed surface to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species.

3. The method of claim 2, wherein the structure comprises a p-metal gate structure and the metal layer comprises a workfunction metal of the p-metal gate structure.

4. 10. The method of claim 1, further comprising forming a silicon dioxide-containing interfacial layer prior to depositing said high-k dielectric layer, said high-k dielectric layer being subsequently formed on said silicon dioxide-containing interfacial layer.

5. The method of claim 1 , wherein the exposed surface is not exposed to air after being exposed to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species.

6. depositing a silicon-containing layer on the exposed surface; subjecting the silicon-containing layer to a thermal annealing treatment; removing the silicon-containing layer; The method of claim 1 further comprising:

7. prior to depositing the metal nitride layer on the high-k dielectric layer; depositing a sacrificial metal nitride layer over the high-k dielectric layer; depositing a silicon-containing layer on the sacrificial metal nitride layer; subjecting the sacrificial metal nitride layer and the silicon-containing layer to a thermal annealing process; removing the sacrificial metal nitride layer and the silicon-containing layer; The method of claim 1 further comprising:

8. 10. The method of claim 1, further comprising exposing a surface of a processing chamber to an oxygen-free plasma prior to exposing the exposed surface to the non-oxidizing plasma-excited hydrogen species and the plasma-excited nitrogen species.

9. The method of claim 8 , wherein the oxygen-free plasma is formed in the processing chamber when the semiconductor substrate is not located in the processing chamber.

10. 10. The method of claim 1, further comprising exposing the exposed surface to air after exposing the exposed surface to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species.

11. 1. A method of forming a structure in a semiconductor device, comprising: depositing a high-k dielectric layer on a semiconductor substrate disposed on the pedestal; depositing a metal nitride layer on the high-k dielectric layer; performing a single step plasma hydrogenation and nitridation process by exposing an exposed surface of the metal nitride layer to non-oxidizing plasma excited hydrogen species and plasma excited nitrogen species while a bias is applied to the pedestal; exposing the exposed surface to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species, and thereafter exposing the exposed surface to air; annealing the high-k dielectric layer and the metal nitride layer after exposing the exposed surfaces to air. The method includes:

12. 12. The method of claim 11, further comprising depositing a metal layer on the exposed surface of the metal nitride layer after annealing the high-k dielectric layer and the metal nitride layer.

13. The non-oxidizing plasma excited hydrogen species is hydrogen gas (H ２ 12. The method of claim 11 , wherein the process gas comprises:

14. The method of claim 11 , wherein the metal nitride layer has a thickness that is less than a diffusion length of oxygen in the metal nitride layer when the metal nitride layer undergoes the anneal.

15. 1. A method of forming a structure in a semiconductor device, comprising: depositing a high-k dielectric layer over a semiconductor substrate; depositing a metal nitride layer on the high-k dielectric layer to form part of the structure while a bias is applied to a pedestal of a process chamber on which the semiconductor substrate rests; reducing the first effective oxide thickness to a second effective oxide thickness by performing a single step plasma hydrogenation and nitridation process by exposing the exposed surface of the deposited metal nitride layer to non-oxidizing plasma excited hydrogen species and plasma excited nitrogen species; The method includes:

16. 16. The method of claim 15, wherein the exposed surface is not exposed to air after being exposed to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species.

17. The non-oxidizing plasma excited hydrogen species is hydrogen gas (H ２ 16. The method of claim 15, wherein the process gas comprises:

18. The plasma excited nitrogen species is nitrogen gas (N ２ ) and ammonia (NH ３ 20. The method of claim 17, wherein the process gas comprises:

19. 14. The method of claim 13, further comprising performing an oxygen-free plasma treatment process in a process chamber in which the exposed surface is exposed to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species prior to exposing the exposed surface to the non-oxidizing plasma excited hydrogen species and the plasma excited nitrogen species.

20. 20. The method of claim 19, wherein the oxygen-free plasma treatment process is performed in the processing chamber when the semiconductor substrate is not located within the processing chamber.

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