Sensor device

Abstract

To provide a sensor device equipped with an AD converter, configured so that AD conversion timing may be synchronized with a reference time.SOLUTION: A sensor device includes: a frequency oscillator which generates clock signals of a predetermined frequency; an AD converter which converts analog signals of a physical quantity of a target, measured by a physical quantity sensor, into digital signals based on the clock signals; and a phase detector which detects a difference of time between a timing at which the AD converter converts the analog signals into the digital signals and a predetermined reference time.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a sensor device.

Background Art

[0002] Patent Document 1 describes that "the DLL circuit 41 delays the system clock signal CK by the variable delay circuits 421 to 42n of n stages, and phase-aligns the delayed clock signal CK' and the system clock signal CK" (abstract). Patent Document 2 describes that "in this system, since it may be necessary to compare the measurement data of each sensor based on time during analysis, time synchronization of each sensor is required" (paragraph 0002). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 9-178407 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-96651

Summary of the Invention

Problems to be Solved by the Invention

[0003] In a sensor device including an AD converter, it is desirable that the timing of AD conversion is synchronized with a reference time.

Means for Solving the Problems

[0004] In a first aspect of the present invention, a sensor device is provided. The sensor device includes a frequency oscillator that generates a clock signal having a predetermined frequency, an AD converter that converts an analog signal of a physical quantity of an object measured by a physical quantity sensor into a digital signal based on the clock signal, and a phase detector that detects a time difference between the timing at which the AD converter converts the analog signal into a digital signal and a predetermined reference time.

[0005] The sensor device may further include a detection unit that detects the end of conversion of an analog signal into a digital signal by an AD converter. The phase detector may detect the time difference between the timing of the end of conversion detected by the detection unit and a reference time.

[0006] The reference time may be an internal time based on a clock signal.

[0007] The reference time may be an external time based on the time distributed by a time server.

[0008] The AD converter may reset the timing for converting the analog signal into a digital signal based on the time difference.

[0009] When the time difference exceeds a predetermined first threshold time difference, the AD converter may reset the timing for converting the analog signal into a digital signal.

[0010] The physical quantities in a plurality of different directions in the object may be respectively measured by physical quantity sensors. Each of the plurality of AD converters may convert each of the analog signals of the plurality of physical quantities into a digital signal based on a clock signal. The phase detector may respectively detect the time difference between each timing at which each of the plurality of AD converters converts each of the analog signals of the plurality of physical quantities into a digital signal and the reference time.

[0011] When at least one of the plurality of time differences detected by the phase detector exceeds the first threshold time difference, all of the plurality of AD converters may reset the timing for converting the analog signal into a digital signal.

[0012] The sensor device may further include a frequency control unit that controls the frequency of the clock signal based on the time difference.

[0013] The frequency control unit may control the frequency of the clock signal based on the sum of the period of the reference time and the time difference.

[0014] When the time difference exceeds a predetermined second threshold time difference, the frequency control unit may control the frequency of the clock signal.

[0015] Each of a plurality of different physical quantities in different directions of the object may be measured by a physical quantity sensor. Each of a plurality of AD converters may convert each of the analog signals of the plurality of physical quantities into a digital signal based on the clock signal. The phase detector may detect the time difference between the timing at which each of the plurality of AD converters converts each of the analog signals of the plurality of physical quantities into a digital signal and the reference time, respectively.

[0016] When all of the plurality of time differences detected by the phase detector exceed the second threshold time difference, the frequency control unit may control the frequency of the clock signal.

[0017] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0018]

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[0019] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

[0020] FIG. 1 is a diagram showing an example of a sensor system 200 according to an embodiment of the present invention. The sensor system 200 includes a sensor device 100 and a host computer 110. The sensor device 100 measures a physical quantity of the object 210. The physical quantity of the object 210 is, for example, the vibration of the object 210. In this example, the object 210 is a desk. The object 210 may be a floor of a building. The host computer 110 collects and analyzes the physical quantity data of the object 210 measured by the sensor device 100. The sensor system 200 may include a plurality of sensor devices 100.

[0021] The sensor system 200 may include a power supply hub 130 and a cable 132. The power supply hub 130 is an interface that communicates with the sensor device 100 and supplies power to the sensor device 100. The power supply hub 130 may be a so-called PoE (Power over Ethernet (registered trademark)). The power supply hub 130 and the sensor device 100 may be connected by a cable 132. The cable 132 is, for example, a LAN cable.

[0022] The sensor system 200 may include a time server 140. The time server 140 is a server that distributes a time adjusted to be synchronized with Coordinated Universal Time. The time adjusted to be synchronized with Coordinated Universal Time is, for example, atomic clock time. The time server 140 may be a so-called NTP server.

[0023] FIG. 2 is a diagram showing an example of a block diagram of a sensor device 100 according to one embodiment of the present invention. The sensor device 100 includes a physical quantity sensor 10, a frequency oscillator 20, and a control unit 30. The physical quantity sensor 10 measures the physical quantity of the object 210 (see FIG. 1). The physical quantity of the object 210 measured by the physical quantity sensor 10 is an analog signal.

[0024] The physical quantity sensor 10 may be an acceleration sensor or a pressure sensor. The acceleration sensor may be a so-called MEMS (Micro Electro Mechanical Systems) acceleration sensor. The physical quantity sensor 10 may be a capacitive MEMS acceleration sensor. The capacitive MEMS acceleration sensor has a fixed electrode and a movable electrode. The movable electrode is displaced by acceleration. The capacitive MEMS acceleration sensor measures the change in capacitance between the fixed electrode and the movable electrode due to the displacement of the movable electrode. The capacitive MEMS acceleration sensor measures the acceleration by measuring the change in capacitance.

[0025] The physical quantity sensor 10 may measure the physical quantities in a plurality of different directions in the object 210 (see FIG. 1). The plurality of different directions in the object 210 may be the X-axis direction component, the Y-axis direction component, and the Z-axis direction component of the physical quantity measured by the physical quantity sensor 10. The Z-axis direction may be the vertical direction. The X-axis direction may be a predetermined direction in the XY plane orthogonal to the Z-axis direction. The Y-axis direction may be a direction orthogonal to the X-axis direction in the XY plane.

[0026] The frequency oscillator 20 generates a clock signal with a predetermined frequency f. Let the clock signal be the clock signal CK. The frequency oscillator 20 may generate a clock signal CK with a frequency f according to a control voltage. A voltage may be supplied to the frequency oscillator 20 by the power supply hub 130. The control unit 30 controls the signal processing in the sensor device 100. The control unit 30 may be a so-called CPU (Central Processing Unit).

[0027] The sensor device 100 may include an analog signal processing unit 50. When the physical quantity sensor 10 is a capacitance-type MEMS acceleration sensor, the analog signal processing unit 50 converts the change in capacitance between the fixed electrode and the movable electrode measured by the physical quantity sensor 10 into a voltage signal.

[0028] The sensor device 100 may include a plurality of analog signal processing units 50. In this example, the sensor device 100 includes three analog signal processing units 50 (analog signal processing unit 50-1 to analog signal processing unit 50-3). The analog signal processing units 50-1 to 50-3 may respectively process the analog signals of the X-axis direction component, Y-axis direction component, and Z-axis direction component of the physical quantity measured by the physical quantity sensor 10.

[0029] The sensor device 100 may include an LPF (low-pass filter) 52. The LPF 52 removes high-frequency components in the voltage signal output from the analog signal processing unit 50. The sensor device 100 may include a plurality of LPFs 52. In this example, the sensor device 100 includes three LPFs 52 (LPF 52-1 to LPF 52-3). In this example, the LPFs 52-1 to 52-3 respectively remove high-frequency components in the voltage signals output from the analog signal processing units 50-1 to 50-3.

[0030] The sensor device 100 includes an AD converter 54. The AD converter 54 converts an analog signal of the physical quantity of the object 210 measured by the physical quantity sensor 10 into a digital signal based on the clock signal CK. In this example, the AD converter 54 converts an analog voltage signal from which high-frequency components have been removed by the LPF 52 into a digital signal based on the clock signal CK.

[0031] The sensor device 100 may include a plurality of AD converters 54. Each of the plurality of AD converters 54 may convert each of the analog signals of the plurality of physical quantities measured by the physical quantity sensor 10 into a digital signal based on the clock signal. In this example, the sensor device 100 includes three AD converters 54 (AD converter 54-1 to AD converter 54-3). In this example, the AD converters 54-1 to 54-3 each convert an analog voltage signal from which high-frequency components have been removed by the LPFs 52-1 to 52-3 into a digital signal based on the clock signal CK.

[0032] The control unit 30 may transmit an AD conversion start signal (described later) for causing the AD converter 54 to start analog-digital conversion. The AD conversion start signal may be generated based on a reference time ts (described later). The AD converter 54 may start analog-digital conversion at the timing when it receives the AD conversion start signal.

[0033] The sensor device 100 may include a DA converter 56. The DA converter 56 converts the digital signal output from the control unit 30 into an analog signal. The digital signal output from the control unit 30 is, for example, an adjustment value (described later) for adjusting the frequency f of the clock signal CK. The DA converter 56 may generate a control signal obtained by converting the adjustment value into an analog signal. The DA converter 56 may output the control signal to the frequency oscillator 20.

[0034] The sensor device 100 may include an interface unit 58 and a storage unit 70. The interface unit 58 may receive power supplied by the power supply hub 130. The interface unit 58 may mediate communication between the power supply hub 130 and the control unit 30. The storage unit 70 will be described later.

[0035] FIG. 3 is a diagram showing an example of a block diagram related to detection of the end of AD conversion in the AD converter 54 shown in FIG. 2. In FIG. 3, the range of the control unit 30 is shown by a thick dashed line frame.

[0036] The sensor device 100 includes a phase detector 62. The phase detector 62 detects the time difference between the timing at which the AD converter 54 converts an analog signal into a digital signal and a predetermined reference time ts (described later). Thereby, the user of the sensor device 100 can recognize the time difference between the timing of AD conversion by the AD converter 54 and the reference time ts (described later). The phase detector 62 may detect the time difference between the respective timings at which each of the plurality of AD converters 54 converts each of the analog signals of the plurality of physical quantities into digital signals and the reference time ts (described later).

[0037] In this example, the control unit 30 includes an internal time setting unit 32, an NTP client 34, an external time acquisition unit 35, and a frequency divider 36. The frequency divider 36 divides the voltage signal oscillated by the frequency oscillator 20 so that the voltage signal becomes a voltage signal having a predetermined frequency f.

[0038] The internal time setting unit 32 sets an internal time based on the clock signal CK. The internal time based on the clock signal CK is the time generated inside the sensor device 100 based on the clock signal CK. Let the internal time based on the clock signal CK be the internal time ti. In this example, the internal time setting unit 32 sets the time when the physical quantity sensor 10 measures the physical quantity of the object 210 (see FIG. 1). In this example, the above-described reference time ts is the internal time ti.

[0039] The NTP client 34 sets an external time based on the time distributed by the time server 140. The time distributed by the time server 140 is, for example, the atomic clock time. The NTP client 34 may set the external time in the sensor device 100 by querying the time server 140 for the atomic clock time. Let the external time be the external time to. The NTP client 34 may synchronize the external time to with the atomic clock time. The external time acquisition unit 35 acquires the external time to from the NTP client 34.

[0040] The sensor device 100 may further include a detection unit 60. The detection unit 60 detects the completion of the conversion (AD conversion) of the analog signal into a digital signal by the AD converter 54. The sensor device 100 may include a plurality of detection units 60. In this example, the sensor device 100 includes three detection units (detection unit 60-1 to detection unit 60-3). Each of the detection units 60-1 to 60-3 detects the completion of the AD conversion by each of the AD converters 54-1 to 54-3.

[0041] The AD converter 54 may output a signal indicating the completion of the AD conversion. Let the signal be the Ready signal. The detection unit 60 may detect the completion of the AD conversion by detecting the Ready signal.

[0042] The sensor device 100 may further include a frequency control unit 22. The frequency control unit 22 controls the frequency of the clock signal CK. The frequency control unit 22 may control the frequency f of the clock signal CK by controlling the control voltage of the frequency oscillator 20.

[0043] In this example, the control unit 30 has a phase detector 33. The phase detector 33 detects the time difference between the internal time ti and the external time to. The phase detector 33 detects the phase difference between the phase of the voltage signal divided by the frequency divider 36 and the phase of the waveform of the external time to synchronized with the atomic clock time. The phase detector 33 detects the time difference between the internal time ti and the external time to by detecting the phase difference.

[0044] The phase detector 62 detects the phase difference between the phase of the voltage signal divided by the frequency divider 36 and the phase of the waveform of the digitized signal detected by the detection unit 60 and then AD-converted. By detecting the said phase difference, the phase detector 62 detects the time difference between the timing of the end of the AD conversion detected by the detection unit 60 and the reference time ts (in this example, the internal time ti).

[0045] The control unit 30 may further include a data management unit 37. The data management unit 37 manages the components of the physical quantity of the object 210 detected by the physical quantity sensor 10, which are the components of the physical quantity in a plurality of mutually orthogonal directions. The plurality of mutually orthogonal directions may be, for example, the components of the physical quantity in two axial directions orthogonal to each other in the horizontal plane and in the vertical direction, respectively. The data management unit 37 may further manage at least one of the internal time ti and the external time to.

[0046] The control unit 30 may further include an interface unit 58. The interface unit 58 may mediate communication between the power supply hub 130 and the data management unit 37. The data management unit 37 may transmit the physical quantity data converted into a digital signal by the AD converter 54 to the host computer 110. When the data management unit 37 manages the components of the physical quantity in a plurality of mutually orthogonal directions, the data management unit 37 may transmit the physical quantity data to the host computer 110 after the components of the plurality of physical quantities are aligned.

[0047] FIG. 4 is a diagram showing another example of a block diagram related to the end detection of AD conversion in the AD converter 54 shown in FIG. 2. In this example, the reference time ts is the external time to. The phase detector 62 detects the time difference between the timing of the end of the AD conversion detected by the detection unit 60 and the reference time ts (in this example, the external time to). In this example, the external time acquisition unit 35 outputs an AD conversion start signal to the AD converter 54. The sensor device 100 in this example is different from the sensor device 100 shown in FIG. 3 in this regard.

[0048] FIG. 5 is a diagram showing an example of a clock signal CK and a timing chart of the clock signal to the AD converter 54. Let the clock signal to the AD converter 54 be a clock signal CK'. The clock signal CK' is the clock signal input to the AD converter 54.

[0049] The times t0 to tn in FIG. 5 are a reference time ts. The times t0 to tn may be an internal time ti or an external time to. Let the period of the reference time ts be a period T. When the times t0 to tn are the internal time ti, the period T is the time over a predetermined number of periods of the clock signal CK detected by the phase detector 33 (see FIGS. 3 and 4). The number of periods is, for example, 1000 periods. The period T is, for example, 10 ms.

[0050] Let the clock signals to the AD converters 54-1 to 54-3 be clock signals CK'1 to CK'3, respectively. As described above, the AD converters 54-1 to 54-3 convert analog signals of physical quantities in the X-axis direction, Y-axis direction, and Z-axis direction into digital signals, for example. In this example, the AD converters 54-1 to 54-3 convert analog signals into digital signals based on the clock signals CK'1 to CK'3, respectively.

[0051] In this example, it is assumed that the AD converter 54 outputs a Ready signal indicating the end of the AD conversion. Let the Ready signal be a signal Re. Let the Ready signals output from the AD converters 54-1 to 54-3 be signals Re1 to Re3, respectively. In FIG. 5, the signals Re1 to Re3 are shown by thick solid lines.

[0052] The distance of the transmission path that transmits the clock signal CK from the frequency oscillator 20 (see FIGS. 3 and 4) to the divider 36 (see FIGS. 3 and 4) may be different from the distance of the transmission path that transmits the clock signal CK to the AD converter 54. Let the transmission path between the frequency oscillator 20 and the divider 36 be the transmission path P1. Let the distance of the transmission path P1 be the distance D1. Let the transmission path between the frequency oscillator 20 and the AD converter 54 be the transmission path P2. Let the distance of the transmission path P2 be the distance D2.

[0053] Current noise or voltage noise generated inside the sensor device 100 or applied from outside the sensor device may propagate through the transmission paths P1 and P2. When the power supply hub 130 and the sensor device 100 are connected by the cable 132 (see FIG. 1), the noise superimposed on the cable 132 may propagate through the transmission paths P1 and P2. When the noise propagates through the transmission paths P1 and P2, noise based on the noise may be superimposed on the clock signal CK.

[0054] When no noise is superimposed on the transmission paths P1 and P2, the clock signal CK and the clock signal CK' are likely to be synchronized. Therefore, when no noise is superimposed on the transmission paths P1 and P2, the time (cycle T) over a predetermined number of cycles of the clock signal CK detected by the phase detector 33 and the time over the same number of cycles of the clock signal CK' detected by the phase detector 62 are likely to match. Therefore, the signal Re is likely to be synchronized with the reference time ts (in this example, time t0 to time n).

[0055] However, when noise is superimposed on the transmission paths P1 and P2, the clock signal CK and the clock signal CK' may not be synchronized. Therefore, when noise is superimposed on the transmission paths P1 and P2, the time (cycle T) over a predetermined number of cycles of the clock signal CK detected by the phase detector 33 and the time over the same number of cycles of the clock signal CK' detected by the phase detector 62 may not match. Let the time over the same number of cycles of the clock signal CK' be the cycle T'.

[0056] When the clock signal CK and the clock signal CK' are not synchronized, it becomes difficult for the signal Re to be synchronized with the reference time ts (in this example, the time t0 to the time tn). When the signal Re is not synchronized with the reference time ts, the AD converter 54 is likely to output the signal Re at a timing different from the reference time ts. Therefore, the detection unit 60 (FIGS. 3 and 4) is likely to detect the timing of the end of the AD conversion by the AD converter 54 at an incorrect timing. In this example, the clock signal CK'1 and the clock signal CK'2 are synchronized with the clock signal CK. In this example, the clock signal CK'3 is not synchronized with the clock signal CK after time 1.

[0057] When the AD converter 54 is arranged near the physical quantity sensor 10, the distance D2 may be longer than the distance D1. When the distance D2 is longer than the distance D1, the noise superimposed on the transmission path P2 is more likely to be larger than the noise superimposed on the transmission path P1. Therefore, the period T' is likely to be shorter than the period T. Therefore, the detection unit 60 (FIGS. 3 and 4) is likely to detect the timing of the end of the AD conversion by the AD converter 54 at an earlier timing compared to the case where the distance D2 and the distance D1 are equal. The example in FIG. 5 is an example in which the detection unit 60-3 detects the timing of the end of the AD conversion by the AD converter 54-3 at an incorrect timing (earlier timing).

[0058] Conversely, when the distance D2 is shorter than the distance D1, the noise superimposed on the transmission path P2 is more likely to be smaller than the noise superimposed on the transmission path P1. Therefore, the period T' is likely to be longer than the period T. Therefore, the detection unit 60 (FIGS. 3 and 4) is likely to detect the timing of the end of the AD conversion by the AD converter 54 at a later timing compared to the case where the distance D2 and the distance D1 are equal.

[0059] The phase detector 62 (see FIGS. 3 and 4) may detect the time difference between the timing of the end of the AD conversion detected by the detection unit 60 and the reference time ts. Let the time difference between the time tn (n≥0) and the signal Re3 be the time difference Δtz. In this example, the phase detector 62 detects the time difference Δtz by detecting the period T'. In this example, the signal Re3 is output at a timing earlier than the time difference Δtz from the time tn (n≥0).

[0060] The longer the time during which noise is superimposed on the transmission line P2, the more likely the time difference Δtz is to increase. FIG. 5 is an example of a case where the time difference Δtz increases with the passage of time during four consecutive periods T.

[0061] Let the time difference Δtz between the time t0 and the time t1 be Δtz1, and the period T' be the period T'1. Let the time difference Δtz between the time t1 and the time t2 be Δtz2, and the period T' be the period T'2. Let the time difference Δtz between the time t2 and the time t3 be Δtz3, and the period T' be the period T'3. Let the time difference Δtz between the time t3 and the time t4 be Δtz4, and the period T' be the period T'4.

[0062] In this example, the time difference Δtz2 is larger than the time difference Δtz1, the time difference Δtz3 is larger than the time difference Δtz2, and the time difference Δtz4 is larger than the time difference Δtz3. In this example, the period T'2 is smaller than the period T'1, the period T'3 is smaller than the period T'3, and the period T'4 is smaller than the period T'3.

[0063] FIG. 6 is a diagram showing an example of a timing chart of the clock signal CK and the clock signal to the AD converter 54. The AD converter 54 may reset the timing for converting the analog signal into a digital signal based on the time difference Δt. In this example, the AD converter 54 resets the timing for converting the analog signal into a digital signal at a predetermined time in the next period from the time tn to the time tn+1 (that is, from the time tn+1 to the time t-1). In FIG. 5, the predetermined time is shown as the time trs.

[0064] When the reference time ts is the internal time ti (the case of FIG. 3), the internal time setting unit 32 (see FIG. 3) may output an AD conversion start signal to the AD converter 54. When the reference time ts is the external time to (the case of FIG. 4), the external time acquisition unit 35 (see FIG. 4) may output an AD conversion start signal to the AD converter 54. The AD converter 54 may reset the timing for converting the analog signal into a digital signal at the timing when the AD conversion start signal is input. In this example, the AD converter 54 resets the AD conversion at the time trs. For this reason, in this example, the AD converter 54 does not output the signal Re at the time t-1 and starts outputting the signal Re again from the time t.

[0065] When the time difference Δt exceeds a predetermined first threshold time difference, the AD converter 54 may reset the timing for converting the analog signal into a digital signal. Let the first threshold time difference be the threshold time difference Δts1. The threshold time difference Δts1 may be stored in the storage unit 70 (see FIG. 2). As shown in FIG. 5, the time difference Δtz tends to increase with the passage of time. In the example shown in FIG. 5, when the time difference Δtz exceeds the threshold time difference Δts1, the AD converter 54 may reset the AD conversion timing.

[0066] The threshold time difference Δts1 may be equal to or greater than 0.05 times and equal to or less than 0.2 times the period T. Δts1 is, for example, 0.1 times the period T. When the time difference Δt is equal to or less than the threshold time difference Δts1, the AD converter 54 does not have to reset the AD conversion timing.

[0067] When at least one of a plurality of time differences Δt detected by a phase detector 62 (see FIGS. 3 and 4) exceeds a threshold time difference Δts1, all of the plurality of AD converters 54 may reset the timing for converting an analog signal into a digital signal. In this example, the time difference Δt between the time tn+1 and the signal Re3 exceeds the threshold time difference Δts1, and the signal Re1 and the signal Re2 are synchronized with the clock signal CK'1 and the clock signal CK'2, respectively. However, all of the AD converters 54-1 to 54-3 reset the timing of the AD conversion. As a result, it becomes easier to suppress the detection unit 60 from detecting the timing of the end of the AD conversion by the AD converter 54 at an incorrect timing.

[0068] The time t-1 is a reference time ts after the time trs and is the reference time ts closest to the time trs. When the AD converter 54 resets the timing of the AD conversion at the time trs, it is difficult for the AD converter 54 to perform the AD conversion at the time t-1. In this example, the AD converter 54 can perform the AD conversion in synchronization with the reference time ts after the time t. As a result, the sensor device 100 can acquire data in which an analog signal of the physical quantity of the object 210 is converted into a digital signal at a timing synchronized with the clock signal CK.

[0069] When the physical quantity sensor 10 is a MEMS acceleration sensor and a plurality of sensor devices 100 are provided at mutually different heights in the object 210, it is preferable that the timing at which each of the plurality of sensor devices 100 acquires data of the physical quantity of the object 210 is synchronized. The case where a plurality of sensor devices 100 are provided at mutually different heights in the object 210 is, for example, a case where the object 210 is a building and a plurality of sensor devices 100 are provided on different floors in the building. The sensor device 100 can acquire data in which an analog signal of the physical quantity of the object 210 is converted into a digital signal at a timing synchronized with the clock signal CK. Therefore, it becomes easier for the plurality of sensor devices 100 to acquire the data at mutually synchronized timings.

[0070] FIG. 7 is a diagram showing a comparative example of a clock signal CK and a timing chart of the clock signal to the AD converter 54. This example is an example of the clock signal CK and the clock signal CK' when no noise is superimposed on the transmission line P1 and the transmission line P2. As described above, when no noise is superimposed on the transmission line P1 and the transmission line P2, the clock signal CK and the clock signal CK' are likely to be synchronized. Therefore, when no noise is superimposed on the transmission line P1 and the transmission line P2, the time (period T) over a predetermined number of cycles of the clock signal CK detected by the phase detector 33 and the time over the same number of cycles of the clock signal CK' detected by the phase detector 62 are likely to match. For this reason, the signal Re is likely to be synchronized with the reference time ts (in this example, time t0 to time tn).

[0071] FIG. 8 is a diagram showing another example of a timing chart of the clock signal CK and the clock signal to the AD converter 54. In this example, between time t1 and time tn, all of the clock signals CK'1 to CK'3 are not synchronized with the clock signal CK. This example is different from the example shown in FIG. 5 in this regard. When the current noise or voltage noise applied to the transmission line P2 is larger than that in the example shown in FIG. 5, all of the clock signals CK'1 to CK'3 may not be synchronized with the clock signal CK.

[0072] In this example, the magnitude relationship of Δtx1 to Δtx4 is the same as the magnitude relationship of Δtz1 to Δtz4 shown in FIG. 5. In this example, the magnitude relationship of Δty1 to Δty4 is the same as the magnitude relationship of Δtz1 to Δtz4 shown in FIG. 5.

[0073] FIG. 9 is a diagram showing another example of a timing chart of a clock signal CK and a clock signal to the AD converter 54. Signals Re1 to Re3 are originally output in synchronization with time tn+1, but in this example, they are output at a timing that is earlier than time tn+1 by a time difference Δt. When the time difference Δt when signals Re1 to Re3 are output at a timing earlier than the original timing is defined as a negative time difference, and the time difference Δt when they are output at a later timing is defined as a positive time difference.

[0074] The frequency control unit 22 (see FIGS. 3 and 4) may control the frequency f of the clock signal CK based on the time difference Δt. Thereby, the frequency oscillator 20 can oscillate a clock signal CK having a frequency f in which the time difference Δt is reflected.

[0075] The frequency control unit 22 may control the frequency f of the clock signal CK based on the sum of the period T of the reference time ts and the time difference Δt. As described above, the period T is the time over a predetermined number of cycles of the clock signal CK detected by the phase detector 33 (see FIGS. 3 and 4). When the time difference Δt is a negative time difference, the sum of the period T and the time difference Δt becomes shorter than the period T. When the time difference Δt is a positive time difference, the sum of the period T and the time difference Δt becomes longer than the period T.

[0076] The frequency control unit 22 may control the frequency f of the clock signal CK such that the time over a predetermined number of periods of the clock signal CK is equal to the sum of the period T and the time difference Δt. When the time difference Δt is a negative time difference, the frequency control unit 22 may control the frequency f of the clock signal CK to a frequency f higher than the frequency f when the time difference Δt is zero. When the time difference Δt is a positive time difference, the frequency control unit 22 may control the frequency f of the clock signal CK to a frequency f lower than the frequency f when the time difference Δt is zero. In this example, since the time difference Δt is a negative time difference, the frequency control unit 22 controls the frequency f of the clock signal CK to a frequency f higher than the frequency f when the time difference Δt is zero. Thereby, at the next reference time ts (time t - 1) of the time tn+1, the respective clock signals CK'1 to CK'3 of the AD converters 54-1 to 54-3 are more likely to be synchronized with the clock signal CK. Thereby, at the time t - 1, the signals Re1 to Re3 are more likely to be synchronized with the clock signal CK.

[0077] When the time difference Δt exceeds a predetermined second threshold time difference, the frequency control unit 22 may control the frequency f of the clock signal CK. Let the second threshold time difference be the threshold time difference Δts2. The threshold time difference Δts2 may be stored in the storage unit 70 (see FIG. 2). As shown in FIG. 8, the time differences Δtx, Δty, and Δtz are likely to increase with the passage of time. In the example shown in FIG. 8, when at least one of the time differences Δtx, Δty, and Δtz exceeds the threshold time difference Δts1, the frequency control unit 22 may control the frequency f of the clock signal CK.

[0078] The threshold time difference Δts2 may be 0.05 times or more and 0.2 times or less of the period T. Δts2 is, for example, 0.1 times the period T. When the time difference Δt is equal to or less than the threshold time difference Δts2, the frequency control unit 22 does not have to control the frequency f of the clock signal CK.

[0079] When all of the plurality of time differences Δt detected by the phase detector 62 (see FIGS. 3 and 4) exceed the threshold time difference Δts2, the frequency control unit 22 may control the frequency f of the clock signal CK. In this example, the three time differences Δt are of the same magnitude, but the magnitudes of the plurality of time differences Δt may be different from each other. When the magnitudes of the plurality of time differences Δt are different from each other, if the largest time difference Δt exceeds the threshold time difference Δts2, the frequency control unit 22 may control the frequency f of the clock signal CK. In the example shown in FIG. 8, when all of the time difference Δtx, the time difference Δty, and the time difference Δtz exceed the threshold time difference Δts1, the frequency control unit 22 may control the frequency f of the clock signal CK. Thereby, all of the clock signals CK' to the plurality of AD converters 54 are likely to be synchronized with the clock signal CK.

[0080] Note that when all of the clock signals CK'1 to CK'3 are not synchronized with the clock signal CK (in the cases of FIGS. 8 and 9), the AD converter 54 may reset the timing for converting the analog signal into a digital signal based on the time difference Δtx, the time difference Δty, and the time difference Δtz.

[0081] As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements may also be included in the technical scope of the present invention.

[0082] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly stated as "before" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to implement in this order.

Description of Symbols

[0083] 10... Physical quantity sensor, 20... Frequency oscillator, 22... Frequency control unit, 30... Control unit, 32... Internal time setting unit, 33... Phase detector, 34... NTP client, 35... External time acquisition unit, 36... Divider, 37... Data management unit, 50... Analog signal processing unit, 52... LPF, 54... AD converter, 56... DA converter, 58... Interface unit, 60... Detection unit, 62... Phase detector, 70... Memory unit, 100... Sensor device, 110... Host computer, 130... Power supply hub, 132... Cable, 140... Time server, 200... Sensor system, 210... Object

Claims

1. A frequency oscillator that generates a clock signal with a predetermined frequency, a plurality of AD converters that convert each of the analog signals of a plurality of physical quantities of an object measured by a physical quantity sensor into a digital signal based on the clock signal, a phase detector that detects, for each of the plurality of AD converters, the time difference between the timing at which each of the analog signals of the plurality of physical quantities is converted into the digital signal and a predetermined reference time, comprising: when at least one of the plurality of time differences detected by the phase detector exceeds a predetermined first threshold time difference, all of the plurality of AD converters reset the timing at which the analog signal is converted into the digital signal, a sensor device.

2. A frequency oscillator that generates a clock signal with a predetermined frequency, an AD converter that converts an analog signal of a physical quantity of an object measured by a physical quantity sensor into a digital signal based on the clock signal, a phase detector that detects the time difference between the timing at which the AD converter converts the analog signal into the digital signal and a predetermined reference time, a frequency control unit that controls the frequency of the clock signal based on the time difference, comprising: a plurality of the reference times are arranged at a predetermined period on the time axis, the frequency control unit controls the frequency of the clock signal based on the sum of the period and the time difference, a sensor device.

3. The sensor device according to claim 2, wherein the frequency control unit controls the frequency of the clock signal when the time difference exceeds a predetermined second threshold time difference.

4. Each of the physical quantities in a plurality of different directions in the object is measured by the physical quantity sensor, each of the plurality of AD converters converts each of the analog signals of the plurality of physical quantities into the digital signal based on the clock signal, the phase detector detects, for each of the plurality of AD converters, the time difference between the timing at which each of the analog signals of the plurality of physical quantities is converted into the digital signal and the reference time, the sensor device according to claim 3.

5. The sensor device according to claim 4, wherein the frequency control unit controls the frequency of the clock signal when all of the plurality of time differences detected by the phase detector exceed the second threshold time difference.

6. A frequency oscillator that generates a clock signal with a predetermined frequency, A plurality of AD converters that convert each of the analog signals of a plurality of physical quantities of the object measured by the physical quantity sensor into a digital signal based on the clock signal, A phase detector that detects, for each of the plurality of AD converters, the time difference between the timing at which each of the analog signals of the plurality of physical quantities is converted into the digital signal and a predetermined reference time, A frequency control unit that controls the frequency of the clock signal based on the time difference, Comprising, When all of the plurality of time differences detected by the phase detector exceed a predetermined second threshold time difference, the frequency control unit controls the frequency of the clock signal, Sensor device.

7. Further comprising a detection unit that detects the end of the conversion of the analog signal into the digital signal by the AD converter, The phase detector detects the time difference between the timing of the end of the conversion detected by the detection unit and the reference time, The sensor device according to any one of claims 1 to 6.

8. The sensor device according to any one of claims 1 to 7, wherein the reference time is an internal time based on the clock signal.

9. The sensor device according to any one of claims 1 to 7, wherein the reference time is an external time based on the time distributed by a time server.

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