Amplifying device

Abstract

To provide an amplification device that reduces glitch noise.SOLUTION: A Ping-Pong auto zero amplifier 1A comprises one error detection amplifier 2 and two auto zero amplifiers 3a, 3b. The auto zero amplifiers 3a, 3b are alternately switched into an amplification mode and a calibration mode so that one is in the amplification mode when the other is in the calibration mode. In the amplification mode, transconductance amplifiers 31a, 31b amplify an input signal Vin and outputs the input signal as an output signal Vout. By a calibration voltage sampled by sampling capacitors C1a, C2a, C1b, C2b, an offset component and a low-frequency noise component are calibrated from the output signal Vout. In the calibration mode, the calibration voltage is sampled by the sampling capacitors C1a, C2a, C1b, C2b. The error detection amplifier 2 is connected to calibration circuits 32a, 32b of the auto zero amplifiers 3a, 3b when they are in the calibration mode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an amplification device.

Background Art

[0002] Amplifiers are widely used for amplifying sensor signals and the like. However, in some application examples, it is required that the offset component and the low-frequency noise component inside the amplifier be very small. In conventional amplifiers, since the offset component and the low-frequency noise component cannot meet the requirement, there are many techniques for reducing the offset component and the low-frequency noise component.

[0003] As a technique for reducing the offset component and the low-frequency noise component, an auto-zero amplifier is known (Patent Document 1, Non-Patent Document 1). The auto-zero amplifier is a technique for reducing the offset component and the low-frequency noise component of the amplifier by a built-in calibration circuit. Generally, the auto-zero amplifier alternately operates in a calibration mode and an amplification mode. In the calibration mode, the amplifier built in the auto-zero amplifier has its inverting input and non-inverting input short-circuited, and the output is connected to a sampling capacitor. Thereby, a calibration voltage for reducing the offset component and the low-frequency noise component is sampled in the sampling capacitor. In the amplification mode, an input signal is input to the amplifier built in the auto-zero amplifier, and the amplifier outputs an output signal obtained by amplifying the input signal. Also, in the amplification mode, the offset component and the low-frequency noise component included in the output signal are reduced by the sampled calibration voltage.

[0004] Therefore, with only one auto-zero amplifier, the input signal cannot be amplified in the calibration mode. Thus, a Ping-Pong auto-zero amplifier is adopted, in which two auto-zero amplifiers are prepared, and when one auto-zero amplifier is in the calibration mode, the other is in the amplification mode to amplify the input signal.

[0005] In this auto-zero amplifier, an error detection amplifier may be provided to amplify the output of the amplifier with the inverting input and the non-inverting input short-circuited and sample it on a sampling capacitor. By providing the error detection amplifier, the input offset voltage of the auto-zero amplifier can be further reduced. Conventionally, an error detection amplifier is provided for each of the two auto-zero amplifiers. However, since each error detection amplifier has an offset component, the input offset voltage fluctuates every time the auto-zero amplifier switches. There has been a problem that glitch noise is generated due to this fluctuation of the input offset voltage.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] The present invention has been made in view of the above circumstances, and an object thereof is to provide an amplification device that reduces glitch noise.

Means for Solving the Problems

[0009] In order to achieve the above object, the amplification device according to the present invention is characterized by the following [1] to [6]. [1] an amplifier, a calibration circuit including a sampling capacitor, an amplification device comprising a plurality of auto-zero amplifiers having a calibration mode for sampling a calibration voltage for calibrating an offset component and a low-frequency noise component of the amplifier into the sampling capacitor, and a switching switch for switching between the calibration mode and an amplification mode for amplifying an input signal by the amplifier with the offset component and the low-frequency noise component reduced by the calibration voltage to output an output signal, amplifying and outputting the input voltage One comprising an error detection amplifier, the switching switch, a first switch connecting the output of the amplifier and the input of the error detection amplifier, and a second switch connecting the input of the calibration circuit and the output of the error detection amplifier, and the voltage applied to the input of the calibration circuit is the voltage sampled in the sampling capacitor as the calibration voltage which is an amplification device. [2] In the amplification device according to [1], further comprising a control unit for controlling the switching switch, the control unit controls the switching switch such that the auto-zero amplifier alternately switches between the calibration mode and the amplification mode, and at least one of the plurality of auto-zero amplifiers operates in the amplification mode, and the other one one controls the switching switch such that the auto-zero amplifier operates in the calibration mode, which is an amplification device. [3] In the amplification device according to [1], three auto-zero amplifiers are provided, each of the three auto-zero amplifiers has a first input path and a second input path to which the input signal is respectively input, and a first output path and a second output path from which the output signal is respectively output, The switching switch has a path switching switch that switches between a first path mode in which the amplifier is connected to the first input path and the first output path and a second path mode in which the amplifier is connected to the second input path and the second output path in the amplification mode. It is an amplification device. [4] In the amplification device according to [3], It includes a control unit that controls the switching switch. The control unit controls the switching switch so that the auto-zero amplifier alternately switches between the calibration mode and the amplification mode, and controls the switching switch so that one of the three auto-zero amplifiers operates in the calibration mode and the remaining auto-zero amplifiers operate in the first path mode or the second path mode. It is an amplification device. [5] In the amplification device according to [2] or [4], The control unit controls the first switch and the second switch of the auto-zero amplifier to be turned off before switching from the calibration mode to the amplification mode. It is an amplification device. [6] In the amplification device according to any one of [1] to [5], The second switch has two third switches connected in series between one of the inputs of the calibration circuit and one of the outputs of the error detection amplifier, a fourth switch connecting the connection point of the two third switches and a predetermined voltage, two fifth switches connected in series between the other of the inputs of the calibration circuit and the other of the outputs of the error detection amplifier, and a sixth switch connecting the connection point of the two fifth switches and the predetermined voltage. It is an amplification device.

Advantages of the Invention

[0010] According to the present invention, an amplification device with reduced glitch noise can be provided.

[0011] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the attached drawings.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0013] Specific embodiments of the present invention will be described below with reference to the respective figures.

[0014] (First Embodiment) First, the first embodiment will be described. FIG. 1 is a diagram showing the configuration of a Ping-Pong auto-zero amplifier 1A as an amplifier device according to the first embodiment. The Ping-Pong auto-zero amplifier 1A includes one error detection amplifier 2 and two auto-zero amplifiers 3a and 3b. The Ping-Pong auto-zero amplifier 1A inverts and amplifies an input signal Vin supplied to the input terminal and outputs it as an output signal Vout from the output terminal.

[0015] The two auto-zero amplifiers 3a and 3b include inputs and outputs connected to the input and output terminals of the Ping-Pong auto-zero amplifier 1A, an error detection path connected to the input of the error detection amplifier 2, and an error feedback path connected to the output of the error detection amplifier 2.

[0016] Next, the details of the above-described error detection amplifier 2 and auto-zero amplifiers 3a and 3b will be described below with reference to FIGS. 2 and 3. First, the auto-zero amplifier 3a will be described. As shown in FIGS. 2 and 3, the auto-zero amplifier 3a includes a transconductance amplifier 31a as an amplifier, a calibration circuit 32a, switches S1a, S2a, S31a, and S32a as switching switches, switches S41a and S42a as a first switch, and switches S51a and S52a as a second switch. The transconductance amplifier 31a inverts and amplifies an input signal Vin supplied to the input and outputs it as an output signal Vout from the output.

[0017] Switch S1a is connected between the inverting input of the mutual conductance amplifier 31a and the input terminal. Switch S2a is connected between the inverting input and the non-inverting input of the mutual conductance amplifier 31a. Switches S31a and S32a are connected between the output of the mutual conductance amplifier 31a and the output terminal. Switches S41a and S42a are connected between the output of the mutual conductance amplifier 31a and the error detection path (i.e., the input of the error detection amplifier 2). Switches S51a and S52a are connected between the error feedback path (i.e., the output of the error detection amplifier 2) and the sampling capacitors C1a and C2a (i.e., the input of the calibration circuit 32a) described later.

[0018] The calibration circuit 32a is a circuit that reduces the offset component and low-frequency noise component of the mutual conductance amplifier 31a included in the output signal Vout. The calibration circuit 32a includes sampling capacitors C1a and C2a and a mutual conductance amplifier 33a.

[0019] One ends of the sampling capacitors C1a and C2a are connected to the ground, and the other ends are connected to switches S51a and S52a. The connection points of switches S51a and S52a and the sampling capacitors C1a and C2a are connected to the input of the mutual conductance amplifier 33a.

[0020] The mutual conductance amplifier 33a inverts and amplifies the input and outputs it. The positive output of the mutual conductance amplifier 33a is connected to the positive output of the mutual conductance amplifier 31a, and the negative output is connected to the negative output of the mutual conductance amplifier 31a.

[0021] Next, the auto-zero amplifier 3b will be described. The auto-zero amplifier 3b has substantially the same configuration as the auto-zero amplifier 3a, and can be described by replacing "a" with "b" in the description of the auto-zero amplifier 3a. Therefore, only the differences from the auto-zero amplifier 3a will be described here, and the detailed description will be omitted. The difference from the auto-zero amplifier 3a is that the switch S1b is connected between the input terminal and the non-inverting input of the mutual conductance amplifier 31b.

[0022] Next, the error detection amplifier 2 will be described. The error detection amplifier 2 includes a mutual conductance amplifier 21 and capacitors C21 and C22 for phase compensation. The mutual conductance amplifier 21 amplifies the input in an inverted manner and outputs it. The inverting input of the mutual conductance amplifier 21 is connected to the negative-side outputs of the mutual conductance amplifiers 31a and 31b via switches S42a and S42b. The non-inverting input of the mutual conductance amplifier 21 is connected to the positive-side outputs of the mutual conductance amplifiers 31a and 31b via switches S41a and S41b.

[0023] Also, the positive-side output of the mutual conductance amplifier 21 is connected to the inverting inputs of the mutual conductance amplifiers 33a and 33b via switches S51a and S51b. The negative-side output of the mutual conductance amplifier 21 is connected to the non-inverting inputs of the mutual conductance amplifiers 33a and 33b via switches S52a and S52b. Further, the capacitor C21 is connected between the inverting input and the positive-side output of the mutual conductance amplifier 21, and the capacitor C22 is connected between the non-inverting input and the negative-side output of the mutual conductance amplifier 21.

[0024] The auto-zero amplifier 3a has a calibration mode and an amplification mode as operation modes, and is provided so as to be alternately switchable between the calibration mode and the amplification mode. In the calibration mode, the auto-zero amplifier 3a is a mode in which calibration voltages for reducing the offset components and low-frequency noise components of the mutual conductance amplifiers 31a and 33a are sampled by the sampling capacitors C1a and C2a.

[0025] In the calibration mode, as shown in FIG. 3, the auto-zero amplifier 3a turns on switches S2a, S41a, S42a, S51a, S52a and turns off switches S1a, S31a, S32a. As a result, the input and output of the transconductance amplifier 31a are disconnected from the input terminal and the output terminal. Also, the inverting input and non-inverting input of the transconductance amplifier 31a are short-circuited, and an offset component and a low-frequency noise component are output from the transconductance amplifier 31a.

[0026] Also, the output of the transconductance amplifier 31a is connected to the input of the error detection amplifier 2, and the output of the error detection amplifier 2 is connected to the sampling capacitors C1a, C2b. As a result, the offset component and the low-frequency noise component of the transconductance amplifier 31a are amplified and sampled on the sampling capacitors C1a, C2b.

[0027] In the amplification mode, as shown in FIG. 2, the auto-zero amplifier 3a turns on switches S1a, S31a, S32a and turns off switches S2a, S41a, S42a, S51a, S52a. As a result, the input and output of the transconductance amplifier 31a are connected to the input terminal and the output terminal, and an output signal Vout obtained by amplifying the input signal Vin by the transconductance amplifier 31a is output from the output terminal. Also, the sampling capacitors C1a, C2a are disconnected from the error detection amplifier 2. As a result, the calibration voltage sampled on the sampling capacitors C1a, C2a is applied to the output of the transconductance amplifier 31a via the transconductance amplifier 33a, and the offset component and the low-frequency noise component included in the output signal Vout are reduced.

[0028] Similar to the auto-zero amplifier 3a, the auto-zero amplifier 3b has a calibration mode and an amplification mode as operation modes, and is provided so as to be alternately switchable between the calibration mode and the amplification mode. Regarding the calibration mode and the amplification mode of the auto-zero amplifier 3b, since the "a" in the description of the calibration mode and the amplification mode of the auto-zero amplifier 3a can be replaced with "b", "FIG. 2" with "FIG. 3", and "FIG. 3" with "FIG. 2", a detailed description is omitted here.

[0029] Next, the operation of the Ping-Pong auto-zero amplifier 1A with the above-described configuration will be described with reference to the time chart shown in FIG. 4. The above-described switches S1a, S31a, S32a, and S2b are supplied with the clock CLK1, and the switches S2a, S1b, S31b, and S32b are supplied with the clock CLK2. The switches S41a, S42a, S51a, and S52a are supplied with the clock CLK3, and the switches S41b, S42b, S51b, and S52b are supplied with the clock CLK4.

[0030] With these clocks CLK1 to CLK4, the auto-zero amplifiers 3a and 3b alternately switch the operation mode between the calibration mode and the amplification mode. Also, as shown in FIGS. 2 and 3, when one of the auto-zero amplifiers 3a and 3b is in the calibration mode, the other is in the amplification mode, and when one is in the amplification mode, the other is in the calibration mode. FIG. 4 shows the operation mode of the auto-zero amplifier 3a. As a result, the Ping-Pong auto-zero amplifier 1A can always amplify the input signal Vin and output it as the output signal Vout. A circuit (not shown) that supplies these clocks CLK1 to CLK4 constitutes a control unit for the auto-zero amplifiers 3a and 3b.

[0031] Also, the error detection amplifier 2 can be connected to the auto-zero amplifiers 3a and 3b that are in the calibration mode, and the error detection amplifier 2 can be shared by the two auto-zero amplifiers 3a and 3b.

[0032] Next, the input offset voltage V io,in of the above-described auto-zero amplifiers 3a and 3b will be described. The input offset voltage V io,in can be expressed by the following equation (1).

[0033]

Equation

[0034] Each variable in Equation (1) represents the offset voltage V of the mutual conductance amplifiers 31a and 31b io1 and the mutual conductance value Gm1, the output resistance R1, the offset voltage V of the mutual conductance amplifier 21 io2 and the mutual conductance value Gm2, the output resistance R2, the offset voltage V of the mutual conductance amplifiers 33a and 33b io3 and the mutual conductance value Gm3, and the output resistance R1. As is clear from Equation (1), when the error detection amplifier 2 is provided, the offset voltages V io1 , V io3 can be further reduced by the mutual conductance value Gm2 of the error detection amplifier 2.

[0035] Also, as is clear from Equation (1), the input offset voltage V io,in is dominated by the influence of the offset voltage V io2 , and the influence of the offset voltages V io1 , V io3 can be regarded as almost negligible. For example, if the offset voltage V io2 is 10 mV and Gm1R1 is 1000 times, the input offset voltage V io,in will be ±10 μV. Therefore, if an error detection amplifier 2 is provided for each of the auto-zero amplifiers 3a and 3b as in the prior art, there is a risk of generating ±10 μV of glitch noise when switching the operation mode.

[0036] In contrast, in this embodiment, the error detection amplifier 2 that generates the offset voltage V io,in which occupies a large part of the input offset voltage V io2 is shared by the two auto-zero amplifiers 3a and 3b. Therefore, the input offset voltages V io,in of the respective auto-zero amplifiers 3a and 3b can be made uniform, and as a result, the glitch noise generated when the operation modes of the auto-zero amplifiers 3a and 3b are switched can be reduced.

[0037] Also, in the present embodiment, the error detection amplifier 2 is included in the loop circuit that feeds back the outputs of the mutual conductance amplifiers 31a and 31b. Therefore, the bandwidth of the loop circuit can also be adjusted by the mutual conductance value Gm2 of the error detection amplifier 2 and the capacitances C21 and C22 subjected to Miller compensation, and the sampling capacitances C1a, C2a, C1b, and C2b can be designed somewhat freely. Thus, the sampling capacitances C1a, C2a, C1b, and C2b can be increased to reduce the influence of the charge injection of the switches S41a, S42a, S51a, S52a, S41b, S42b, S51b, and S52b.

[0038] Note that in the above-described embodiment, the clocks CLK2 and CLK3 are the same clock, and the clocks CLK1 and CLK4 are the same clock, but this is not restrictive. For example, as shown in FIG. 5, the timing at which the clock CLK3 switches from H to L may be made slightly earlier than the timing at which the clock CLK2 switches from H to L, and the timing at which the clock CLK4 switches from H to L may be made slightly earlier than the timing at which the clock CLK1 switches from H to L. In this case, an operation of adjusting the output signal Vout of the auto-zero amplifiers 3a and 3b may be added to the time from when the switches S41a, S42a, S51a, S52a turn off until the switches S2a, S1b, S31b, S32b turn off, or the time from when the switches S41b, S42b, S51b, S52b turn off until the switches S1a, S31a, S32a, S2b turn off (for example, short-circuiting the output terminals, aligning the outputs of the auto-zero amplifiers 3a and 3b using a glitch correction circuit, etc.).

[0039] Also, the switches S51a, S52a, S51b, and S52b as switching switches and also as second switches may have a T-shaped switch configuration as shown in FIG. 6. More specifically, the switches S51a and S51b include two switches S101 and S102 (third switches) connected in series with each other between one of the error feedback paths (i.e., one of the inputs of the calibration circuits 32a and 32b) and one of the outputs of the error detection amplifier 2, and a switch S103 (fourth switch) connected between the connection point of the switches S101 and S102 and the common-phase voltage Vcm (predetermined voltage). The switches S52a and S52b each include switches S201 and S202 (fifth switches) connected in series between the other of the error feedback paths (i.e., the other of the inputs of the calibration circuits 32a and 32b) and the other of the outputs of the error detection amplifier 2, and a switch S203 (sixth switch) connected between the connection point of the switches S201 and S202 and the common-phase voltage Vcm.

[0040] Also, the same clock CLK is supplied to the switches S101, S102, S201, and S202 to turn them on and off simultaneously. On the other hand, an inverted clock CLK￣ is supplied to the switches S103 and S203. When the switches S101, S102, S201, and S202 are off, the switches S103 and S203 are turned on, and when the switches S101, S102, S201, and S202 are on, the switches S103 and S203 are turned off.

[0041] For example, if the switches S51a and S52a do not have a T-shaped switch configuration, since the voltages applied to the switches S51a and S52a are different, a bias is likely to occur in the leakage current, and this flows as a differential error current into the sampling capacitors C1a and C2a. On the other hand, as shown in FIG. 6, by configuring the switches S51a and S52a to have a T-shaped switch configuration, the voltages applied to the switches S51a and S52a can be made closer to the common-phase voltage Vcm, so that the bias of the leakage current can be reduced, and as a result, the differential error current flowing into the sampling capacitors C1a and C2a can be reduced. The same applies to the switches S51b and S52b.

[0042] (Second Embodiment) Next, the second embodiment will be described. In the second embodiment, as shown in FIG. 7, a phase-inverting auto-zero amplifier 1B as an amplification device is configured using the auto-zero amplifiers 3a and 3b described in the first embodiment. The phase-inverting auto-zero amplifier 1B includes an error detection amplifier 2 and two auto-zero amplifiers 3a and 3b. The difference between the first embodiment and the second embodiment is that the input of the auto-zero amplifier 3b is reversely connected. That is, the inverting input of the mutual conductance amplifier 31b constituting the auto-zero amplifier 3b is connected to the non-inverting input of the mutual conductance amplifier 31a constituting the auto-zero amplifier 3a, and the non-inverting input of the mutual conductance amplifier 31b is connected to the inverting input of the mutual conductance amplifier 31a.

[0043] Similar to the Ping-Pong auto-zero amplifier 1A, in the phase-inverting auto-zero amplifier 1B, when one of the two auto-zero amplifiers 3a and 3b is switched to the calibration mode, the other is switched to the amplification mode. When one of the two auto-zero amplifiers 3a and 3b is switched to the amplification mode, the other is switched to the calibration mode. Thereby, the phase-inverting auto-zero amplifier 1B always outputs an output signal Vout with reduced offset components and low-frequency components, and the output signal Vout is inverted every time the mode is switched from the amplification mode to the calibration mode.

[0044] (Third Embodiment) Next, the third embodiment will be described. As shown in FIG. 8, the amplifier-sharing auto-zero amplifier 1C of the third embodiment has a first path mode in which it is input from the first input path and output from the first output path, and a second path mode in which it is input from the second input path and output from the second output path. The amplifier-sharing auto-zero amplifier 1C includes the error detection amplifier 2 described in the first embodiment and three auto-zero amplifiers 31C, 32C, and 33C. Since the error detection amplifier 2 is the same as the error detection amplifier 2 described in the first embodiment, a detailed description thereof will be omitted here.

[0045] The auto-zero amplifiers 31C, 32C, and 33C are connected in parallel with each other. Since the auto-zero amplifiers 31C, 32C, and 33C have the same configuration, the auto-zero amplifier 31C will be described as a representative here. Similar to the first embodiment, the auto-zero amplifier 31C has an error detection path and an error feedback path. Also, the auto-zero amplifier 31C has two first and second input paths for inputting the input signal Vin and two first and second output paths for outputting the output signal Vout. As shown in FIGS. 9 to 11, the auto-zero amplifier 31C includes two mutual conductance amplifiers 341 and 342 (amplifiers), and switches S11 to S14, S21 to S24, S31 to S34 as switching switches and also as path switching switches, switches S41 and S42 as switching switches and also as first switches, switches S51 and S52 as switching switches and also as second switches, and a calibration circuit 35C.

[0046] The outputs of the mutual conductance amplifiers 341 and 342 are connected to each other. The switches S11 and S12 are connected between the first input path and the input of the mutual conductance amplifier 341. The switches S13 and S14 are connected between the second input path and the input of the mutual conductance amplifier 342. The switches S21 and S22 are connected between the input of the mutual conductance amplifier 341 and the common-mode voltage Vcm.

[0047] The switches S21 and S22 are connected on the input side of the mutual conductance amplifier 341 closer to the input than the switches S11 and S12. The switches S23 and S24 are connected between the input of the mutual conductance amplifier 341 and the input of the mutual conductance amplifier 342. The switches S23 and S24 are connected on the input side of the mutual conductance amplifier 341 closer to the input than the switches S11 and S12 and on the input side of the mutual conductance amplifier 342 closer to the input than the switches S13 and S14.

[0048] Switches S31 and S32 are connected between the outputs of mutual conductance amplifiers 341 and 342 connected to each other and the first output path. Switches S33 and S34 are connected between the outputs of mutual conductance amplifiers 341 and 342 connected to each other and the second output path. Switches S41 and S42 are connected between the outputs of mutual conductance amplifiers 341 and 342 connected to each other and the error detection path (i.e., the input of error detection amplifier 2). Switches S51 and S52 are connected between the error feedback path (i.e., the output of error detection amplifier 2 and the sampling capacitors C1 and C2 (i.e., the input of calibration circuit 35C) described later).

[0049] Calibration circuit 35C includes sampling capacitors C1 and C2 and mutual conductance amplifier 351. One ends of sampling capacitors C1 and C2 are connected to ground, and the other ends are connected to switches S51 and S52. The connection points between switches S51 and S52 and sampling capacitors C1 and C2 are connected to the input of mutual conductance amplifier 351.

[0050] Mutual conductance amplifier 351 inverts and amplifies the input and outputs it. The positive output of mutual conductance amplifier 351 is connected to the positive outputs of mutual conductance amplifiers 341 and 342, and the negative output is connected to the negative outputs of mutual conductance amplifiers 341 and 342.

[0051] The auto-zero amplifier 31C has a calibration mode, a first path mode, and a second path mode in the amplification mode. In the calibration mode, as shown in FIG. 9, switches S11 to S14, S31 to S34 are off, and switches S21 to S24, S41, S42, S51, S52 are on. As a result, the inputs and outputs of the mutual conductance amplifiers 341 and 342 are disconnected from the first and second input paths and the first and second output paths. Also, the inputs of the mutual conductance amplifiers 341 and 342 are short-circuited, and an offset component and a low-frequency noise component are output from the mutual conductance amplifiers 341 and 342. Further, the offset component and the low-frequency noise component output from the mutual conductance amplifiers 341 and 342 are amplified by the error detection amplifier 2 and sampled as a calibration voltage in the sampling capacitors C1 and C2.

[0052] In the first path mode, as shown in FIG. 10, switches S11, S12, S23, S24, S31, S32 are on, and switches S13, S14, S21, S22, S33, S34, S41, S42, S51, S52 are off. As a result, the inputs and outputs of the mutual conductance amplifiers 341 and 342 are connected to the first input path and the first output path. Thereby, the mutual conductance amplifiers 341 and 342 amplify the input signal Vin input from the first input path and output it as an output signal Vout from the first output path.

[0053] In the second path mode, as shown in FIG. 11, switches S13, S14, S21, S22, S33, S34 are on, and switches S11, S12, S23, S24, S31, S32 are off. As a result, the input and output of the mutual conductance amplifier 342 are connected to the second input path and the second output path. Also, the inverting input and the non-inverting input of the mutual conductance amplifier 341 are short-circuited. Thereby, the mutual conductance amplifier 342 amplifies the input signal Vin input from the second input path and outputs it as an output signal Vout from the second output path.

[0054] Next, the operation of the amplifier sharing auto-zero amplifier 1C with the above-described configuration will be described with reference to the time chart shown in FIG. 12. The switches S11, S12, S31, and S32 of the auto-zero amplifier 31C are supplied with the clock CLK1, the switches S13, S14, S33, and S34 are supplied with the clock CLK2, and the switches S41, S42, S51, and S52 are supplied with the clock CLK3. The switches S21 and S22 are supplied with the clock CLK4, and the switches S23 and S24 are supplied with the clock CLK5.

[0055] With these clocks CLK1 to CLK5, the auto-zero amplifier 31C switches its operation mode in the order of the calibration mode (FIG. 9), the first path mode of the amplification mode (FIG. 10), the calibration mode, and the second path mode of the amplification mode (FIG. 11), and repeats this switching. A circuit (not shown) that supplies these clocks CLK1 to CLK5 constitutes a control unit.

[0056] The clocks CLK1 to CLK5 supplied to the auto-zero amplifiers 31C, 32C, and 33C are 120 degrees out of phase. As a result, as shown in FIG. 13, when one of the auto-zero amplifiers 31C, 32C, and 33C is in the calibration mode, the other two are in the first path mode or the second path mode. Also, the auto-zero amplifiers 31C, 32C, and 33C sequentially enter the calibration mode. Thereby, the amplifier sharing auto-zero amplifier 1C can always output an output signal Vout obtained by amplifying the input signal Vin from one or both of the first output path and the second output path.

[0057] Note that, as shown in FIG. 14, as the clocks CLK1 to CLK5, the timing at which the clock CLK3 switches from H to L may be made slightly earlier. In this case, an operation of adjusting the output signals Vout of the auto-zero amplifiers 31C to 33C may be added to the time from when the switches S41, S42, S51, and S52 are turned off in the calibration mode until the switching to the first path mode or the second path mode (for example, short-circuiting the output terminals, aligning the outputs of the auto-zero amplifiers 31C to 33C using a glitch correction circuit, etc.).

[0058] Also, as the switches S51 and S52, a T-shaped switch configuration as shown in FIG. 6 may be used. In this case, as described above, the bias of the leakage current can be reduced, and as a result, the differential error current flowing into the sampling capacitors C1 and C2 can be reduced.

[0059] (Fourth Embodiment) Next, the fourth embodiment will be described. As shown in FIG. 15, in the fourth embodiment, an amplification device 100 having two or more stages of amplifiers is configured using the Ping-Pong auto-zero amplifier 1A described in the first embodiment. The amplification device 100 includes a Ping-Pong auto-zero amplifier 1A serving as an input stage, and an amplifier 101 that amplifies the output of the Ping-Pong auto-zero amplifier 1A. The input signal Vin input to the Ping-Pong auto-zero amplifier 1A is amplified by the Ping-Pong auto-zero amplifier 1A and the amplifier 101 and output as an output signal Vout. With this configuration, the amplification device 100 can be made more accurate.

[0060] (Fifth Embodiment) Next, the fifth embodiment will be described. As shown in FIG. 16, in the fifth embodiment, a chopper-stabilized amplifier 105 is configured using the Ping-Pong auto-zero amplifier 1A described in the first embodiment. The chopper-stabilized amplifier 105 includes a chopper modulator 106, a Ping-Pong auto-zero amplifier 1A, a chopper modulator 107, and an amplifier 108.

[0061] The chopper modulator 106 modulates the input signal Vin to a high-frequency band. The Ping-Pong auto-zero amplifier 1A amplifies and outputs the signal modulated by the chopper modulator 106. The chopper modulator 107 demodulates the signal component of the output of the Ping-Pong auto-zero amplifier 1A to a low-frequency band, and modulates and outputs the offset component and the low-frequency noise component to a high-frequency band. The amplifier 108 amplifies the output of the chopper modulator 107 and outputs it as the output signal Vout. In this way, by using the Ping-Pong auto-zero amplifier 1A described in the fifth embodiment, the accuracy of the chopper-stabilized amplifier 105 can be improved.

[0062] (Sixth Embodiment) Next, the sixth embodiment will be described. As shown in FIG. 17, in the sixth embodiment, a chopper-stabilized amplifier 110 having three or more stages is configured by using the Ping-Pong auto-zero amplifier 1A shown in FIG. 1 or the phase-inverting auto-zero amplifier 1B shown in FIG. 7. The chopper-stabilized amplifier 110 includes a chopper modulator 111, a transconductance amplifier 112, a chopper output circuit 113, an amplifier 114, and a transconductance amplifier 115.

[0063] The chopper modulator 111 modulates the input signal Vin to a high-frequency band. The transconductance amplifier 112 amplifies and outputs the signal modulated by the chopper modulator 111. The chopper output circuit 113 is configured as shown in FIG. 18, for example. As shown in the figure, the chopper output circuit 113 includes a chopper modulator 116 and a noise reduction loop circuit 117. The chopper modulator 116 demodulates the signal component of the output of the transconductance amplifier 112 to a low-frequency band, and modulates and outputs the offset component and the low-frequency noise component to a high-frequency band.

[0064] The noise reduction loop circuit 117 extracts the offset component of the mutual conductance amplifier 112 and negatively feeds back the extracted offset component to the output of the mutual conductance amplifier 112. By this noise reduction loop circuit 117, the offset component and the low-frequency noise component generated in the mutual conductance amplifier 112 can be reduced, and the ripple noise included in the output of the chopper output circuit 113 can be reduced (see FIGS. 20(B) and 20(C)).

[0065] In the example shown in FIG. 18, the noise reduction loop circuit 117 has a configuration including the Ping-Pong auto-zero amplifier 1A described in the first embodiment that amplifies the input of the noise reduction loop circuit 117, a filter circuit 118 that reduces the high-frequency signal component of the output of the Ping-Pong auto-zero amplifier 1A, and a mutual conductance amplifier 119 that amplifies the output of the filter circuit 118. The output of the mutual conductance amplifier 112 is input to the Ping-Pong auto-zero amplifier 1A. The filter circuit 118 has a function of amplifying the low-frequency signal component of the output of the Ping-Pong auto-zero amplifier 1A and reducing the high-frequency signal component. By the filter circuit 118, the high-frequency signal component can be reduced and the offset component of the amplifier can be fed back.

[0066] Also, the chopper output circuit 113 may be configured as shown in FIG. 19, for example. As shown in the figure, the chopper output circuit 113 includes a chopper modulator 116 and a ripple correction circuit 120. The chopper modulator 116 is the same as the chopper modulator 116 shown in FIG. 8.

[0067] The ripple correction circuit 120 has its input connected to the output of the chopper modulator 116 and its output connected to the input of the chopper modulator 116. The ripple correction circuit 120 extracts the high-frequency noise component (ripple noise) from the output of the chopper modulator 116, modulates the extracted ripple noise into an offset component, and negatively feeds back the modulated offset component to the output of the mutual conductance amplifier 112. By the ripple correction circuit 120, the offset component included in the output of the mutual conductance amplifier 112 can be reduced, and the ripple noise included in the output of the chopper modulator 116 can be reduced (see FIGS. 20(B) and 20(C)).

[0068] In the present embodiment, the ripple correction circuit 120 includes a high-pass filter 121 that reduces the low-frequency noise component input to the ripple correction circuit 120 and detects the ripple noise, a phase-inverting auto-zero amplifier 1B that demodulates the ripple noise at the output of the high-pass filter 121 into a low-frequency component and modulates it into an offset component, a filter circuit 122 that reduces the high-frequency component at the output of the phase-inverting auto-zero amplifier 1B, and a mutual conductance amplifier 123 that amplifies the output of the filter circuit 122.

[0069] FIG. 20 is a characteristic diagram showing an example of the time waveforms and frequency characteristics of the signal component, noise component, and offset component by the chopper stabilization amplifier shown in FIG. 17. In FIG. 20, for each of the signal component, noise component, and offset component, an image of the change process of the time waveform and frequency distribution is shown. In FIG. 20, the upper row shows the time waveform and the lower row shows the frequency characteristic. Let the chopping frequency of the chopper modulators 111 and 116 be fch.

[0070] The signal component (Fig. 20(A)) input to the chopper-stabilized amplifier shown in Fig. 17 is modulated to a high-frequency band by the chopper modulator 111 (Fig. 20(B)) and amplified by the mutual conductance amplifier 112. Thereafter, the signal component is demodulated (Fig. 20(C)) by passing through the output chopper circuit 113 via the chopper modulator 116, and is amplified by the subsequent-stage amplifier and output. In the present embodiment, by using the noise reduction loop circuit 117 or the ripple correction circuit 120, as indicated by the broken line → solid line in the figure, the offset component and the low-frequency noise component of the mutual conductance amplifier 112 are reduced. For this reason, the ripple noise output at the output terminal of the output chopper circuit 113 is reduced, and the ripple noise finally output as the output of the amplification device is reduced.

[0071] As shown in Fig. 17, the amplifier 114 amplifies the signal component output from the chopper output circuit 113. In the present embodiment, the output of the amplifier 114 becomes the output terminal of the chopper-stabilized amplifier 110, and the output signal Vout is output. The amplifier 114 includes a mutual conductance amplifier 124, an amplifier 125, and a phase compensation circuit 126 that performs phase compensation for the amplifier 125. The input of the amplifier 125 is connected to the output of the mutual conductance amplifier 124, and the output of the amplifier 125 becomes the output of the amplifier 114, that is, the output terminal of the chopper-stabilized amplifier 110.

[0072] The phase compensation circuit 126 is composed of capacitors Cc1 to Cc3. The capacitor Cc1 is connected between the input and output of the amplifier 125. The capacitor Cc2 is connected between the inverting input of the mutual conductance amplifier 124 and the output of the amplifier 125. The capacitor Cc3 is connected between the non-inverting input of the mutual conductance amplifier 124 and the ground.

[0073] The mutual conductance amplifier 115 is connected between the input terminal and the input of the amplifier 125 and functions as a feed-forward amplifier. In this way, by using the Ping-Pong auto-zero amplifier 1A described in the first embodiment and the phase-inverting auto-zero amplifier 1B described in the second embodiment, it is possible to improve the accuracy of the three-stage or more chopper-stabilized amplifier 110.

[0074] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the material, shape, dimensions, number, arrangement location, etc. of each component in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

[0075] For example, the amplifier 114 in the output stage shown in the above-described sixth embodiment is composed of the mutual conductance amplifier 124 and the amplifier 125, but it is not limited to this. For example, as shown in FIG. 21, instead of the mutual conductance amplifier 124, two mutual conductance amplifiers 131 and 132 may be provided. In the example shown in FIG. 21, the phase compensation circuit 126 is composed of two capacitors Cc4 and Cc5. The capacitor Cc4 is connected between the inverting input and the positive output of the mutual conductance amplifier 131. The capacitor Cc5 is connected between the non-inverting input and the negative output of the mutual conductance amplifier 131.

[0076] Also, the noise reduction loop circuit 117 shown in FIG. 18 described in the above-described sixth embodiment may be configured as shown in FIG. 22. In the example shown in FIG. 22, instead of the Ping-Pong auto-zero amplifier 1A shown in FIG. 18 and the amplifier 114 shown in FIG. 17, the mutual conductance amplifiers 341 and 342 of the amplifier sharing auto-zero amplifier 1C described in the third embodiment are used. As shown in the figure, the output of the chopper modulator 116 is connected to the first input path of the amplifier sharing auto-zero amplifier 1C, and the first output path becomes the output terminal. Also, the output of the mutual conductance amplifier 119 is connected to the second input path, and the filter circuit 118 is connected to the second output path.

Explanation of Reference Numerals

[0077] 1A Ping-Pong Auto-Zero Amplifier (Amplifying Device) 1B Phase Inverting Auto-Zero Amplifier (Amplifying Device) 2 Error Detection Amplifier 3a, 3b Auto-Zero Amplifier 31a, 31b Transconductance Amplifier (Amplifier) 32a, 32b Calibration Circuit 31C, 32C, 33C Auto-Zero Amplifier 341, 342 Transconductance Amplifier (Amplifier) 35C Calibration Circuit C1, C2 Sampling Capacitance C1a, C2a, C1b, C2b Sampling Capacitance S11~S14, S21~S24, S31~S34 Switch (Switching Switch, Route Switching Switch) S41, S42 Switch (Switching Switch, First Switch) S51, S52 Switch (Switching Switch, Second Switch) S1a, S2a, S31a, S32a Switch (Switching Switch) S1b, S2b, S31b, S32b Switch (Switching Switch) S41a, S42a, S41b, S42b Switch (Switching Switch, First Switch) S51a, S52a, S51b, S52b Switch (Switching Switch, Second Switch) S101, S102 Switch (Switching Switch, Second Switch, Third Switch) S103 Switch (Switching Switch, Second Switch, Fourth Switch) S201, S202 Switch (Switching Switch, Second Switch, Fifth Switch) S203 Switch (Switching Switch, Second Switch, Sixth Switch) Vin Input Signal Vout Output Signal

Claims

1. an amplifier; a calibration circuit including a sampling capacitor; a calibration mode for sampling a calibration voltage for calibrating an offset component and a low-frequency noise component of the amplifier into the sampling capacitor, and a switching switch for switching between the calibration mode and an amplification mode for amplifying an input signal by the amplifier with the offset component and the low-frequency noise component reduced by the calibration voltage to output an output signal. In an amplification device including a plurality of auto-zero amplifiers, comprising one error detection amplifier for amplifying and outputting an input voltage; the switching switch, a first switch connecting an output of the amplifier and an input of the error detection amplifier; and a second switch connecting an input of the calibration circuit and an output of the error detection amplifier, wherein a voltage applied to the input of the calibration circuit is a voltage sampled into the sampling capacitor as the calibration voltage, an amplification device.

2. The amplification device according to claim 1, further comprising a control unit for controlling the switching switch, wherein the control unit controls the switching switch such that the auto-zero amplifier alternately switches between the calibration mode and the amplification mode, and controls the switching switch such that at least one of the plurality of auto-zero amplifiers operates in the amplification mode and another one of the auto-zero amplifiers operates in the calibration mode. an amplification device.

3. The amplification device according to claim 1, wherein three auto-zero amplifiers are provided, each of the three auto-zero amplifiers having a first input path and a second input path to which the input signal is respectively input, and a first output path and a second output path from which the output signal is respectively output, wherein the switching switch has a path switching switch for switching between a first path mode in which the amplifier is connected to the first input path and the first output path and a second path mode in which the amplifier is connected to the second input path and the second output path in the amplification mode. an amplification device.

4. The amplification device according to claim 3, comprising a control unit for controlling the switching switch, The control unit controls the switching switch so that the auto-zero amplifier alternately switches between the calibration mode and the amplification mode, and controls the switching switch so that one of the three auto-zero amplifiers operates as the calibration mode and the remaining auto-zero amplifiers operate as the first path mode or the second path mode. Amplification device.

5. In the amplification device according to claim 2 or 4, The control unit controls the first switch and the second switch of the auto-zero amplifier to be turned off before switching from the calibration mode to the amplification mode. Amplification device.

6. In the amplification device according to any one of claims 1 to 5, The second switch includes two third switches connected in series between one of the inputs of the calibration circuit and one of the outputs of the error detection amplifier, a fourth switch connecting the connection point of the two third switches and a predetermined voltage, two fifth switches connected in series between the other of the inputs of the calibration circuit and the other of the outputs of the error detection amplifier, and a sixth switch connecting the connection point of the two fifth switches and the predetermined voltage. Amplification device.

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