Low-noise amplifier and radio-frequency chip

Abstract

The present invention relates to the technical field of wireless communications. Disclosed in the present invention are a low-noise amplifier and a radio-frequency chip. The low-noise amplifier comprises a signal input end, a power amplifier circuit, an output matching circuit, an attenuation network and a signal output end, which are sequentially and electrically connected; and the low-noise amplifier further comprises a bypass circuit. The bypass circuit comprises a bypass switch circuit and a bypass matching circuit, wherein a first end of the bypass switch circuit serves as an input end of the bypass circuit, a first output end of the bypass switch circuit serves as a first output end of the bypass circuit, a second output end of the bypass switch circuit is connected to an input end of the bypass matching circuit, and an output end of the bypass matching circuit serves as a second output end of the bypass circuit; and the bypass switch circuit comprises a first bypass switch unit and a second bypass switch unit. The low-noise amplifier of the present invention has a simple structure, occupies a small area, and has high linearity.

Description

Low noise amplifier and RF chip Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a low noise amplifier and a radio frequency chip. Background Art

[0002] Low-noise amplifiers (LNAs) are key components of wireless communication systems. They are primarily used in the RF front-end of wireless communication receivers and play a crucial role in the performance of the receiving system. With increasing demands for improved signal quality, some communication systems require a signal bypass function in the LNA path. When required by the system or when an abnormality occurs in the LNA path, an internal switch can be used to switch to bypass mode, providing an optimal path for the uplink signal and ensuring normal operation of the base station.

[0003] The performance of a low-noise amplifier (LNA) in related technologies is a key component of a receiver, and its performance directly impacts the overall receiver performance (gain, power consumption, noise figure, linearity, area, etc.). In smart terminal applications, if the antenna input signal strength is very strong, the LNA no longer requires high gain and may even require attenuation. The bypass structure, as a purely passive structure, offers many advantages unmatched by other amplification modes, such as high linearity, low noise, and extremely low power consumption.

[0004] However, in the above-mentioned related technologies, in some sub3G (5G frequency band) applications, there are often multiple input ports, which occupy a large area and increase the cost of bypass; at the same time, the adjustment and control effect of multiple input ports is poor, resulting in poor overall performance. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a low-noise amplifier that matches different frequency bands by connecting capacitors of different capacitance values, and outputs the output after passing through an output matching circuit and attenuation network shared with a power amplifier circuit; thereby solving the problems of existing low-noise amplifiers such as poor multi-band and multi-attenuation adjustment effects, high costs, and poor overall performance.

[0006] To solve the above technical problems, in a first aspect, an embodiment of the present invention provides a low-noise amplifier, comprising a signal input terminal, a power amplifier circuit, an output matching circuit, an attenuation network, and a signal output terminal electrically connected in sequence; the low-noise amplifier further comprises a bypass circuit, wherein an input terminal of the bypass circuit is connected to the signal input terminal, a first output terminal of the bypass circuit is connected to the input terminal of the power amplifier circuit, and a second output terminal of the bypass circuit is connected to the output terminal of the power amplifier circuit;

[0007] The bypass circuit includes a bypass switch circuit and a bypass matching circuit, wherein the input end of the bypass switch circuit serves as the input end of the bypass circuit, the first output end of the bypass switch circuit serves as the first output end of the bypass circuit, the second output end of the bypass switch circuit is connected to the input end of the bypass matching circuit, and the output end of the bypass matching circuit serves as the second output end of the bypass circuit;

[0008] The bypass switch circuit includes a first bypass switch unit and a second bypass switch unit; the input end of the first bypass switch unit and the input end of the second bypass switch unit are connected and serve together as the input end of the bypass switch circuit, the output end of the first bypass switch unit serves as the second output end of the bypass switch circuit, and the output end of the second bypass switch unit serves as the first output end of the bypass switch circuit;

[0009] The bypass matching circuit includes a first capacitor, a second capacitor, a third capacitor, a first switching transistor and a second switching transistor; the first end of the first capacitor is respectively connected to the first end of the second capacitor and the first end of the third capacitor, the second end of the first capacitor is respectively connected to the drain of the first switching transistor and the drain of the second switching transistor, the second end of the second capacitor is connected to the source of the first switching transistor, the second end of the third capacitor is connected to the source of the second switching transistor, and the gate of the first switching transistor and the gate of the second switching transistor are respectively used to connect to an external logic control circuit; the first end of the first capacitor serves as the input end of the bypass matching circuit, and the second end of the first capacitor serves as the output end of the bypass matching circuit.

[0010] Preferably, the first bypass switch unit includes a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

[0011] The source of the third switching transistor is connected to the first end of the first resistor and both serve as the input end of the first bypass switch unit; the drain of the third switching transistor is respectively connected to the second end of the first resistor, the first end of the second resistor, and the source of the fourth switching transistor; the drain of the fourth switching transistor is respectively connected to the second end of the second resistor, the source of the fifth switching transistor, the first end of the third resistor, the first end of the fifth resistor, and the drain of the seventh switching transistor; the source of the seventh switching transistor is connected to the second end of the fifth resistor and both are grounded; the drain of the fifth switching transistor is respectively connected to the second end of the third resistor, the first end of the fourth resistor, and the source of the sixth switching transistor; the drain of the sixth switching transistor is connected to the second end of the fourth resistor and both serve as the output end of the first bypass switch unit;

[0012] The gate of the third switch transistor, the gate of the fourth switch transistor, the gate of the fifth switch transistor, the gate of the sixth switch transistor, and the gate of the seventh switch transistor are respectively used to connect to the external logic control circuit.

[0013] Preferably, the second bypass switch unit includes an eighth switch transistor, a ninth switch transistor, a tenth switch transistor, a sixth resistor, a seventh resistor and an eighth resistor;

[0014] The drain of the eighth switch transistor is connected to the first end of the seventh resistor, the source of the eighth switch transistor is respectively connected to the drain of the ninth switch transistor, the second end of the seventh resistor, and the first end of the eighth resistor, and the source of the ninth switch transistor is connected to the second end of the eighth switch and is grounded.

[0015] The source of the tenth switch transistor is connected to the first end of the sixth resistor and the drain of the eighth switch transistor respectively, the drain of the tenth switch transistor is connected to the second end of the sixth resistor and serves as the output end of the second bypass switch unit, and the source of the tenth switch transistor serves as the input end of the second bypass switch unit;

[0016] The gate of the eighth switch transistor, the gate of the ninth switch transistor, and the gate of the tenth switch transistor are respectively used to connect to the external logic control circuit.

[0017] Preferably, the power amplifier circuit includes a first amplifier and a second amplifier; the gate of the first amplifier serves as the input end of the power amplifier circuit, the source of the first amplifier is grounded, the drain of the first amplifier is connected to the source of the second amplifier, the drain of the second amplifier serves as the output end of the power amplifier circuit, and the gate of the second amplifier is used to connect to an external bias circuit.

[0018] Preferably, the output matching circuit includes a first output matching network and a second output matching network; the input end of the first output matching network serves as the input end of the output matching circuit, the output end of the first output matching network is connected to the input end of the second output matching network, and the output end of the second output matching network serves as the output end of the output matching circuit;

[0019] The first output matching network includes a first inductor, a fourth capacitor, a fifth capacitor, an eleventh switching transistor and a twelfth switching transistor;

[0020] The first end of the first inductor is connected to the source of the eleventh switching transistor and the source of the twelfth switching transistor, respectively; the second end of the first inductor is connected to the power supply voltage, the first end of the fifth capacitor, and the second end of the sixth capacitor, respectively; the second end of the fifth capacitor is connected to the drain of the eleventh switching transistor, and the second end of the sixth capacitor is connected to the drain of the twelfth switching transistor; the first end of the first inductor serves as the input end of the first output matching network, and the source of the twelfth switching transistor serves as the output end of the first output matching network;

[0021] The gate of the eleventh switching transistor and the gate of the twelfth switching transistor are respectively used to connect to the external logic control circuit;

[0022] The second output matching network includes a sixth capacitor, a seventh capacitor, an eighth capacitor, a thirteenth switching transistor and a fourteenth switching transistor;

[0023] The first end of the sixth capacitor is connected to the first end of the seventh capacitor and the first end of the eighth capacitor respectively, and the second end of the sixth capacitor is connected to the drain of the thirteenth switching transistor and the drain of the fourteenth switching transistor respectively; the second end of the seventh capacitor is connected to the source of the thirteenth switching transistor, and the second end of the eighth capacitor is connected to the source of the fourteenth switching transistor;

[0024] The gate of the thirteenth switching transistor and the gate of the fourteenth switching transistor are respectively used to connect to the external logic control circuit.

[0025] Preferably, the bypass switch circuit includes multiple, the first ends of the multiple bypass switch circuits are connected to the signal input end, the first output end of the bypass switch circuit is connected to the input end of the power amplifier circuit, and the second output end of the bypass switch circuit is connected to the input end of the bypass matching circuit.

[0026] In a second aspect, the present invention provides a radio frequency chip, comprising the above-mentioned low noise amplifier.

[0027] Compared with the prior art, the low-noise amplifier in the present invention connects the input end of the first bypass switch unit and the input end of the second bypass switch unit of the bypass switch circuit and serves as the input end of the bypass switch circuit, the output end of the first bypass switch unit serves as the second output end of the bypass switch circuit, and the output end of the second bypass switch unit serves as the first output end of the bypass switch circuit; the first end of the first capacitor is connected to the first end of the second capacitor and the first end of the third capacitor respectively, the second end of the first capacitor is connected to the drain of the first switching transistor and the drain of the second switching transistor respectively, the second end of the second capacitor is connected to the source of the first switching transistor, the second end of the third capacitor is connected to the source of the second switching transistor, and the gate of the first switching transistor and the gate of the second switching transistor are respectively used to connect to an external logic control circuit; the first end of the first capacitor serves as the input end of the bypass matching circuit, and the second end of the first capacitor serves as the output end of the bypass matching circuit. Matching of different frequency bands is achieved by accessing different capacitance values. The input signal passes through a bypass switch and is output after passing through an output matching circuit and an attenuation network shared by the matching capacitor and the power amplifier circuit in the amplification mode. The attenuation network is used to provide different attenuation amounts to meet the requirements of different gain levels in modern communication receivers. At the same time, the low-noise amplifier has a simple structure, is easy to implement, occupies a small area, saves costs, and has good overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0029] FIG1 is an overall circuit diagram of a low noise amplifier provided by an embodiment of the present invention;

[0030] FIG2 is a partial enlarged view of FIG1 ;

[0031] FIG3 is a second partial enlarged view of FIG1 .

[0032] In the figure, 100, low noise amplifier, 1, signal input end, 2, power amplifier circuit, 3, output matching circuit, 31, first output matching network, 32, second output matching network, 4, attenuation network, 5, signal output end; 6, bypass circuit, 61, bypass switch circuit, 611, first bypass switch unit, 612, second bypass switch unit, 62, bypass matching circuit. DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] Example 1

[0035] 1 to 3 , an embodiment of the present invention provides a low-noise amplifier 100, which includes a signal input terminal 1 (RFIN1), a power amplifier circuit 2, an output matching circuit 3, an attenuation network 4, and a signal output terminal 5 (RFOUT) electrically connected in sequence; the low-noise amplifier 100 also includes a bypass circuit 6, wherein an input terminal of the bypass circuit 6 is connected to the signal input terminal 1, a first output terminal of the bypass circuit 6 is connected to the input terminal of the power amplifier circuit 2, and a second output terminal of the bypass circuit 6 is connected to the output terminal of the power amplifier circuit 2.

[0036] The bypass circuit 6 includes a bypass switch circuit 61 and a bypass matching circuit 62. The input end of the bypass switch circuit 61 serves as the input end of the bypass circuit 6. The first output end of the bypass switch circuit 61 serves as the first output end of the bypass circuit 6. The second output end of the bypass switch circuit 61 is connected to the input end of the bypass matching circuit 62. The output end of the bypass matching circuit 62 serves as the second output end of the bypass circuit 6.

[0037] Optionally, the bypass circuit 6 includes multiple, preferably two.

[0038] The bypass switch circuit 61 includes a first bypass switch unit 611 and a second bypass switch unit 612. The input end of the first bypass switch unit 611 and the input end of the second bypass switch unit 612 are connected and serve together as the input end of the bypass switch circuit 61. The output end of the first bypass switch unit 611 serves as the second output end of the bypass switch circuit 61, and the output end of the second bypass switch unit 612 serves as the first output end of the bypass switch circuit 61. Bypass mode control is achieved by outputting different judgments by the first bypass switch unit 611. Different signals are output by the second bypass switch unit 612 to control the input switch of the amplification module of the power amplifier circuit 2. The bypass mode and the amplification mode share the same output matching circuit 3 and attenuation network 4, which reduces the number of components and saves area.

[0039] The bypass matching circuit 62 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first switching transistor M1 and a second switching transistor M2; the first end of the first capacitor C1 is respectively connected to the first end of the second capacitor C2 and the first end of the third capacitor C3, the second end of the first capacitor C1 is respectively connected to the drain of the first switching transistor M1 and the drain of the second switching transistor M2, the second end of the second capacitor C2 is connected to the source of the first switching transistor M1, the second end of the third capacitor C3 is connected to the source of the second switching transistor M2, and the gate of the first switching transistor M1 and the gate of the second switching transistor M2 are respectively used to connect to an external logic control circuit; the first end of the first capacitor C1 serves as the input end of the bypass matching circuit 62, and the second end of the first capacitor C1 serves as the output end of the bypass matching circuit 62. The first switching transistor M1 and the second switching transistor M2 are controlled by an external logic control circuit, so that matching of different frequency bands is achieved by accessing different capacitance values. The input signal passes through the bypass switch, and is output after passing through the output matching circuit 3 and the attenuation network 4 shared by the matching capacitor and the power amplifier circuit 2 in the amplification mode. The attenuation network 4 is used to provide different attenuation amounts for it to meet the requirements of different gain levels in modern communication receivers. At the same time, the low-noise amplifier 100 has a simple structure, is easy to implement, occupies a small area, saves costs, and has good overall performance.

[0040] In this embodiment, the first bypass switch unit 611 includes a third switch transistor M3, a fourth switch transistor M4, a fifth switch transistor M5, a sixth switch transistor M6, a seventh switch transistor M7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5.

[0041] The source of the third switch transistor M3 is connected to the first end of the first resistor R1 and collectively serves as the input end of the first bypass switch unit 611. The drain of the third switch transistor M3 is respectively connected to the second end of the first resistor R1, the first end of the second resistor R2, and the source of the fourth switch transistor M4. The drain of the fourth switch transistor M4 is respectively connected to the second end of the second resistor R2, the source of the fifth switch transistor M5, the first end of the third resistor R3, the first end of the fifth resistor R5, and the drain of the seventh switch transistor M7. The source of the seventh switch transistor M7 is connected to the second end of the fifth resistor R5 and are commonly grounded to GND. The drain of the fifth switch transistor M5 is respectively connected to the second end of the third resistor R3, the first end of the fourth resistor R4, and the source of the sixth switch transistor M6. The drain of the sixth switch transistor M6 is connected to the second end of the fourth resistor R4 and collectively serves as the output end of the first bypass switch unit 611.

[0042] The gate of the third switch transistor M3 , the gate of the fourth switch transistor M4 , the gate of the fifth switch transistor M5 , the gate of the sixth switch transistor M6 , and the gate of the seventh switch transistor M7 are respectively used to connect to the external logic control circuit.

[0043] The third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 form a high-isolation switch. Resistors connected across the switch source and drain provide a DC operating point. The third switching transistor M3, the fourth switching transistor M4, the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 are individually controlled by an externally connected control circuit, achieving excellent switching control.

[0044] In this embodiment, the second bypass switch unit 612 includes an eighth switch transistor M8, a ninth switch transistor M9, a tenth switch transistor M10, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8.

[0045] The drain of the eighth switch transistor M8 is connected to the first end of the seventh resistor R7, the source of the eighth switch transistor M8 is respectively connected to the drain of the ninth switch transistor M9, the second end of the seventh resistor R7 and the first end of the eighth resistor R8, and the source of the ninth switch transistor M9 is connected to the second end of the eighth switch and is commonly grounded GND.

[0046] The source of the tenth switch transistor M10 is respectively connected to the first end of the sixth resistor R6 and the drain of the eighth switch transistor M8, the drain of the tenth switch transistor M10 is connected to the second end of the sixth resistor R6 and serves as the output end of the second bypass switch unit 612, and the source of the tenth switch transistor M10 serves as the input end of the second bypass switch unit 612.

[0047] The gate of the eighth switch transistor M8 , the gate of the ninth switch transistor M9 , and the gate of the tenth switch transistor M10 are respectively used to connect to the external logic control circuit.

[0048] By using the tenth switching transistor M10 as the input switch of the power amplifier circuit 2 in the amplification mode, the nonlinear capacitance brought by the power amplifier circuit 2 is isolated, the linearity in the bypass mode is improved, and the parasitic capacitance from the RF input terminal to the ground is reduced, which is more conducive to matching in the bypass mode; the eighth switching transistor M8 and the ninth switching transistor M9 are switches connected in parallel to the ground at the input terminal, providing higher isolation for different input ports.

[0049] In this embodiment, the power amplifier circuit 2 includes a first amplifier M01 and a second amplifier M02. The gate of the first amplifier M01 serves as the input of the power amplifier circuit 2. The source of the first amplifier M01 is connected to ground GND. The drain of the first amplifier M01 is connected to the source of the second amplifier M02. The drain of the second amplifier M02 serves as the output of the power amplifier circuit 2. The gate of the second amplifier M02 is used to connect to an external bias circuit. The first amplifier M01 and the second amplifier M02 form a cascode amplifier tube. By isolating the nonlinear capacitance caused by the cascode amplifier tube, the linearity in bypass mode is improved.

[0050] Preferably, the source of the first amplifier M01 is connected to the inductor and then to the ground GND, which is beneficial to the linearity of the bypass mode.

[0051] The first amplifier M01 and the second amplifier M02 are both MOS tubes.

[0052] In this embodiment, the output matching circuit 3 includes a first output matching network 31 and a second output matching network 32; the input end of the first output matching network 31 serves as the input end of the output matching circuit 3, the output end of the first output matching network 31 is connected to the input end of the second output matching network 32, and the output end of the second output matching network 32 serves as the output end of the output matching circuit 3.

[0053] In this embodiment, the first output matching network 31 includes a first inductor L1 , a fourth capacitor C4 , a fifth capacitor C5 , an eleventh switching transistor M11 , and a twelfth switching transistor M12 .

[0054] The first end of the first inductor L1 is respectively connected to the source of the eleventh switching transistor M11 and the source of the twelfth switching transistor M12; the second end of the first inductor L1 is respectively connected to the power supply voltage VDD, the first end of the fifth capacitor C5, and the second end of the sixth capacitor C6; the second end of the fifth capacitor C5 is connected to the drain of the eleventh switching transistor M11, and the second end of the sixth capacitor C6 is connected to the drain of the twelfth switching transistor M12; the first end of the first inductor L1 serves as the input end of the first output matching network 31, and the source of the twelfth switching transistor M12 serves as the output end of the first output matching network 31.

[0055] The gate of the eleventh switching transistor M11 and the gate of the twelfth switching transistor M12 are respectively used to connect to the external logic control circuit.

[0056] In this embodiment, the second output matching network 32 includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a thirteenth switch transistor M13, and a fourteenth switch transistor M14.

[0057] The first end of the sixth capacitor C6 is connected to the first end of the seventh capacitor C7 and the first end of the eighth capacitor C8, respectively; the second end of the sixth capacitor C6 is connected to the drain of the thirteenth switching transistor M13 and the drain of the fourteenth switching transistor M14, respectively; the second end of the seventh capacitor C7 is connected to the source of the thirteenth switching transistor M13, and the second end of the eighth capacitor C8 is connected to the source of the fourteenth switching transistor M14.

[0058] The gate of the thirteenth switching transistor M13 and the gate of the fourteenth switching transistor M14 are respectively used to connect to the external logic control circuit.

[0059] The first inductor L1, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8 are switched and controlled by the corresponding eleventh switching transistor M11, the twelfth switching transistor M12, the thirteenth switching transistor M13, and the fourteenth switching transistor M14, thereby matching different frequency bands by connecting different capacitance values. The attenuation network 4 provides different attenuation amounts to meet the different gain requirements of modern communication receivers.

[0060] Preferably, the first switch transistor M1 to the fourteenth switch transistor M14 are all MOS transistors.

[0061] In this embodiment, the bypass switch circuit 61 includes multiple circuits, each of which has an input connected to the signal input terminal 1, a first output connected to the input of the power amplifier circuit 2, and a second output connected to the input of the bypass matching circuit 62. This enables control of multiple frequency bands and multiple attenuation levels, improving the linearity of the bypass mode.

[0062] Example 2

[0063] The present invention provides a radio frequency chip, which includes the above-mentioned low noise amplifier 100.

[0064] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0065] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low-noise amplifier, the low-noise amplifier comprising a signal input end, a power amplification circuit, an output matching circuit, an attenuation network, and a signal output end that are electrically connected in sequence; characterized in that, The low-noise amplifier further includes a bypass circuit. The input end of the bypass circuit is connected to the signal input end. The first output end of the bypass circuit is connected to the input end of the power amplifier circuit. The second output end of the bypass circuit is connected to the output end of the power amplifier circuit. The bypass circuit includes a bypass switch circuit and a bypass matching circuit. The input end of the bypass switch circuit serves as the input end of the bypass circuit. The first output end of the bypass switch circuit serves as the first output end of the bypass circuit. The second output end of the bypass switch circuit is connected to the input end of the bypass matching circuit. The output end of the bypass matching circuit serves as the second output end of the bypass circuit. The bypass switch circuit includes a first bypass switch unit and a second bypass switch unit. The input ends of the first bypass switch unit and the second bypass switch unit are connected and jointly serve as the input end of the bypass switch circuit. The output end of the first bypass switch unit serves as the second output end of the bypass switch circuit. The output end of the second bypass switch unit serves as the first output end of the bypass switch circuit. The bypass matching circuit includes a first capacitor, a second capacitor, a third capacitor, a first switching transistor, and a second switching transistor. The first end of the first capacitor is respectively connected to the first end of the second capacitor and the first end of the third capacitor. The second end of the first capacitor is respectively connected to the drain of the first switching transistor and the drain of the second switching transistor. The second end of the second capacitor is connected to the source of the first switching transistor. The second end of the third capacitor is connected to the source of the second switching transistor. The gates of the first switching transistor and the second switching transistor are respectively used to connect to an external logic control circuit. The first end of the first capacitor serves as the input end of the bypass matching circuit. The second end of the first capacitor serves as the output end of the bypass matching circuit.

2. The low-noise amplifier according to claim 1, characterized in that The first bypass switch unit includes a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The source of the third switching transistor is connected to the first end of the first resistor and jointly serves as the input end of the first bypass switch unit. The drain of the third switching transistor is respectively connected to the second end of the first resistor, the first end of the second resistor, and the source of the fourth switching transistor. The drain of the fourth switching transistor is respectively connected to the second end of the second resistor, the source of the fifth switching transistor, the first end of the third resistor, the first end of the fifth resistor, and the drain of the seventh switching transistor. The source of the seventh switching transistor is connected to the second end of the fifth resistor and jointly grounded. The drain of the fifth switching transistor is respectively connected to the second end of the third resistor, the first end of the fourth resistor, and the source of the sixth switching transistor. The drain of the sixth switching transistor is connected to the second end of the fourth resistor and jointly serves as the output end of the first bypass switch unit. The gates of the third switching transistor, the fourth switching transistor, the fifth switching transistor, the sixth switching transistor, and the seventh switching transistor are respectively used to connect to the external logic control circuit.

3. The low-noise amplifier according to claim 1, characterized in that The second bypass switch unit includes an eighth switching transistor, a ninth switching transistor, a tenth switching transistor, a sixth resistor, a seventh resistor, and an eighth resistor; The drain of the eighth switching transistor is connected to the first end of the seventh resistor. The source of the eighth switching transistor is respectively connected to the drain of the ninth switching transistor, the second end of the seventh resistor, and the first end of the eighth resistor. The source of the ninth switching transistor is connected to the second end of the eighth switching transistor and they are grounded together; The source of the tenth switching transistor is respectively connected to the first end of the sixth resistor and the drain of the eighth switching transistor. The drain of the tenth switching transistor is connected to the second end of the sixth resistor and they are jointly used as the output terminal of the second bypass switch unit. The source of the tenth switching transistor is used as the input terminal of the second bypass switch unit; The gates of the eighth switching transistor, the ninth switching transistor, and the tenth switching transistor are respectively used to connect to the external logic control circuit.

4. The low-noise amplifier according to claim 1, characterized in that The power amplifier circuit includes a first amplifier and a second amplifier. The gate of the first amplifier is used as the input terminal of the power amplifier circuit. The source of the first amplifier is grounded. The drain of the first amplifier is connected to the source of the second amplifier. The drain of the second amplifier is used as the output terminal of the power amplifier circuit. The gate of the second amplifier is used to connect to an external bias circuit.

5. The low-noise amplifier according to claim 1, characterized in that The output matching circuit includes a first output matching network and a second output matching network. The input terminal of the first output matching network is used as the input terminal of the output matching circuit. The output terminal of the first output matching network is connected to the input terminal of the second output matching network. The output terminal of the second output matching network is used as the output terminal of the output matching circuit; The first output matching network includes a first inductor, a fourth capacitor, a fifth capacitor, an eleventh switching transistor, and a twelfth switching transistor; The first end of the first inductor is respectively connected to the source of the eleventh switching transistor and the source of the twelfth switching transistor. The second end of the first inductor is respectively connected to the power supply voltage, the first end of the fifth capacitor, and the second end of the sixth capacitor. The second end of the fifth capacitor is connected to the drain of the eleventh switching transistor. The second end of the sixth capacitor is connected to the drain of the twelfth switching transistor. The first end of the first inductor is used as the input terminal of the first output matching network. The source of the twelfth switching transistor is used as the output terminal of the first output matching network; The gates of the eleventh switching transistor and the twelfth switching transistor are respectively used to connect to the external logic control circuit; The second output matching network includes a sixth capacitor, a seventh capacitor, an eighth capacitor, a thirteenth switching transistor, and a fourteenth switching transistor; The first end of the sixth capacitor is respectively connected to the first end of the seventh capacitor and the first end of the eighth capacitor, and the second end of the sixth capacitor is respectively connected to the drain of the thirteenth switching transistor and the drain of the fourteenth switching transistor; the second end of the seventh capacitor is connected to the source of the thirteenth switching transistor, and the second end of the eighth capacitor is connected to the source of the fourteenth switching transistor; The gates of the thirteenth switching transistor and the fourteenth switching transistor are respectively used for connecting to the external logic control circuit.

6. The low-noise amplifier according to claim 1, characterized in that, There are multiple bypass switch circuits. The input ends of the multiple bypass switch circuits are connected to the signal input end, the first output end of the bypass switch circuit is connected to the input end of the power amplifier circuit, and the second output end of the bypass switch circuit is connected to the input end of the bypass matching circuit.

7. A radio frequency chip, characterized in that, The radio frequency chip includes the low-noise amplifier according to any one of claims 1-6.

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