Process, System, and Software for a Maskless Lithography System

Abstract

Embodiments of the systems, methods, and software provided herein pattern a substrate using digital lithography patterning controlled by a field programmable gate array (FPGA). Stage position data is provided from a lithography environment to the FPGA, and this data is loaded from the FPGA into memory. A graphics processing unit reads the data from the memory and calculates instructions based on the data. At least a portion of the substrate positioned on the stage is processed using the instructions provided by the FPGA.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a lithography system. More particularly, embodiments of the present disclosure use a field programmable gate array (FPGA) and an image processing unit to send files readable by each component of a lithography environment, for updating one or more of a mask pattern, device parameters of maskless lithography, and lithography process parameters, and relate to a system, software application, and method for lithography processing.

Background Art

[0002] Maskless lithography is used in the manufacture of semiconductor devices for displays such as liquid crystal displays (LCDs) and light emitting diode displays (LEDs). A large-area substrate such as a flat panel may include a layer of liquid crystal material that forms pixels sandwiched between two plates. When power from a power source is applied to the entire liquid crystal material, the amount of light passing through the liquid crystal material is controlled by pixel positions capable of generating an image. Micro-lithography techniques are utilized to generate electrical features incorporated as part of a portion of the liquid crystal material layer that forms the pixels. According to this technique, a photosensitive photoresist is applied to at least one surface of the substrate. Then, a pattern generator exposes selected regions of the photosensitive photoresist as part of a pattern, causing a chemical change in the photoresist within the selected regions, and preparing the selected regions so that subsequent material removal processes and / or material addition processes generate electrical features.

[0003] Depending on the digital lithography environment, the substrate is placed on the moving stage of the lithography environment and exposed to one or more optical projection modules. This moving stage may have a positional deviation, and this positional deviation is taken into account in order to generate an image pattern used to control each pixel on the micromirror projection device used in one or more optical projection modules. The real-time adjustments used have a large amount of geometry processing power, are costly, are difficult to adapt to the changing pattern complexity, and are difficult to adapt to future upgrades.

[0004] Accordingly, what is needed in the art is an improved lithography environment and lithography process. SUMMARY OF THE INVENTION

[0005] In one embodiment, a method is provided that includes receiving stage position data at a field programmable gate array (FPGA). This data is received into memory from the FPGA and a graphics processing unit (GPU), the data is read from this memory, and instructions are calculated based on this data. Using the instructions provided by the GPU to the FPGA, at least a portion of the substrate disposed on the stage is processed.

[0006] In another embodiment, a non-transitory computer-readable medium is provided that stores instructions for causing a computer system to execute a method of patterning a substrate when executed by a processor. The method includes receiving stage position data at a field programmable gate array (FPGA). This data is received by the memory from the FPGA, the GPU reads the data from the memory, and instructions are calculated based on that data. Using the instructions provided by the GPU to the FPGA, at least a portion of the substrate disposed on the stage is processed.

[0007] In another embodiment, a digital lithography system is provided that includes a processor and a memory that stores instructions that, when executed by the processor, perform a method of patterning a substrate. The method includes detecting at least one attribute of a stage of the lithography system and inputting the at least one attribute into an FPGA. Data from the at least one attribute is loaded from the FPGA into the memory. A GPU reads data from the memory and uses the GPU to compute a set of instructions based on the at least one attribute. At least a portion of the substrate disposed on the stage is patterned using the instructions provided by the FPGA.

[0008] To better understand the above features of the present disclosure, a more specific description of the present disclosure briefly outlined above may be added by referring to each embodiment, some of which are shown in the accompanying drawings. However, it should be noted that these accompanying drawings only show exemplary embodiments and should not be considered as limiting the scope. Other equally valid embodiments may be recognized.

Brief Description of the Drawings

[0009]

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DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, where possible, the same reference numbers have been used to denote the same elements common to each figure. It is contemplated that the elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

[0011] Embodiments of the present disclosure generally relate to a lithography system. More specifically, the present disclosure as a whole relates to a method of patterning a substrate that includes transmitting data to a field programmable gate array (FPGA) and loading this data from the FPGA into a memory. The data in the memory is readable by a graphics processing unit (GPU) and is used to calculate mask characteristics used to provide instructions to the FPGA. The FPGA transmits instructions to an image projection system that patterns the substrate. This method, system, and software are described in the context of a particular process in a lithography environment, such as mask patterning of a substrate, but the methods, systems, and software of the present disclosure are also applicable to other processes of digital lithography.

[0012] FIG. 1 is a schematic diagram of a lithography environment 100. As shown in the figure, the lithography environment 100 includes, but is not limited to, a virtual mask apparatus 102, a measurement apparatus 104, an evaluation apparatus 106, a maskless lithography apparatus 108, a controller 110, a plurality of communication links 101, and a transfer system 103. Each of the lithography environment apparatuses is operable to be connected to each other via the communication link 101. Each of the lithography environment apparatuses is operable to be connected to the controller 110 by the communication link 101. Alternatively, or additionally, each of the lithography environment apparatuses can communicate indirectly by first communicating with the controller 110, followed by the controller communicating with the target lithography environment apparatus. This lithography environment 100 can be arranged in the same area or production facility, or each of the lithography environment apparatuses can be arranged in various areas.

[0013] Each of the virtual mask apparatus 102, the measurement apparatus 104, the evaluation apparatus 106, the maskless lithography apparatus 108, and the controller 110 is indexed and includes an on-board processor and memory, and this memory is configured to store instructions. The communication link 101 includes at least one of a wired connection, a wireless connection, a satellite connection, etc. The communication link 101 further includes transmitting and receiving files and / or data according to the embodiments described herein. The communication link 101 can include temporarily or permanently storing this file or data in the cloud before transferring or copying the file or data to a lithography system tool.

[0014] The maskless lithography apparatus 108 and the measuring apparatus 104 are connected by a transfer system 103. The transfer system is operable to transfer a substrate between the maskless lithography apparatus 108 and the measuring apparatus 104. In one embodiment that can be combined with other embodiments described herein, the transfer system 103 can include a robot or other device connectable to a controller 110 operable to transfer a patterned wafer. In one embodiment that can be combined with other embodiments described herein, the transfer system 103 is physically operable by a user.

[0015] The controller 110 includes a central processing unit (CPU) 112, a graphics processing unit (GPU), and a memory 116. The CPU 112 can be one of any form of computer processor that can be used in an industrial environment for controlling a lithography environment device. The memory 116 is coupled to the CPU 112. The memory 116 can be one or more of easily accessible writable memories such as random access memory (RAM). The controller 110 includes an electronic circuit such as a field programmable gate array (FPGA) 114, and uses this to receive information such as stage position information and send the information to be calculated into instructions readable by one or more processes of the lithography system to execute each aspect of the present disclosure. Although a single FPGA 114 is shown, it is contemplated that two or more FPGAs 114, such as a first FPGA communicatively coupled to a first lithography tool such as a stage, or a second FPGA coupled to a second lithography tool such as one or more image projection systems, are used for a particular process. Each FPGA is configured to control real-time tasks. The controller 110 includes a graphics processing unit (GPU) 120 that includes hardware / firmware capable of receiving data, executing user-defined program instructions on the data, and sending program results. Although a single GPU is shown, it is contemplated that multiple GPUs may be communicatively coupled to the FPGA within the server via a bus such as PCI Express. The GPU 120 operates on a software platform such as the Radeon Open Compute Platform (AMD ROCm) provided by Advanced Micro Devices Inc., which is executed on the Linux operating system. It is contemplated that other computing platforms and operating systems may be adapted by the embodiments described herein.

[0016] Memory 116 can include one or more software applications and stored media data that are used by FPGA 114 to execute the methods described herein. CPU 112 can be a hardware unit or a combination of hardware units that can execute software applications and process data. A purely hardware-controlled system requires customization, which may not be very flexible in an application. On the other hand, a purely software-controlled system may have a long latency in an application that requires frequent time-dependent updates. As used herein, the term "latency" refers to the time obtained by subtracting the time spent by the data-dependent part (algorithm) of a process from the total time spent by the process, and thus is regarded as the time overhead of the process. Depending on the implementation form, heterogeneous processing systems such as a system that uses a GPU to offload and accelerate certain high-frequency algorithms from an FPGA are used. The long latency of a software-controlled system is due to the time required for the FPGA to notify the system software that new input data has been copied to the system RAM and is ready for processing at any time, and the time required for the software to notify the GPU that it is necessary to execute a kernel (e.g., a program and / or an instruction) using this input data, and the time required for the GPU to execute this kernel.

[0017] FIG. 2 is a perspective view of an exemplary maskless lithography apparatus 108, such as a digital lithography system, that can benefit from the embodiments described herein. This maskless lithography apparatus 108 includes a stage 214 and a processing unit 204. The stage 214 is supported by a pair of tracks 216. The substrate 220 is supported by this stage 214. The stage 214 is operable to move along a pair of tracks 216. An encoder 218 is coupled to the stage 214 and provides information on the position of this stage 214 to the controller 110.

[0018] The controller 110 is designed to facilitate the control and automation of various process techniques. The controller 110 is coupled to, or communicates with, the processing unit 204, the stage 214, and the encoder 218. The processing unit 204 and the encoder 218 provide the controller 110 with information regarding substrate processing and substrate alignment. For example, the processing unit 204 provides the controller 110 with information for warning the controller 110 that substrate processing has been completed. The controller 110 facilitates the control and automation of the maskless lithography process based on the design file provided by the interface 230. A design file (or computer instructions), referred to as an image processing design file, readable by the controller 110 determines which tasks should be performed on the substrate. The design file 118 includes mask pattern data. This mask pattern data includes the pattern and code of the mask for monitoring and controlling the processing time and the substrate position. The mask pattern corresponds to the pattern written to the photoresist using electromagnetic radiation.

[0019] The substrate 220 is made of, or includes, any suitable material, such as glass, that is used as part of a flat panel display. In other embodiments that can be combined with other embodiments described herein, the substrate 220 is made of other materials that can be used as part of a flat panel display, or the substrate 220 is made of materials that can be used as part of advanced packaging applications, such as chip packaging. The substrate 220 has a film layer patterned on the substrate, such as by pattern etching, and a photoresist layer formed on the patterned film layer, and this photoresist layer is highly sensitive to electromagnetic radiation, such as ultraviolet (UV) or deep ultraviolet "light". A positive photoresist includes portions of the photoresist that, when exposed to radiation and after a pattern is written into the photoresist using this electromagnetic radiation, are each dissolved in a photoresist developer solution applied to the photoresist. A negative photoresist includes portions of the photoresist that, when exposed to radiation and after a pattern is written into the photoresist using this electromagnetic radiation, will not be dissolved in a photoresist developer solution applied to the photoresist. The chemical composition of the photoresist determines whether the photoresist is a positive photoresist or a negative photoresist. Examples of photoresists include, but are not limited to, at least one of diazonaphthoquinone, phenol formaldehyde resin, poly(methyl methacrylate), poly(methylglutarimide), and SU-8. After exposing the photoresist to electromagnetic radiation, the resist is developed to leave the patterned photoresist on the underlying film layer. The patterned photoresist is then used to pattern-etch the underlying thin film through the openings in the photoresist to form a part of the electronic circuit of the display panel.

[0020] The processing unit 204 is supported by a support 208 such that the processing unit 204 straddles a pair of tracks 216. The support 208 provides an opening 212 for a pair of tracks 216 and a stage 214 to pass under the processing unit 204. The processing unit 204 is a pattern generator configured to receive mask pattern data from an interface 230 and expose a photoresist in a maskless lithography process using one or more image projection systems 206 operable to project a write beam of electromagnetic radiation onto a substrate 220. The pattern generated by the processing unit 204 is projected by the image projection system 206 to expose the photoresist of the substrate 220 to the mask pattern written in the photoresist. During operation, one of the stages 214 moves in the X direction from a loading position to a processing position. The processing position refers to one or more positions of the stage when the stage 214 passes under the processing unit 204. Each stage 214 can move in the Y direction by moving along a track so as to process and / or index a substrate.

[0021] In one embodiment that can be combined with other embodiments described herein, each image projection system 206 includes a spatial light modulator for modulating incident light to generate a desired image. Each spatial light modulator includes a plurality of individually controllable, electrically addressable elements. Each electrically addressable element may be in an "on" position or an "off" position based on correction provided by mask pattern data and a position correction model. When light reaches the spatial light modulator, the electrically addressable elements in the "on" position project a plurality of write beams onto a projection lens (not shown). This projection lens then projects the write beams onto the substrate 220. The electrically addressable elements include, but are not limited to, digital micromirrors, liquid crystal displays (LCDs), liquid crystal on silicon (LCoS) devices, ferroelectric liquid crystal on silicon (FLCoS) devices, microshutters, micro LEDs, vertical cavity surface emitting lasers (VCSELs), liquid crystal displays (LCDs), or any solid radiation source of electromagnetic radiation.

[0022] The mask pattern data includes a mask pattern having one or more polygons corresponding to each portion of the photoresist that is exposed to the electromagnetic radiation projected by the processing unit 204. It should be understood that any polygon shaped to the required shape can be used as the one or more polygons such that the exposed portions form one or more various features within the photoresist.

[0023] FIG. 3 is a schematic diagram of a lithography system 300 having a plurality of image projection systems 206. Although the lithography system 300 is shown as having four image projection systems 206, it is contemplated that other configurations and / or image projection systems may be used instead of, or in addition to, the image projection systems 206 shown in FIG. 3. In operation, each image projection system 206 generates a plurality of writing beams 302 on the surface 304 of the substrate 220. As the coordinate system in FIG. 3 indicates, when the substrate 220 moves in the X direction and / or the Y direction, the writing beams 302 pattern the surface 304 (e.g., the entire surface spanning the substrate 220 from edge to edge). In various embodiments, the number of image projection systems 206 included in the system varies based on factors such as the size of the substrate 220 (as shown in FIG. 2) and / or the speed of the stage 214.

[0024] Each image projection system 206 is individually adjusted for each local area of the substrate to be patterned in real time to achieve pattern uniformity on the substrate. Hierarchical mask data is either embodied within system 300 or converted to a flat format by a software program communicating with this system 300. The flattened mask data is further processed and used with an arrayed parallel image processing writer system to generate high-quality images. In the arrayed parallel image processing writer system, the mask data structure is flattened and divided into fragments of a predefined size and supplied appropriately and evenly to each image projection system 206. The mask data structure includes information indicating the placement of each fragment of mask data associated with each image projection system 206. Further, the mask data structure includes information specifying how features spanning multiple image projection systems 206 will be divided among them. Data placement adjustment is recognized through the mask data structure associated with adjacent mask data regions from the image projection system 206. Mask patterning partially overlaps between adjacent image projection systems 206 so as to blend around the boundaries of the patterning. Each segmented mask data pattern is input into its corresponding image projection system, and each part of the substrate is patterned in one of several possible ways. Each way is selected based on the substrate, a given final device, a given throughput, and other considerations. At the boundaries between adjacent substrate parts, micro mirror pixels are used to correct the overlapping parts or other parts of the pattern. This correction algorithm uses the high-frequency position data of stage 214 provided by encoder 218 and transmits a correction factor to each corresponding image projection system 206. This correction factor may vary depending on the relative image processing position on the substrate. The timing of this correction can be adjusted to detect this correction factor by the time the stage reaches a predefined position where the correction is to be applied and for use by the image projection system 206.

[0025] A method for adjusting data for parallel image processing includes writing a beam on the surface of a substrate, and as the substrate moves in the X and Y directions, the entire surface is patterned by the writing beam of the image projection system 206. During patterning, the controller 110 processes one or more graphical objects on the surface of the substrate. Processing of this graphical object generates one or more graphical objects and / or divides this one or more graphical objects into a plurality of convex polygons. To facilitate the acceleration of parallel image processing, this polygon is tessellated into convex polygons such as convex quadrilaterals and / or convex triangles. This tessellation occurs along the scanning direction. By tessellating each polygon into a lower-level primitive convex quadrilateral, rasterization, which is the second stage of the patterning process, is simplified. This rasterization process uses the geometric data from the tessellation process and the stage position data from the encoder 218 to microscopically shift the pattern and then convert this data into instructions readable by the image projection system 206.

[0026] FIG. 4 is a schematic diagram 400 of a computer system for providing a rasterization application. This rasterization application includes, but is not limited to, a GPU 120, an I / O device interface 230 configured to connect to an I / O device, a network interface 404 configured to transmit data via a communication network, a memory 116, and an FPGA 114, which communicate via an interconnect 406 such as a PCI Express bus within a CPU ASIC. ROCm and application-specific driver software are executed within the operating system.

[0027] FIG. 5 is a schematic diagram 500 of the communication flow between the memory 116, the GPU 120, and the FPGA 114 according to an embodiment described in this specification. Mask pattern data is input by a user to the interface 230. The mask pattern data includes image data such as the design file 118. The design file 118 is usually loaded into the memory prior to the processing of the substrate. As described with reference to FIGS. 2 and 3, when the design file 118 is loaded, the substrate is processed. The encoder 218 extracts information about the position of the stage during processing, and this position data is transmitted to the FPGA 114 at a high frequency in real time (e.g., 502).

[0028] The stage position data is copied to the memory 116, and the FPGA 114 notifies the GPU 120 that this data is available for executing the rasterization algorithm (e.g., 504). This function is made operable by ROCm, which provides the virtual memory address of the GPU register (e.g., "doorbell"). ROCm includes the AMD driver used to control the GPU 120. The virtual memory address of the GPU register points to a location within the GPU 120. The ROCm platform can execute the algorithm of the GPU 120 in real time during substrate processing using the input data from the FPGA 114. The function of directly executing the GPU 120 in real time from the input of the FPGA 114 uses hardware control made operable by the driver. This driver is software that interacts with an operating system such as Linux and communicates directly with the hardware (e.g., FPGA 114). Specifically, this driver uses the virtual memory address provided by ROCm to determine the physical memory address programmed into the FPGA 114 in this case. This physical memory address refers to the bus address within the electronic data connection (e.g., interconnect 406) between the GPU 120, the FPGA 114, and the memory 116, which is used for communication. According to embodiments that can be combined with other embodiments described herein, this bus is PCI Express. It has been found that encoding the driver to reveal the physical address of the doorbell makes the register write from the FPGA 114 available instead of the ROCm software.

[0029] The driver software enables the FPGA 114 to write directly to the GPU registers, and the GPU 120 uses the data to execute kernels (e.g., programs and / or instructions) (e.g., 506). Without using the driver, this process would rely on software to synchronize the reception of input data from the FPGA 114 and the initialization of the GPU algorithm. In kernel startup in a lithography system such as the lithography system described herein, GPU instruction code is loaded before any real-time process. As a result, with each startup, real-time sensor data from the FPGA 114 is transferred to the system memory (RAM), and the FPGA 114 uses this data as input arguments to start the execution of the GPU code. As part of that execution, the GPU reads the input arguments from the RAM, performs calculations to provide a program or instruction, and transfers the output result back to the FPGA 114 (e.g., 508). The FPGA 114 supplies an output that includes instructions for controlling each image projection system 206.

[0030] The method of the present disclosure has been described in connection with receiving data for a rasterization application and outputting instructions, but other applications that use high-frequency data with low latency are also contemplated to benefit from the present disclosure. According to embodiments that can be combined with other embodiments described herein, the method includes detecting at least one attribute of a stage of a lithography system and inputting the at least one attribute into an FPGA. The at least one attribute is loaded from the FPGA into memory, and this attribute is read from the memory by a GPU. The GPU calculates a set of instructions based on the at least one attribute. The lithography apparatus uses this set of instructions from the FPGA to pattern at least a portion of a substrate disposed on the stage. Other processes and / or attributes, such as those described herein, that are not as sensitive to execution timing and / or have large file sizes can be appropriately initiated and / or controlled by software, but have been found to be improved using GPU computing initiated using FPGA control. The GPU computing described herein is useful in high-throughput, latency-sensitive processes such as the rasterization process.

[0031] The longest latency of the process described herein is from about 7200 ns to about 8000 ns, such as about 7500 ns. In comparison, the longest delay when using a low-latency polling technique is about 17000 ns. In the calculations utilized in the lithography system, by developing a driver to eliminate software control and enable direct communication between the FPGA and the GPU, the expected latency range of the FPGA, as well as the longest latency, is reduced. Each embodiment of the present disclosure also reduces the likelihood of long latencies (e.g., the longest latency), which sometimes occur during digital lithography. This consideration is beneficial for operations where the output is to be timed with parallel execution processes that cannot be paused.

[0032] In digital lithography, each execution of the GPU algorithm is completed within 100 μs, achieving sufficient productivity. The total waiting time of the method described in this specification is shorter than about 7.5 μs in a rasterization application, which is a very small part of the total throughput budget. Using an exemplary design file, the calculation time of the upper shape dimensions in a specific design file was compared.

[0033] Since the software is notified when the FPGA writes to the memory, software control is insufficient in such a system, which increases the waiting time for the process. The software notification can be a process of periodically checking for updates (polling) or an interrupt-based notification that can increase the occasional waiting time problem. Eliminating the occasional waiting time problem reduces failures in the process and improves the throughput of the device.

[0034] Each embodiment described in this specification further includes, when executed by a processor, a method of inputting mask pattern data having a plurality of exposure polygons to the FPGA of a digital lithography system and loading this mask pattern data from the FPGA to the memory, and storing instructions for causing a computer system to execute the method in a non-transitory computer-readable medium. The FPGA notifies the graphic processing unit of the mask pattern data loaded into the memory and uses the data from a plurality of image projection systems that receive this mask pattern data. Each image projection system corresponds to a first part of a first substrate and receives an exposure polygon data set corresponding to this first part. The graphic processing unit reads the mask pattern data from the memory and provides instructions to the FPGA for patterning at least the first part of the first substrate using a plurality of image projection systems.

[0035] Briefly, a method is provided that includes providing data from a sensor to a field programmable gate array (FPGA). This data is loaded into memory from the FPGA and a graphics processing unit, data is read from this memory, and a set of instructions is computed based on this data. At least a portion of a substrate disposed on a stage is processed using the instructions provided by the FPGA.

Claims

Claim 1 A method of patterning a substrate, comprising: providing data from a lithography system to a field programmable gate array (FPGA); loading the data from the FPGA into a memory; a graphics processing unit (GPU) calculating a mask data structure based on the data from the memory; the GPU providing instructions to the FPGA using the mask data structure; using the instructions provided by the FPGA to pattern at least a portion of a substrate disposed on a stage ; wherein the lithography system has a plurality of image projection systems, and the mask data structure provided to the FPGA includes information indicating the arrangement of each fragment of mask data supplied to each image projection system, and information specifying how features spanning the plurality of image projection systems are divided among the plurality of image projection systems, and the arrangement of each fragment of the mask data is corrected using high-frequency position data of the stage. Claim 2 The method of claim 1, further comprising positioning the substrate on the stage of the lithography system before patterning the portion of the substrate. Claim 3 The method of claim 1, further comprising reading position data of the stage from an encoder, wherein the data loaded from the FPGA into the memory includes the position data of the stage. Claim 4 The method of claim 1, wherein the FPGA and the GPU are communicatively coupled to transmit and receive the data loaded from the FPGA into the memory to each other. Claim 5 The method of claim 1, wherein patterning the at least a portion of the substrate includes providing instructions to the plurality of image projection systems. Claim 6 The method of claim 1, further comprising determining a physical memory address based on a virtual memory address of a GPU register of the GPU using driver software. Claim 7 The method of claim 6, further comprising programming the physical memory address into the FPGA. Claim 8 The method of claim 6, wherein the virtual memory address is provided by open source software. Claim 9 The method according to claim 6, further comprising directly writing data input from the FPGA to the physical memory address.

10. The method according to claim 1, wherein the GPU operates on a software platform, and the software platform and the application-specific driver are executed on an operating system.

11. The method according to claim 1, wherein a longest time between transmitting a kernel execution request from the FPGA and receiving an instruction from the GPU is 8000 ns.

12. The method according to claim 1, wherein the memory is a random access memory.

13. A non-transitory computer-readable medium storing instructions, which when executed by a processor, cause a computer system to provide data from a lithography system to a field programmable gate array (FPGA); load the data from the FPGA into a memory; calculate a mask data structure by the GPU based on the data from the memory; provide an instruction to the FPGA by the GPU using the mask data structure; pattern at least a portion of a substrate disposed on a stage using the instruction provided by the FPGA and wherein the lithography system has a plurality of image projection systems, and the mask data structure provided to the FPGA includes information indicating an arrangement for each fragment of mask data supplied to each image projection system and information specifying how features spanning the plurality of image projection systems are divided among the plurality of image projection systems, and the arrangement for each fragment of the mask data is corrected using high-frequency position data of the stage.

14. The non-transitory computer-readable medium according to claim 13, wherein calculating the mask data structure further includes forming an actual grid map including actual image positions on the substrate.

15. The non-transitory computer-readable medium according to claim 14, further comprising comparing the actual grid map with a grid model and determining a correction factor for patterning the substrate.

16. The non - transitory computer - readable medium according to claim 13, wherein during patterning, the processor synchronizes the movement of the image projection system and the movement of the stage.

17. The non - transitory computer - readable medium according to claim 13, wherein the FPGA and the GPU are communicatively coupled to transmit and receive the data loaded from the FPGA to the memory to each other.

18. Determining the position of the stage of the lithography system; Calculating mask image correction written to the portion of the substrate based on the data loaded from the FPGA to the memory; The non - transitory computer - readable medium according to claim 13, further comprising.

19. A digital lithography system comprising a processor and a memory storing instructions that, when executed by the processor, perform a method for patterning a substrate, wherein the method comprises: detecting at least one attribute of a stage of a lithography system; inputting the at least one attribute to an FPGA; loading the at least one attribute from the FPGA to a memory; reading the at least one attribute from the memory by a GPU; using the GPU to calculate a mask data structure used to provide a set of instructions based on the at least one attribute; using the instructions provided by the FPGA to pattern at least a portion of a substrate disposed on the stage; wherein the lithography system has a plurality of image projection systems, the mask data structure provided to the FPGA includes information indicating the arrangement of each fragment of mask data supplied to each image projection system, and information specifying how features spanning the plurality of image projection systems are divided among the plurality of image projection systems, and the arrangement of each fragment of the mask data is corrected using high - frequency position data of the stage.

20. The system according to claim 19, wherein the at least one attribute is the position of the stage. ​ ​ ​

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