Display panel and display device

Abstract

A display panel and a display device, the display device comprising a base substrate (1), an insulating layer group (14) and a plurality of binding pins (12), the base substrate (1) having a display area (A) and a binding area (B) located on at least one side of the display area (A), the insulating layer group (14) being provided on one side of the base substrate (1) and having a first recess (61) located in the binding area (B), the plurality of binding pins (12) being provided in the binding area (B), the binding pin (12) having a first binding electrode (93) and a filling portion (101), the first binding electrode (93) being located far from the base substrate (1) of the insulating layer group (14). a first binding electrode (93) having a second recess (94), the orthogonal projection of the second recess (94) onto the base substrate (1) being located within the orthogonal projection of the first recess (61) onto the base substrate (1); the first binding electrode (93) includes at least a first conductor layer (931) and a second conductor layer (932), the first conductor layer (931) being located on the side of the second conductor layer (932) farther from the base substrate (1), the metal activity of the first conductor layer (931) being lower than that of the second conductor layer (932); a filling portion (101) being located on the side of the second recess (94) farther from the base substrate (1), the filling portion (101) being at least partially located within the second recess (94).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a display panel and a display device including the display panel.

Background Art

[0002] With the rapid development of active-matrix organic light-emitting diodes (AMOLEDs), high resolution and narrow bezels have become the direction of industrial development. As the resolution and PPI (Pixels Per Inch, the number of pixels per inch, i.e., pixel density) of the display panel increase, the number of binding electrodes in the binding region also increases, and defects such as displaying dark spots after binding are likely to appear.

[0003] It should be noted that the information disclosed in the above background art section is only for the purpose of enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those skilled in the art.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to overcome the above-mentioned drawbacks of the prior art and provide a display panel and a display device including the display panel.

Means for Solving the Problems

[0005] According to one aspect of the present disclosure, a display panel is provided, a base substrate having a display area and a binding area located on at least one side of the display area, an insulating layer group provided on one side of the base substrate 1 and having a first recess located in the binding area, and a plurality of binding pins provided in the binding area, wherein the binding pin includes a first binding electrode and a filling portion. The first binding electrode is provided on the side of the insulating layer group far from the base substrate. The first binding electrode has a second recess, and the orthographic projection of the second recess on the base substrate is located within the orthographic projection of the first recess on the base substrate. The first binding electrode includes at least a first conductor layer and a second conductor layer arranged in a stacked manner. The first conductor layer is provided on the side of the second conductor layer far from the base substrate, and the metal activity of the first conductor layer is lower than that of the second conductor layer. The filling portion is provided on the side of the second recess far from the base substrate, and the filling portion is at least partially located within the second recess.

[0006] In an exemplary embodiment of the present disclosure, the binding pin further includes a second binding electrode provided between the base substrate and the first binding electrode. The first recess is a first via, and the first binding electrode is connected to the second binding electrode through the first via.

[0007] In an exemplary embodiment of the present disclosure, the binding pin further includes a third binding electrode provided between the first binding electrode and the second binding electrode. The third binding electrode has a third recess, and the orthographic projection of the second recess on the base substrate is located within the orthographic projection of the third recess on the base substrate. The orthographic projection of the third recess on the base substrate is located within the orthographic projection of the first recess on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the display panel further includes a protective layer provided between the first binding electrode and the third binding electrode. The protective layer has a second via, and the third binding electrode is connected to the first binding electrode through the second via.

[0009] In an exemplary embodiment of the present disclosure, the orthographic projection of the third recess on the base substrate is located within the orthographic projection of the second via on the base substrate.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes an insulating portion provided between adjacent binding pins, and a vertical distance from a surface of the insulating portion far from the base substrate to the base substrate is greater than or equal to a vertical distance from a surface of the filling portion far from the base substrate to the base substrate.

[0011] In an exemplary embodiment of the present disclosure, in the display area, the display panel further includes a plurality of sub-pixels, and the sub-pixels include a thin-film transistor, a second planarization layer, and a display element. The second planarization layer is located on a side of the thin-film transistor far from the base substrate so as to cover the thin-film transistor. The display element is located on a side of the second planarization layer far from the base substrate. The second planarization layer has a third via. The thin-film transistor includes an active layer, a gate, a source, a drain, and a connection electrode. The source and the drain are electrically connected to the active layer. The connection electrode is electrically connected to the source or the drain. The connection electrode is electrically connected to the display element through the third via.

[0012] In an exemplary embodiment of the present disclosure, the active layer is provided on one side of the base substrate, the gate is provided on a side of the active layer far from the base substrate, the source and the drain are provided on a side of the gate far from the base substrate, and the connection electrode is provided on a side of the source and the drain far from the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the second binding electrode is provided in the same layer as the gate and made of the same material, the third binding electrode is provided in the same layer as the source and the drain and made of the same material, and the first binding electrode is provided in the same layer as the connection electrode and made of the same material.

[0014] In an exemplary embodiment of the present disclosure, a second planarization layer is provided on the side of the connection electrode far from the base substrate, and the filling portion and the insulating portion are provided in the same layer as the second planarization layer and made of the same material.

[0015] In an exemplary embodiment of the present disclosure, a buffer layer is provided between the base substrate and the active layer, a first gate insulating layer is provided between the active layer and the gate, a second gate insulating layer is provided between the gate and the source and the drain, and an interlayer dielectric layer is provided on the side of the second gate insulating layer far from the base substrate. The insulating layer group is provided in the same layer as the second gate insulating layer and the interlayer dielectric layer and made of the same material, or the insulating layer group is provided in the same layer as the buffer layer and the first gate insulating layer and made of the same material.

[0016] In an exemplary embodiment of the present disclosure, the vertical distance from at least a part of the surface of the first binding electrode far from the base substrate to the base substrate is greater than or equal to the vertical distance from the surface of the filling portion far from the base substrate to the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the first conductor layer has a cutting portion, and the cutting portion is located in the second recess.

[0018] In an exemplary embodiment of the present disclosure, the second conductor layer has a fourth recess facing the cutting portion.

[0019] In an exemplary embodiment of the present disclosure, the number of the cutting portions is two, the number of the corresponding fourth recesses is also two, and a part of the first conductor layer is between the two fourth recesses.

[0020] In an exemplary embodiment of the present disclosure, the first binding electrode further includes a third conductor layer, and the second conductor layer is provided between the third conductor layer and the first conductor layer.

[0021] In an exemplary embodiment of the present disclosure, the third conductor layer and the first conductor layer are made of titanium, and the second conductor layer is made of aluminum.

[0022] According to another aspect of the present disclosure, a display device is provided, which includes the display panel according to any one of the above items.

[0023] According to the display panel of the present disclosure, in the binding region, a first recess is provided on the insulating layer group, and a plurality of binding pins are further provided. The binding pin includes a first binding electrode, and a second recess is formed when the first binding electrode is formed in the first recess. The first binding electrode includes at least a first conductor layer and a second conductor layer arranged in a stacked manner. The first conductor layer is arranged on the side away from the base substrate of the second conductor, and the metal activity of the first conductor layer is lower than that of the second conductor layer. Since the film formation quality in the second recess is poor, the first conductor layer cannot well wrap the second conductor layer. In the subsequent anode etching process, Ag+ (silver ions) in the etching solution undergoes a substitution reaction with the exposed second conductor layer to generate Ag elemental particles, and in this process, the Ag elemental particles progress to the display region of the display panel, resulting in a defect of displaying dark spots. The filling portion is provided on the side away from the base substrate of the second recess and is at least partially located within the second recess. The filling portion can protect the exposed second conductor layer, thereby avoiding the substitution reaction of Ag+ (silver ions) in the etching solution with the exposed second conductor layer to generate Ag elemental particles during the subsequent anode etching, and avoiding the display defect of dark spots caused by the progress of the Ag elemental particles to the display region of the display panel in this process. In addition, the added filling portion can increase the structural strength of the binding pin and further prevent the binding pin from breaking during the binding process.

[0024] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present disclosure.

Brief Description of the Drawings

[0025] The drawings incorporated in the specification and constituting a part of the specification show embodiments consistent with the present disclosure and explain the principles of the present disclosure together with the specification. The drawings in the following description show only some embodiments of the present disclosure, and it is obvious that those skilled in the art can obtain other drawings from these drawings without creative labor.

[0026]

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[0027] Next, exemplary embodiments will be described more comprehensively with reference to the drawings. However, the exemplary embodiments can be embodied in various forms and should not be construed as being limited to the embodiments described herein. In contrast, by providing these embodiments, the present disclosure is comprehensive and complete, and can fully convey the concept of the exemplary embodiments to those skilled in the art. Since the same reference numerals in the drawings represent the same or similar structures, detailed descriptions thereof are omitted. Also, the drawings are only schematic diagrams of the present disclosure and need not be drawn to scale.

[0028] In this specification, relative terms such as "upper" and "lower" are used to describe the relative relationship of one component of an icon to other components. However, in this specification, these terms are used only for convenience and are used to explain according to the directions of the examples shown in the drawings, for example. It is understood that when the device of the icon is reversed, the component described as "upper" will become the component described as "lower". When a certain structure is "above" another structure, it may mean that a certain structure is formed entirely on another structure, or that a certain structure is "directly" arranged on another structure, or that a certain structure is "indirectly" arranged on another structure via another structure.

[0029] The terms "one", "a", "said", "the", and "at least one" are used to represent the existence of one or more elements / components, etc. The terms "comprising" and "having" are used to represent open inclusion, meaning that there may be additional elements / components, etc., in addition to the listed elements / components, etc. The terms "first", "second", "third", etc. are used only as marks and do not limit the number of objects.

[0030] Referring to FIG. 1, the AMOLED display panel pursues a narrow bezel, and is limited by the width of the lower bezel of the display panel. As the resolution and pixel density increase, the number of binding electrodes increases, so it is necessary to make the width of the binding electrodes narrower and narrower. Currently, in order to eliminate the increase in resistance caused by the decrease in the width of the binding electrodes, a multi-layer binding electrode connected in parallel is widely used. When multi-layer binding electrodes (for example, the first binding electrode 93, the second binding electrode 32, and the third binding electrode 73) are connected in parallel, it is necessary to connect the binding electrodes located on both sides of the insulating layer by forming the first via 61 on the insulating layer. Therefore, the first binding electrode 93 formed above the first via 61 forms a second recess 94 in the first via 61. The film formation quality of the first binding electrode 93 on the side wall of the first via 61 is poor, and the upper-layer metal titanium of the first binding electrode 93 forms a cut portion 934. Therefore, the upper-layer metal titanium of the first binding electrode 93 cannot well wrap the metal aluminum. During the subsequent anode etching, Ag+ (silver ions) in the etching solution reacts with the exposed Al to generate Ag elemental particles. However, in this process, the Ag elemental particles advance into the display area A of the display panel, resulting in a defect of displaying dark spots.

[0031] Referring to FIG. 2, a plurality of gate lines 152 and a plurality of data lines 151 are arranged in the display area A of the display panel, and a plurality of binding pins 12 are arranged in the binding area B. The gate lines 152 extend in a first direction, the data lines 151 extend in a second direction, the first direction intersects the second direction, and the plurality of gate lines 152 intersect the plurality of data lines 151 to form a mesh shape. The data lines 151 and the gate lines 152 are connected to the binding pins 12. In the first direction, a plurality of binding pins 12 are arranged in one row, and in the second direction, two rows of binding pins 12 are arranged. Of course, in the second direction, one row of binding pins 12 can also be arranged, and more rows of binding pins 12 can also be arranged.

[0032] Embodiments of the present disclosure provide a schematic structural diagram of a display panel of the present disclosure, as shown in FIGS. 3, 4, 5, 6, and 7. The display panel can include a base substrate 1, an insulating layer group 14, and a plurality of binding pins 12. The base substrate 1 has a display area A and a binding area B provided on at least one side of the display area A. The insulating layer group 14 is provided on one side of the base substrate 1, and a first recess 61 is provided in the insulating layer group 14. The first recess 61 is located within the binding area B. A plurality of binding pins 12 are provided in the binding area B. The binding pin 12 includes a first binding electrode 93 and a filling portion 101. The first binding electrode 93 is provided on the side of the insulating layer group 14 far from the base substrate 1. A second recess 94 is provided in the first binding electrode 93. The orthographic projection of the second recess 94 onto the base substrate 1 is located within the orthographic projection of the first recess 61 onto the base substrate 1. The first binding electrode 93 includes at least a first conductor layer 931 and a second conductor layer 932 arranged in a stacked manner. The first conductor layer 931 is provided on the side of the second conductor layer 932 far from the base substrate 1, and the metal activity of the first conductor layer 931 is lower than that of the second conductor layer 932. The filling portion 101 is provided on the side of the second recess 94 far from the base substrate 1, and the filling portion 101 is at least partially located within the second recess 94.

[0033] In the display panel and the manufacturing method of the display panel of the present disclosure, the filling portion 101 is provided on the side of the second recess 94 far from the base substrate 1 and is at least partially located within the second recess 94. The filling portion 101 can protect the exposed second conductor layer 932. Therefore, during subsequent anode etching, Ag+ (silver ions) in the etching solution is prevented from undergoing a substitution reaction with the exposed second conductor layer 932 to generate Ag elemental particles, and it is avoided that the Ag elemental particles migrate to the display area A of the display panel and cause the defect of displaying dark spots. In addition, the added filling portion 101 can increase the structural strength of the binding pin 12 and further prevent the binding pin 12 from breaking during the binding process.

[0034] In this embodiment, the base substrate 1 can be a glass plate, a quartz plate, a metal plate, a resin plate, or the like. For example, the material of the base substrate 1 can include an organic material, and the organic material can be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 1 can be formed from a plurality of material layers. For example, the base substrate 1 can include a base material, and the material of the base material can be composed of the above materials.

[0035] The buffer layer 2 can be formed as a transition layer on one surface side of the base substrate 1. Thereby, not only can harmful substances in the base substrate 1 be prevented from entering the interior of the display panel, but also the adhesion of the film layer in the display panel to the base substrate 1 can be enhanced. For example, the material of the buffer layer 2 may be silicon oxide, silicon nitride, silicon nitride, or the like.

[0036] The base substrate 1 has a display area A and a peripheral area surrounding at least a part of the display area A. Further, the peripheral area includes at least one binding area B located on at least one side of the display area A. Of course, a plurality of binding areas B may be provided on one side of the display area A, or a plurality of binding areas B may be provided on a plurality of sides of the display area A.

[0037] Referring to FIG. 7, a plurality of binding pins 12 are provided in the binding area B. Referring to FIGS. 7 and 9, a plurality of first vias 61 and a plurality of filling portions 101 are provided in one binding pin.

[0038] The binding pin 12 can include a second binding electrode 32, a third binding electrode 73, and a first binding electrode 93 that are sequentially stacked and arranged. The second binding electrode 32 is closer to the base substrate 1 than the first binding electrode 93. The third binding electrode 73 is connected to the second binding electrode 32 via the first via 61.

[0039] Specifically, as shown in FIG. 11, the second binding electrode 32 is provided on the side of the buffer layer 2 far from the base substrate 1. Referring to FIG. 12, the second gate insulating layer 42 is provided on the side of the second binding electrode 32 far from the base substrate 1, the interlayer dielectric layer 6 is provided on the side of the second gate insulating layer 42 far from the base substrate 1, and the second gate insulating layer 42 and the interlayer dielectric film 6 constitute the insulating layer group 14. That is, the insulating layer group 14 is provided in the same layer as the second gate insulating layer 42 and the interlayer dielectric layer 6 and is made of the same material. A plurality of first vias 61 are provided on the second gate insulating layer 42 and the interlayer dielectric layer 6. The first via 61 forms the first recess 61, and the first via 61 is connected to the second binding electrode 32, that is, the first via 61 penetrates the second gate insulating layer 42 and the interlayer dielectric layer 6. In other exemplary embodiments of the present disclosure, the insulating layer group 14 can include a buffer layer and a first gate insulating layer. That is, the insulating layer group 14 is provided in the same layer and the same material as the buffer layer and the first gate insulating layer. The insulating layer group 14 can also include various insulating layers such as a passivation layer and a planarization layer. That is, the insulating layer group 14 can include one or more insulating layers. For example, it can include one or more of a passivation layer, a planarization layer, a gate insulating layer, and an interlayer dielectric layer. The insulating layer group 14 may be an organic insulating layer, an inorganic insulating layer, or a mixed layer group of an organic insulating layer and an inorganic insulating layer.

[0040] Referring again to FIG. 12, the third binding electrode 73 is provided on the side of the interlayer dielectric layer 6 farther from the base substrate 1. The third binding electrode 73 is electrically connected to the second binding electrode 32 via a plurality of first vias 61. The third binding electrode 73 forms a third recess 74 in the second via 81. Since the third binding electrode 73 fills the sidewall of the first via 61, the orthographic projection of the third recess 74 onto the base substrate 1 is located within the orthographic projection of the first via 61 onto the base substrate 1. Also, a planar portion 75 is formed around the third recess 74.

[0041] The third binding electrode 73 can include a first conductor layer, a second conductor layer, and a third conductor layer. The materials of the first conductor layer and the third conductor layer may be metallic titanium, and the material of the second conductor layer may be metallic aluminum. Of course, the third binding electrode 73 may include only one conductor layer or two conductor layers or more conductor layers.

[0042] Referring to FIG. 13, the protective layer 8 is provided on the side of the third binding electrode 73 farther from the base substrate 1. A plurality of second vias 81 are arranged on the protective layer 8. The protective layer 8 extends to the side of the planar portion 75 of the third binding electrode 73 farther from the base substrate 1. The orthographic projection of the first via 61 onto the base substrate 1 is located within the orthographic projection of the second via 81 onto the base substrate 1, that is, the opening area of the second via 81 is larger than the opening area of the first via 61. Also, the orthographic projection of the third recess 74 onto the base substrate 1 is located within the orthographic projection of the base substrate 1 of the second via 81 so that the contact area between the first binding electrode 93 and the third binding electrode 73 formed later becomes relatively large.

[0043] Referring to FIG. 1, the first binding electrode 93 is provided on the side of the protective layer 8 far from the base substrate 1 and is electrically connected to the third binding electrode 73 through a plurality of second vias 81. The first binding electrode 93 can include a first conductor layer 931, a second conductor layer 932, and a third conductor layer 933. The second conductor layer 932 is provided between the third conductor layer 933 and the first conductor layer 931. The materials of the first conductor layer 931 and the third conductor layer 933 may be metallic titanium, and the material of the second conductor layer 932 may be metallic aluminum. Of course, the first binding electrode 93 may include the first conductor layer 931 and the second conductor layer 932. The first conductor layer 931 covers the second conductor layer 932, that is, the first conductor layer 931 is provided on the side of the second conductor layer 932 far from the base substrate 1. The metal activity of the first conductor layer 931 is lower than that of the second conductor layer 932. The second conductor layer 932 easily undergoes a substitution reaction with Ag+ (silver ions) in the etching solution. The metal activity means the tendency (e.g., the degree of difficulty) of a metal simple substance to lose electrons in the same solution (e.g., water) to form metal cations. The materials of the first conductor layer 931, the second conductor layer 932, and the third conductor layer 933 are only examples and do not constitute a limitation of the present application.

[0044] Since the thicknesses of the second gate insulating layer 42 and the interlayer dielectric layer 6 are large, the depth of the first via 61 formed on the second gate insulating layer 42 and the interlayer dielectric layer 6 is relatively deep. The first binding electrode 93 formed later forms a second recess 94 in the first via 61, and the orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the first via 61 on the base substrate 1. The film formation quality of the first binding electrode 93 formed in the first via 61, particularly the film formation quality of the first conductor layer 931 formed at the corners of the sidewalls and the bottom of the first via 61, is poor. Also, since the thickness of the first conductor layer 932 is originally thin, the finally formed first conductor layer 931 has a cut portion 934 that cannot cover the second conductor layer 932. As shown in FIG. 1, the first conductor layer 931 cannot cover the second conductor layer 932 at the corners of the bottom of the second recess 94, and two cut portions 934 that cause the exposure of aluminum in the second conductor layer 932 are formed. In the subsequent anode etching process, Ag+ (silver ions) in the etching solution undergoes a substitution reaction with the exposed Al to form Ag elemental particles. The Ag elemental particles of this type proceed to the display region A of the display panel during the process and result in a defect of displaying dark spots. Also, due to the action of the etching solution, a fourth recess 935 is further formed on the second conductor layer 932 facing the cut portion 934, that is, the fourth recess 935 is formed on the second conductor layer 932 not covered by the first conductor layer 931, and one, two, or more fourth recesses 935 can be formed. When forming two or more fourth recesses 935, a portion of the first conductor layer 931 remains between two adjacent fourth recesses 935.

[0045] Referring to FIGS. 3, 4, 5, and 6, the filling portion 101 is provided on the side of the second recess 94 far from the base substrate 1, and the filling portion 101 is at least partially located within the second recess 94. For example, as shown in FIG. 3, the orthographic projection of the second recess 94 on the base substrate 1 can be located within the orthographic projection of the filling portion 101 on the base substrate 1, that is, the filling portion 101 extends not only within the second recess 94 but also beyond the edge of the second recess 94 so as to cover the edge of the second recess 94. In this case, the filling portion 101 reliably covers the side wall of the second recess 94 to protect the exposed second conductor layer 932, and avoids generating Ag elemental particles by the substitution reaction between Ag+(silver ions) in the etching solution and the exposed Al during the subsequent anode etching. Thereby, the display defect of dark spots caused by the progress of Ag elemental particles into the display area A of the display panel during this process is avoided. In addition, the added filling portion 101 can increase the structural strength of the binding pin 12, and can further prevent the binding pin 12 from breaking during the binding process.

[0046] Referring to FIGS. 3, 5, and 6, since the filling portion 101 protects the second conductor layer 932, the etching solution does not etch the second conductor layer 932 and does not form the fourth recess 935 during the subsequent anode etching. Referring to FIGS. 4, 8, and 9, because the film forming quality of the second conductor layer 932 formed in the second recess 94 is poor, there is still a possibility that the fourth recess 935 is formed.

[0047] Also, the orthographic projection of the second recess 94 on the base substrate 1 overlaps with the orthographic projection of the filling portion 101 on the base substrate 1. That is, the filling portion 101 covers only the second recess 94. Also in this case, the filling portion 101 surely covers the side wall of the second recess 94 in order to protect the exposed second conductor layer 932, and avoids generating Ag elemental particles due to the substitution reaction between Ag+(silver ions) in the etching solution and the exposed Al during the subsequent anode etching. Thereby, the display defect of dark spots caused by the progress of Ag elemental particles into the display area A of the display panel during this process is avoided. In addition, the added filling portion 101 can increase the structural strength of the binding pin 12, and can further prevent the binding pin 12 from breaking during the binding process.

[0048] Of course, referring to FIG. 4, the orthographic projection of the filling portion 101 on the base substrate 1 may be slightly smaller than the orthographic projection of the second recess 94 on the base substrate 1. Also in that case, the effect of protecting the first binding electrode 93 can be obtained.

[0049] Also, the protective layer 8 extends to the side far from the base substrate 1 of the flat portion 75 of the third binding electrode 73, whereby the base formed by the first binding electrode 93 is not flat, is low at a position close to the third recess 74, and is high at a position far from the third recess 74. Therefore, the height of the portion of the first binding electrode 93 formed subsequently is low at a portion close to the second recess 94 and high at a portion far from the second recess. Thereby, the vertical distance from the surface on the side far from the base substrate 1 of the filling portion 101 formed next to the base substrate 1 is equal to or less than the vertical distance from at least a part of the surface on the side far from the base substrate 1 of the first binding electrode 93 to the base substrate 1. That is, the surface of the filling portion 101 away from the base substrate 1 and at least a part of the surface of the first binding electrode 93 away from the base substrate 1 are substantially in the same plane, or the height of the filling portion 101 is lower than the height of at least a part of the first binding electrode 93, thereby facilitating subsequent binding.

[0050] Note that the structure of the binding pin 12 is not limited to the above. For example, as shown in FIG. 5, the binding pin 12 can include a first binding electrode 93 and a second binding electrode 32, that is, it does not include a third binding electrode 73. The second binding electrode 32 is provided on one side of the base substrate 1, and a second gate insulating layer 42 is provided on the side of the second binding electrode 32 far from the base substrate 1. The interlayer dielectric layer 6 is provided on the side of the second gate insulating layer 42 far from the base substrate 1, and a plurality of first vias 61 are provided on the second gate insulating layer 42 and the interlayer dielectric layer 6. The first via 61 is connected to the second binding electrode 32, that is, the first via 61 penetrates through the second gate insulating layer 42 and the interlayer dielectric layer 6.

[0051] The first binding electrode 93 is provided on the side of the interlayer dielectric layer 6 far from the base substrate 1 and is electrically connected to the second binding electrode 32 through a plurality of first vias 61.

[0052] Since the thicknesses of the second gate insulating layer 42 and the interlayer dielectric layer 6 are large, the depth of the first via 61 formed on the second gate insulating layer 42 and the interlayer dielectric layer 6 is relatively deep. Next, the first binding electrode 93 to be formed forms a second recess 94 in the first via 61, and the orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the first via 61 on the base substrate 1. The film formation quality of the first binding electrode 93 formed in the first via 61, particularly the film formation quality of the first conductor layer 931 formed at the corners of the sidewalls and the bottom of the first via 61, is poor. Also, since the thickness of the first conductor layer 932 is originally thin, the finally formed first conductor layer 931 has a cut portion 934 that cannot cover the second conductor layer 932. For example, since the cut portion 93 is formed at the corner of the bottom of the second recess 944, the first conductor layer 931 cannot cover the second conductor layer 932, that is, at the corner of the bottom of the second recess 94, the first conductor layer 933 cannot cover the second conductor layer 932, exposing the aluminum of the second conductor layer 932. In the subsequent anodic etching process, Ag+ (silver ions) in the etching solution undergoes a substitution reaction with the exposed Al to form Ag elemental particles. During this process, this type of Ag elemental particles advances into the display region A of the display panel, resulting in a defect of displaying dark spots.

[0053] The filling portion 101 is provided on the side of the second recess 94 far from the base substrate 1 and is at least partially located within the second recess 94. For example, the orthographic projection of the second recess 94 on the base substrate 1 can be located within the orthographic projection of the filling portion 101 on the base substrate 1, that is, the filling portion 101 extends not only to the second recess 94 but also beyond the edge of the second recess 94 so as to cover the edge of the second recess 94. In this case, the filling portion 101 reliably covers the side wall of the second recess 94 to protect the exposed second conductor layer 932, and avoids the substitution reaction between Ag+(silver ions) in the etching solution and the exposed Al during the subsequent anode etching to form Ag elemental particles, and avoids the display defect of dark spots caused by the progress of Ag elemental particles into the display area A of the display panel during this process. In addition, the added filling portion 101 can increase the structural strength of the binding pin 12 and further prevent the binding pin 12 from breaking during the binding process.

[0054] The orthographic projection of the second recess 94 on the base substrate 1 can overlap with the orthographic projection of the filling portion 101 of the base substrate 1. That is, the filling portion 101 covers only the second recess 94. Also in this case, the filling portion 101 reliably covers the side wall of the second recess 94 to protect the exposed second conductor layer 932.

[0055] Of course, the orthographic projection of the filling portion 101 on the base substrate 1 can be slightly smaller than the orthographic projection of the second recess 94 on the base substrate, and in that case, the effect of protecting the first binding electrode 93 can also be obtained.

[0056] Furthermore, the binding pin 12 can include only the first binding electrode 93. For example, when a first recess 61 that does not need to be a via is provided on the insulating layer group 14 and the first binding electrode 93 needs to be formed on the side of the first recess 61 far from the base substrate 1, a second recess 94 is also formed in the first binding electrode 93. Due to poor film formation quality, the second conductor layer 932 may not cover the first conductor layer 931 in the second recess 94. Therefore, the filling portion 101 is provided on the first binding electrode 93 to fill and protect the second recess 94 on the first binding electrode 93, thereby avoiding the substitution reaction between Ag+ (silver ions) in the etching solution and the exposed Al during subsequent anode etching to form Ag elemental particles, and avoiding the display defect of dark spots caused by the progress of Ag elemental particles into the display area A of the display panel in this process.

[0057] Referring to FIGS. 7 and 8, the display panel can further include an insulating portion 102 disposed between two adjacent binding pins 12. The vertical distance from the surface of the insulating portion 102 far from the base substrate 1 to the base substrate 1 is equal to or greater than the vertical distance from the surface of the filling portion 101 far from the base substrate 1 to the base substrate 1. The insulating portion 102 serves to insulate two adjacent binding pins 12. The surfaces of the insulating portion 102 and the binding pin 12 far from the base substrate 1 are substantially in the same plane, that is, the height of the insulating portion 102 and the height of the binding pin 12 with respect to the base substrate 1 are basically equal. Alternatively, the surface of the insulating portion 102 far from the base substrate 1 is higher than the surface of the filling portion 101 far from the base substrate 1, that is, the height of the insulating portion is higher than the height of the filling portion 101.

[0058] Note that the "height" is the vertical distance from the surface of the structure (such as the insulating portion 102) far from the base substrate 1 to the base substrate 1.

[0059] As the thickness of the insulating portion 102 increases, the structural strength of the gap portion between the binding pins 12 of the display panels located in different rows can be enhanced, and it is further possible to prevent the gap portion between the binding pins 12 of the display panels located in different rows from breaking during binding.

[0060] The binding region B of the display panel is as described above, and the display region A of the display panel is as follows.

[0061] In the display region A, the display panel can include a plurality of pixel units arranged as an array, each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor and a display element.

[0062] Specifically, in the structure of the thin film transistor, the active layer 5 is provided on the side far from the base substrate 1 of the buffer layer 2. The first gate insulating layer 41 is provided on the side far from the base substrate 1 of the active layer 5, and the material of the first gate insulating layer 41 may be one or two of silicon oxide and silicon nitride. A fourth via connected to the active layer is provided in the first gate insulating layer. The gate 31 is provided on the side far from the base substrate 1 of the first gate insulating layer 41, and the material of the gate 31 may be molybdenum, nickel, nickel manganese alloy, nickel chromium alloy, nickel molybdenum iron alloy, etc. The second gate insulating layer 42 is provided on the side far from the base substrate 1 of the gate 31, and the material of the second gate insulating layer 42 may be one or two of silicon oxide and silicon nitride. A fifth via is provided on the second gate insulating layer 42, and the fifth via is connected to the fourth via. The interlayer dielectric layer 6 is provided on the side far from the base substrate 1 of the second gate insulating layer 42, and the material of the interlayer dielectric layer 6 may be silicon oxide. A sixth via is provided in the interlayer dielectric layer 6, and the sixth via is connected to the fourth via and is also connected to the active layer 5. The source 71 and the drain 72 are provided on the side far from the base substrate 1 of the interlayer dielectric layer 6. The source 71 and the drain 72 are connected to the active layer 5 via the sixth via, the fifth via, and the fourth via, and the materials of the source 71 and the drain 72 can be composed of Ti, Al, and Ti (i.e., three layers of titanium, aluminum, and titanium). The protective layer 8 is provided on the side far from the base substrate 1 of the source 71 and the drain 72. A seventh via 82 is provided on the protective layer 8, and the seventh via 82 can be connected to the source 71 or the drain 72. The first planarization layer 13 is provided on the side far from the base substrate 1 of the protective layer 8. An eighth via is provided on the first planarization layer 13, and the eighth via is connected to the seventh via. The connection electrode 91 is provided on the side far from the base substrate 1 of the first planarization layer 13 and is connected to the source 71 or the drain 72 via the seventh via and the eighth via.

[0063] The second planarization layer 103 is provided on the side of the connection electrode 91 far from the base substrate 1, and the third via 104 is provided on the second planarization layer 103. The display element (not shown) is provided on the side of the second planarization layer 103 far from the base substrate 1, and the display element is connected to the connection electrode 91 via the third via 104.

[0064] The above-described thin film transistor is a top gate type. Of course, in other exemplary embodiments of the present disclosure, the thin film transistor may be a bottom gate type (see FIG. 6) or a double gate type.

[0065] The second binding electrode 32 is provided in the same layer as the gate 31 and made of the same material. The third binding electrode 73 is provided in the same layer as the source 71 and the drain 72 and made of the same material. The first binding electrode 93 is provided in the same layer as the connection electrode 91 and made of the same material. The filling portion 101 and the insulating portion 102 are provided in the same layer as the second planarization layer 103 and made of the same material.

[0066] Of course, when the third binding electrode 73 is not provided, the first binding electrode 93 may be provided in the same layer as the source 71 and the drain 72 and formed of the same material.

[0067] Note that being provided in the same layer and made of the same material means being formed by the same composition process, which will be described in detail in the following method for manufacturing a display panel.

[0068] Furthermore, the embodiments of the present disclosure provide a method for manufacturing a display panel. Referring to the flowchart of the method for manufacturing a display panel shown in FIG. 10, the method for manufacturing a display panel can include the following steps.

[0069] In step S10, a base substrate 1 is provided, and the base substrate 1 has a display area A and a binding area B provided on at least one side of the display area A.

[0070] In step S20, an insulating layer group 14 is formed on one side of the base substrate 1, and a first recess 61 located within the binding region B is formed on the insulating layer group 14.

[0071] In step S30, in the binding region B, a plurality of binding pins 12 are formed on the side of the insulating layer group 14 far from the base substrate 1. Forming the binding pins 12 includes forming a first binding electrode 93 having a second recess 94.

[0072] In step S40, a filling portion 101 that is at least partially located within the second recess 94 is formed on the side of the second recess 94 far from the base substrate 1.

[0073] The orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the first recess 61 on the base substrate 1. The first binding electrode 93 includes at least a first conductor layer 931 and a second conductor layer 932 provided in a stacked manner. The first conductor layer 931 is provided on the side of the second conductor layer 932 far from the base substrate 1. The metal activity of the first conductor layer 931 is lower than that of the second conductor layer 932.

[0074] Referring to FIGS. 11 to 15, each step of the method for manufacturing a display panel will be described in detail.

[0075] Referring to FIG. 11, a base substrate 1 is provided, and a buffer layer 2 is deposited on one side of the base substrate 1.

[0076] An active material layer is formed on the side of the buffer layer 2 far from the base substrate 1, and the material of the active material layer may be SiN, SiO, or a-Si (amorphous silicon). The thickness of SiN is 0.3 μm or more and 0.7 μm or less. The thickness of SiO is 1.0 μm or more and 1.2 μm or less. The thickness of a-Si is about 0.05 μm. Next, dehydrogenate the active material layer so that the hydrogen explosion phenomenon during the excimer laser crystallization (ELA) process does not occur, and the dehydrogenation conditions can be between 300 °C and 350 °C. After dehydrogenation, perform the excimer laser crystallization process to convert amorphous silicon to polycrystalline silicon. Finally, form a silicon island mask using a digital exposure machine or a mask, and then dry-etch the active material layer, and CF4 + O2 can be used for dry etching. Then, wet-etch the silicon island mask to form a silicon island pattern (active layer 5). Form a mask in the channel region and perform ion implantation in the non-channel region to dope polycrystalline silicon to make it conductive, thereby finally forming the active layer 5, and here it can be doped using phosphine or borane.

[0077] The first gate insulating layer 41 is deposited on the side of the active layer 5 far from the base substrate 1, and the first gate insulating film 41 is etched to form a fourth via connected to the active layer 5. A gate material layer is deposited on the side of the first gate insulating layer 41 far from the base substrate 1, and the material of the gate material layer can be molybdenum, nickel, nickel manganese alloy, nickel chromium alloy, nickel molybdenum iron alloy, etc. The thickness of the gate material layer is 0.25 μm or more and 0.3 μm or less. Form a gate mask using a digital exposure machine or a mask, and then perform dry etching using CF4 + O2 to form a gate 31 in the display area A and a second binding electrode 32 in the binding area B, and here a high CF4 + low O2 dry etching mixed gas can be used. Specifically, the flow rate of CF4 may be 2000 sccm to 2500 sccm (standard cubic centimeter per minute), and the flow rate of O2 may be 1000 sccm to 1500 sccm. Then, wet-split the gate mask.

[0078] Referring to FIG. 12, a second gate insulating layer 42 is deposited on the side of the gate 31 away from the base substrate 1.

[0079] An interlayer dielectric layer 6 is deposited on the side of the second gate insulating layer 42 far from the base substrate 1. The interlayer dielectric layer 6 in the display region A is etched to form a sixth via, and the second gate insulating layer 42 is etched to form a fifth via. The sixth via is connected to the fifth via and the fourth via. At the same time, the interlayer dielectric layer 6 in the binding region B and the second gate insulating layer 42 (the interlayer dielectric layer 6 and the second gate insulating layer 42 in the binding region B form an insulating layer group 14) are etched to form a first via 61 connected to the second binding electrode 32. The first via 61 may be square, that is, the cross-section parallel to the base substrate 1 of the first via 61 may be square, and the side length of the first via 61 may be 2 μm or more and 3 μm or less. The first via 61 may be circular, that is, the cross-section parallel to the base substrate 1 of the first via 61 may be circular, and the diameter of the first via 61 may be 2 μm or more and 3 μm or less. Of course, the first via 61 may have other shapes, which will not be described in detail here.

[0080] The first conductor layer 931, the second conductor layer 932, and the third conductor layer 933 are sequentially deposited on the side of the interlayer dielectric layer 6 far from the base substrate 1 to form a source-drain metal layer. The material of the source-drain metal layer is Ti-Al-Ti, that is, the material of the first conductor layer 931 is Ti, the material of the second conductor layer 932 is Al, and the material of the third conductor layer 933 is Ti. Then, the source-drain metal layer is etched to form a source 71 and a drain 72 in the display region A, and a third binding electrode 73 is formed in the binding region B. Of course, the source 71, the drain 72, and the third binding electrode 73 may have a structure of one or two conductor layers.

[0081] Referring to FIG. 13, a protective layer 8 is formed on the side of the base substrate 1 away from the source 71, the drain 72, and the third binding electrode 73. The protective layer 8 is etched to form a seventh via 82 in the display region A and a second via 81 in the binding region B.

[0082] Referring to FIG. 1, in the display region, a first planarization layer 13 is deposited on the side of the protective layer 8 away from the base substrate 1, and the first planar layer 13 is etched to form an eighth via. Next, a first conductor layer 931, a second conductor layer 932, and a third conductor layer 933 are sequentially deposited on the side of the first planarization layer 13 and the protective layer 8 away from the base substrate 1. The first conductor layer 931, the second conductor layer 932, and the third conductor layer 933 form a connection electrode layer. The connection electrode layer is etched to form a connection electrode 91 in the display region A. The connection electrode 91 is connected to the source 71 or the drain 72 via the seventh via and the eighth via, and a first binding electrode 93 is formed in the binding region B. The first binding electrode 93 is connected to the third binding electrode 73 via the second via 81.

[0083] Referring to FIG. 14, a planar material layer 10 is formed on the side of the connection electrode 91 and the first binding electrode 93 away from the base substrate 1. The planar material layer 10 is etched to form a third via 104 in the display region A, a filling portion 101 and an insulating portion 102 in the binding region B, and a gap is formed between the filling portion 101 and the insulating portion 102.

[0084] The material of the planar material layer 10 may be a positive photoresist.

[0085] The specific etching process of the flat material layer 10 is as follows. As shown in FIG. 15, a mask 11 is coated on the side of the flat material layer 10 far from the base substrate 1. The mask 11 has a fully transparent region 114, a semi-transparent region 113, and an opaque region 115. The light transmittance of the fully transparent region 114 is about 100%, the light transmittance of the semi-transparent region 113 is 20% or more and 70% or less, and the light transmittance of the opaque region 115 is about 0%. The orthographic projection of the fully transparent region 114 on the base substrate 1 basically overlaps with the orthographic projection of the third via 104 and the gap on the base substrate 1. The orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the semi-transparent region 113 on the base substrate 1. The remaining part is the opaque region 115.

[0086] The flat material layer 10 covered with the mask 11 is exposed and developed. The flat material 10 facing the fully transparent region 114 is completely removed to form the third via 104 and the gap, and the flat material layer 10 facing the semi-transparent region 113 is partially removed to form the filling portion 101. Since the orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the semi-transparent region 113 on the base substrate 1, the orthographic projection of the second recess 94 on the base substrate 1 is located within the orthographic projection of the formed filling portion 101 on the base substrate 1. Specifically, the distance between the edge of the orthographic projection of the second recess 94 on the base substrate 1 and the edge of the orthographic projection of the second recess 94 on the base substrate 1 is 1 μm or more and 2.5 μm or less.

[0087] Furthermore, in other exemplary embodiments of the present disclosure, as shown in FIG. 16, the mask 11 has a first opaque region 111, a second opaque region 112, and a fully transparent region 114, and the fully transparent region 114 is located between the first opaque region 111 and the second opaque region 112. The first opaque region 111 is provided opposite to the second recess 94, and the orthographic projection of the first opaque region 111 onto the base substrate 1 is located within the orthographic projection of the second recess 94 onto the base substrate 1. Specifically, the distance between the edge of the orthographic projection of the first opaque region 111 on the base substrate 1 and the edge of the orthographic projection of the second recess 94 on the base substrate 1 is 0 μm or more and 0.5 μm or less. Since the length of the side of the first via 61 is 2 μm or more and 3 μm or less, the length of the side of the second recess 94 formed by filling the first via 61 into the first binding electrode 93 becomes smaller, and the first opaque region 111 becomes smaller than the length of the side of the second recess 94. Therefore, when the flat material layer 10 is exposed and developed, light is incident on the flat material layer 10 opposite to the first opaque region 111 by diffraction, and after light irradiation, the flat material layer 10 opposite to the first opaque region 111 is partially removed, and a filling portion 101 for filling the second recess 94 is formed.

[0088] Of course, the orthographic projection of the second recess 94 on the base substrate 1 can overlap with the orthographic projection of the semi-transparent region 113 on the base substrate 1, and the orthographic projection of the first opaque region 111 on the base substrate 1 can overlap with the orthographic projection of the second recess 94 on the base substrate 1, whereby the orthographic projection of the formed filling portion 101 onto the base substrate 1 is overlapped with the orthographic projection of the second recess 94 onto the base substrate 1.

[0089] It should be noted that although each step of the method for manufacturing a display panel in the present disclosure is described in a specific order in the drawings, it does not require or imply that these steps must be executed in a specific order, or that all the steps illustrated must be executed to obtain the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined and executed as one step, and / or one step can be decomposed and executed as multiple steps.

[0090] Furthermore, an embodiment of the present disclosure further provides a display device that can include the display panel described in any of the above. Since the specific configuration of the display panel has been described in detail above, it will not be described here.

[0091] The specific type of the display device is not particularly limited, but can particularly be a mobile device such as a mobile phone, a wearable device such as a wristwatch, a VR device, etc. Those skilled in the art can make corresponding selections according to the specific use of the display device, and will not be described further here.

[0092] In addition to the display panel, taking the display as an example, it should be noted that it specifically includes necessary components and configurations such as a housing, a circuit board, a power line, etc. Those skilled in the art can make corresponding supplements according to the specific use requirements of the display device, and will not be described further here.

[0093] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the display panel provided by the above-described exemplary embodiments, and will not be described further here.

[0094] After those skilled in the art implement the present invention considering the descriptions disclosed in this specification, they can easily conceive of other embodiments of the present disclosure. This application aims to cover modifications, uses, or adaptive changes of the present disclosure that follow the general principles of the present disclosure and include common general knowledge or general technical means in the technical field not disclosed in the present disclosure. The specification and examples are only considered illustrative, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A base substrate having a display area and a binding area located on at least one side of the display area, An insulating layer group provided on one side of the base substrate and having a first recess located in the binding area, A plurality of binding pins provided in the binding area, The binding pin includes a first binding electrode and a filling portion, The first binding electrode is provided on the side of the insulating layer group far from the base substrate. The first binding electrode has a second recess, and the orthographic projection of the second recess on the base substrate is located within the orthographic projection of the first recess on the base substrate. The first binding electrode includes at least a first conductor layer and a second conductor layer arranged in a stacked manner. The first conductor layer is provided on the side of the second conductor layer far from the base substrate, and the metal activity of the first conductor layer is lower than that of the second conductor layer. The filling portion is provided on the side of the second recess far from the base substrate, and the filling portion is at least partially located within the second recess. The first conductor layer has a cutting portion, and the cutting portion is located within the second recess. A display panel characterized by the above.

2. The binding pin further includes A second binding electrode provided between the base substrate and the first binding electrode. The first recess is a first via, and the first binding electrode is connected to the second binding electrode through the first via. The display panel according to claim 1, characterized by the above.

3. The binding pin further includes A third binding electrode provided between the first binding electrode and the second binding electrode. The third binding electrode has a third recess, and the orthographic projection of the second recess on the base substrate is located within the orthographic projection of the third recess on the base substrate. The orthographic projection of the third recess on the base substrate is located within the orthographic projection of the first recess on the base substrate. The display panel according to claim 2, characterized by the above.

4. The display panel further includes a protective layer provided between the first binding electrode and the third binding electrode. The protective layer has a second via, and the third binding electrode is connected to the first binding electrode through the second via. The display panel according to claim 3, characterized in that...

5. The orthographic projection of the third recess on the base substrate is located within the orthographic projection of the second via on the base substrate. The display panel according to claim 4, characterized in that...

6. Further comprising an insulating portion provided between adjacent binding pins, The vertical distance from the surface of the insulating portion far from the base substrate to the base substrate is greater than or equal to the vertical distance from the surface of the filling portion far from the base substrate to the base substrate. The display panel according to claim 4, characterized in that...

7. In the display area, the display panel further comprises a plurality of sub-pixels, and the sub-pixels include a thin film transistor, a second planarization layer, and a display element. The second planarization layer is located on the side of the thin film transistor far from the base substrate so as to cover the thin film transistor. The display element is located on the side of the second planarization layer far from the base substrate. The second planarization layer has a third via. The thin film transistor includes an active layer, a gate, a source, a drain, and a connection electrode. The source and the drain are electrically connected to the active layer, the connection electrode is electrically connected to the source or the drain, and the connection electrode is electrically connected to the display element through the third via. The display panel according to claim 6, characterized in that...

8. The active layer is provided on one side of the base substrate, the gate is provided on the side of the active layer far from the base substrate, the source and the drain are provided on the side of the gate far from the base substrate, and the connection electrode is provided on the side of the source and the drain far from the base substrate. The display panel according to claim 7, characterized in that...

9. The second binding electrode is provided in the same layer as the gate and made of the same material. The third binding electrode is provided in the same layer as the source and the drain and made of the same material. The first binding electrode is provided in the same layer as the connection electrode and made of the same material. The display panel according to claim 7, characterized in that...

10. The second planarization layer is provided on the side of the connection electrode far from the base substrate. The filling portion and the insulating portion are provided in the same layer as the second planarization layer and made of the same material. The display panel according to claim 7, characterized in that...

11. A buffer layer is provided between the base substrate and the active layer, a first gate insulating layer is provided between the active layer and the gate, a second gate insulating layer is provided between the gate and the source and the drain, and an interlayer dielectric layer is provided on the side of the second gate insulating layer farther from the base substrate. The insulating layer group is provided in the same layer as the second gate insulating layer and the interlayer dielectric layer and is made of the same material. The display panel according to claim 7, characterized in that.

12. The vertical distance from at least a part of the surface of the first binding electrode farther from the base substrate to the base substrate is equal to or greater than the vertical distance from the surface of the filling portion farther from the base substrate to the base substrate. The display panel according to claim 1, characterized in that.

13. The second conductor layer has a fourth recess facing the cutting portion. The display panel according to claim 1, characterized in that.

14. The number of the cutting portions is two, the number of the corresponding fourth recesses is also two, and a part of the first conductor layer is between the two fourth recesses. The display panel according to claim 13, characterized in that.

15. The first binding electrode further includes a third conductor layer, and the second conductor layer is provided between the third conductor layer and the first conductor layer. The display panel according to claim 1, characterized in that.

16. The third conductor layer and the first conductor layer are made of titanium, and the second conductor layer is made of aluminum. The display panel according to claim 15, characterized in that.

17. A display device including the display panel according to any one of claims 1 to 16.

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