Indicating device

Abstract

To provide a display device which offers appropriate display characteristic.SOLUTION: A display device is provided, comprising a substrate, multiple first light-emitting elements and multiple second light-emitting elements provided in a display area of the substrate, a first lens overlapping each of the multiple first light-emitting elements and having a first diameter in plan view from a direction perpendicular to the substrate, and a second lens overlapping each of the multiple second light-emitting elements and having a second diameter smaller than the first diameter in plan view from the direction perpendicular to the substrate.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] Display devices using micro-sized light-emitting diodes (micro LEDs) as display elements have attracted attention (see, for example, Patent Document 1). Patent Document 1 describes a technique for changing the emission light distribution in a display area by tilting a light-emitting element and mounting it on an array substrate. Patent Document 2 provides a plurality of microlenses arranged on a predetermined curved surface facing each pixel of the display device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In displays using micro-sized light-emitting diodes, suitable display characteristics such as a high viewing angle and high brightness are required. In Patent Document 1, the process of transferring a light-emitting element to an array substrate may become difficult. In Patent Document 2, since the light emitted from a plurality of microlenses is arranged to converge on the eye, a large brightness can be obtained in the front direction, but the brightness in directions other than the front direction may decrease.

[0005] An object of the present invention is to provide a display device capable of realizing suitable display characteristics.

Means for Solving the Problems

[0006] A display device according to one aspect of the present invention includes a substrate, a plurality of first light-emitting elements and a plurality of second light-emitting elements provided in a display area of the substrate, a first lens provided to overlap each of the plurality of first light-emitting elements and having a first diameter in a plan view from a direction perpendicular to the substrate, and a second lens provided to overlap each of the plurality of second light-emitting elements and having a second diameter smaller than the first diameter in a plan view from a direction perpendicular to the substrate.

Brief Description of Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the content described in the following embodiments. Further, the constituent elements described below include those that can be easily assumed by those skilled in the art and substantially the same ones. Furthermore, the constituent elements described below can be combined as appropriate. Note that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, the same reference numerals may be given to the same elements as those described above with respect to the previously shown drawings, and detailed descriptions may be omitted as appropriate.

[0009] In this specification and the claims, when expressing the aspect of arranging one structure on another structure, when simply expressed as "on", unless otherwise specified, it includes both the case of arranging another structure directly on a certain structure in contact with it and the case of arranging another structure above a certain structure via still another structure.

[0010] (First Embodiment) FIG. 1 is a plan view schematically showing a display device according to the first embodiment. As shown in FIG. 1, the display device 1 includes an array substrate 2, pixels PX, a driving circuit 12, a driving IC (Integrated Circuit) 210, and a cathode wiring 60. The array substrate 2 is a driving circuit substrate for driving each pixel PX, and is also called a backplane or an active matrix substrate. The array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitors, and various wirings.

[0011] As shown in FIG. 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged overlapping a plurality of pixels PX and displays an image. The peripheral area GA is an area that does not overlap with the plurality of pixels PX and is arranged outside the display area AA.

[0012] The plurality of pixels PX are arranged in a first direction Dx and a second direction Dy in the display area AA of the substrate 21. Note that the first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect the second direction Dy without being orthogonal. A third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. Hereinafter, a plan view means a positional relationship when viewed from the third direction Dz.

[0013] In the display device 1 of the first embodiment, the display area AA includes a first area AAs1 and a plurality of second areas AAs2. The first area AAs1 is located at the center of the display area AA in the first direction Dx. The plurality of second areas AAs2 are located at the outer edge of the display area AA in the first direction Dx and are provided along the side extending in the second direction Dy of the display area AA. The first area AAs1 is provided between the plurality of second areas AAs2 in the first direction Dx. The display area AA is arranged in the order of the second area AAs2, the first area AAs1, and the second area AAs2 in the first direction Dx.

[0014] Note that the arrangements of the first region AAs1 and the second region AAs2 shown in FIG. 1 are merely examples, and can be appropriately changed according to the display characteristics (viewing angle, luminance, etc.) required for the display device 1. For example, the second region AAs2 may be provided along one side of the display region AA, or may be provided to surround the first region AAs1 along the four sides of the display region AA. Further, in FIG. 1, only a part of the pixels PX in the display region AA is shown, but a plurality of pixels PX are arranged in a matrix across the first region AAs1 and the second region AAs2.

[0015] The drive circuit 12 is a circuit that drives a plurality of gate lines (for example, a reset control signal line L5, an output control signal line L6, a pixel control signal line L7, an initialization control signal line L8 (see FIG. 3)) based on various control signals supplied via wirings drawn from the drive IC 210. The drive circuit 12 sequentially or simultaneously selects a plurality of gate lines, and supplies a gate drive signal to the selected gate lines. Thereby, the drive circuit 12 selects a plurality of pixels PX connected to the gate lines.

[0016] The drive IC 210 is a circuit that controls the display of the display device 1. A plurality of wirings are drawn from the drive IC 210 toward a plurality of pixels PX (for example, a video signal line L2, a reset power supply line L3, and an initialization power supply line L4 (see FIG. 3)). The drive IC 210 is mounted as a COG (Chip On Glass) in the peripheral region GA of the substrate 21. However, it is not limited thereto, and the drive IC 210 may be mounted on a flexible printed circuit board or a rigid board connected to the peripheral region GA of the substrate 21.

[0017] The cathode wiring 60 is provided in the peripheral region GA of the substrate 21. The cathode wiring 60 is provided to surround a plurality of pixels PX in the display region AA and the drive circuit 12 in the peripheral region GA. The cathodes of the plurality of light emitting elements 3 are connected to a common cathode wiring 60, and a fixed potential (for example, a ground potential) is supplied. More specifically, the cathode electrode 32 (see FIG. 4) of the light emitting element 3 is connected to the cathode wiring 60 via the counter cathode electrode 22 (see FIG. 4) formed on the array substrate 2.

[0018] FIG. 2 is a plan view showing a plurality of pixels. As shown in FIG. 2, one pixel PX includes a plurality of sub-pixels 49. For example, the pixel PX has a sub-pixel 49R, a sub-pixel 49G, and a sub-pixel 49B. The sub-pixel 49R displays the primary color red as the first color. The sub-pixel 49G displays the primary color green as the second color. The sub-pixel 49B displays the primary color blue as the third color. As shown in FIG. 2, in one pixel PX, the sub-pixel 49R and the sub-pixel 49B are arranged in the first direction Dx. Also, the sub-pixel 49B and the sub-pixel 49G are arranged in the second direction Dy. Note that the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as complementary colors can be selected. Hereinafter, when it is not necessary to distinguish the sub-pixel 49R, the sub-pixel 49G, and the sub-pixel 49B from each other, they are simply referred to as the sub-pixel 49.

[0019] The sub-pixel 49 has a light-emitting element 3 and an anode connection electrode 23, respectively. A first lens 71 (or a second lens 72 (see FIG. 5)) is provided so as to overlap the light-emitting element 3. The display device 1 displays an image by emitting different lights for each of the light-emitting elements 3R, 3G, and 3B in the sub-pixels 49R, 49G, and 49B. The light-emitting element 3 is an inorganic light-emitting diode (LED: Light Emitting Diode) chip having a size of about 3 μm or more and 300 μm or less in a plan view, and is called a micro LED. The display device 1 including a micro LED in each pixel is also called a micro LED display device. Note that the micro of the micro LED does not limit the size of the light-emitting element 3.

[0020] Note that the detailed configurations of the light-emitting element 3 and the first lens 71 will be described later. Also, the plurality of light-emitting elements 3 may emit four or more different lights. Also, the arrangement of the plurality of sub-pixels 49 is not limited to the configuration shown in FIG. 2. For example, the sub-pixel 49R may be adjacent to the sub-pixel 49G in the second direction Dy. Also, the sub-pixels 49R, 49G, and 49B may be repeatedly arranged in this order in the first direction Dx.

[0021] FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 3 shows a pixel circuit PICA provided in one sub-pixel 49, and the pixel circuit PICA is provided in each of a plurality of sub-pixels 49. As shown in FIG. 3, the pixel circuit PICA includes a light-emitting element 3, five transistors, and two capacitors. Specifically, the pixel circuit PICA includes a driving transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The driving transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are each composed of an n-type TFT (Thin Film Transistor). Further, the pixel circuit PICA includes a first capacitor Cs1 and a second capacitor Cs2.

[0022] The cathode (cathode electrode 32) of the light-emitting element 3 is connected to the cathode power line L10. Also, the anode (anode electrode 33) of the light-emitting element 3 is connected to the anode power line L1 via the anode connection electrode 23, the driving transistor DRT, and the output transistor BCT. An anode power potential PVDD is supplied to the anode power line L1. A cathode power potential PVSS is supplied to the cathode power line L10 via the cathode wiring 60 and the cathode electrode 32. The anode power potential PVDD is a potential higher than the cathode power potential PVSS.

[0023] The anode power line L1 supplies the anode power potential PVDD, which is a driving potential, to the sub-pixel 49. Specifically, ideally, the light-emitting element 3 emits light by being supplied with a forward current (driving current) due to the potential difference (PVDD - PVSS) between the anode power potential PVDD and the cathode power potential PVSS. That is, the anode power potential PVDD has a potential difference for causing the light-emitting element 3 to emit light with respect to the cathode power potential PVSS. The anode electrode 33 of the light-emitting element 3 is electrically connected to the anode connection electrode 23, and the second capacitor Cs2 is formed between the anode connection electrode 23 and the anode power line L1.

[0024] The source electrode of the driving transistor DRT is connected to the anode electrode 33 of the light-emitting element 3 via the anode connection electrode 23, and the drain electrode is connected to the source electrode of the output transistor BCT. The gate electrode of the driving transistor DRT is connected to the first capacitor Cs1, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

[0025] The gate electrode of the output transistor BCT is connected to the output control signal line L6. An output control signal BG is supplied to the output control signal line L6. The drain electrode of the output transistor BCT is connected to the anode power supply line L1.

[0026] The source electrode of the initialization transistor IST is connected to the initialization power supply line L4. An initialization potential Vini is supplied to the initialization power supply line L4. The gate electrode of the initialization transistor IST is connected to the initialization control signal line L8. An initialization control signal IG is supplied to the initialization control signal line L8. That is, when the initialization transistor IST is turned on, the initialization power supply line L4 is connected to the gate electrode of the driving transistor DRT via the initialization transistor IST.

[0027] The source electrode of the pixel selection transistor SST is connected to the video signal line L2. A video signal Vsig is supplied to the video signal line L2. The pixel control signal line L7 is connected to the gate electrode of the pixel selection transistor SST. A pixel control signal SG is supplied to the pixel control signal line L7.

[0028] The source electrode of the reset transistor RST is connected to the reset power supply line L3. A reset power supply potential Vrst is supplied to the reset power supply line L3. The gate electrode of the reset transistor RST is connected to the reset control signal line L5. A reset control signal RG is supplied to the reset control signal line L5. The drain electrode of the reset transistor RST is connected to the anode connection electrode 23 (the anode electrode 33 of the light-emitting element 3) and the source electrode of the drive transistor DRT. By the reset operation of the reset transistor RST, the voltages held in the first capacitor Cs1 and the second capacitor Cs2 are reset.

[0029] A first capacitor Cs1 is formed between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress fluctuations in the gate voltage due to the parasitic capacitance and leakage current of the drive transistor DRT by the first capacitor Cs1 and the second capacitor Cs2.

[0030] In the following description, the anode power supply line L1 and the cathode power supply line L10 may be simply referred to as the power supply line. The video signal line L2, the reset power supply line L3, and the initialization power supply line L4 may be referred to as the signal line. The reset control signal line L5, the output control signal line L6, the pixel control signal line L7, and the initialization control signal line L8 may be referred to as the gate line.

[0031] A potential corresponding to the video signal Vsig (or the gradation signal) is supplied to the gate electrode of the drive transistor DRT. That is, the drive transistor DRT supplies a current corresponding to the video signal Vsig to the light-emitting element 3 based on the anode power supply potential PVDD supplied via the output transistor BCT. Thus, since the anode power supply potential PVDD supplied to the anode power supply line L1 drops by the drive transistor DRT and the output transistor BCT, a potential lower than the anode power supply potential PVDD is supplied to the anode electrode 33 of the light-emitting element 3.

[0032] An anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 via an anode power supply line L1, and a potential lower than the anode power supply potential PVDD is supplied to the other electrode of the second capacitor Cs2. That is, a potential higher than that of the other electrode of the second capacitor Cs2 is supplied to one electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example, a counter electrode 25 connected to the anode power supply line L1 shown in FIG. 4, and the other electrode of the second capacitor Cs2 is an anode connection electrode 23 connected to the source of the drive transistor DRT shown in FIG. 4.

[0033] In the display device 1, the drive circuit 12 (see FIG. 1) sequentially selects a plurality of pixel rows starting from the top row (for example, the pixel row located at the uppermost part in the display area AA in FIG. 1). The drive IC 210 writes a video signal Vsig (video writing potential) to the sub-pixels 49 of the selected pixel row to cause the light-emitting element 3 to emit light. The drive IC 210 supplies the video signal Vsig to the video signal line L2, supplies the reset power supply potential Vrst to the reset power supply line L3, and supplies the initialization potential Vini to the initialization power supply line L4 every horizontal scanning period. The display device 1 repeats these operations for each frame of the image.

[0034] Next, the cross-sectional structure of the display device 1 will be described. FIG. 4 is a cross-sectional view taken along the line IV-IV' of FIG. 2. As shown in FIG. 4, the light-emitting element 3 is provided on the array substrate 2. The array substrate 2 has a substrate 21, various transistors, various wirings, and various insulating films. The substrate 21 is an insulating substrate, and for example, a glass substrate, a resin substrate, or a resin film is used.

[0035] In this specification, in the direction perpendicular to the surface of the substrate 21, the direction from the substrate 21 toward the light-emitting element 3 is referred to as "upper side" or simply "up". Also, the direction from the light-emitting element 3 toward the substrate 21 is referred to as "lower side" or simply "down".

[0036] An undercoat film 91 is provided on the substrate 21. The undercoat film 91 has, for example, a three-layer laminated structure including insulating films 91a, 91b, and 91c. The insulating film 91a is a silicon oxide film, the insulating film 91b is a silicon nitride film, and the insulating film 91c is a silicon oxide film.

[0037] The configuration of the undercoat film 91 is not limited to that shown in FIG. 4. For example, the undercoat film 91 may be a single-layer film or a two-layer laminated film, or may be laminated with four or more layers. Further, when the substrate 21 is a glass substrate, since the silicon nitride film has relatively good adhesion, a silicon nitride film may be directly formed on the substrate 21.

[0038] The light-shielding film 65 is provided on the insulating film 91a. The light-shielding film 65 is provided between the semiconductor layer 61 and the substrate 21. By the light-shielding film 65, the intrusion of light from the substrate 21 side into the channel region 61a of the semiconductor layer 61 can be suppressed. Alternatively, by forming the light-shielding film 65 with a conductive material and applying a predetermined potential, a back-gate effect can be given to the driving transistor DRT. Note that the light-shielding film 65 may be provided on the substrate 21, and the insulating film 91a may be provided to cover the light-shielding film 65.

[0039] The driving transistor DRT is provided on the undercoat film 91 on the main surface side of the substrate 21. In FIG. 4, one driving transistor DRT is shown corresponding to the light-emitting element 3, but the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST (see FIG. 3) included in the pixel circuit PICA are also formed with the same laminated structure as the driving transistor DRT.

[0040] The semiconductor layer 61 is provided on the undercoat film 91. The semiconductor layer 61 has a channel region 61a, a source region 61b, a drain region 61c, and a low-concentration impurity region 61d. The low-concentration impurity region 61d is provided between the channel region 61a and the source region 61b, and is also provided between the channel region 61a and the drain region 61c.

[0041] The gate insulating film 92 is provided on the undercoat film 91 covering the semiconductor layer 61. The gate insulating film 92 is, for example, a silicon oxide film. The gate electrode 64 is provided on the gate insulating film 92. Further, the first wiring 66 is provided in the same layer as the gate electrode 64. The gate electrode 64 and the first wiring 66 are made of, for example, molybdenum tungsten (MoW).

[0042] In the example shown in FIG. 4, the driving transistor DRT has a top gate structure in which the gate electrode 64 is provided above the semiconductor layer 61. However, the present invention is not limited to this, and the driving transistor DRT may have a bottom gate structure in which the gate electrode 64 is provided below the semiconductor layer 61, or a dual gate structure in which the gate electrodes 64 are provided on both the upper and lower sides of the semiconductor layer 61.

[0043] The interlayer insulating film 93 is provided on the gate insulating film 92 covering the gate electrode 64. The interlayer insulating film 93 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 93. The source electrode 62 is connected to the source region 61b through contact holes provided in the gate insulating film 92 and the interlayer insulating film 93. The drain electrode 63 is connected to the drain region 61c through contact holes provided in the gate insulating film 92 and the interlayer insulating film 93. A second wiring 67 serving as a lead wiring is connected to the source electrode 62. The source electrode 62, the drain electrode 63, and the second wiring 67 can adopt, for example, a three-layer laminated structure of titanium (Ti), aluminum (Al), and titanium (Ti).

[0044] A part of the second wiring 67 is formed in a region overlapping the first wiring 66. The first capacitance Cs1 is formed by the first wiring 66 and the second wiring 67 facing each other through the interlayer insulating film 93. Further, the first wiring 66 is formed in a region overlapping a part of the semiconductor layer 61. The first capacitance Cs1 also includes a capacitance formed by the semiconductor layer 61 and the first wiring 66 facing each other through the gate insulating film 92.

[0045] The first organic insulating film 94 is provided on the interlayer insulating film 93 so as to cover the driving transistor DRT and the second wiring 67. As the first organic insulating film 94, an organic material such as photosensitive acrylic is used. The organic material such as photosensitive acrylic is superior in coverage of wiring steps and surface flatness compared with the inorganic insulating material formed by CVD or the like.

[0046] On the first organic insulating film 94, the counter electrode 25, the capacitive insulating film 95, and the anode connection electrode 23 are laminated in this order. The counter electrode 25 is made of a conductive material having translucency such as ITO (Indium Tin Oxide), for example. Although not shown, the counter electrode 25 is connected to the anode power line L1 (see FIG. 3) at the bottom of the contact hole provided in the first organic insulating film 94. A connection electrode 26a is provided in the same layer as the counter electrode 25. The connection electrode 26a is provided so as to cover the inside of the contact hole H1 provided in the first organic insulating film 94, and is connected to the second wiring 67 at the bottom of the contact hole H1.

[0047] The capacitive insulating film 95 is provided so as to cover the counter electrode 25 and the connection electrode 26a, and has an opening in a region overlapping with the contact hole H1. The capacitive insulating film 95 is, for example, a silicon nitride film. The anode connection electrode 23 faces the counter electrode 25 with the capacitive insulating film 95 interposed therebetween. The anode connection electrode 23 is electrically connected to the connection electrode 26a and the second wiring 67 through the contact hole H1. Thereby, the anode connection electrode 23 is electrically connected to the driving transistor DRT.

[0048] The anode connection electrode 23 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). However, it is not limited thereto, and the anode connection electrode 23 may be a material containing any one or more of molybdenum and titanium metals. Alternatively, the anode connection electrode 23 may be an alloy containing any one or more of molybdenum and titanium, or a translucent conductive material. Also, a second capacitance Cs2 is formed between the anode connection electrode 23 and the counter electrode 25 facing each other with the capacitive insulating film 95 interposed therebetween.

[0049] The second organic insulating film 97 is provided on the anode connection electrode 23. The same organic material as that of the first organic insulating film 94 is used for the second organic insulating film 97. The mounting electrode 24 is provided on the second organic insulating film 97 and is electrically connected to the anode connection electrode 23 through the contact hole H2. The mounting electrode 24 has a stacked structure of titanium and aluminum similar to that of the anode connection electrode 23. However, a conductive material different from that of the anode connection electrode 23 may be used for the mounting electrode 24. Also, an organic material different from that of the first organic insulating film 94 may be used for the second organic insulating film 97.

[0050] The light-emitting elements 3R, 3G, and 3B are mounted on the corresponding mounting electrodes 24. Each light-emitting element 3 is mounted such that the anode electrode 33 contacts the mounting electrode 24. The joining member 28 between the anode electrode 33 and the mounting electrode 24 of each light-emitting element 3 is not particularly limited as long as good conduction can be ensured between the two and the formation on the array substrate 2 is not damaged. The joining member 28 is, for example, solder or a conductive paste. Examples of the joining of the anode electrode 33 and the mounting electrode 24 include a reflow process using a low-temperature melting solder material and a method of baking and bonding after placing the light-emitting element 3 on the array substrate 2 via a conductive paste.

[0051] The light-emitting element 3 has a semiconductor layer 31, a cathode electrode 32, and an anode electrode 33. The semiconductor layer 31 can adopt a structure in which an n-type clad layer, an active layer, and a p-type clad layer are stacked. For the semiconductor layer 31, compound semiconductors such as gallium nitride (GaN), aluminum indium phosphide (AlInP), and indium gallium nitride (InGaN) are used, for example. Different materials may be used for the semiconductor layer 31 for each of the light-emitting elements 3R, 3G, and 3B. Also, as the active layer, a multiple quantum well structure (MQW structure) in which a well layer and a barrier layer each composed of several atomic layers are periodically stacked may be adopted for high efficiency.

[0052] An element insulating film 98 is provided between a plurality of light-emitting elements 3. The element insulating film 98 is formed of a resin material. The element insulating film 98 covers at least the side surfaces of the light-emitting elements 3, and the cathode electrode 32 of the light-emitting element 3 is exposed from the element insulating film 98. The element insulating film 98 is formed flat so that the upper surface of the element insulating film 98 and the upper surface of the cathode electrode 32 form the same plane. However, the position of the upper surface of the element insulating film 98 may be different from the position of the upper surface of the cathode electrode 32.

[0053] The counter cathode electrode 22 covers the plurality of light-emitting elements 3 and the element insulating film 98 and is electrically connected to the plurality of light-emitting elements 3. For the counter cathode electrode 22, a conductive material having translucency such as ITO is used. Thereby, the light emitted from the light-emitting element 3 can be efficiently extracted to the outside. The counter cathode electrode 22 is electrically connected to the cathode electrodes 32 of the plurality of light-emitting elements 3 mounted in the display area AA. The counter cathode electrode 22 is connected to a cathode wiring 60 (see FIG. 1) provided on the array substrate 2 at a contact portion provided outside the display area AA.

[0054] A first lens 71 is provided so as to overlap each of the plurality of light-emitting elements 3. The first lens 71 and the second lens 72 (see FIG. 5) are optical members for adjusting the illuminance distribution of the light emitted from the plurality of light-emitting elements 3 and are also called microlenses. The configurations of the plurality of light-emitting elements 3, the first lens 71, and the second lens 72 will be described later with reference to FIG. 5 and below.

[0055] As described above, the display device 1 using the light-emitting element 3 as a display element is configured. Note that an overcoat layer or a cover substrate may be laminated on the upper sides of the counter cathode electrode 22, the first lens 71, and the second lens 72 as necessary for the display device 1. Further, a circular polarizing plate, a touch panel, or the like may be provided on the upper side of the counter cathode electrode 22 for the display device 1.

[0056] In addition, FIG. 4 shows a face-up structure connected to the counter cathode electrode 22 above the light-emitting element 3. However, the present invention is not limited to this, and the light-emitting element 3 may be a flip-chip type light-emitting element in which an anode electrode 33 (p-type electrode) and a cathode electrode 32 (n-type electrode) are provided on the same surface side facing the array substrate 2.

[0057] FIG. 5 is a plan view schematically showing a first light-emitting element, a first lens, a second light-emitting element, and a second lens. FIG. 6 is a cross-sectional view schematically showing a first light-emitting element, a first lens, a second light-emitting element, and a second lens. FIGS. 5 and 6 are schematic views showing an enlarged part of a second region AAs2, a first region AAs1, and a part of the second region AAs2 arranged side by side in a first direction Dx in a display region AA of a substrate 21. FIGS. 5 and 6 show an enlarged view of a light-emitting element 3R among the light-emitting elements 3R, 3G, and 3B included in a pixel PX, and the description of the light-emitting element 3R is also applicable to the light-emitting elements 3G and 3B. In addition, in FIG. 6, a detailed configuration of the array substrate 2 is shown in an omitted manner.

[0058] As shown in FIGS. 5 and 6, a first light-emitting element 3-1 (first light-emitting element 3R-1) and a first lens 71 are provided in a first region AAs1. A second light-emitting element 3-2 (second light-emitting element 3R-2) and a second lens 72 are provided in a second region AAs2. In the following description, among a plurality of light-emitting elements 3, those mounted in the first region AAs1 are represented as a first light-emitting element 3-1, and those mounted in the second region AAs2 are represented as a second light-emitting element 3-2. However, the first light-emitting element 3-1 and the second light-emitting element 3-2 are elements formed of the same material and having the same stacked structure.

[0059] The first lens 71 is provided so as to overlap the first light-emitting element 3-1. The second lens 72 is provided so as to overlap the second light-emitting element 3-2. The first lens 71 and the second lens 72 are provided on an element insulating film 98 and a counter cathode electrode 22 that cover the first light-emitting element 3-1 and the second light-emitting element 3-2. The first lens 71 and the second lens 72 are provided in the same layer. However, a protective film or the like formed of an insulating material may be provided between the first lens 71 and the second lens 72 and the counter cathode electrode 22.

[0060] As shown in FIG. 5, in the first region AAs1, in a plan view, the first lens 71 has a first diameter D1. The first diameter D1 of the first lens 71 is larger than the first width W1 in the first direction Dx of the first light-emitting element 3-1. One first lens 71 is provided so as to overlap one first light-emitting element 3-1. The center (optical axis) of the first lens 71 overlaps with the geometric center of the first light-emitting element 3-1 in a plan view.

[0061] In the second region AAs2, in a plan view, the second lens 72 has a second diameter D2. The second diameter D2 of the second lens 72 is smaller than the second width W2 in the first direction Dx of the second light-emitting element 3-2. Also, the second diameter D2 of the second lens 72 is smaller than the first diameter D1 of the first lens 71. Four second lenses 72 are provided so as to overlap one second light-emitting element 3-2. The centers (optical axes) of the four second lenses 72 are arranged so as to surround the geometric center of the second light-emitting element 3-2 in a plan view.

[0062] Note that the first width W1 of the first light-emitting element 3-1 and the second width W2 of the second light-emitting element 3-2 are, for example, the widths in the first direction Dx on the upper surface (the surface facing the first lens 71 and the second lens 72) of the respective semiconductor layers 31.

[0063] As shown in FIG. 6, in the first region AAs1, the light emitted from the first light-emitting element 3-1 is condensed by the first lens 71, and the intensity of the light Lz traveling in the third direction Dz becomes larger than the intensity of the light Lxy traveling in a direction other than the third direction Dz. In the first region AAs1, the first lens 71 is provided so as to overlap each of the plurality of first light-emitting elements 3-1. Thereby, in the first region AAs1, the luminance in the third direction Dz, that is, the front direction of the display device 1, is improved as a whole.

[0064] In the second region AAs2, the light emitted from the second light-emitting element 3-2 is condensed by each of the plurality of second lenses 72. The intensity of the light Lz traveling in the third direction Dz from the plurality of second lenses 72 is smaller than the intensity of the light Lz traveling in the third direction Dz from the first lens 71 in the first region AAs1. On the other hand, the intensity of the light Lxy traveling in a direction other than the third direction Dz from the second lens 72 is larger than that from the first lens 71. As a result, in the second region AAs2, the luminance in the direction inclined with respect to the third direction Dz as a whole is improved, and a viewing angle can be ensured.

[0065] As described above, the display device 1 of the present embodiment includes a substrate 21, a plurality of first light-emitting elements 3-1 and a plurality of second light-emitting elements 3-2 provided in the display region AA of the substrate 21, and a plurality of first light-emitting elements 3-1. A first lens 71 having a first diameter D1 in a plan view from a direction perpendicular to the substrate 21, and a plurality of second lenses 72 provided so as to overlap with each of the second light-emitting elements 3-2 and having a second diameter D2 smaller than the first diameter D1 in a plan view from a direction perpendicular to the substrate 21.

[0066] Thus, in the display device 1 of the first embodiment, in the first region AAs1 and the second region AAs2, the first diameter D1 (curvature radius) of the first lens 71 and the second diameter D2 (curvature radius) of the second lens 72 are different, and the number of first lenses 71 overlapping the first light-emitting element 3-1 is different from the number of second lenses 72 overlapping the second light-emitting element 3-2. Thereby, the distribution of the light extracted from the light-emitting element 3 can be made different for each region within the display region AA. Specifically, the display device 1 can ensure the viewing angle in the second region AAs2 while ensuring the luminance in the front direction in the first region AAs1.

[0067] As shown in FIG. 5, the semiconductor layer 31 of the light-emitting element 3 is square in plan view. However, it is not limited to this, and the semiconductor layer 31 may have other shapes such as rectangular, polygonal, and circular in plan view. Also, the number of second lenses 72 overlapping one second light-emitting element 3-2 is not limited to four, and may be two, three, or five or more.

[0068] (First Modification Example of the First Embodiment) FIG. 7 is a cross-sectional view schematically showing a first light-emitting element, a first lens, a second light-emitting element, and a second lens according to the first modification example of the first embodiment. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant descriptions are omitted.

[0069] As shown in FIG. 7, in the display device 1A according to the first modification example of the first embodiment, the light-emitting element 3 is a flip-chip type light-emitting element. The anode electrode 33 (p-type electrode) and the cathode electrode 32 (n-type electrode) are provided side by side on the surface of the semiconductor layer 31 facing the array substrate 2.

[0070] The anode electrode 33 is connected to a first mounting electrode 24A provided on the array substrate 2 via a bonding member 28A. Further, the cathode electrode 32 is connected to the first mounting electrode 24A provided on the array substrate 2 via a bonding member 28A.

[0071] In the first region AAs1, a first lens 71A is provided covering the upper surface and the side surface of the first light-emitting element 3-1. The first lens 71A is provided covering the bonding members 28A and 28B as well. In other words, the first lens 71A also serves as a function of the element insulating film 98.

[0072] In the second region AAs2, the element insulating film 98 is provided covering the second light-emitting element 3-2. A plurality of second lenses 72 are provided overlapping the second light-emitting element 3-2 on the element insulating film 98. Also in this modification example, in plan view, the first diameter D1 (see FIG. 5) of the first lens 71A is larger than the second diameter D2 (see FIG. 5) of the second lens 72. Further, in cross-sectional view, the radius of curvature (height) of the first lens 71A is larger than the radius of curvature (height) of the second lens 72 and is also larger than the height of the first light-emitting element 3-1.

[0073] Thus, the first lens 71A and the second lens 72 may be provided in different layers. By providing the first lens 71A having a large radius of curvature on the array substrate 2 (more specifically, on the first mounting electrodes 24A and the second mounting electrodes 24B), the display device 1A can be made thinner than in the first embodiment.

[0074] (Second Modification of the First Embodiment) FIG. 8 is a perspective view schematically showing an array substrate included in a display device according to a second modification of the first embodiment. In the above-described first embodiment and the first modification, an example in which the substrate 21 is flat has been shown, but the present invention is not limited to this. As shown in FIG. 8, the display device 1B according to the second modification of the first embodiment is a curved display.

[0075] The array substrate 2A included in the display device 1B has a shape curved along the first direction Dx and has a shape curved in an S shape when viewed from the second direction Dy. The array substrate 2A includes a first curved surface region TA, a second curved surface region CA, and a low curvature region FA.

[0076] The first curved surface region TA has a curved surface that is convex toward the display surface side. The second curved surface region CA has a curved surface that is concave on the side opposite to the first curved surface region TA. The first curved surface region TA and the second curved surface region CA are each curved with a certain curvature. The first curved surface region TA and the second curved surface region CA may have the same curvature or different curvatures. Further, the first curved surface region TA and the second curved surface region CA are not limited to the case where the curvature is constant, and the curvature may be different along the first direction Dx.

[0077] The low curvature region FA is disposed between the first curved surface region TA and the second curved surface region CA in the first direction Dx. The low curvature region FA is a region having a curvature smaller than that of the first curved surface region TA and the second curved surface region CA. In other words, the low curvature region FA is a region that does not have a bent portion and smoothly connects the first curved surface region TA and the second curved surface region CA.

[0078] The display area AA has a first display area AA-1 and a second display area AA-2. The first display area AA-1 and the second display area AA-2 are arranged adjacent to each other in the first direction Dx. Specifically, the first display area AA-1 is an area that overlaps with a part of the first curved surface area TA and a low-curvature area FA adjacent to the first curved surface area TA. The second display area AA-2 is an area that overlaps with a part of the second curved surface area CA and a low-curvature area FA adjacent to the second curved surface area CA.

[0079] The display area AA is formed in a substantially rectangular shape when viewed from the third direction Dz, but the shape of the outer contour of the display area AA is not limited. For example, the display area AA may have a notch, or the display area AA may be formed in another polygonal shape, or the display area AA may be formed in another shape such as a circular shape or an elliptical shape. Also, the first display area AA-1 and the second display area AA-2 are not limited to being provided continuously and displaying one image, and may be provided separately and display different images respectively.

[0080] The first display area AA-1 includes a first area AAc1 and a second area AAc2. The first area AAc1 is located at the center of the first display area AA-1 in the first direction Dx. The first area AAc1 is provided between a plurality of second areas AAc2 in the first direction Dx. The first display area AA-1 is arranged in the order of the second area AAc2, the first area AAc1, and the second area AAc2 in the first direction Dx.

[0081] The second display area AA-2 includes a third area AAc3 and a fourth area AAc4. The third area AAc3 is located at the center of the second display area AA-2 in the first direction Dx. The third area AAc3 is provided between a plurality of fourth areas AAc4 in the first direction Dx. The second display area AA-2 is arranged in the order of the fourth area AAc4, the third area AAc3, and the fourth area AAc4 in the first direction Dx. The fourth area AAc4 and the second area AAc2 are arranged adjacent to each other in the low-curvature area FA.

[0082] In the first region AAc1 and the third region AAc3, the normal direction of the array substrate 2A (substrate 21A) is directed in the front direction, and the plurality of first light-emitting elements 3-1 and the first lens 71 (or the first lens 71A) described above are provided. In the second region AAc2 and the fourth region AAc4, the normal direction of the array substrate 2A (substrate 21A) is directed in a direction inclined with respect to the front direction, and the plurality of second light-emitting elements 3-2 and the second lens 72 described above are provided.

[0083] Thereby, in the first region AAc1 and the third region AAc3, the light emitted from the plurality of first light-emitting elements 3-1 is condensed by the first lens 71 (or the first lens 71A), and the luminance in the front direction is improved. Also, in the second region AAc2 and the fourth region AAc4, a part of the light emitted from the plurality of second light-emitting elements 3-2 travels in the front direction through the second lens 72. Thereby, the luminance in the front direction in the second region AAc2 and the fourth region AAc4 is improved as compared with the case where the second lens 72 is not provided.

[0084] The array substrate 2A has a first gate line GLA, a second gate line GLB, a first signal line SLA, a second signal line SLB, a first gate line driving circuit 12A, a second gate line driving circuit 12B, a first signal line driving circuit 14A, a second signal line driving circuit 14B, a first driving IC 210A, and a second driving IC 210B.

[0085] The first gate line GLA and the first signal line SLA are provided in the first display region AA-1. The first gate line GLA is curved convexly according to the shapes of the first curved surface region TA and the low curvature region FA. The first gate line GLA is connected to the first gate line driving circuit 12A. The first signal line SLA extends in the second direction Dy and is connected to the first signal line driving circuit 14A. The first driving IC 210A is mounted in a region between the first signal line driving circuit 14A and the end of the array substrate 2A.

[0086] The second gate line GLB and the second signal line SLB are provided in the second display area AA-2. The second gate line GLB is curved in a concave shape according to the shapes of the second curved surface area CA and the low curvature area FA. The second gate line GLB is connected to the second gate line driving circuit 12B. The second signal line SLB extends in the second direction Dy and is connected to the second signal line driving circuit 14B. The second driving IC 210B is mounted in the area between the second signal line driving circuit 14B and the end of the array substrate 2A.

[0087] Note that the configurations of the first gate line GLA, the second gate line GLB, the first signal line SLA, the second signal line SLB, and various peripheral circuits are merely examples and can be changed as appropriate. For example, the first gate line GLA and the second gate line GLB may be continuously formed across the first display area AA-1 and the second display area AA-2. Also, the array substrate 2A (substrate 21A) is not limited to the shape that curves in an S shape and may simply be a shape that curves convexly or concavely.

[0088] (Second Embodiment) FIG. 9 is a plan view schematically showing a first light emitting element, a first lens, a second light emitting element, and a second lens included in one pixel of the display device according to the second embodiment. FIG. 10 is a cross-sectional view schematically showing a first light emitting element, a first lens, a second light emitting element, and a second lens included in one pixel of the display device according to the second embodiment. Note that in FIG. 10, the first light emitting element 3R-1 and the second light emitting element 3R-2 arranged in the second direction Dy are schematically shown side by side.

[0089] In the first embodiment described above, a configuration was shown in which the first light emitting element 3-1 and the first lens 71 (or the first lens 71A) are arranged in the first area AAs1, and the second light emitting element 3-2 and the second lens 72 are arranged in the second area AAs2 within the display area AA, but the present invention is not limited to this.

[0090] As shown in FIGS. 9 and 10, in the display device 1C according to the second embodiment, one pixel PXA includes first light-emitting elements 3R-1, 3G-1, 3B-1 and second light-emitting elements 3R-2, 3G-2, 3B-2. The first light-emitting elements 3R-1, 3G-1, 3B-1 are arranged in the first direction Dx. Also, the second light-emitting elements 3R-2, 3G-2, 3B-2 are arranged in the first direction Dx and are arranged adjacent to the first light-emitting elements 3R-1, 3G-1, 3B-1 in the second direction Dy. In FIG. 9, the first light-emitting element 3-1 (for example, the first light-emitting element 3R-1) and the second light-emitting element 3-2 (for example, the second light-emitting element 3R-2) that emit the same color light are arranged adjacent to each other in the second direction Dy.

[0091] In plan view, a first lens 71 is provided so as to overlap each of the first light-emitting elements 3R-1, 3G-1, 3B-1. Also, a plurality of second lenses 72 are provided so as to overlap each of the second light-emitting elements 3R-2, 3G-2, 3B-2. That is, one first lens 71 and a plurality of second lenses 72 are arranged adjacent to each other in the second direction Dy.

[0092] In other words, in the present embodiment, within one pixel PXA, a first sub-pixel 49-1 having the first light-emitting element 3-1 and the first lens 71 and a second sub-pixel 49-2 having the second light-emitting element 3-2 and the second lens 72 are arranged adjacent to each other in the second direction Dy. The pixels PXA are arranged in a matrix in the display area AA in a set of six first sub-pixels 49-1 and second sub-pixels 49-2.

[0093] The stacked structure of the first light-emitting element 3R-1, the first lens 71, the second light-emitting element 3R-2, and the second lens 72 is the same as that of the first embodiment described above, and repeated description is omitted. Also, the relationship between the first diameter D1 of the first lens 71, the second diameter D2 of the second lens 72, and the width of each light-emitting element 3 is the same as that of the first embodiment.

[0094] FIG. 11 is a circuit diagram showing a pixel circuit according to the second embodiment. As shown in FIG. 11, a first pixel circuit PICA-1 is provided corresponding to the first light-emitting element 3R-1. A second pixel circuit PICA-2 is provided corresponding to the second light-emitting element 3R-2. The first pixel circuit PICA-1 and the second pixel circuit PICA-2 are provided adjacent to each other, and some wirings are shared. In FIG. 11, the pixel circuits PICA of the first light-emitting element 3R-1 and the second light-emitting element 3R-2 are shown, but pixel circuits PICA are also provided for the other first light-emitting elements 3G-1, 3B-1 and the second light-emitting elements 3G-2, 3B-2, respectively.

[0095] Specifically, the reset power line L3, the reset control signal line L5, the output control signal line L6, the pixel control signal line L7, the initialization control signal line L8, and the cathode power line L10 are connected to each of the first pixel circuit PICA-1 and the second pixel circuit PICA-2. The configurations of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 are the same as those of the pixel circuit PICA shown in FIG. 3. However, in the first pixel circuit PICA-1 and the second pixel circuit PICA-2, the configuration in which the reset transistor RST is connected between the output transistor BCT and the driving transistor DRT is different.

[0096] With such a configuration, in the display device 1C according to the second embodiment, in one pixel PXA, the luminance in the front direction is improved by the first light-emitting element 3-1 and the first lens 71 of the first sub-pixel 49-1, and a wide viewing angle can be ensured by the second light-emitting element 3-2 and the second lens 72 of the second sub-pixel 49-2. Further, the display device 1C may control the lighting and non-lighting of the first light-emitting element 3-1 and the second light-emitting element 3-2 for each region for the pixels PXA arranged in a matrix in the display region AA.

[0097] (Third modification of the second embodiment) FIG. 12 is a plan view schematically showing a pixel according to a third modification of the second embodiment. As shown in FIG. 12, in a display device 1D according to the third modification of the second embodiment, a pixel PXA further includes a first driver IC 211 and a second driver IC 212. The first driver IC 211 and the second driver IC 212 are also called micro ICs.

[0098] The first driver IC 211 is a circuit that drives the first light-emitting elements 3R-1, 3G-1, and 3B-1. The second driver IC 212 is a circuit that drives the second light-emitting elements 3R-2, 3G-2, and 3B-2. The first driver IC 211 and the second driver IC 212 are mounted on each of a plurality of pixels PXA. That is, the first driver IC 211 and the second driver IC 212 respectively have the functions of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 shown in FIG. 11. Note that the first driver IC 211 and the second driver IC 212 may be configured to have a part of the functions of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 shown in FIG. 11, and other functions may be realized by each transistor on the array substrate 2.

[0099] According to the third modification of the second embodiment, the number of transistors on the array substrate 2 can be reduced.

[0100] (Third Embodiment) FIG. 13 is a perspective view schematically showing a display device according to the third embodiment. As shown in FIG. 13, in a display device 1E according to the third embodiment, a main surface of a substrate 21 on which a light-emitting element 3 is mounted has a convexly curved shape. More specifically, the array substrate 2 (substrate 21) of the display device 1E has a convexly curved shape in a cross-sectional structure in a first direction Dx, and also has a convexly curved shape in a cross-sectional structure in a second direction Dy intersecting the first direction Dx.

[0101] Also in this embodiment, the configurations of the above-described embodiments and modified examples can be adopted. For example, the display area AA of the substrate 21 includes a first area AAd1 provided at the central portion of the display area AA and a second area AAd2 provided at the outer edge portion of the display area AA. A plurality of first light-emitting elements 3-1 and a plurality of first lenses 71 are provided in the first area AAd1. A plurality of second light-emitting elements 3-2 and a plurality of second lenses 72 are provided in the second area AAd2.

[0102] Alternatively, the array substrate 2 (substrate 21) of the third embodiment and the configuration of the pixel PXA of the second embodiment can also be combined.

[0103] As described above, the preferred embodiments of the present invention have been described. However, the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, substitutions, and changes of components can be made without departing from the gist of each of the above-described embodiments and each modified example.

Explanation of Reference Numerals

[0104] 1, 1A, 1B, 1C, 1D, 1E Display device 2, 2A Array substrate 3, 3R, 3G, 3B Light-emitting element 3-1, 3R-1, 3G-1, 3B-1 First light-emitting element 3-2, 3R-2, 3G-2, 3B-2 Second light-emitting element 12 Driving circuit 21 Substrate 22 Opposite cathode electrode 23 Anode connection electrode 24 Mounting electrode 25 Opposite electrode 28 Bonding member 31 Semiconductor layer 32 Cathode electrode 33 Anode electrode 71, 71A First lens 72 Second lens 98 Element insulating film AA Display area AAs1, AAc1, AAd1 First region AAs2, AAc2, AAd2 Second region GA Peripheral region

Claims

1. A substrate, a plurality of first light-emitting elements and a plurality of second light-emitting elements provided in a display area of the substrate, a first lens provided so as to overlap each of the plurality of first light-emitting elements and having a first diameter in a plan view from a direction perpendicular to the substrate, a second lens provided so as to overlap each of the plurality of second light-emitting elements and having a second diameter smaller than the first diameter in a plan view from a direction perpendicular to the substrate, and only one first lens is provided so as to overlap one of the first light-emitting elements, a plurality of the second lenses are provided so as to overlap one of the second light-emitting elements, the first diameter of the first lens is larger than a first width of the first light-emitting element, and the first lens covers the entire surface of the first light-emitting element, the second diameter of the second lens is smaller than a second width of the second light-emitting element, and the second lens is arranged so as to partially overlap only a peripheral portion of the second light-emitting element, the display area of the substrate includes a first area provided with the plurality of first light-emitting elements and the plurality of first lenses, and a second area provided with the plurality of second light-emitting elements and the plurality of second lenses, in a first direction, the first area is provided at a central portion of the display area, and the second area is provided at an outer edge portion of the display area A display device.

2. having a plurality of pixels arranged on the substrate, one of the pixels includes a plurality of the first light-emitting elements and a plurality of the second light-emitting elements, in a plan view from a direction perpendicular to the substrate, the first light-emitting element and the first lens, and the second light-emitting element and the plurality of second lenses are arranged adjacent to each other The display device according to Claim 1.

3. In one of the pixels, adjacent ones of the first light-emitting element and the second light-emitting element emit light of the same color The display device according to Claim 2.

4. One of the pixels has a first driver IC for driving the first light-emitting element and a second driver IC for driving the second light-emitting element The display device according to Claim 2 or Claim 3.

5. having an element insulating film covering side surfaces of the plurality of first light-emitting elements and the plurality of second light-emitting elements, the first lens and the second lens are provided on the element insulating film The display device according to any one of Claims 1 to 4.

6. having an element insulating film covering side surfaces of the plurality of second light-emitting elements, the first lens is provided on the substrate so as to cover an upper surface and a side surface of the first light-emitting element, The second lens is provided on the element insulating film. The display device according to any one of claims 1 to 4. **Claim 7** The substrate has a curved shape in which a main surface on which a plurality of the first light-emitting elements and a plurality of the second light-emitting elements are mounted is convexly curved. The display device according to any one of claims 1 to 6.

Images