Memory control device, information processing system, and memory control method

Abstract

To provide a memory control device capable of reducing a load on a processor in expansion processing of compressed data.SOLUTION: A memory control device which controls a memory having compressed data stored therein includes: an expansion circuit that expands the data which is read from the memory in response to a request from a processor, by hardware processing; and a data holding circuit that temporarily holds data which is expanded by the expansion circuit, as held data and outputs the held data to the processor in response to a request from the processor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory control device, an information processing system, and a memory control method.

Background Art

[0002] The following Patent Document 1 discloses a computer system including a data storage unit storing compressed data and a data decompression unit decompressing the compressed data read from the data storage unit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the computer system disclosed in the above Patent Document 1, the data decompression unit is implemented by being incorporated into an operating system or as a file management program operating on the operating system. That is, the data decompression unit decompresses the compressed data read from the data storage unit by software processing by a processor.

[0005] Therefore, when the compressed data is compressed with high compression efficiency, it takes a long time to decompress the compressed data by software processing of the processor, or it is necessary to implement a high-performance processor capable of executing the decompression process at high speed, resulting in an increase in cost.

[0006] The present invention has been made in view of such circumstances, and an object thereof is to obtain a memory control device, an information processing system, and a memory control method capable of reducing the load on the processor associated with the decompression process of compressed data.

Means for Solving the Problems

[0007] A memory control device according to an aspect of the present invention is a memory control device that controls a memory in which compressed data is stored, and includes a decompression circuit that decompresses data read from the memory in response to a request from a processor by hardware processing, and a data holding circuit that temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor.

[0008] According to this aspect, the decompression circuit decompresses data read from the memory in response to a request from the processor by hardware processing. Further, the data holding circuit temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor. Therefore, it is not necessary to decompress compressed data by software processing of the processor, so that the load on the processor associated with the decompression process can be reduced. In addition, data that the processor will use in the future can be read out from the memory in advance, and the data decompressed by the decompression circuit can be buffered in the data holding circuit. As a result, the memory control device can immediately transfer the data from the data holding circuit to the processor in response to a transfer request for the data from the processor.

[0009] In the above aspect, a parameter holding circuit is further provided that holds a plurality of decompression parameters used for decompressing data by the decompression circuit, selects a decompression parameter corresponding to the data to be decompressed from among the plurality of held decompression parameters, and inputs the selected decompression parameter to the decompression circuit.

[0010] According to this aspect, the parameter holding circuit holds the decompression parameters used for decompressing data by the decompression circuit. Since it is not necessary to generate decompression parameters by an initialization process before the decompression process, it is possible to avoid the occurrence of latency associated with the initialization process. Further, the parameter holding circuit selects the decompression parameter corresponding to the data to be decompressed from among the plurality of held decompression parameters and inputs it to the decompression circuit. Therefore, the decompression circuit can perform data decompression using the optimal decompression parameter according to the data to be decompressed. As a result, it is possible to improve the compression efficiency of the data as compared with the case where one fixed parameter is used.

[0011] In the above aspect, the data stored in the memory is compressed with a first compression efficiency, and a compression circuit further compresses the data decompressed by the decompression circuit with a second compression efficiency lower than the first compression efficiency and inputs the recompressed data to the data holding circuit. The data holding circuit holds the data input from the compression circuit as the held data.

[0012] According to this aspect, the compression circuit recompresses the data decompressed by the decompression circuit and inputs the recompressed data to the data holding circuit. Therefore, since the data holding circuit transfers the recompressed data to the processor, it is possible to improve the transfer throughput as compared with the case of transferring the decompressed data. Further, since the compression circuit performs recompression with a second compression efficiency lower than the first compression efficiency, it is possible to reduce the load on the processor associated with the decompression process of the compressed data as compared with the case of decompressing the data compressed with the first compression efficiency.

[0013] In the above aspect, the compression circuit variably sets the second compression efficiency based on a first parameter.

[0014] According to this aspect, it is possible to appropriately set the second compression efficiency when the compression circuit recompresses the data decompressed by the decompression circuit.

[0015] In the above aspect, the first parameter includes at least one of the performance of the processor, the processing congestion situation of the processor, and the communication congestion situation of the processor.

[0016] According to this aspect, it becomes possible to appropriately set the second compression efficiency when the compression circuit recompresses the data extended by the extension circuit according to the performance of the processor, the processing congestion situation, or the communication congestion situation.

[0017] In the above aspect, the compression circuit recompresses the held data held by the data holding circuit while changing the second compression efficiency based on a second parameter.

[0018] According to this aspect, it becomes possible to recompress the held data held by the data holding circuit while appropriately changing the second compression efficiency.

[0019] In the above aspect, the second parameter includes at least one of the read frequency of the held data held by the data holding circuit, the performance of the processor, the processing congestion situation of the processor, and the communication congestion situation of the processor.

[0020] According to this aspect, it becomes possible to appropriately set the second compression efficiency when recompressing the held data held by the data holding circuit according to the read frequency of the held data, the performance of the processor, the processing congestion situation, or the communication congestion situation.

[0021] In the above aspect, the second parameter includes the read frequency, and when the read frequency is less than a first threshold value, the compression circuit changes the second compression efficiency to a value higher than the current value.

[0022] According to this aspect, when the read frequency is less than a first threshold value, the compression circuit changes the second compression efficiency to a value higher than the current value. Thereby, it is possible to reduce the amount of data held in the data holding circuit and improve the transfer throughput in the data transfer from the data holding circuit to the processor.

[0023] In the above aspect, the second parameter includes the read frequency, and when the read frequency is greater than or equal to a first threshold value, the compression circuit changes the second compression efficiency to a value lower than the current value.

[0024] According to this aspect, when the read frequency is greater than or equal to a first threshold value, the compression circuit changes the second compression efficiency to a value lower than the current value. Thereby, it is possible to reduce the load on the processor associated with the decompression process of the compressed data.

[0025] In the above aspect, the second parameter includes the communication congestion situation, and when the communication congestion situation is greater than or equal to a second threshold value, the compression circuit changes the second compression efficiency to a value higher than the current value.

[0026] According to this aspect, when the communication congestion situation of the processor is greater than or equal to a second threshold value, the compression circuit changes the second compression efficiency to a value higher than the current value. Thereby, it is possible to improve the transfer throughput in the data transfer from the data holding circuit to the processor.

[0027] In the above aspect, the second parameter includes the communication congestion situation, and when the communication congestion situation is less than a second threshold value, the compression circuit changes the second compression efficiency to a value lower than the current value.

[0028] According to this aspect, when the communication congestion situation of the processor is less than a second threshold value, the compression circuit changes the second compression efficiency to a value lower than the current value. Thereby, it is possible to reduce the load on the processor associated with the decompression process of the compressed data.

[0029] An information processing system according to one aspect of the present invention includes a processor, a memory storing compressed data, and a memory control device for controlling the memory. The memory control device includes a decompression circuit that decompresses data read from the memory in response to a request from the processor by hardware processing, and a data holding circuit that temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor.

[0030] According to this aspect, the decompression circuit decompresses data read from the memory in response to a request from the processor by hardware processing. Further, the data holding circuit temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor. Therefore, since it is not necessary to decompress compressed data by software processing of the processor, it is possible to reduce the load on the processor associated with the decompression process. Also, data that the processor will use in subsequent times can be read out from the memory in advance, and the data decompressed by the decompression circuit can be buffered in the data holding circuit. As a result, the memory control device can immediately transfer the data from the data holding circuit to the processor in response to a transfer request for the data from the processor.

[0031] A memory control method according to one aspect of the present invention is a memory control method for controlling a memory storing compressed data, wherein a decompression circuit decompresses data read from the memory in response to a request from the processor by hardware processing, a data holding circuit temporarily holds the data decompressed by the decompression circuit as holding data, and outputs the holding data to the processor in response to a request from the processor.

[0032] According to this aspect, the expansion circuit expands data read from the memory in response to a request from the processor by hardware processing. Further, the data holding circuit temporarily holds the data expanded by the expansion circuit as held data, and outputs the held data to the processor in response to a request from the processor. Therefore, since it is not necessary to expand the compressed data by the software processing of the processor, it is possible to reduce the load on the processor associated with the expansion processing. Further, data that the processor will use in the future can be read out from the memory in advance, and the data expanded by the expansion circuit can be buffered in the data holding circuit. As a result, the memory control device can immediately transfer the data from the data holding circuit to the processor in response to a transfer request for the data from the processor.

Effects of the Invention

[0033] According to the present invention, it is possible to reduce the load on the processor associated with the expansion processing of compressed data.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 7

Figure 8

Mode for Carrying Out the Invention

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that elements denoted by the same reference numerals in different drawings indicate the same or corresponding elements. Also, the following plurality of embodiments can be arbitrarily combined and applied.

[0036] <First Embodiment> FIG. 1 is a diagram showing a simplified configuration of an information processing system 1A according to a first embodiment of the present invention. The information processing system 1 includes a host device 11 such as a personal computer and a memory 12 that can be detachably connected to the host device 11. The memory 12 is configured as a memory card using, for example, a NAND type flash memory.

[0037] The host device 11 includes a processor such as a CPU 21 and a controller 22A as a memory control device that controls the memory 12. The controller 22A is configured using hardware such as an ASIC or an FPGA. The controller 22A includes a data holding circuit 31 and an extension circuit 32.

[0038] Note that the controller 22A may be mounted in the memory 12 or may be interposed between the host device 11 and the memory 12. The same applies to other embodiments.

[0039] Compressed data D1 regarding arbitrary content such as an image or audio is stored in the memory 12. In order to suppress an increase in memory cost due to the enlargement of content data, the data D1 stored in the memory 12 is compressed at a predetermined compression efficiency (first compression efficiency).

[0040] The CPU 21 inputs a read request for the data D1 from the memory 12 to the controller 22A. The data D1 to be read is, for example, data that the CPU 21 will use next time or later. However, the data D1 to be read may also be data that the CPU 21 uses this time.

[0041] The controller 22A reads the data D1 from the memory 12 according to the read request input from the CPU 21. The data D1 read from the memory 12 is input to the expansion circuit 32.

[0042] The expansion circuit 32 expands the compressed data D1 by hardware processing and inputs the expanded data D2 to the data holding circuit 31.

[0043] The data holding circuit 31 temporarily holds the expanded data D2 as held data. As a result, the previously read data D1 can be expanded by the expansion circuit 32, and the expanded data D2 can be buffered in the data holding circuit 31.

[0044] The controller 22A transfers the data D2 from the data holding circuit 31 to the CPU 21 in response to a transfer request input from the CPU 21.

[0045] According to this embodiment, the expansion circuit 32 expands the data D1 read from the memory 12 in response to a read request from the CPU 21 by hardware processing. Further, the data holding circuit 31 temporarily holds the data D2 expanded by the expansion circuit 32 as held data, and outputs the data D2 toward the CPU 21 in response to a transfer request from the CPU 21. Therefore, since it is not necessary to expand the compressed data (data D1) by the software processing of the CPU 21, it is possible to reduce the load on the CPU 21 associated with the expansion processing. Also, the data D1 used by the CPU 21 in subsequent times can be read in advance from the memory 12, and the data D2 expanded by the expansion circuit 32 can be buffered in the data holding circuit 31. Thereby, the controller 22A can immediately transfer the data D2 from the data holding circuit 31 to the CPU 21 in response to a transfer request for the data D2 from the CPU 21.

[0046] <Second Embodiment> FIG. 2 is a diagram schematically showing the configuration of the information processing system 1B according to the second embodiment of the present invention.

[0047] The host device 11 includes a processor such as the CPU 21 and a controller 22B as a memory control device. The controller 22B includes a data holding circuit 31, an expansion circuit 32, and a parameter holding circuit 33.

[0048] The compressed data D1 is stored in the memory 12. The data D1 is compressed by a compression and decompression algorithm that employs entropy encoding such as Deflate or Zstandard. In such a compression and decompression algorithm, compression processing and decompression processing are performed in predetermined block units of the data to be compressed or decompressed, and a process of dynamically generating compression parameters or decompression parameters by an initialization process before the compression processing or the decompression processing is required. The compression parameters or the decompression parameters are, for example, a Huffman code table. The compression parameters or the decompression parameters are generated in the above block units. In the present embodiment, instead of dynamically generating decompression parameters by an initialization process, data D3 of a decompression parameter group including a plurality of preset decompression parameters is stored in the memory 12.

[0049] In the startup process when the information processing system 1B is powered on, the controller 22B reads the data D3 from the memory 12 and inputs the read data D3 to the parameter holding circuit 33. The parameter holding circuit 33 holds the input data D3. Note that instead of the decompression parameters themselves such as a Huffman code table, the data for generating them is stored in the memory 12, and in the startup process, the controller 22B generates decompression parameters based on the data for generation read from the memory 12, and the parameter holding circuit 33 holds the generated decompression parameters. This configuration is also acceptable.

[0050] When the parameter holding circuit 33 is configured using a volatile memory, the transfer process of the data D3 from the memory 12 to the parameter holding circuit 33 is performed for each startup process of the information processing system 1B. When the parameter holding circuit 33 is configured using a non-volatile memory, the parameter holding circuit 33 continuously holds the once-input data D3 even after the power is turned off.

[0051] The CPU 21 inputs a read request for the data D1 from the memory 12 to the controller 22B.

[0052] In accordance with the read request input from the CPU 21, the controller 22B reads the data D1 from the memory 12. The data D1 read from the memory 12 is input to the decompression circuit 32.

[0053] To the header of each block of the data D1, parameter selection information indicating the decompression parameter corresponding to the compression parameter used during compression among the plurality of decompression parameters included in the data D3 is added. The parameter selection information is input from the decompression circuit 32 to the parameter holding circuit 33. The parameter holding circuit 33 selects the decompression parameter corresponding to the input parameter selection information among the plurality of decompression parameters included in the held data D3, and inputs the data D4 of the selected decompression parameter to the decompression circuit 32.

[0054] The decompression circuit 32 uses the decompression parameter indicated by the data D4 to decompress the compressed data D1 by hardware processing, and inputs the decompressed data D2 to the data holding circuit 31.

[0055] The data holding circuit 31 temporarily holds the decompressed data D2 as held data.

[0056] In response to the transfer request input from the CPU 21, the controller 22B transfers the data D2 from the data holding circuit 31 to the CPU 21.

[0057] According to the present embodiment, the parameter holding circuit 33 holds the expansion parameters (data D3) used for expanding the data D1 by the expansion circuit 32. Since it is not necessary to generate the expansion parameters by the initialization process before the expansion process, it is possible to avoid the occurrence of latency associated with the initialization process. Further, the parameter holding circuit 33 selects the expansion parameter (data D4) corresponding to the data D1 to be expanded from among the plurality of held expansion parameters (data D3) and inputs it to the expansion circuit 32. Therefore, the expansion circuit 32 can expand the data D1 using the optimal expansion parameter according to the data D1 to be expanded. As a result, it is possible to improve the compression efficiency of the data D1 as compared with the case where one fixed parameter is used.

[0058] Instead of the above configuration in which parameter selection information is added to the header of each block of the data D1, mapping information indicating the correspondence between the identification information of each of the plurality of blocks included in the data D1 and the identification information of each of the plurality of expansion parameters included in the data D3 is created in advance, and the parameter holding circuit 33 may be configured to hold the mapping information. The parameter holding circuit 33 selects, based on the mapping information, the expansion parameter corresponding to the block to be expanded from among the plurality of expansion parameters included in the held data D3, and inputs the data D4 of the selected expansion parameter to the expansion circuit 32.

[0059] Further, the controller 22B classifies the data D1 stored in the memory 12 into high-frequency data and low-frequency data based on a predetermined threshold related to the read frequency, and applies parameter selection from among the plurality of expansion parameters according to the present embodiment to the high-frequency data, and may apply dynamic generation of optimal expansion parameters by the initialization process to the low-frequency data. Thereby, it is possible to achieve both avoidance of the occurrence of latency related to high-frequency data and improvement of the compression efficiency related to low-frequency data.

[0060] Furthermore, if the pre-reading of the data D1 from the memory 12 is not performed, the data holding circuit 31 may be omitted. FIG. 3 is a diagram schematically showing the configuration of an information processing system 1B according to a modification of the second embodiment of the present invention. The data holding circuit 31 is omitted from the configuration shown in FIG. 2. The data D2 output from the expansion circuit 32 is directly input to the CPU 21 without passing through the data holding circuit 31.

[0061] <Third Embodiment> FIG. 4 is a diagram schematically showing the configuration of an information processing system 1C according to the third embodiment of the present invention.

[0062] The host device 11 includes a processor such as the CPU 21 and a controller 22C as a memory control device. The controller 22C includes a data holding circuit 31, an expansion circuit 32, and a compression circuit 34.

[0063] The CPU 21 inputs a read request for the data D1 from the memory 12 to the controller 22C.

[0064] The controller 22C reads the data D1 from the memory 12 in accordance with the read request input from the CPU 21. The data D1 read from the memory 12 is input to the expansion circuit 32.

[0065] The expansion circuit 32 expands the compressed data D1 by hardware processing and inputs the expanded data D2 to the compression circuit 34.

[0066] The compression circuit 34 recompresses the data D2 input from the expansion circuit 32 with a compression efficiency (second compression efficiency) lower than the first compression efficiency regarding the data D1, and inputs the recompressed data D5 to the data holding circuit 31. As the compression algorithm of the compression circuit 34, any algorithm with low latency and low compression such as MTF or ASE can be used.

[0067] The data holding circuit 31 temporarily holds the data D5 input from the compression circuit 34 as held data.

[0068] In response to the transfer request input from the CPU 21, the controller 22C transfers the data D5 from the data holding circuit 31 to the CPU 21.

[0069] The CPU 21 performs the decompression process of the data D5 by software processing.

[0070] According to the present embodiment, the compression circuit 34 recompresses the data D2 decompressed by the decompression circuit 32, and inputs the recompressed data D5 to the data holding circuit 31. Therefore, since the data holding circuit 31 transfers the recompressed data D5 to the CPU 21, it is possible to improve the transfer throughput as compared with the case of transferring the decompressed data D2. In addition, since the compression circuit 34 performs recompression with a second compression efficiency lower than the first compression efficiency, it is possible to reduce the load on the CPU 21 associated with the decompression process of the compressed data as compared with the case of decompressing the data D1 compressed with the first compression efficiency.

[0071] If the pre-reading of the data D1 from the memory 12 is not performed, the data holding circuit 31 may be omitted. FIG. 5 is a diagram schematically showing the configuration of the information processing system 1C according to a modification of the third embodiment of the present invention. The data holding circuit 31 is omitted from the configuration shown in FIG. 4. The data D5 output from the compression circuit 34 is directly input to the CPU 21 without passing through the data holding circuit 31.

[0072] <Fourth Embodiment> In the third embodiment described above, the compression efficiency (second compression efficiency) of the data D2 by the compression circuit 34 may be variable.

[0073] FIG. 6 is a diagram schematically showing the configuration of the information processing system 1D according to the fourth embodiment of the present invention.

[0074] The host device 11 includes a processor such as a CPU 21 and a controller 22D as a memory control device. The controller 22D includes a data holding circuit 31, an expansion circuit 32, and a compression circuit 34. The compression circuit 34 includes a plurality of compression circuits with different compression efficiencies (in this example, three compression circuits 34A to 34C), a selection circuit 35, and switching circuits 36 and 37. In the following example, the compression circuit 34B has the second compression efficiency, the compression circuit 34A has a compression efficiency higher than the second compression efficiency (the third compression efficiency), and the compression circuit 34C has a compression efficiency lower than the second compression efficiency (the fourth compression efficiency).

[0075] The selection circuit 35 can select one of the compression circuits 34A to 34C by switching the switching circuits 36 and 37 with a selection signal D6. The selection circuit 35 selects the compression circuits 34A to 34C according to the performance of the CPU 21 (one of the first parameters) mounted on the host device 11. For example, when the performance of the CPU 21 is at a high level, the compression circuit 34A is selected; when the performance of the CPU 21 is at a medium level, the compression circuit 34B is selected; and when the performance of the CPU 21 is at a low level, the compression circuit 34C is selected. Alternatively, the selection circuit 35 selects the compression circuits 34A to 34C according to the congestion status of the processing of the CPU 21 (one of the first parameters). For example, when the degree of the congestion status of the processing is at a high level, the compression circuit 34C is selected; when the degree of the congestion status of the processing is at a medium level, the compression circuit 34B is selected; and when the degree of the congestion status of the processing is at a low level, the compression circuit 34A is selected. Alternatively, the selection circuit 35 selects the compression circuits 34A to 34C according to the congestion status of the communication of the data bus to which the CPU 21 is connected (one of the first parameters). For example, when the degree of the congestion status of the communication is at a high level, the compression circuit 34A is selected; when the degree of the congestion status of the communication is at a medium level, the compression circuit 34B is selected; and when the degree of the congestion status of the communication is at a low level, the compression circuit 34C is selected. The first parameter includes at least one of the performance of the CPU 21, the processing congestion status, and the communication congestion status, and the controller 22D acquires such information from the CPU 21. Alternatively, the controller 22D itself may detect the first parameter.

[0076] According to the present embodiment, since the second compression efficiency when the compression circuit 34 recompresses the data D2 extended by the extension circuit 32 is variable, it is possible to appropriately set the second compression efficiency according to the performance of the CPU 21, the congestion status of processing and communication, etc.

[0077] Note that if the pre-reading of the data D1 from the memory 12 is not performed, the data holding circuit 31 may be omitted. FIG. 7 is a diagram schematically showing the configuration of an information processing system 1D according to a modification of the fourth embodiment of the present invention. The data holding circuit 31 is omitted from the configuration shown in FIG. 6. The data D5 output from the compression circuit 34 is directly input to the CPU 21 without passing through the data holding circuit 31.

[0078] <Fifth Embodiment> In the third or fourth embodiment described above, the held data held by the data holding circuit 31 may be recompressed based on a second parameter. The second parameter includes at least one of the read frequency of the held data held by the data holding circuit 31, the performance of the CPU 21, the processing congestion status of the CPU 21, and the communication congestion status of the CPU 21. The controller 22E acquires information regarding the performance, processing congestion status, and communication congestion status of the CPU 21 from the CPU 21. Alternatively, the controller 22E itself may detect the second parameter.

[0079] FIG. 8 is a diagram schematically showing the configuration of an information processing system 1E according to the fifth embodiment of the present invention.

[0080] The host device 11 includes a processor such as a CPU 21 and a controller 22E as a memory control device. The controller 22E includes a data holding circuit 31, an expansion circuit 32, and a compression circuit 34. The compression circuit 34 includes a plurality of compression circuits and a plurality of expansion circuits with different compression efficiencies (in this example, three compression circuits 34A to 34C and three expansion circuits 40A to 40C), selection circuits 35 and 41, and switching circuits 36 to 39 and 42. In the following example, the compression circuit 34B and the expansion circuit 40B have the second compression efficiency, the compression circuit 34A and the expansion circuit 40A have a compression efficiency higher than the second compression efficiency (third compression efficiency), and the compression circuit 34C and the expansion circuit 40C have a compression efficiency lower than the second compression efficiency (fourth compression efficiency).

[0081] During the execution of normal processing, the selection circuit 41 switches the input of the switching circuit 42 to the expansion circuit 32 side by the selection signal D9, and during the execution of the recompression process of the data D5, the selection circuit 41 switches the input of the switching circuit 42 to the switching circuit 39 side by the selection signal D9.

[0082] The selection circuit 35 can select one of the compression circuits 34A to 34C by switching the switching circuits 36 and 37 by the selection signal D6, and can select one of the expansion circuits 40A to 40C by switching the switching circuits 38 and 39 by the selection signal D7.

[0083] For example, when the read frequency of the held data held by the data holding circuit 31 is less than the first threshold value, the held data is recompressed with a compression efficiency higher than the current compression efficiency. For example, when the current compression efficiency of the held data is the second compression efficiency, the selection circuit 35 selects the expansion circuit 40B and the compression circuit 34A to recompress the held data with a third compression efficiency higher than the second compression efficiency and overwrite the held data in the data holding circuit 31.

[0084] On the one hand, when the read frequency of the held data held by the data holding circuit 31 is equal to or higher than a first threshold value, the held data is recompressed at a compression efficiency lower than the current compression efficiency. For example, when the current compression efficiency of the held data is the second compression efficiency, the selection circuit 35 selects the decompression circuit 40B and the compression circuit 34C to recompress the held data at a fourth compression efficiency lower than the second compression efficiency, and overwrite the held data in the data holding circuit 31.

[0085] Also, when the communication congestion situation of the CPU 21 is equal to or higher than a second threshold value, the held data is recompressed at a compression efficiency higher than the current compression efficiency. For example, when the current compression efficiency of the held data is the second compression efficiency, the selection circuit 35 selects the decompression circuit 40B and the compression circuit 34A to recompress the held data at a third compression efficiency higher than the second compression efficiency, and overwrite the held data in the data holding circuit 31.

[0086] On the other hand, when the communication congestion situation of the CPU 21 is less than the second threshold value, the held data is recompressed at a compression efficiency lower than the current compression efficiency. For example, when the current compression efficiency of the held data is the second compression efficiency, the selection circuit 35 selects the decompression circuit 40B and the compression circuit 34C to recompress the held data at a fourth compression efficiency lower than the second compression efficiency, and overwrite the held data in the data holding circuit 31.

[0087] Similarly, when the performance of the CPU 21 is equal to or higher than a threshold value, the held data is recompressed at a compression efficiency higher than the current compression efficiency, and when the performance of the CPU 21 is less than the threshold value, the held data is recompressed at a compression efficiency lower than the current compression efficiency. Also, when the processing congestion situation of the CPU 21 is less than a threshold value, the held data is recompressed at a compression efficiency higher than the current compression efficiency, and when the processing congestion situation of the CPU 21 is equal to or higher than the threshold value, the held data is recompressed at a compression efficiency lower than the current compression efficiency. Note that the process of changing the compression efficiency to a value higher than the current value and the process of changing the compression efficiency to a value lower than the current value may both be executed, or only either one of them may be executed.

[0088] According to this embodiment, when the read frequency is less than the first threshold, the compression circuit 34 recompresses the held data with a third compression efficiency higher than the second compression efficiency. Thereby, it is possible to reduce the amount of data held in the data holding circuit 31 and improve the transfer throughput in the data transfer from the data holding circuit 31 to the CPU 21. Further, when the read frequency is equal to or higher than the first threshold, the compression circuit 34 recompresses the held data with a fourth compression efficiency lower than the second compression efficiency. Thereby, it is possible to reduce the load on the CPU 21 associated with the decompression process of the compressed data.

[0089] In addition, when the communication congestion situation of the CPU 21 is equal to or higher than the second threshold, the compression circuit 34 recompresses the held data with a third compression efficiency higher than the second compression efficiency. Thereby, it is possible to improve the transfer throughput in the data transfer from the data holding circuit 31 to the CPU 21. Further, when the communication congestion situation of the CPU 21 is less than the second threshold, the compression circuit 34 recompresses the held data with a fourth compression efficiency lower than the second compression efficiency. Thereby, it is possible to reduce the load on the CPU 21 associated with the decompression process of the compressed data.

[0090] The functions of the elements disclosed herein may be implemented using a general-purpose processor, a dedicated processor, an integrated circuit, an ASIC ("application-specific integrated circuit"), a conventional circuit configuration, and / or a circuit configuration or processing circuit configuration that is configured to execute the disclosed elements or programmed to execute the disclosed functions. A processor is considered a processing circuit configuration or circuit configuration when it includes transistors and other circuit configurations therein. In the present disclosure, a circuit configuration, unit, or means is hardware that executes the recited functions or hardware programmed to execute the functions. The hardware may be any hardware disclosed herein or other known hardware that is programmed to execute the recited functions or configured to execute the functions. When the hardware is a processor that may be considered a type of circuit configuration, the circuit configuration, means, or unit is a combination of hardware and software, software used to configure the hardware, and / or a processor.

Description of Reference Numerals

[0091] 1A to 1E Information processing system 11 Host device 12 Memory 21 CPU 22A to 22E Controller 31 Data holding circuit 32 Expansion circuit 33 Parameter holding circuit 34, 34A to 34C Compression circuit

Claims

1. A memory control device that controls a memory storing compressed data, comprising: a decompression circuit that decompresses data read from the memory in response to a request from a processor by hardware processing; a data holding circuit that temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor; a parameter holding circuit that holds a plurality of decompression parameters used for decompressing data by the decompression circuit, selects a decompression parameter corresponding to the data to be decompressed from the plurality of held decompression parameters, and inputs the selected decompression parameter to the decompression circuit; The decompression circuit inputs parameter selection information added to a header of the data read from the memory to the parameter holding circuit, The parameter holding circuit selects the decompression parameter based on the input parameter selection information. A memory control device.

2. The data stored in the memory is compressed at a first compression efficiency, A compression circuit that recompresses the data decompressed by the decompression circuit at a second compression efficiency lower than the first compression efficiency and inputs the recompressed data to the data holding circuit; The data holding circuit holds the data input from the compression circuit as the holding data. The memory control device according to claim 1.

3. The compression circuit variably sets the second compression efficiency based on a first parameter. The memory control device according to claim 2.

4. A memory control device that controls a memory storing compressed data, comprising: a decompression circuit that decompresses data read from the memory in response to a request from a processor by hardware processing; a data holding circuit that temporarily holds the data decompressed by the decompression circuit as holding data and outputs the holding data to the processor in response to a request from the processor; The data stored in the memory is compressed at a first compression efficiency, A compression circuit that recompresses the data decompressed by the decompression circuit at a second compression efficiency lower than the first compression efficiency and inputs the recompressed data to the data holding circuit; The data holding circuit holds the data input from the compression circuit as the holding data. ​ The compression circuit variably sets the second compression efficiency based on a first parameter. The first parameter includes at least one of the performance of the processor, the processing congestion status of the processor, and the communication congestion status of the processor, and is a memory control device. **Claim 5**: A memory control device for controlling a memory in which compressed data is stored, an expansion circuit that expands data read from the memory in response to a request from a processor by hardware processing; a data holding circuit that temporarily holds the data expanded by the expansion circuit as holding data and outputs the holding data to the processor in response to a request from the processor; comprising: the data stored in the memory is compressed at a first compression efficiency; a compression circuit that recompresses the data expanded by the expansion circuit at a second compression efficiency lower than the first compression efficiency and inputs the recompressed data to the data holding circuit; further comprising: the data holding circuit holds the data input from the compression circuit as the holding data; the compression circuit variably sets the second compression efficiency based on a first parameter; the compression circuit changes the second compression efficiency based on a second parameter and further performs expansion and recompression on the holding data held by the data holding circuit, and is a memory control device. **Claim 6** The second parameter includes at least one of the read frequency of the holding data held by the data holding circuit, the performance of the processor, the processing congestion status of the processor, and the communication congestion status of the processor. The memory control device according to claim 5. **Claim 7** The second parameter includes the read frequency; the compression circuit changes the second compression efficiency to a value higher than the current value when the read frequency is less than a first threshold. The memory control device according to claim 6. **Claim 8** The second parameter includes the read frequency; the compression circuit changes the second compression efficiency to a value lower than the current value when the read frequency is greater than or equal to a first threshold. The memory control device according to claim 6 or 7. **Claim 9** The second parameter includes the communication congestion status. The compression circuit changes the second compression efficiency to a value higher than the current value when the communication congestion situation is equal to or higher than a second threshold value, according to the memory control device of claim 6.

10. The second parameter includes the communication congestion situation, The compression circuit changes the second compression efficiency to a value lower than the current value when the communication congestion situation is less than a second threshold value, according to the memory control device of claim 6 or 9.

11. A processor, A memory storing compressed data, A memory control device for controlling the memory, Comprising: The memory control device, An expansion circuit that expands data read from the memory in response to a request from the processor by hardware processing, A data holding circuit that temporarily holds the data expanded by the expansion circuit as holding data and outputs the holding data to the processor in response to a request from the processor, A parameter holding circuit that holds a plurality of expansion parameters used for expanding data by the expansion circuit, selects an expansion parameter corresponding to the data to be expanded from the plurality of held expansion parameters, and inputs the selected expansion parameter to the expansion circuit, Having: The expansion circuit inputs parameter selection information added to a header of the data read from the memory to the parameter holding circuit, The parameter holding circuit selects the expansion parameter based on the input parameter selection information, an information processing system.

12. A memory control method for controlling a memory storing compressed data, comprising: An expansion circuit expands data read from the memory in response to a request from a processor by hardware processing, A data holding circuit temporarily holds the data expanded by the expansion circuit as holding data and outputs the holding data to the processor in response to a request from the processor, A parameter holding circuit holds a plurality of expansion parameters used for expanding data by the expansion circuit, selects an expansion parameter corresponding to the data to be expanded from the plurality of held expansion parameters, and inputs the selected expansion parameter to the expansion circuit, The expansion circuit inputs parameter selection information added to a header of the data read from the memory to the parameter holding circuit, A memory control method in which the parameter holding circuit selects the expansion parameter based on the input parameter selection information.

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