Vertical transmon qubit device

Abstract

The chip surface-based device structure comprises a first superconducting material physically bonded to a crystalline substrate, the crystalline substrate physically bonded to a second superconducting material, the second superconducting material physically bonded to the second crystalline substrate; and in one embodiment, the chip surface-based device structure comprises a vertical Josephson junction positioned in a via in the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and a second superconducting material; and in one embodiment, the chip surface-based device structure comprises a vertical transmon qubit device comprising a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

Description

Technical Field

[0001] The present invention generally relates to superconducting devices, and more particularly to the manufacture of a vertical transmon qubit device having a vertical Josephson junction.

Background Art

[0002] Quantum computing generally refers to the use of quantum mechanical phenomena for the purpose of performing computational and information processing functions. Quantum computing can generally be considered in contrast to classical computing, which operates with binary values using transistors. That is, while a classical computer can operate with bit values of 0 or 1, a quantum computer operates with qubits that include superpositions of 0 and 1, can entangle multiple qubits, and utilizes interference.

[0003] The hardware of quantum computing can be different from that of classical computing. In particular, superconducting quantum circuits generally rely on Josephson junctions that can be fabricated in semiconductor devices. A Josephson junction generally gives rise to the Josephson effect of a supercurrent, where in this case the current can flow unrestrictedly across the Josephson junction without the application of a voltage. A Josephson junction can be formed, for example, by weakly coupling two superconductors (materials that conduct electricity without resistance and are also referred to as superconductors) by a tunnel barrier.

[0004] As a method of making Josephson junctions available for quantum computing, there is a method of constructing a quantum bit (qubit) by embedding a Josephson junction in a superconducting circuit. A Josephson junction can be used to construct a qubit by being arranged in parallel with a shunt capacitor. Such an arrangement of a Josephson junction in parallel with a shunt capacitor is sometimes referred to as a transmon (a shortened form of a phrase transmission line shunted plasma oscillation qubit) when the shunt capacitor has a large capacitance such that the typical ratio of the Josephson energy to the charging energy in the qubit is greater than 10. In some scenarios where the ratio of the Josephson energy to the charging energy in the qubit is small, it may not be referred to as a transmon, but in this specification, the term "transmon" can represent any arrangement of a Josephson junction in parallel with a shunt capacitor. There are also other superconducting qubits that are not transmon qubits.

[0005] Transmons are generally less sensitive to charge noise compared to some other types of qubits. One mechanism by which the sensitivity of a transmon to charge noise can be reduced is an increase in the ratio of the Josephson energy to the charging energy.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Some problems with some prior art transmon qubits include the fact that they occupy a relatively large space. Specifically, the planar capacitors used in some transmon qubits occupy a large area. The miniaturization of such transmon qubits is limited by both surface losses and dielectric losses.

[0008] And for some types of prior art Josephson junctions, there are also problems when applying them to the manufacture of transmons from these Josephson junctions. Low-loss and low-critical-current types of Josephson junctions can be composed of obliquely evaporated aluminum, aluminum oxide, and aluminum (Al-AlOx-Al). However, problems with such Josephson junctions include the fact that once the Josephson junction is formed, the resulting device is subject to low-temperature and process constraints.

Means for Solving the Problems

[0009] The following presents an overview that enables a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify key or important elements, nor is it intended to define any scope of a particular embodiment or claims. Its sole purpose is to present concepts in a simplified form as an introduction to the more detailed description presented below. In one or more embodiments described herein, a device, system, chip surface-based device structure, computer-implemented method, apparatus, or computer program product, or a combination thereof, that results in a vertical transmon qubit device is described.

[0010] According to one embodiment, a chip surface-based device structure is provided. In one example, this chip surface-based device structure is a first superconducting material physically bonded to a crystalline substrate, where the crystalline substrate is physically bonded to a second superconducting material, and the second superconducting material is physically bonded to a second crystalline substrate, and includes the first superconducting material. In one or more embodiments, this chip surface-based device structure is a vertical Josephson junction positioned in a via of the crystalline substrate, and may further include a vertical Josephson junction including a first superconducting material, a tunnel barrier, and a second superconducting material. Also, in one or more embodiments, this chip surface-based device structure may include a transmon qubit including a vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

[0011] In some examples, this chip surface-based device structure further includes an information transfer circuit in the second superconducting material communicatively coupled to the transmon qubit. An advantage of such a chip surface-based device structure is that the transmon qubit and the information transfer circuit can be separated from each other (except for an intentional coupling for the purpose of computing), so that quantum information does not leak unnoticed from the transmon qubit.

[0012] In another embodiment, a method is provided. In one example, the method includes physically bonding a first superconducting material to a crystalline substrate. The method may further include physically bonding the crystalline substrate to a second superconducting material physically bonded to a second crystalline substrate. The method may further include forming a vertical Josephson junction, including the first superconducting material, a tunnel barrier, and the second superconducting material, in a via of the crystalline substrate. The method may further include forming a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. As an advantage of such a method, it is considered possible to be used in the manufacture of a transmon qubit with improved scaling due to the reduced mounting area of the shunt capacitor as compared to other types of capacitors.

[0013] In some examples, the method may further include removing a portion of the crystalline substrate such that an edge of the crystalline substrate is positioned within an edge of the second superconducting material. As an advantage of such a method, it is considered that the coupling to an external circuit is suppressed by such a narrow superconducting material.

[0014] In another embodiment, a chip surface-based device structure is provided. In one example, the chip surface-based device structure is a vertical Josephson junction formed in a via of a crystalline substrate and includes a vertical Josephson junction including a first superconducting material physically bonded to a tunnel barrier physically bonded to a second superconducting material. In one or more embodiments, the chip surface-based device structure may further include a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. As an advantage of such a chip surface-based device structure, it is considered possible to enable scaling due to the reduction in the mounting area of the capacitor as compared to other types of capacitors.

[0015] In some examples, this chip surface-based device structure is formed by a first superconducting material and a crystal substrate, and further includes a second transmon qubit separated from cross-talk from the transmon qubit. As an advantage of such a chip surface-based device structure, the transmon qubit and the second transmon qubit are sufficiently controlled, and unnecessary transfer of quantum information does not occur between the two qubits. As an advantage of such a chip surface-based device structure, the transmon qubit and other superconducting qubits are sufficiently controlled, and unnecessary transfer of quantum information does not occur between the two qubits (i.e., other superconducting qubits are separated from cross-talk from the transmon qubit).

[0016] In another embodiment, a method is provided. In one example, the method includes configuring a vertical Josephson junction including a first superconducting material physically coupled to a tunnel barrier physically coupled to a second superconducting material in a via of a crystal substrate. The method may further include configuring a transmon qubit including a vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. As an advantage of such a method, it is considered to be usable for manufacturing a transmon qubit with improved scaling due to a smaller mounting area of the capacitor compared to other types of capacitors.

[0017] In some examples, the method may further include covering a part of the second superconducting material located outside the vertical Josephson junction with a crystal substrate. As an advantage of covering a part of the second superconducting material with the substrate in this way, it is considered that the said part of the second superconducting material is protected from oxidation.

[0018] In another embodiment, a chip surface-based device structure is provided. In one example, this chip surface-based device structure is a vertical Josephson junction formed in a silicon-on-metal (SOM)-based via, where the SOM comprises a vertical Josephson junction that is a superconductor. In one or more embodiments, this chip surface-based device structure may further comprise a transmon qubit having a capacitor formed between a part of the vertical Josephson junction and the superconductor of the SOM and a second superconducting material. The advantage of such a chip surface-based device structure is considered to enable scaling by reducing the mounting area of the capacitor compared to other types of capacitors.

Brief Description of the Drawings

[0019]

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DETAILED DESCRIPTION OF THE INVENTION

[0020] The following detailed description is merely an example and is not intended to limit the embodiments or the application and / or use of the embodiments, either singly or in combination. Further, there is no intention to be bound by any express or implied information presented in the foregoing background or summary sections or the detailed description sections.

[0021] Hereinafter, one or more embodiments will be described with reference to the drawings, and throughout the description, the same reference numerals will be used to refer to the same elements. In the following description, for the purpose of explanation, many specific details are set forth to enable a deeper understanding of one or more embodiments. However, it is clear that one or more embodiments can be implemented without these specific details in various cases.

[0022] Given the above problems with conventional transmon qubits, the present disclosure can be implemented to produce a solution to at least some of these problems in the form of a transmon qubit with a vertical Josephson junction. As used herein, some embodiments describing a transmon qubit (or a Josephson junction) may represent a vertical transmon qubit (or a vertical Josephson junction). Such a vertical transmon qubit may have the advantage of direct integration into a circuit. Also, such a vertical transmon qubit has improved qubit characteristics because transmon decoherence is suppressed compared to some other vertical transmon qubits. Such a vertical transmon qubit may have the advantage of being embedded in a very low-loss environment. Such a vertical transmon qubit may have the advantage of enabling scaling by reducing the capacitor mounting area. Also, the capacitor associated with the transmon is in parallel with the Josephson junction (i.e., shunts), and thus may also be referred to as a shunt capacitor. Such a vertical transmon qubit may have the advantage of improved frequency variation with respect to a vertical transmon qubit formed using an oblique evaporation process.

[0023] Such a vertical transmon qubit may have the advantage of enabling scaling of the production of qubit junctions because a manufacturing (or process) flow that is compatible with chip manufacturing techniques is involved. Such a vertical transmon qubit may have the advantage of suppressing the occupied volume while maintaining a uniform electric field distribution in the associated shunt capacitor (i.e., while avoiding local electric field concentration) because the electric field distribution is restricted within the vertical transmon qubit. Such a vertical transmon qubit may have the advantage of enabling a plurality of techniques for capacitively coupling the vertical transmon qubit to a resonator.

[0024] FIG. 1 shows an exemplary and non-limiting chip surface-based device structure with a vertical Josephson junction according to one or more embodiments described herein. The chip surface-based device structure 100 includes a substrate 102, a superconductor 104, substrates 106A, 106B, a superconductor 108, a tunnel barrier 110, a superconductor 112, and a superconductor 114. Details of exemplary materials and exemplary manufacturing techniques are described below and are also described in the related U.S. Patent Application No. 15 / 934,400, filed on March 23, 2018.

[0025] In some examples, substrates 102 and 106 may have an initial thickness of about 500 micrometers (μm) to 800 μm. And in some examples, various materials can be used at temperatures up to about 500 °C. In some examples, low melting point materials such as aluminum (Al) can be used, but these materials begin to deform at about 300 °C.

[0026] Of course, some similar components of the chip surface-based device structure 100 contact each other. For example, superconductor 104 and superconductor 108 contact each other, and superconductor 112 and superconductor 114 contact each other. Of course, this is a logical depiction. In some embodiments, these contacting superconductors can be of the same material and can be deposited in one step. In other embodiments, these contacting superconductors can be of different (or still the same) materials deposited in separate steps.

[0027] The vertical Josephson junction of the chip surface base device structure 100 includes a tunnel barrier 110, where superconductor 108 functions as the first capacitor plate of the vertical Josephson junction (optionally, in combination with superconductor 104), and superconductor 112 functions as the second capacitor plate of the vertical Josephson junction (optionally, in combination with superconductor 114). In some examples, the thickness of the superconductor of the first capacitor plate and the thickness of the superconductor of the second capacitor plate are substantially the same. This thickness can be more than 100 nm.

[0028] In an example where the same superconducting material is used for both the first capacitor plate and the second capacitor plate, the superconducting gaps on both sides of the tunnel barrier can be made equal, which can be utilized in determining the critical current of the vertical Josephson junction. The value of the critical current of the vertical Josephson junction can be based on the materials used, the thickness of the tunnel barrier 110, and the surface area of the materials during the junction. Forming a plurality of vertical Josephson junctions with higher reproducibility between the relevant critical currents can be based on the type of materials used, the thickness of the materials, and the size of the openings of the vertical Josephson junctions.

[0029] Another measurement criterion associated with the vertical Josephson junction is the thickness of the material of the vertical Josephson junction where the magnetic field does not penetrate. When Al is used as the material of a certain layer, the thickness of such material can be 100 - 200 nm. Another material that can be used is tungsten (W), which has different properties from Al when applied to the penetration of the magnetic field.

[0030] A vertical Josephson junction can be formed in a via of a substrate layer including substrate 106A and substrate 106B, and originally may have included a substrate on which superconductor 108, tunnel barrier 110, and superconductor 112 were positioned. The via generally can include an opening through a layer of the chip - base surface capable of forming a conductive connection between two other layers. This via can be formed by etching the substrate. In some examples, etching lithography can be implemented to etch a via with a depth of 100 - 200 nm. In some examples, a 1:1 aspect ratio of the height to the width of the via can be achieved.

[0031] Naturally, chip surface base - device structure 100 presents one of multiple embodiments of a vertical Josephson junction that can be utilized in a vertical transmons qubit according to the technology of the present disclosure. For example, there can be an embodiment of a vertical Josephson junction in which superconductor 108 is omitted such that tunnel barrier 110 contacts superconductor 104. For example, there can also be an embodiment of a vertical Josephson junction in which superconductor 112 is omitted (thereby thickening superconductor 108), and a tunnel barrier exists at the "top" of the via, which is a location in the via at the opposite end of superconductor 104.

[0032] In some examples, tunnel barrier 110 can be deposited on chip surface base - device structure 100 using a sputtering technique, a vapor deposition technique, an atomic layer deposition (ALD) technique, or chemical modification (e.g., oxidation) of superconductor 104 or superconductor 108. In some examples, as tunnel barrier 110, aluminum oxide (Al2O3), a non - superconducting metal (sometimes referred to as a typical metal), an oxide, or a nitride is possible. In some examples, tunnel barrier 110 can be formed by oxidation of the exposed surface (after etching) of superconductor 104 or superconductor 108. Generally, as the tunnel barrier layer, a thin layer of a non - conductive material is possible.

[0033] In the chip surface-based device structure 100, the superconductor 104 and the superconductor 108 (and the superconductor 112 and the superconductor 114) are in contact with or close to each other. Generally, two superconductors arranged adjacent to each other in this configuration or a similar configuration behave as a single superconductor, and even if these two superconductors are made of different materials from each other, they will exhibit a single superconducting layer.

[0034] The chip surface-based device structure 100 is considered an embedded metal flow. In some examples, a part of the superconductor 104 is deposited on the substrate 102, and a part of the superconductor 104 is deposited on the substrate 106. Then, by integrally bonding these two parts of the superconductor 104, the substrate 102 can be connected to the superconductor 104 and the substrate 106. In other words, after depositing each part of the superconductor 104 on the substrate 102 and the substrate 106 respectively, the exposed surface of the first part of the superconductor 104 can be bonded to the exposed surface of the second part of the superconductor 104. In some examples, the bonding can be achieved by low-temperature annealing or another adhesion technique. There are other terms that can refer to the configuration of the chip surface-based device structure, such as silicon-on-metal (SOM).

[0035] And the upper substrate layer including the substrates 106A and 106B can be polished to a thickness of about 100 - 200 nm either before or after the integral bonding of the substrate 106, the superconductor 104, and the substrate 102. This thickness of 100 - 200 nm can be obtained by acquiring a crystalline silicon wafer of this thickness (such as those grown by the manufacturer), or by acquiring a crystalline silicon wafer with a thickness greater than 100 - 200 nm and removing a part of the crystalline silicon so that the thickness becomes 100 - 200 nm after bonding the substrate, the superconductor, and the second substrate.

[0036] In some examples, in addition to superconductor 104, other superconductors described herein may include titanium (Ti), tantalum (Ta), and titanium nitride (TiN). In other examples, in addition to superconductor 108, some superconductors described herein may include niobium (Nb) or aluminum (Al). Conditions related to the arrangement of materials in the chip surface-based device structure, such as the properties of specific materials and the amount of heat treatment involved in a layer of the chip surface-based device structure, can affect the selection of materials.

[0037] A side cross-sectional view of the chip surface-based device structure 100 shows that the substrates 106A and 106B are separated. However, of course, holes are formed in this substrate layer as shown in this side cross-sectional view, and the substrates 106A and 106B are still connected (for example, when viewed from above, it appears that a hole is formed in the center of this substrate). Other materials in the side cross-sectional view can be attached in the same way, but in the side cross-sectional view, they appear to be separated.

[0038] In some examples, in addition to substrate 102, substrate 106A, and substrate 106B, one or more of the other substrates described herein may include crystalline silicon (Si). The use of crystalline Si can improve the coherence time of qubits associated with the vertical Josephson junctions described herein. Also, in some examples, high-resistance crystalline Si can be utilized to further improve the coherence time. In some examples, this crystalline Si can be grown.

[0039] In some examples, these various superconductors (i.e., superconductor 104, superconductor 108, superconductor 112, and superconductor 114) may include different types of materials. In other examples, the same type of material is possible for two or more of these various superconductors. In one embodiment, it is possible that superconductor 104 is Ti, superconductor 108 is Ta, superconductor 112 is Ta (the same as superconductor 108), and superconductor 114 is TiN. In some examples, superconductor 112 is deposited thicker than superconductor 104 or superconductor 108 or both, and this increase in thickness can facilitate better control when later removing part or all of the layer of superconductor 108.

[0040] FIG. 2 shows an exemplary and non-limiting chip surface-based device structure of FIG. 1 after removing some materials, according to one or more embodiments described herein. Such removal of some materials may be performed in the process of forming a vertical transmon qubit from the vertical Josephson junction of FIG. 1.

[0041] In FIG. 2, a part of substrate 106A is removed to produce substrate 206A. In the chip surface-based device structure 200, a part of substrate 106B is removed to produce substrate 206B. A part of superconductor 114 is removed to produce superconductor 214, which may also be referred to as a top plate. As shown in FIG. 2 and elsewhere, etching (such as etching lithography, etc.) can be used to achieve material removal. In some examples, the chip surface-based device structure 200 is formed from the chip surface-based device structure 100 using a mask reactive ion etching (RIE) technique.

[0042] Figure 3 shows an exemplary and non-limiting chip surface-based device structure of FIG. 2 after removing some materials to form a vertical transmon qubit 350. In the chip surface-based device structure 300, a part of the superconductor 104 is removed to generate a superconductor 304A, a superconductor 304B, and a superconductor 304C. For this reason, the chip surface-based device structure 300 includes a vertical transmon qubit including a superconductor 304B (also referred to as a bottom plate), a substrate 206A, a substrate 206B, a superconductor 108, a tunnel barrier 110, a superconductor 112, and a superconductor 214. In some examples, the chip surface-based device structure 300 is formed from the chip surface-based device structure 200 using a mask-RIE technique.

[0043] In one example, the superconductor 214 may have a width of about 7.5 micrometers (μm). The superconductor 112, the tunnel barrier 110, and the superconductor 108 may have a width of about 100 nanometers (nm). The substrates 206A and 206B may have a height of about 100 nm. Also, the distance between the superconductor 304A and the superconductor 30 4B and the distance between the superconductor 304B and the superconductor 304C can be about 10 μm. Using these exemplary dimensions, the transmon of the chip surface-based device structure 300 will have measurement criteria such as a capacitance C of about 60 femtofarads (fF), a height and width of a vertical Josephson junction of about 100 nm each, a dielectric constant (εSi) of Si of about 11.7, and a lateral size of the transmon of about 7.5 μm.

[0044] Also, the substrates 206A and 206B may have a thickness of 50 - 300 nm or 20 - 500 nm with the width of the corresponding vertical Josephson junction. Here, the capacitance can be determined as capacitance = (dielectric constant of the plate × area / interval) × dielectric constant of vacuum. And the dielectric constant of vacuum is 8.85×10 -12It is F / m. Thereafter, for a given capacitance, the corresponding spacing of the plate or plate area can be determined. This estimated value is neither the parasitic capacitance to the ground nor the inherent capacitance of the vertical Josephson junction, and relies on the assumption that the capacitance of the transmon is dominated by the plate of the shunt capacitor.

[0045] Since the transmon in this example is smaller, these dimensions and measurement criteria bring relatively typical transmon advantages. In contrast to this smaller transmon, a typical transmon can have a lateral size of 700 μm, which is nearly two orders of magnitude larger than the lateral size of the transmon in this example.

[0046] FIG. 4 shows an exemplary and non-limiting chip surface-based device structure of FIG. 2 after removing some materials to form another vertical transmon qubit 450 according to one or more embodiments described herein. As a difference between the chip surface-based device structure 300 and the chip surface-based device structure 400, in the chip surface-based device structure 400, some materials of the upper superconducting layer (superconductor 414 (also referred to as the top plate)) and the upper substrate layer (substrates 406A and 406B) are removed with respect to the superconductor 304B, so that the edge of the superconductor 304B extends beyond the corresponding edges of the substrates 406A, 406B, and the superconductor 414.

[0047] In some examples, the superconductor 304B can have a single-sided connection, and in some examples, it can also have a multi-sided connection. As shown in the figure, since the vertical Josephson junction of the chip surface-based device structure 400 can have a height of about 100 - 200 nm, the spacing from the related bottom plate (superconductor 304B) to the resonator can be in the range of several microns. The top plate of the vertical Josephson junction (superconductor 414) can be narrowed with respect to the corresponding top plate of the chip surface-based device structure 300, thereby suppressing the coupling to the external circuit.

[0048] FIG. 5 shows an exemplary and non-limiting chip surface-based device structure of FIG. 3 after removing some materials to form another vertical transmon qubit 550 according to one or more embodiments described herein. As a difference between the chip surface-based device structure 300 and the chip surface-based device structure 500, in the chip surface-based device structure 500, some materials of the upper superconducting layer (superconductor 514 (also referred to as the top plate)) are removed with respect to the superconductor 304B, the substrate 206A, and the substrate 206B, so that the edges of the superconductor 304B, the substrate 206A, and the substrate 206B extend beyond the corresponding edges of the superconductor 514.

[0049] FIG. 6 is a top view of an exemplary and non-limiting chip surface-based device structure of FIG. 4 according to one or more embodiments described herein. The dashed line 616 indicates the location of a side cross-sectional view of the chip surface-based device structure 400 with respect to the chip surface-based device structure 600. While the chip surface-based device structure 400 shows a side view of the chip surface-based device structure, the chip surface-based device structure 600 shows a corresponding top view of this chip surface-based device structure. According to the chip surface-based device structure 600, (in contrast to the rectangular shape of the vertical transmon qubit of the chip surface-based device structure 700) the vertical transmon qubit is formed in a circular shape.

[0050] The chip surface-based device structure 600 is characterized by a circular capacitor pad shape. In one embodiment where the superconductor 304B is formed in a circular shape, the superconductor 604B includes the superconductor 304B. In one embodiment where the superconductor 414 is configured in a circular shape, the superconductor 614 includes the superconductor 414. Similarly, in the top view of this chip surface-based device structure 600, in one embodiment where the substrate 102 is substantially circularly exposed, the substrate 602 includes the substrate 102 (however, there is a portion of the substrate 602 that is not exposed in this figure, and the substrate 602 can extend across the entire chip surface-based device structure 600).

[0051] In the chip surface-based device structure 600, the superconductor 304A and the superconductor 304C can function as couplers to an external circuit. Also, through the same circuit, a plurality of qubits can be connected.

[0052] In this specification, circular and rectangular (or square) shapes are described. Of course, suitable shapes can be substantially circular, substantially elliptical, substantially rectangular, or substantially square, and other embodiments using other shapes may exist.

[0053] The superconductor 604D and the superconductor 604E include any superconductor that is not visible when considering the cross-sectional view of FIG. 4.

[0054] In FIG. 6 (and similar drawings showing top views), the superconductor 304A and the superconductor 304C function as microwave interconnects or resonators (also sometimes referred to as microwave resonators or resonant buses). That is, since the superconductor 304A, the superconductor 304B, and the superconductor 304C can be considered as the lower superconductor layer of the chip surface-based device structure, this lower superconductor layer can be used for communicating access to the vertical transmon qubit. In various examples, the vertical transmon qubit includes a vertical Josephson junction and two capacitor pads (sometimes referred to as an upper capacitor pad and a lower capacitor pad respectively), and a communication connection can also be configured using either of these two capacitor pads.

[0055] The coupling between the resonator and the qubit is affected by placing a capacitor between the resonator and the qubit. The resonator can enable the measurement of the transmon, the control of the transmon, the coupling to the transmon, or the coupling of the transmon to other transmons, or a combination thereof.

[0056] FIG. 7 is another top view of an exemplary and non-limiting chip surface-based device structure of FIG. 4, according to one or more embodiments described herein. While chip surface-based device structure 400 shows a side view of the chip surface-based device structure, chip surface-based device structure 700 shows a corresponding top view of this chip surface-based device structure. According to chip surface-based device structure 700, a vertical transmon qubit is formed in a rectangular shape (in contrast to the circular shape of the vertical transmon qubit of chip surface-based device structure 600).

[0057] Chip surface-based device structure 700 is characterized by a rectangular capacitor pad shape. In one embodiment where superconductor 304B is formed in a rectangular (or square) shape, superconductor 704B includes superconductor 304B. In one embodiment where superconductor 414 is configured in a rectangular shape, superconductor 714 includes superconductor 414. Similarly, in a top view of this chip surface-based device structure 700, in one embodiment where substrate 102 is substantially rectangular and exposed, substrate 702 includes substrate 102 (however, there is a portion of substrate 702 that is not exposed in this figure, and substrate 702 can extend across the entire chip surface-based device structure 700).

[0058] Given this configuration, chip surface-based device structure 700 is considered to have an etched island layout. There are other terms that can refer to the configuration of the chip surface-based device structure.

[0059] FIG. 8 shows an exemplary and non-limiting chip surface-based device structure of FIG. 1 after removing some materials to form another vertical transmon qubit. The chip surface-based device structure 800 is similar to the chip surface-based device structure 300, but in the chip surface-based device structure 800, substrates 806C and 806D are present (because they have not been removed by etching). By having substrates 806C and 806D, the superconducting conductors 304A and 304B are not exposed to air, thus improving the protection from oxidation for the chip surface-based device structure 300. The configuration in this chip surface-based device structure 800 can correct the metal-air contribution to the resonator, for example, as compared to the configuration in the chip surface-based device structure 500.

[0060] FIG. 9 is a top view of the exemplary and non-limiting chip surface-based device structure of FIG. 8 according to one or more embodiments described herein. The dashed line 916 indicates the location of a side cross-sectional view of the chip surface-based device structure 800 with respect to the chip surface-based device structure 900. While the chip surface-based device structure 800 shows a side view of the chip surface-based device structure, the chip surface-based device structure 900 shows a corresponding top view of this chip surface-based device structure. According to the chip surface-based device structure 900, the vertical transmon qubit is formed in a circular shape (in contrast to the rectangular shape of the vertical transmon qubit of the chip surface-based device structure 1000).

[0061] The chip surface-based device structure 900 features a circular capacitor pad shape. In one embodiment where the substrates 106A and 106B are formed in a circular shape, the substrate 906A includes both substrates 106A and 106B. In side view, the substrates 106A and 106B appear to be separated by a vertical Josephson junction. However, in top view, they appear to be connected as represented by the substrate 906A. In one embodiment where the superconductor 414 is configured in a circular shape, the superconductor 914 includes the superconductor 414. Similarly, in one embodiment where the substrate 102 is configured substantially in a circular shape, the substrate 902 includes the substrate 102.

[0062] The substrates 906D and 906E include any substrates that are not visible when considering the cross-sectional view of FIG. 8. In the chip surface-based device structure 900, multiple qubits can be connected through the same circuit.

[0063] FIG. 10 is a top view of an exemplary and non-limiting chip surface-based device structure according to one or more embodiments described herein. The dashed line 1016 indicates the location of a side cross-sectional view of the chip surface-based device structure 800 with respect to the chip surface-based device structure 1000. While the chip surface-based device structure 800 shows a side view of the chip surface-based device structure, the chip surface-based device structure 1000 shows a corresponding top view of this chip surface-based device structure. According to the chip surface-based device structure 1000, (in contrast to the circular shape of the vertical transmon qubit of the chip surface-based device structure 900) the vertical transmon qubit is formed in a rectangular shape.

[0064] The chip surface-based device structure 1000 features a rectangular capacitor pad shape. In one embodiment where substrates 106A and 106B are formed in a rectangular (or square) shape, substrate 1006A includes both substrates 106A and 106B. In a side view, substrates 106A and 106B appear to be separated by a vertical Josephson junction. However, in a top view, they appear to be connected as represented by substrate 1006A. In one embodiment where the superconductor 414 is configured in a rectangular (or square) shape, superconductor 1014 includes superconductor 414. Similarly, in one embodiment where substrate 102 is configured substantially in a rectangular (or square) shape, substrate 1002 includes substrate 102.

[0065] Given this configuration, the chip surface-based device structure 1000 is considered to have an etched island layout.

[0066] FIG. 11 shows an exemplary and non-limiting chip surface-based device structure of FIG. 1 after performing both addition and removal of some materials to form another vertical transmon qubit 1120 according to one or more embodiments described herein. As a difference between the chip surface-based device structure 1100 and the chip surface-based device structure 300, in the chip surface-based device structure 1100, superconductor 1114 extends wider than superconductor 214 of the chip surface-based device structure 300. That is, superconductor 1114 (also referred to as the top plate) extends wider than superconductor 304B. In some examples, superconductor 1114 can extend so as to cross both the interval between superconductor 304A and superconductor 304B and the interval between superconductor 304B and superconductor 304C. In some examples, superconductor 1114 extends above at least a part of one or both of superconductor 304A and superconductor 304B.

[0067] By lengthening the superconductor 1114 relative to other top plates, an elongation of the top plate may enable coupling away from the associated vertical Josephson junction 1116 (formed in the vias 1118 of the superconductors 206A and 206B). In other embodiments, while the top plate is lengthened, it does not overlap with the lower superconductors (i.e., superconductors 304A and 304C) that may include outer circuit island portions.

[0068] In some examples, as the superconductor 304A (or 304C), a part of the information transfer circuit communicatively coupled to the transmon qubit 1120 (or 350, 450, 550) is possible. In different examples, the information transfer circuit may include an input, output, or readout circuit, or one or more resonant buses.

[0069] In some examples, at least a part of the second superconducting material 304A (or 304C) can be positioned outside the transmon qubit and used as the resonant bus 304A (or 304C). In some examples, at least a part of the second superconducting material positioned outside the transmon qubit can be covered by a crystal substrate (similar to the way the crystal substrate 806C in FIG. 8 covers a part of the superconductor 304A).

[0070] In some examples, the resonant bus 304C can electrically couple the transmon qubit to a second transmon qubit, an input, output, or readout circuit, or a second resonant bus 304A, and the resonant bus 304C is formed on a second superconducting material (e.g., superconductor 304B). In some examples, the resonant bus 304A (or 304B) can be covered by a crystal substrate (similar to the way the crystal substrate 806C in FIG. 8 covers a part of the superconductor 304A).

[0071] In some examples, the resonance bus 304C can electrically couple a transmon qubit to another superconducting qubit, an input, output, or readout circuit, or a second resonance bus 304A, and the resonance bus 304C is formed on a second superconducting material (e.g., superconductor 304B). In some examples, the resonance bus 304A (or 304B) can be covered by a crystalline substrate (e.g., in a manner similar to the crystalline substrate 806C covering a portion of the superconductor 304A in FIG. 8).

[0072] FIG. 12 shows an exemplary and non-limiting chip surface-based device structure of FIG. 1 after initially removing some materials in the process of constructing the vertical transmon qubit 1120 of FIG. 11, according to one or more embodiments described herein. Of course, the chip surface-based device structure 1200 is similar to the chip surface-based device structure 200, but without the superconductor 214. Further, of course, there may be embodiments in which the chip surface-based device structure 1200 is formed by starting from a chip surface-based device structure different from the chip surface-based device structure 100, such as a chip surface-based device structure with the superconductor 114 omitted. In some examples, the chip surface-based device structure 1200 is formed from the chip surface-based device structure 100 using a mask-RIE technique.

[0073] FIG. 13 shows an exemplary and non-limiting chip surface-based device structure of FIG. 12 after removing some materials, according to one or more embodiments described herein. Of course, the chip surface-based device structure 1300 is similar to the chip surface-based device structure 300, but the superconductor 214 does not exist. The difference between the chip surface-based device structure 1300 and the chip surface-based device structure 1200 is that in the chip surface-based device structure 1300, by removing a part of the superconductor 104 with respect to the chip surface-based device structure 1200, the superconductors 304A, 304B, and 304C are generated. Also, the distance between the superconductor 304A and the superconductor 304B and the distance between the superconductor 304B and the superconductor 304C may be larger in the chip surface-based device structure 1300 than in the chip surface-based device structure 300. In some examples, the chip surface-based device structure 1300 is formed from the chip surface-based device structure 1200 using a mask-RIE technique.

[0074] FIG. 14 shows an exemplary and non-limiting chip surface-based device structure of FIG. 13 after adding some materials, according to one or more embodiments described herein. The material added in the chip surface-based device structure 1400 with respect to the chip surface-based device structure 1300 is the sacrificial material 1416. By adding the sacrificial material 1416, after finally providing a platform for adding the superconductor 1114, the sacrificial material 1416 is finally removed.

[0075] In some examples, the sacrificial material 1416 may include an oxide. In other examples, instead of using a sacrificial material that will be completely removed later, epitaxial silicon can be used as an addition or alternative to the sacrificial material, and at least any epitaxial silicon will remain in the resulting chip surface-based device structure with a vertical transmon qubit.

[0076] FIG. 15 shows an exemplary and non-limiting chip surface-based device structure of FIG. 14 after removing some of the materials, according to one or more embodiments described herein. In the chip surface-based device structure 1500, by removing some of the sacrificial material 1416 with respect to the chip surface-based device structure 1400, sacrificial material 1516A and sacrificial material 1516B are generated. In other words, the sacrificial material is removed up to the top height of the substrate 206A, substrate 206B, and superconductor 112. In an example where the sacrificial material 1516A contains silicon, CMP can be used for material removal. In an example where the sacrificial material 1516A contains an oxide, RIE can be used for material removal.

[0077] FIG. 16 shows an exemplary and non-limiting chip surface-based device structure of FIG. 15 after adding some of the materials, according to one or more embodiments described herein. In the chip surface-based device structure 1600, a superconductor 1114 is added with respect to the chip surface-based device structure 1500. The sacrificial material 1516A and the sacrificial material 1516B provide a support portion on which the superconductor 1114 can be placed while the superconductor 1114 is being added to the chip surface-based device structure 1600.

[0078] Thereafter, by removing the sacrificial material 1516A and the sacrificial material 1516B, the chip surface-based device structure 1100 of FIG. 11 can be generated. In some examples, the sacrificial material 1516A and the sacrificial material 1516B can be removed by vapor etching using hydrogen fluoride (HF) or the like.

[0079] Figure 17 is a top view of an exemplary and non-limiting chip surface-based device structure of FIG. 11 according to one or more embodiments described herein. While chip surface-based device structure 1100 shows a side cross-sectional view of the chip surface-based device structure, chip surface-based device structure 1700 shows a corresponding top view of this chip surface-based device structure. The position of the side cross-sectional view of FIG. 11 relative to the top view of FIG. 17 is indicated by line 1716. According to chip surface-based device structure 1700, (in contrast to the rectangular shape of the vertical transmon qubit of chip surface-based device structure 1800) the vertical transmon qubit is formed in a circular shape. In one embodiment where superconductor 1114 is formed in a circular shape, superconductor 1714 includes superconductor 1114.

[0080] Chip surface-based device structure 1700 is characterized by a circular capacitor pad shape. In chip surface-based device structure 1700, multiple qubits can be connected through the same circuit.

[0081] Figure 18 is another top view of an exemplary and non-limiting chip surface-based device structure of FIG. 11 according to one or more embodiments described herein. While chip surface-based device structure 1100 shows a side view of the chip surface-based device structure, chip surface-based device structure 1800 shows a corresponding top view of this chip surface-based device structure. According to chip surface-based device structure 1800, (in contrast to the circular shape of the vertical transmon qubit of chip surface-based device structure 1700) the vertical transmon qubit is formed in a rectangular shape. In one embodiment where superconductor 1114 is formed in a circular shape, superconductor 1814 includes superconductor 1114.

[0082] Chip surface-based device structure 1800 is characterized by a rectangular capacitor pad shape. Given this configuration, chip surface-based device structure 1800 is considered to have an etched island layout.

[0083] FIG. 19 is a flow diagram of an exemplary and non-limiting computer-implemented method that facilitates the implementation of a vertical transmon qubit device according to one or more embodiments described herein. In some examples, flow diagram 1900 can be implemented by computer 2112. Of course, the operations of flow diagram 1900 can be implemented in an order different from that shown.

[0084] In a non-limiting and exemplary embodiment, a computer device (or system) (e.g., computer 2112) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate the execution of the operations described herein, including the non-limiting method shown in the flow diagram of FIG. 19. As a non-limiting example, the one or more processors can facilitate the execution of the above method by instructing or controlling one or more devices operable to perform semiconductor manufacturing.

[0085] As an advantage of the method as shown in FIG. 19, it is considered possible to be used in the manufacture of a vertical transmon qubit device that can be scaled due to the reduced implementation area of the capacitor compared to other types of capacitors.

[0086] Operation 1902 indicates physically coupling a first superconducting material to a crystalline substrate (e.g., by computer 2112). As used herein, physically coupling two materials represents mechanically or chemically bonding these materials and is distinguishable from an electrical coupling that may include configuring two objects to transfer electrical signals to each other. In some examples, this physical coupling configuration can be represented as various materials being stacked on top of each other and can include a SOM base. Operation 1904 indicates physically coupling the crystalline substrate to a second superconducting material physically coupled to a second crystalline substrate (e.g., by computer 2112).

[0087] In some examples, this operation includes removing a portion of the substrate such that an edge of the substrate is positioned within an edge of a second superconducting material. For example, in a chip surface-based device structure 400, substrates 406A and 406B are possible as the substrate, and superconductor 304B is possible as the second superconducting material. In this example, it can be seen that superconductor 304B extends horizontally further away from the transmons than substrates 406A or 406B. Thus, the edges of substrates 406A and 406B that extend away from the transmons are positioned within the edges of superconductor 304B that extend away from the transmons.

[0088] In some examples, this operation includes removing a portion of the superconducting material such that an edge of the superconducting material is coplanar with an edge of the substrate. For example, in a chip surface-based device structure 400, substrates 406A and 406B are possible as the substrate, and superconductor 414 is possible as the superconducting material. In this example, it can be seen that superconductor 414 extends horizontally away from the transmons by the same amount as substrates 406A or 406B. Thus, the edges of superconductor 414 that extend away from the transmons are coplanar with the edges of substrates 406A and 406B that extend away from the transmons.

[0089] In some examples, this operation includes removing a portion of the superconducting material such that an edge of the superconducting material is positioned within an edge of the substrate. For example, in a chip surface-based device structure 500, substrates 206A and 206B are possible as the substrate, and superconductor 514 is possible as the superconducting material. In this example, it can be seen that substrates 206A and 206B extend horizontally further away from the transmons than superconductor 514. Thus, the edges of superconductor 514 that extend away from the transmons are positioned within the edges of substrates 206A and 206B that extend away from the transmons.

[0090] Operation 1906 shows forming a vertical Josephson junction, including a first superconducting material, a tunnel barrier, and a second superconducting material, in a via of a crystal substrate (e.g., by computer 2112).

[0091] For example, in chip surface-based device structure 100, the vertical Josephson junction can include superconductor 108, tunnel barrier 110 (functioning as the tunnel barrier in this case), and superconductor 112. This vertical Josephson junction is formed in the vias of substrates 106A and 106B (which could have been a continuous part of the substrate before the vias were formed and substrates 106A and 106B remained).

[0092] Operation 1908 shows forming a transmon qubit with a vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material (e.g., by computer 2112).

[0093] In some examples, forming a vertical transmon qubit with a vertical Josephson junction and a capacitor includes forming a second vertical transmon qubit separated from cross-talk from the vertical transmon qubit by a space in the second superconducting material from the superconducting material and the substrate. That is, a chip surface-based device structure such as chip surface-based device structure 100 can include a plurality of vertical transmon qubits, and these plurality of vertical transmon qubits can be separable from each other's cross-talk. In some examples where the chip surface-based device structure includes a plurality of vertical transmon qubits or where there are a plurality of vertical transmon qubits, a resonant bus can couple the vertical transmon qubit and the second vertical transmon qubit.

[0094] In some examples, the resonant bus is coupled to a second superconducting material. For example, this second superconducting material can include superconductor 304A or superconductor 304C of the chip surface-based device structure 300, and the resonant bus can be part of superconductor 304A or superconductor 304C, or can be coupled to superconductor 304A or superconductor 304C.

[0095] In some examples, the first superconducting material includes the resonant bus. For example, in the chip surface-based device structure 100, when the vertical Josephson junction is separated, a part of the superconductor 114 away from the vertical Josephson junction remains, and this part can function as the resonant bus.

[0096] Similarly, in some examples, the resonant bus is coupled to the superconducting material. Taking the chip surface-based device structure 100 as an example, when the vertical Josephson junction is separated, a part of the superconductor 114 away from the vertical Josephson junction remains, and this part can function as the resonant bus.

[0097] In some examples, the resonant bus is coupled to a vertical transmon qubit, and a second resonant bus is also coupled to the vertical transmon qubit. For example, in FIG. 6, both superconductor 304A and superconductor 304C can function as the resonant bus. Thus, as superconductor 304A, a resonant bus coupled to the vertical transmon qubit is possible, and as superconductor 304C, a second resonant bus coupled to the vertical transmon qubit is possible. In some examples, three or more resonant buses can be coupled to the vertical transmon qubit.

[0098] In some examples, the readout resonator is coupled to and addresses a vertical transmon qubit without coupling to a second vertical transmon qubit of the chip surface-based device structure. The chip surface-based device structure may comprise a plurality of vertical transmon qubits. When the chip surface-based device structure may comprise a plurality of vertical transmon qubits, a particular readout resonator may be coupled to only one of these vertical transmon qubits. For example, in a chip surface-based device structure 600, a superconductor 304A may function as a readout resonator and may be coupled to one vertical transmon qubit.

[0099] In some examples, the vertical transmon qubit comprises a vertical transmon qubit. Generally, as a vertical transmon qubit, a vertical transmon qubit with a vertical Josephson junction is possible. The vertical Josephson junction may be present, for example, in a chip surface-based device structure 100 and comprises a superconductor 108, a tunnel barrier 110, and a superconductor 112.

[0100] In some examples, this operation may include coupling the resonator to a first surface of the superconducting material such that the superconducting material includes a single-sided bond. A single-sided bond generally includes coupling of one resonator to a vertical transmon qubit. In a chip surface-based device structure 600, when a superconductor 304A functions as a resonator and a superconductor 304C is omitted, the superconductor 304A functions as a single-sided coupler to constitute a single-sided bond.

[0101] In some examples, this operation includes coupling a first resonator to a first surface of a superconducting material and coupling a second resonator to a second surface of the superconducting material such that the superconducting material includes a multi-faceted coupling (i.e., a plurality of resonators are electrically coupled to a plurality of surfaces of the first superconducting material). A multi-faceted coupling generally includes coupling of a plurality of resonators to one vertical transmon qubit. In the chip surface-based device structure 600, when both the superconductor 304A and the superconductor 304C each function as a resonator, the chip surface-based device structure 600 may have a multi-faceted coupling.

[0102] In some examples, a portion of a second superconducting material positioned outside of a vertical Josephson junction is exposed to air. For example, in the chip surface-based device structure 300, the superconductor 304A and the superconductor 304C can be portions of the superconducting material positioned outside of the vertical Josephson junction. Since the superconductor 304A and the superconductor 304C are not covered by another material such as a substrate, they are considered to be exposed to air. This configuration is in contrast to the chip surface-based device structure 800, where the superconductor 304A and the superconductor 304C are each covered by the substrate 806C and the substrate 806D, and thus are considered not to be exposed to air.

[0103] In some examples, this operation includes covering a portion of a second superconducting material positioned outside a vertical Josephson junction with a substrate such that the portion of the second superconducting material positioned outside the vertical Josephson junction is covered by the substrate. For example, in a chip surface-based device structure 800, the portion of the second superconducting material can be superconductor 304A and superconductor 304C. As seen in the chip surface-based device structure, superconductor 304A and superconductor 304C are each covered by substrate 806C and substrate 806D, respectively. By covering superconductor 304A and superconductor 304C with substrate 806C and substrate 806D, respectively, the upper interfaces of superconductor 304A and superconductor 304C are changed, and superconductor 304A and superconductor 304C can be protected against oxidation as a result of exposure to air.

[0104] FIG. 20 is a flow diagram of an exemplary and non-limiting computer-implemented method that facilitates the implementation of a vertical transmon qubit device according to one or more embodiments described herein. In some examples, flow diagram 2000 can be implemented by computer 2112. Of course, the operations of flow diagram 2000 can be implemented in an order different from that shown.

[0105] In a non-limiting and exemplary embodiment, a computer device (or system) (e.g., computer 2112) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate the execution of the operations described herein, including the non-limiting method shown in the flow diagram of FIG. 20. As a non-limiting example, the one or more processors can facilitate the execution of the above method by instructing or controlling one or more devices operable to perform semiconductor manufacturing.

[0106] As an advantage of the method as shown in FIG. 20, it is considered that it can be used for manufacturing a vertical transmon qubit device capable of scaling because the mounting area of the capacitor is smaller compared with other types of capacitors.

[0107] Operation 2002 shows configuring a vertical Josephson junction including a first superconducting material physically coupled to a tunnel barrier physically coupled to a second superconducting material in a via of a crystal substrate (e.g., by computer 2112). As used herein, physically coupling two materials is distinguishable from an electrical coupling that may include configuring two objects to transfer electrical signals while representing mechanically or chemically bonding these materials. In some examples, this physical coupling configuration can be represented as various materials being stacked on top of each other and may include a SOM base.

[0108] For example, in chip surface base device structure 100, the vertical Josephson junction may include a superconductor 108, a tunnel barrier 110 (functioning as a tunnel barrier in this case), and a superconductor 112. This vertical Josephson junction is formed in the vias of substrates 106A and 106B (which may have been a continuous portion of the substrate before the vias were formed and substrates 106A and 106B remained).

[0109] In some examples, this operation includes removing a portion of the substrate such that an edge of the substrate is positioned within an edge of the second superconducting material. For example, in chip surface base device structure 400, substrates 406A and 406B are possible as substrates, and superconductor 304B is possible as the second superconducting material. In this example, it can be seen that superconductor 304B extends horizontally further away from the transmon than substrates 406A or 406B. Therefore, the edges of substrates 406A and 406B that extend away from the transmon are positioned within the edges of superconductor 304B that extend away from the transmon.

[0110] In some examples, this operation includes removing a portion of the superconducting material such that an edge of the superconducting material is coplanar with an edge of the substrate. For example, in a chip surface-based device structure 400, substrates 406A and 406B are possible substrates, and superconductor 414 is a possible superconducting material. In this example, it can be seen that superconductor 414 extends horizontally from the transmons by the same amount as substrate 406A or substrate 406B. Thus, the edge of superconductor 414 that extends away from the transmons is coplanar with the edges of substrate 406A and substrate 406B that extend away from the transmons.

[0111] In some examples, this operation includes removing a portion of the superconducting material such that an edge of the superconducting material is positioned within an edge of the substrate. For example, in a chip surface-based device structure 500, substrates 206A and 206B are possible substrates, and superconductor 514 is a possible superconducting material. In this example, it can be seen that substrates 206A and 206B extend horizontally further away from the transmons than superconductor 514. Thus, the edge of superconductor 514 that extends away from the transmons is positioned within the edges of substrate 206A and substrate 206B that extend away from the transmons.

[0112] Operation 2004 is shown to configure a transmon qubit with a vertical Josephson junction and a capacitor formed between a first superconducting material and a second superconducting material (e.g., by computer 2112).

[0113] In some examples, forming a vertical transmon qubit with a vertical Josephson junction and a capacitor includes forming a second vertical transmon qubit from superconducting materials and a substrate that is separated from cross-talk from the vertical transmon qubit by a space in a second superconducting material. That is, a chip surface-based device structure, such as chip surface-based device structure 100, can include a plurality of vertical transmon qubits, and these plurality of vertical transmon qubits can be separable from each other's cross-talk. In some examples where a chip surface-based device structure includes a plurality of vertical transmon qubits, or where a plurality of vertical transmon qubits are present, a resonant bus can couple a vertical transmon qubit and a second vertical transmon qubit.

[0114] In some examples, a resonant bus is coupled to a second superconducting material. For example, this second superconducting material can include superconductor 304A or superconductor 304C of chip surface-based device structure 300, and the resonant bus can be coupled to superconductor 304A or superconductor 304C.

[0115] In some examples, a first superconducting material includes a resonant bus. For example, in chip surface-based device structure 100, when a vertical Josephson junction is separated, a portion of superconductor 114 that is away from the vertical Josephson junction remains, and this portion can function as a resonant bus.

[0116] Similarly, in some examples, a resonant bus is coupled to a superconducting material. Using chip surface-based device structure 100 as an example, when a vertical Josephson junction is separated, a portion of superconductor 114 that is away from the vertical Josephson junction remains, and this portion can function as a resonant bus.

[0117] In some examples, a resonance bus is coupled to a vertical transmon qubit, and a second resonance bus is also coupled to the vertical transmon qubit. For example, in FIG. 6, both the superconductor 304A and the superconductor 304C can function as resonance buses. Thus, as the superconductor 304A, a resonance bus coupled to the vertical transmon qubit is possible, and as the superconductor 304C, a second resonance bus coupled to the vertical transmon qubit is possible. In some examples, three or more resonance buses can be coupled to the vertical transmon qubit.

[0118] In some examples, without coupling to a second vertical transmon qubit of the chip surface-based device structure, a readout resonator is coupled to the vertical transmon qubit for addressing. The chip surface-based device structure can include a plurality of vertical transmon qubits. When the chip surface-based device structure can include a plurality of vertical transmon qubits, a particular readout resonator can be coupled to only one of these vertical transmon qubits. For example, in the chip surface-based device structure 600, the superconductor 304A can function as a readout resonator and can be coupled to one vertical transmon qubit.

[0119] In some examples, the vertical transmon qubit includes a vertical transmon qubit. Generally, as the vertical transmon qubit, a vertical transmon qubit with a vertical Josephson junction is possible. The vertical Josephson junction exists, for example, in the chip surface-based device structure 100 and includes a superconductor 108, a tunnel barrier 110, and a superconductor 112.

[0120] In some examples, this operation may include coupling a resonator to a first surface of a superconducting material such that the superconducting material includes a single-sided coupling. Single-sided coupling generally includes coupling one resonator to a vertical transmon qubit. In the chip surface-based device structure 600, when the superconductor 304A functions as a resonator and the superconductor 304C is omitted, the superconductor 304A functions as a single-sided coupler to constitute a single-sided coupling.

[0121] In some examples, this operation includes coupling a first resonator to a first surface of a superconducting material and coupling a second resonator to a second surface of the superconducting material such that the superconducting material includes a multi-sided coupling. Multi-sided coupling generally includes coupling one of a plurality of resonators to a vertical transmon qubit. In the chip surface-based device structure 600, when both the superconductor 304A and the superconductor 304C function as resonators respectively, the chip surface-based device structure 600 may have a multi-sided coupling.

[0122] In some examples, a portion of a second superconducting material positioned outside a vertical Josephson junction is exposed to air. For example, in the chip surface-based device structure 300, the superconductor 304A and the superconductor 304C can be the portions of the superconducting material positioned outside the vertical Josephson junction. Since the superconductor 304A and the superconductor 304C are not covered by another material such as a substrate, they are considered to be exposed to air. This configuration is in contrast to the chip surface-based device structure 800, where the superconductor 304A and the superconductor 304C are covered by the substrate 806C and the substrate 806D respectively and are thus considered not to be exposed to air.

[0123] In some examples, this operation includes covering a portion of a second superconducting material positioned outside a vertical Josephson junction with a substrate such that the portion of the second superconducting material positioned outside the vertical Josephson junction is covered by the substrate. For example, in the chip surface-based device structure 800, the portion of the second superconducting material can be superconductor 304A and superconductor 304C. As seen in the chip surface-based device structure, superconductor 304A and superconductor 304C are each covered by substrate 806C and substrate 806D, respectively. By covering superconductor 304A and superconductor 304C with substrate 806C and substrate 806D, respectively, the upper interfaces of superconductor 304A and superconductor 304C are changed and superconductor 304A and superconductor 304C can be protected against oxidation as a result of exposure to air.

[0124] To provide background for various aspects of the subject matter of this disclosure, FIGS. 21 and the following description are intended to provide an overview of a suitable environment in which various aspects of the subject matter of this disclosure may be implemented. For example, an exemplary and non-limiting aspect of a computer-implemented method for facilitating the implementation of the vertical Josephson junction superconducting device of FIGS. 12 and 13 can use the operating environment 2100.

[0125] FIG. 21 is a block diagram of an exemplary and non-limiting operating environment that may bring about one or more embodiments described herein. Repeated descriptions of the same elements employed in other embodiments described herein are omitted for simplicity. Referring to FIG. 21, a suitable operating environment 2100 for implementing various aspects of the present disclosure may also include a computer 2112. The computer 2112 may also include a processing unit 2114, a system memory 2116, and a system bus 2118. The system bus 2118 couples system components including the system memory 2116 to the processing unit 2114, but the system components are not limited thereto. Any of a variety of available processors may be used as the processing unit 2114. Also, a multiprocessor architecture such as a dual microprocessor may be employed as the processing unit 2114. The system bus 2118 may be a memory bus or memory controller, a peripheral bus or external bus, or a local bus using any of a variety of available bus architectures such as Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE1394), Small Computer System Interface (SCSI), and any combination thereof, or any other suitable bus structure.

[0126] In addition, system memory 2116 may also include volatile memory 2120 and non-volatile memory 2122. The basic input / output system (BIOS) containing the basic routines for transferring information between elements within computer 2112 during startup and the like is stored in non-volatile memory 2122. As a non-limiting example, non-volatile memory 2122 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Also, volatile memory 2120 may include random access memory (RAM) that acts as an external cache memory. As a non-limiting example, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct rambus RAM (DRRAM), direct rambus dynamic RAM (DRDRAM), and rambus dynamic RAM, etc.

[0127] In addition, computer 2112 may include a removable / non-removable volatile / non-volatile computer storage medium. FIG. 21 shows, for example, disk storage 2124. Disk storage 2124 may include, but is not limited to, devices such as a magnetic disk drive, a floppy (R) disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 2124 may also include a storage medium that is separate from or used in combination with other storage media, including, but not limited to, optical disk drives such as a compact disk ROM device (CD-ROM), a CD recordable drive (CD-R drive), a CD rewritable drive (CD-RW drive), or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of disk storage 2124 to system bus 2118, a removable or non-removable interface, such as interface 2126, is typically used. FIG. 21 also shows software that acts as an intermediate means between the basic computer resources described in the preferred operating environment 2100 for the user. Such software may include, for example, operating system 2128. Operating system 2128, which may be stored in disk storage 2124, acts to control and allocate the resources of computer 2112.

[0128] System application 2130 utilizes resource management by an operating system 2128 through, for example, program modules 2132 and program data 2134 stored in system memory 2126 or disk storage 2124. Of course, the present disclosure can be realized by various operating systems or combinations of operating systems. A user inputs commands or information into computer 2112 through input device 2136. Input device 2136 includes, but is not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, etc. The above and other input devices are connected to processing unit 2114 through system bus 2118 via interface port 2138. Interface port 2138 includes, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output device 2140 uses some of the same types of ports as input device 2136. Thus, for example, by using a USB port, input can be provided to computer 2112 and information can be output from computer 2112 to output device 2140. Among the several output devices 2140, an output adapter 2142 is provided to indicate the existence of output devices 2140 such as monitors, speakers, and printers that require special adapters. As an example, output adapter 2142 includes, but is not limited to, video and sound cards that provide connection means between output device 2140 and system bus 2118. It should be noted that other devices or systems of devices or both, such as remote computer 2144, provide both input and output functions.

[0129] Computer 2112 can operate in a networked environment using a logical connection to one or more remote computers, such as remote computer 2144. Remote computer 2144 can be a computer, server, router, network PC, workstation, microprocessor-based consumer product, peer device, or other common network node, etc., and typically can include many or all of the elements described for computer 2112. For simplicity, only memory storage device 2146 is shown for remote computer 2144. Remote computer 2144 is logically connected to computer 2112 through network interface 2148 and then physically connected through communication connection 2150. Network interface 2148 includes wired or wireless communication networks, or both, such as local area network (LAN), wide area network (WAN), cellular network, etc. LAN technologies include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet (R), token ring, etc. WAN technologies include point-to-point links, circuit-switched networks such as integrated services digital network (ISDN) and its variations, packet-switched networks, and digital subscriber line (DSL), but are not limited to these. Communication connection 2150 represents the hardware / software employed to connect network interface 2148 to system bus 2118. Communication connection 2150 is shown inside computer 2112 for clarity of illustration, but can also be placed outside computer 2112. Also, the hardware / software for connection to network interface 2148 can include internal and external technologies such as modems, such as typical telephone modems, cable modems, and DSL modems, ISDN adapters, and Ethernet (R) cards, etc., but these are for illustrative purposes only.

[0130] The present invention can be a system, method, apparatus, or computer program product, or a combination thereof, at any conceivable level of technical detail integration. The computer program product may comprise one or more computer-readable storage media storing computer-readable program instructions for causing a processor to execute aspects of the present invention. As the computer-readable storage media, a tangible device capable of holding and storing instructions used by an instruction execution device is possible. As the computer-readable storage media, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof is possible, but not limited thereto. Also, a non-exhaustive list of more specific examples of the computer-readable storage media may include a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy (R) disk, a punch card, or a mechanical encoding device such as a raised structure in a groove in which instructions are recorded, and any suitable combination thereof. As used herein, the computer-readable storage media shall not be construed as an essentially transient signal, such as a free-propagating electromagnetic wave such as a radio wave, an electromagnetic wave propagating through a transmission medium such as a waveguide (for example, an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0131] The computer-readable program instructions described in this specification can be downloaded from a computer-readable storage medium to each computer / processing device, or can be downloaded to an external computer or external storage device via, for example, the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include a transmission copper cable, a transmission optical fiber, wireless transmission, a router, a firewall, a switch, a gateway computer, or an edge server, or a combination thereof. The network adapter card or network interface of each computer / processing device receives the computer-readable program instructions from the network, transfers the computer-readable program instructions, and stores them in the computer-readable storage medium within each computer / processing device. The computer-readable program instructions for performing the operations of the present invention can be source code or object code described in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit setting data, or object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed in whole or in part on the user's computer as a stand-alone software package, or in part on the user's computer and in part on a remote computer, or in whole on a remote computer or server. In the latter scenario, it is also possible to connect a remote computer to the user's computer through any type of network, such as a local area network (LAN) or a wide area network (WAN), or to connect to an external computer (for example, through the Internet by using an Internet service provider).In some embodiments, to carry out aspects of the present invention, by using state information of computer-readable program instructions to customize an electronic circuit, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions.

[0132] In this specification, aspects of the present invention are described with reference to flowchart diagrams and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart diagrams and / or block diagrams and combinations of blocks therein can be implemented by computer-readable program instructions. These computer-readable program instructions are provided to the processor of a programmable data processing apparatus such as a computer, so as to generate means for implementing the specified functions / operations in one or more blocks of the flowchart diagrams and / or block diagrams, thereby configuring a machine through execution via the processor of the programmable data processing apparatus such as a computer. Also, these computer-readable program instructions can be stored in a computer-readable storage medium that can contain, when the computer-readable storage medium stores instructions for implementing the specified functions / operations of one or more blocks of the flowchart diagrams and / or block diagrams, a manufactured product including the computer-readable storage medium that functions in a specific manner for a computer, a programmable data processing apparatus, or other devices, or combinations thereof. Further, the computer-readable program instructions can configure a computer implementation process by causing a series of operations to be executed on a computer, another programmable apparatus, or other devices by loading the instructions onto the computer, another programmable data processing apparatus, or other devices to implement the specified functions / operations in one or more blocks of the flowchart or block diagrams and / or both.

[0133] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that include one or more executable instructions for implementing a particular logical function. In some alternative embodiments, the functions noted in the blocks may occur out of the order noted in the drawings. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending upon the functionality involved, or may sometimes be executed in the reverse order. Also, each block of the block diagrams or flowchart diagrams, or both, and combinations of blocks in the block diagrams or flowchart diagrams, or both, can be implemented by a dedicated hardware-based system that performs a particular function or operation, or by a combination of dedicated hardware and computer instructions.

[0134] The subject matter has been described above in the general context of computer-executable instructions of one or more computers or computer program products that operate on both. However, those skilled in the art will recognize that the present disclosure can be implemented in combination with other program modules or by combination. Generally, program modules include routines, programs, components, data structures, etc. that perform specific tasks or implement specific abstract data types or both. Further, it will be apparent to those skilled in the art that the computer implementation method according to the present invention can be realized by other computer system configurations such as single-processor or multi-processor computer systems, minicomputer devices, mainframe computers, in addition to computers, handheld computer devices (e.g., PDAs, telephones), microprocessor-based or programmable household appliances or industrial electronic devices, etc. Also, the illustrated embodiments can be realized in a distributed computing environment where tasks are performed by remote processing devices connected through a communication network. However, even if not all aspects of the present disclosure, some of them can be realized on a stand-alone computer. In a distributed computing environment, program modules can be arranged in both local and remote memory storage devices.

[0135] As used herein, the terms "component", "system", "platform", "interface", etc. can represent or include, or both, computer-related entities or entities associated with computing machines having one or more specific functions. Entities disclosed herein can be hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer, or a combination thereof. As an example, both an application running on a server and the server can be components. One or more components can be present in a process or an execution thread or both, and a component can be limited to one computer or distributed between two or more computers or both. In another example, each component can be executable from various computer-readable media storing various data structures. A component can communicate through local or remote or both processes, such as signals having one or more data packets (data from one component interacting with another component of a local system, a distributed system, or another system via a network such as the Internet, or both). As another example, a component can be a device having a specific function provided by a mechanical part operated by an electrical or electronic circuit operated by software or a firmware application executed by a processor. In such a case, the processor can be placed inside or outside the device and can execute at least a part of the software or the firmware application.As yet another example, as a component, it is possible to have a device that provides a specific function through an electronic component without mechanical parts, and the electronic component may include means such as a processor that executes software or firmware that provides at least a part of the function. In one aspect, the component can emulate the electronic component via a virtual machine, for example, within a cloud computing system.

[0136] Also, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or not apparent from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, "X employs A or B" is satisfied in any of these instances where X employs A, X employs B, or X employs both A and B. Further, unless otherwise specified to indicate the singular form and not apparent from the context, the articles "a" and "an" used in this specification and the accompanying drawings are generally to be construed to mean "one or more". As used herein, the terms "example" or "exemplary" or both are utilized to mean serving as an example. To avoid misunderstanding, the subject matter disclosed herein is not limited by such examples. Also, any aspect or design described herein as "example" or "exemplary" or both is not necessarily construed as being more preferred or advantageous than other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0137] As employed herein, the term "processor" can represent substantially any computer processing unit or device, including but not limited to a single-core processor, a single processor capable of multi-threaded execution of software, a multi-core processor, a multi-core processor capable of multi-threaded execution of software, a multi-core processor with hardware multi-threading technology, a parallel platform, and a parallel platform with distributed shared memory. Also, a processor can represent an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a processor can utilize, but is not limited to, molecular and quantum dot-based transistors, switches, and gates as a nanoscale architecture for optimizing space usage or improving the performance of a user device. Also, a processor can be realized as a combination of computer processing units. In the present disclosure, terms such as "store", "storage", "data store", "data storage", "database", etc., and substantially any other information storage component related to the operation and function of a component are used to represent a "memory" or a "memory component" entity embodied in a component with a memory. Of course, the memory or memory component or both described herein can be either volatile memory or non-volatile memory, or can include both volatile and non-volatile memory.As a non-limiting example, non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memories can include, for example, RAM operable as an external cache memory. As a non-limiting example, RAM can be available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct rambus RAM (DRRAM), direct rambus dynamic RAM (DRDRAM), and rambus dynamic RAM (RDRAM). Also, the memory components of the system or computer-implemented method disclosed herein are intended to non-exclusively include the above and any other suitable types of memory.

[0138] The above are only examples of systems and computer-implemented methods. Of course, for the purpose of this disclosure, it is not possible to describe all possible combinations of components or computer-implemented methods. However, those skilled in the art will recognize that many other combinations and permutations of this disclosure are possible. Further, to the extent that the terms "includes", "has", "possesses", etc. are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is construed when adopted as a transitional term in a claim.

[0139] The above descriptions of various embodiments have been presented for illustrative purposes, but these are not intended to be exhaustive or to limit the disclosed embodiments. Many improvements and modifications will be apparent to those skilled in the art without departing from the scope of the above embodiments. The technical terms used herein have been selected for the best explanation of the principles of the embodiments, the practical application, or the technical improvements found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip surface-based device structure, comprising: a first superconducting material physically bonded to a first crystal substrate, the first crystal substrate being physically bonded to a first portion of a second superconducting material, the first portion of the second superconducting material being physically bonded to a second crystal substrate; the chip surface-based device structure further comprising: a vertical Josephson junction positioned in a via of the first crystal substrate, the vertical Josephson junction including the first superconducting material, a tunnel barrier physically bonded to the first superconducting material, and the first portion of the second superconducting material; a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the first portion of the second superconducting material on both sides of the first crystal substrate; A chip surface-based device structure comprising the above.

2. The chip surface-based device structure according to claim 1, wherein a second portion of the second superconducting material, which is physically bonded to the second crystal substrate and separated from the first portion of the second superconducting material, is positioned outside the transmon qubit and used as an information transfer circuit.

3. The chip surface-based device structure according to claim 2, wherein the second portion of the second superconducting material positioned outside the transmon qubit is covered with the same material as the first crystal substrate.

4. The chip surface-based device structure according to claim 1, further comprising an information transfer circuit in a second portion of the second superconducting material, which is separated from the transmon qubit and communicatively coupled to the transmon qubit.

5. The chip surface-based device structure according to claim 1, further comprising an information transfer circuit that electrically couples the transmon qubit to one or more other qubits or input, output, or readout circuits, wherein the information transfer circuit is formed in the second portion of the second superconducting material.

6. The chip surface-based device structure according to claim 2, wherein the information transfer circuit comprises a resonant bus, and the transmon qubit is communicatively coupled to the resonant bus using a second capacitor.

7. The chip surface base device structure according to claim 6, wherein the resonant bus is covered with the same material as the first crystal substrate.

8. physically bonding a first superconducting material to a first crystal substrate; physically bonding the first crystal substrate to a first portion of a second superconducting material physically bonded to a second crystal substrate; forming a vertical Josephson junction including the first superconducting material, a tunnel barrier physically bonded to the first superconducting material, and the first portion of the second superconducting material in a via of the first crystal substrate; forming a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material on both sides of the first crystal substrate and the first portion of the second superconducting material; A method comprising the steps of:

9. The method according to claim 8, further comprising removing a part of the first crystal substrate such that an edge of the first crystal substrate is positioned within an edge of the first portion of the second superconducting material.

10. The method according to claim 8, further comprising removing a part of the first superconducting material such that an edge of the first superconducting material is coplanar with the edge of the first crystal substrate.

11. The method according to claim 8, further comprising removing a part of the first superconducting material such that an edge of the first superconducting material is positioned within an edge of the first crystal substrate.

12. The method according to claim 8, further comprising removing a part of the first superconducting material such that an edge of the first superconducting material extends beyond an edge of the first portion of the second superconducting material.

13. The method according to claim 8, further comprising electrically coupling a resonator to a first surface of the first superconducting material or the first portion of the second superconducting material.

14. The method according to claim 8, further comprising electrically coupling a plurality of resonators to the first superconducting material, the first portion of the second superconducting material, or both.

15. In the method according to claim 8, a second portion of the second superconducting material, which is physically bonded to the second crystal substrate, separated from the first portion of the second superconducting material, and positioned outside the vertical Josephson junction, is exposed to air.

16. The chip surface-based device structure according to claim 1, further comprising a readout resonator that is electrically coupled to the transmon qubit of the chip surface-based device structure for addressing.

17. Another superconducting qubit, a resonant bus that electrically couples the transmon qubit and the another superconducting qubit, The chip surface-based device structure according to claim 1, further comprising.

18. Physically bonding a first superconducting material to a first crystal substrate, physically bonding a first portion of a second superconducting material to a second crystal substrate, and physically bonding the first crystal substrate to the first portion of the second superconducting material; Forming a vertical Josephson junction including the first superconducting material, a tunnel barrier physically bonded to the first superconducting material, and the first portion of the second superconducting material in a via of the first crystal substrate; Configuring a transmon qubit including the vertical Josephson junction and a capacitor formed between the first superconducting material on both sides of the first crystal substrate and the first portion of the second superconducting material; A method including.

19. The method according to claim 18, further comprising covering a second portion of the second superconducting material, which is physically bonded to the second crystal substrate, separated from the first portion of the second superconducting material, and positioned outside the vertical Josephson junction, with the same material as the first crystal substrate.

20. The method according to claim 18, further comprising configuring the first superconducting material such that an edge of the first superconducting material extends beyond an edge of the first crystal substrate.

21. The method according to claim 18, further comprising a plurality of other superconducting qubits and a plurality of resonant buses, each resonant bus electrically coupling the transmon qubit to one or more of the plurality of other superconducting qubits or to an input, output, or readout circuit.

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