High-frequency signal processing circuit and wireless device

Abstract

To provide a high frequency signal processing circuit and a radio device, capable of improving radio communication quality.SOLUTION: According to an embodiment, a high frequency signal processing circuit includes a first to a fourth waveform synthesizers, and each of the waveform synthesizers includes a first and a second terminals to which input signals are inputted and a third terminal from which an output signal synthesized from the input signals is output. Frequencies of the first to the fourth input signals inputted respectively to the waveform synthesizers are mutually equal, and relative to a phase of the first input signal, phases of the second input signal, the third input signal, and the fourth input signal are 180-degree lag or close value, 90-degree lag or close value and 270-degree lag or close value, respectively, and states of output signals respectively from the waveform synthesizers transit from one side to the other side in conjunction with an input signal inputted to the first terminal or an input signal inputted to the second terminal, and transit from the other side to the one side in conjunction with an input signal inputted to the first terminal of each waveform synthesizer.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a high-frequency signal processing circuit and a wireless device.

Background Art

[0002] In recent digital wireless communications, the IQ direct conversion modulation method is mainly adopted in transceivers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the method of Patent Document 1, it is known that the phase and amplitude errors between IQ signals in the intermediate frequency band (IF frequency band, Intermediate Frequency) of the mixer output have an adverse effect on wireless communication quality.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to an embodiment, the high-frequency signal processing circuit includes a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal; a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; and a first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer. Each waveform synthesizer has a first terminal and a second terminal to which an input signal is input, and a third terminal from which an output signal obtained by synthesizing a plurality of the input signals is output. The first input signal, the second input signal, the third input signal, and the fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal. The frequencies of the input signals are equal to each other. The phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay with respect to the phase of the first input signal. The state of the output signal output from the third terminal of each waveform synthesizer transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal of each waveform synthesizer, and the state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer.

[0008] According to an embodiment, the wireless device includes an antenna impedance matcher, a transmitter, a receiver, a digital circuit, a PLL, and an LO frequency divider. The LO frequency divider includes a frequency divider and the high-frequency signal processing circuit connected between the frequency divider and the mixer.

Advantages of the Invention

[0009] According to the above embodiment, it is possible to provide a high-frequency signal processing circuit and a wireless device capable of improving wireless communication quality.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Mode for Carrying Out the Invention

[0011] For the sake of clarity of explanation, the following description and drawings are appropriately omitted and simplified. Also, in each drawing, the same reference numerals are assigned to the same elements, and redundant explanations are omitted as necessary.

[0012] (Comparative Example) First, a high-frequency signal processing circuit according to a comparative example and problems discovered by the inventor with respect to the same will be described. Note that the high-frequency signal processing circuit and problems according to the comparative example are also included in the scope of the technical idea of the embodiments.

[0013] For example, in a receiver using the IQ quadrature modulation / demodulation method, the phase error between the IQ signals in the IF frequency band of the mixer output (referred to as the IQ phase error) may degrade the image rejection ratio (IRR) in the case of the Low-IF method, or may degrade the IQ orthogonality in the case of the Zero-IF method. Thus, the phase error between the IQ signals affects the image CH interference wave and the modulation accuracy (EVM, Error Vector Magnitude). When the IQ orthogonality of the LO (Local Oscillator) signal is incomplete and there is an IQ phase error, the IQ orthogonality in the IF frequency band also becomes incomplete. The embodiments described later are, as an example, techniques for improving the IQ orthogonality of the LO signal, that is, reducing the IQ phase error.

[0014] FIG. 1 is a circuit diagram illustrating a high-frequency signal processing circuit according to a comparative example. As shown in FIG. 1, the high-frequency signal processing circuit 1001 according to the comparative example has a circuit configuration of a Low-IF receiver as an example of the IQ quadrature modulation / demodulation method. The high-frequency signal processing circuit 1001 includes an antenna 23, an antenna impedance matching network (sometimes referred to as MN), a low noise amplifier (sometimes referred to as LNA) 27, mixers (sometimes referred to as MIXER) 21a and 21b, band pass filters (sometimes referred to as BPF) 28a and 28b, programmable gain amplifiers (sometimes referred to as PGA) 28c and 28d, analog-to-digital converters (sometimes referred to as ADC) 29a and 29b, an LODIV (frequency divider for local oscillator, sometimes referred to as LO divider) 22, a voltage controlled oscillator (sometimes referred to as VCO) 19, and a phase locked loop (sometimes referred to as PLL) 41. Note that when collectively referring to the mixers 21a and 21b, the band pass filters 28a and 28b, and the analog-to-digital converters 29a and 29b, they are referred to as mixers 21, band pass filters 28, and analog-to-digital converters 29, respectively.

[0015] Antenna 23 is connected to antenna impedance matcher 24. Antenna impedance matcher 24 is connected to low-noise amplifier 27. Low-noise amplifier 27 is connected to mixers 21a and 21b. Mixer 21a is connected to analog-to-digital converter 29a via band-pass filter 28a and programmable gain amplifier 28c. Mixer 21b is connected to analog-to-digital converter 29b via band-pass filter 28b and programmable gain amplifier 28d. Analog-to-digital converters 29a and 29b are connected to a digital circuit.

[0016] Also, mixers 21a and 21b are connected to LODIV22. And LODIV22 is connected to VCO19 and PLL41. PLL41 is connected to a digital circuit. The block including LODIV22, VCO19, and PLL41 is called LO block (Local Oscillator Block, sometimes also called local oscillator block) LB. That is, LO block LB includes LODIV22, VCO19, and PLL41. The output of VCO19 is called output VCOOUT. VCO19 outputs output VCOOUT to LODIV22. The output of LODIV22 is called output LOOUT. LODIV22 outputs output LOOUT to mixer 21. Therefore, LO block LB outputs output LOOUT to mixer 21. In the present embodiment described later, LO block LB in the figure has characteristics.

[0017] Note that the IQ quadrature demodulation method is not limited to the Low-IF method and may also be the Zero-IF method. Also, high-frequency signal processing circuit 1001 is not limited to a receiver having the IQ quadrature demodulation method and may be applied to a transmitter having the IQ quadrature modulation method.

[0018] <Causes of IQ phase error> Next, the causes of the IQ phase error will be described. FIG. 2 is a block diagram illustrating the connection between the LO block LB and the mixer 21 without measures for reducing the IQ phase error in the high-frequency signal processing circuit 1001 according to the comparative example. As shown in FIG. 2, the LO block LB includes a VCO 19, a DIV (frequency divider) 20, and a plurality of buffers BUF. Therefore, the LODIV 22 includes the DIV 20 and a plurality of buffers BUF. Note that some reference numerals are omitted so that the figure does not become complicated.

[0019] In general, in order to suppress an increase in power consumption, the high-frequency signal processing circuit 1001 needs to minimize the shortest signal path before the DIV 20 with the highest frequency. Therefore, the DIV 20 is laid out at a position close to the VCO 19. For this reason, the signal transmission distance between the DIV 20 and the mixer 21 is extended. Therefore, it is necessary to arrange intermediate buffers BUF. For example, in FIG. 2, a total of two stages of intermediate buffers BUF are arranged near the DIV 20 and near the mixer 21.

[0020] Specifically, the VCO 19 is connected to the DIV 20. The VCO 19 outputs an output VCOOUT including a pos signal and a neg signal to the DIV 20. The DIV 20 is connected to the mixer 21 via a plurality of buffers BUF. The LODIV 22 including the DIV 20 and a plurality of buffers BUF outputs an output LOOUT including an I signal, an IB signal, a Q signal, and a QB signal to the mixer 21.

[0021] FIG. 3 is a diagram illustrating waveforms of the output VCOOUT of the VCO 19 and the output LOOUT of the LODIV 22 in the high-frequency signal processing circuit 1001 according to the comparative example. The horizontal axis represents time, and the vertical axis represents intensity. As shown in FIG. 3, the IQ signals of the output LOOUT are generated from the rising edge of the differential signal in the output VCOOUT of the VCO 19. For this reason, the IQ phase error randomly occurs due to the differential imbalance of the VCO 19 and the IQ imbalance of the intermediate buffer BUF.

[0022] Figures 4(a) and (b) are diagrams illustrating the causes of IQ phase error variations in the high-frequency signal processing circuit 1001 according to the comparative example. As shown in Fig. 4(a), the phase error of the output VCOOUT of the VCO 19 is caused by, for example, an error due to differential imbalance of the VCO 19 and has a spread in a normal distribution. As shown in Fig. 4(b), the phase error of the output LOOUT of the LODIV 22 is caused by the phase error of the VCO 19 and the IQ signal non-uniformity of the relay buffer BUF and has a spread in a normal distribution. Measures for reducing such IQ phase errors are required.

[0023] <Problems found by the inventors> Figures 5(a) to (e) are diagrams illustrating general measures for reducing IQ phase errors in the high-frequency signal processing circuit 1001 according to the comparative example. As shown in Figs. 5(a) to (e), the following measures can be considered as general measures for reducing IQ phase errors. However, each measure has problems.

[0024] Measure (1): Reduce the element mismatch. As a result, as shown in Fig. 5(a), the distribution width of the phase error can be narrowed. However, increasing the element size or the common centroid arrangement causes an increase in parasitic capacitance, resulting in an increase in area and current. Therefore, there is a limit to reducing the element mismatch.

[0025] Measure (2): As shown in Fig. 5(b), reduce those with large errors by test sorting. However, since it costs for sorting and defective products are produced, the product cost increases.

[0026] Countermeasure (3): As shown in Fig. 5(c), a calibration mechanism (adjustment mechanism & detection mechanism & algorithm) is installed. However, installing such a mechanism causes an increase in area and current. For example, as countermeasure (3-1), it is conceivable to perform calibration at the time of IC shipment, but a memory for storing the calibration results is required, increasing the product cost. Also, as countermeasure (3-2), it is conceivable to perform calibration when the reception operation is not being performed, but this increases the current for the calibration time itself. Also, the control becomes complicated. As countermeasure (3-3), it is conceivable to perform calibration on the customer side, but this increases the burden on the customer side and increases the cost of the final product.

[0027] For example, as shown in Fig. 5(d), the adjustment mechanism in the calibration mechanism enables phase adjustment by adding an adjustable capacitor CP that can be independently varied for the I signal and the Q signal to the buffer BUF section. The adjustable capacitor CP requires a sufficiently wide variable range and correction accuracy according to the target image rejection ratio (IRR) in order to correct all the errors in Fig. 4(b). For this reason, as shown in Fig. 5(e), the adjustable capacitor CP has an area larger than that of the LODIV22 + buffer BUF main body. Also, adding a variable capacitor that becomes the adjustable capacitor CP increases the parasitic capacitance and reduces the amplitude. For this reason, it is necessary to increase the size of the buffer BUF. This is a factor in the increase in current.

[0028] Thus, each countermeasure has been a factor in the increase in power consumption current and the increase in product cost (due to chip area and testing). For example, in BLE (2.4 GHz), the current in the LO section occupies more than half of the total current in the transmit / receive mode, so the impact is significant.

[0029] (Embodiment 1) Next, a high-frequency signal processing circuit according to this embodiment will be described. This embodiment is a new countermeasure approach that does not belong to any of countermeasures (1) to (3) in Figs. 5(a) to (e) described above.

[0030] <Feature (1)> FIG. 6 is a block diagram illustrating a high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 6, the feature (1) of this embodiment is that a retiming circuit (sometimes referred to as an IQ Retiming circuit) 34 is arranged near the mixer 21. Specifically, the retiming circuit 34 is arranged between the DIV20 and the mixer 21. Thereby, compared with the comparative example, the area and current penalty can be reduced, and the error factors can be reduced. The retiming circuit 34 has, for example, an analog automatic correction function. Also, the retiming circuit 34 can reduce the area occupied by the entire circuit and can reduce the current penalty. Also, a phase calibration mechanism can be made unnecessary. Hereinafter, it will be described with reference to the drawings. Strictly speaking, a phase error caused by the retiming circuit 34 remains in the LO signal of the output LOOUT, but depending on the required specifications, calibration of such a phase error is also unnecessary.

[0031] <Feature (2)> FIGS. 7(a) to 7(d) are circuit diagrams illustrating the configuration of the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 7(a), the retiming circuit 34 is arranged between the DIV20 and the mixer 21. The retiming circuit 34 has a function of generating an LO signal by combining edges between the IQ signals. However, any configuration may be used as long as it is a circuit that performs a desired edge synthesis. Also, as a prerequisite for using the retiming circuit 34, it is preferable that the input waveform of the retiming circuit 34 is a substantially 25% or substantially 75% duty cycle (sometimes referred to as a Duty Cycle). Note that the operating frequencies of the I signal, the IB signal, the Q signal, and the QB signal are the same.

[0032] In an actual implementation, in order to suppress the phase error after the retiming circuit 34, the retiming circuit 34 and the mixer 21 are arranged at positions close to each other in terms of layout (see Fig. 8). Also, as shown in Fig. 7(a), it is also a feature that the mixer 21 is configured with P-type MOS so as not to sandwich an inverter after the retiming circuit 34. Note that when the output of the retiming circuit 34 is 25%, it is preferable to configure the mixer 21 with N-type MOS.

[0033] Specifically, the retiming circuit 34 includes an input terminal 1, an input terminal 2, an input terminal 3, an input terminal 4, an output terminal 9, an output terminal 10, an output terminal 11, an output terminal 12, an RT circuit 5, an RT circuit 6, an RT circuit 7, and an RT circuit 8. The RT circuits 5, 6, 7, and 8 are collectively referred to as the RT circuit 30. The RT circuit 30 has a function as a waveform synthesizer for synthesizing waveforms.

[0034] An I signal, an IB signal, a Q signal, and a QB signal are input to the input terminal 1, the input terminal 2, the input terminal 3, and the input terminal 4, respectively, as input signals. The frequencies of the respective input signals are equal to each other.

[0035] As shown in Fig. 7(b), each RT circuit 30 (RT circuits 5 to 8) has a terminal 31 and a terminal 32 to which an input signal is input, and a terminal 33 from which an output signal obtained by synthesizing the plurality of input signals input is output.

[0036] As shown in Fig. 7(a), the terminal 31 of the RT circuit 5 is connected to the input terminal 1. The terminal 32 of the RT circuit 5 is connected to the input terminal 4. The terminal 33 of the RT circuit 5 is connected to the output terminal 9. The terminal 31 of the RT circuit 6 is connected to the input terminal 2. The terminal 32 of the RT circuit 6 is connected to the input terminal 3. The terminal 33 of the RT circuit 6 is connected to the output terminal 10.

[0037] Terminal 31 of the RT circuit 7 is connected to the input terminal 3. Terminal 32 of the RT circuit 7 is connected to the input terminal 1. Terminal 33 of the RT circuit 7 is connected to the output terminal 11. Terminal 31 of the RT circuit 8 is connected to the input terminal 4. Terminal 32 of the RT circuit 8 is connected to the input terminal 2. Terminal 33 of the RT circuit 8 is connected to the output terminal 12.

[0038] As shown in FIGS. 7(c) and (d), the RT circuit 30 including the retiming buffer may have a plurality of inverter circuits 13 and 14, a plurality of PMOS transistors 15 and 16, and a plurality of NMOS transistors 17 and 18.

[0039] For example, as shown in FIG. 7(c), in the RT circuit 30, terminal 31 is connected to the gates of PMOS transistor 16 and NMOS transistor 17. Terminal 32 is connected to the inverter circuit 13. The inverter circuit 13 is connected to the inverter circuit 14 and the gate of NMOS transistor 18. The inverter circuit 14 is connected to the gate of PMOS transistor 15. The drain of PMOS transistor 15 is connected to the source of PMOS transistor 16. The drain of NMOS transistor 18 is connected to the source of NMOS transistor 17. The drains of PMOS transistor 16 and NMOS transistor 17 are connected to terminal 33.

[0040] Also, for example, as shown in FIG. 7(d), in the RT circuit 30, the terminal 31 is connected to the gates of the PMOS transistor 15 and the NMOS transistor 18. The terminal 32 is connected to the inverter circuit 13. The inverter circuit 13 is connected to the inverter circuit 14 and the gate of the NMOS transistor 17. The inverter circuit 14 is connected to the gate of the PMOS transistor 16. The drain of the PMOS transistor 15 is connected to the source of the PMOS transistor 16. The drain of the NMOS transistor 18 is connected to the source of the NMOS transistor 17. The drains of the PMOS transistor 16 and the NMOS transistor 17 are connected to the terminal 33.

[0041] <Arrangement example of LODIV> FIGS. 8(a) to (c) are diagrams illustrating the arrangement of the LODIV 22 in the high-frequency signal processing circuit according to the first embodiment. First, the basic concept of the arrangement of the LODIV 22 including the DIV 20 and the retiming circuit 34 will be described. As shown in FIG. 8(a), the LODIV 22 needs to supply signals to both the transmission circuit 51 and the reception circuit 52. Usually, in order to achieve the balance between transmission and reception, a design of arranging it near either the transmission or the reception is not considered. Also, for the LODIV 22, since the VCO 19, the transmission circuit 51, and the reception circuit 52 include inductors, their sizes are large, and the transmission wiring from the LODIV 22 to the transmission circuit 51 and the reception circuit 52 becomes long.

[0042] For example, as shown in FIG. 8(b), in the comparative example, the distance between the LODIV 22 and the reception circuit 52 is equal to the distance between the LODIV 22 and the transmission circuit 51.

[0043] On the one hand, as shown in FIG. 8(c), in the present embodiment, both the distance between LODIV22 and the receiving circuit 52 and the distance between LODIV22 and the transmitting circuit 51 are shorter than those in the comparative example. Also, the distance between LODIV22 and the receiving circuit 52 is shorter than the distance between LODIV22 and the transmitting circuit 51. Thus, in the present embodiment, the floor plans of the VCO 19, the transmitting circuit 51, and the receiving circuit 52 are devised so that the wiring of LODIV22 is shortened. Further, in order to maximize the retiming effect, in particular, the mixer 21 of the receiving circuit 52 and LODIV22 are arranged in close proximity so that the distance therebetween is shortened.

[0044] <Effect: Conclusion of the effect> Next, the effect of reducing the IQ phase error by the retiming circuit 34 according to Embodiment 1 will be described. FIG. 9 is a block diagram for explaining the reduction of the IQ phase error by the retiming circuit 34 according to Embodiment 1. As shown in FIG. 9, in order to simplify the explanation of the reduction of the IQ phase error by the retiming circuit 34, the mixer 21 is configured with NMOS, and the input and output of the retiming circuit 34 are non-inverted.

[0045] FIGS. 10(a) and (b) are conceptual diagrams illustrating the reduction of the IQ phase error by the retiming circuit 34 according to Embodiment 1. As shown in FIGS. 10(a) and (b), the present embodiment has two types of effects of reducing the IQ phase error. The first is the effect that the IQ phase error component due to the differential imbalance of the VCO 19 is canceled at the output LOOUT, as shown by the change in FIG. 10(a). The second is the effect that the IQ phase error due to the IQ imbalance of the relay buffer BUF can be reduced at the output LOOUT, as shown by the change in FIG. 10(b). For example, according to theoretical calculations, a reduction of about 70% is calculated as an expected value. Hereinafter, each effect will be described using a timing chart or the like.

[0046] <Effect: Outline of the effect (no IQ phase error)> Figs. 11(a) and (b) are diagrams for explaining the timing of the input and output signals of the RT circuit 30 under the condition of no IQ phase error in the high-frequency signal processing circuit according to Embodiment 1. As shown in Fig. 11(a), the RT circuit 30 has two inputs and one output. The output signal output from the terminal 33 of the RT circuit 30 is a digital signal that takes two states, a first state and a second state. In conjunction with the first input signal input to the terminal 31 or the second input signal input to the terminal 32, the output signal transitions from the first state to the second state. Also, in conjunction with the first input signal input to the terminal 31, the output signal transitions from the second state to the first state.

[0047] Specifically, for example, among the rising edge of the first input signal and the falling edge of the second input signal, the edge with the larger phase delay propagates to the rising edge of the output signal. The falling edge of the first input signal propagates to the falling edge of the output signal. As shown in Fig. 11(b), for a signal with a 25% duty ratio, the rise and fall have a relationship of a 90-degree delay.

[0048] Fig. 12 is a timing chart diagram illustrating the input and output signals of the RT circuit 30 under the condition of no IQ phase error in the high-frequency signal processing circuit according to Embodiment 1. As shown in Fig. 12, under the condition of no phase error, both the rising edge of the I signal and the falling edge of the QB signal propagate to the rising edge of the I' signal. The falling edge of the I signal propagates to the falling edge of the I' signal. Hereinafter, the same things occur in the second to fourth rows as in the first row.

[0049] That is, both the rising edge of the Q signal and the falling edge of the I signal propagate to the rising edge of the Q' signal. The falling edge of the Q signal propagates to the falling edge of the Q' signal. Both the rising edge of the IB signal and the falling edge of the Q signal propagate to the rising edge of the IB' signal. The falling edge of the IB signal propagates to the falling edge of the IB' signal. Both the rising edge of the QB signal and the falling edge of the IB signal propagate to the rising edge of the QB' signal. The falling edge of the QB signal propagates to the falling edge of the QB' signal.

[0050] Thus, the output signal output from the terminal 33 of each RT circuit 30 changes its state from one of the first and second states to the other in conjunction with the input signal input to the terminal 31 of each RT circuit 30 or the input signal input to the terminal 32. Then, the state changes from the other to one in conjunction with the input signal input to the terminal 31 of each RT circuit 30.

[0051] FIGS. 13(a) and (b) are diagrams illustrating the relationship between the input / output phase and the phase error of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIGS. 13(a) and (b), regarding the relationship between the input / output phases of the RT circuit 30, the phases of the IB signal, the Q signal, and the QB signal are values delayed by 180 degrees, 90 degrees, and 270 degrees, respectively, with respect to the phase of the I signal serving as the input signal. Under the condition that the rise and fall are signals with a 25% duty ratio and have a 90-degree delay relationship, all phase errors are 0.

[0052] <Effect: Outline (with IQ phase error)> Next, the case with an IQ phase error will be described. Specifically, with respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are values delayed by 180 degrees or values close to a 180-degree delay, 90 degrees or values close to a 90-degree delay, and 270 degrees or values close to a 270-degree delay, respectively. Here, the values close to a 180-degree delay, the values close to a 90-degree delay, and the values close to a 270-degree delay are values including a phase error of 180 degrees, values including a phase error of 90 degrees, and values including the phase error of 270 degrees, respectively. And at least one of the second input signal, the third input signal, and the fourth input signal is a value including a phase error.

[0053] FIG. 14 is a timing chart diagram illustrating the input / output signals of the RT circuit 30 under the condition of having an IQ phase error in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 14, as an example, it is assumed that the Q signal and the QB signal are each delayed by 90 degrees + 1 degree from the I signal and the IB signal.

[0054] In the first stage, since the falling edge of the QB signal lags behind the rising edge of the I signal, the rising edge of the I' signal is propagated from the falling edge of the QB signal. In the second stage, since the rising edge of the Q signal lags behind the falling edge of the I signal, the rising edge of the Q' signal is propagated from the rising edge of the Q signal. Hereinafter, in the third stage, the same thing as the top stage occurs. In the fourth stage, the same thing as the second stage occurs.

[0055] That is, in the third stage, since the falling edge of the Q signal lags behind the rising edge of the IB signal, the rising edge of the IB' signal is propagated from the falling edge of the Q signal. In the fourth stage, since the rising edge of the QB signal lags behind the falling edge of the IB signal, the rising edge of the QB' signal is propagated from the rising edge of the QB signal.

[0056] FIGS. 15(a) and (b) are diagrams illustrating the relationship between the input / output phases and phase errors of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIGS. 15(a) and (b), in the first input signal, an error occurs once at the rising edge and falling edge of the Q signal and the QB signal, and the average phase error between the Q signal and the QB signal becomes 1 degree. On the other hand, the average phase error between the I signal and the IB signal is 0 degree. Therefore, the phase error between the I signal and the Q signal becomes 1 degree. At this time, the reason for using the average value will be explained.

[0057] FIG. 16 is a diagram illustrating the influence of the differential-phase error of the differential signal in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 16, the differential transmission signal is finally subjected to a subtraction process between the two signals, whereby the phase error between the differentials is averaged. Therefore, in the above description, the average value is used.

[0058] On the other hand, at the output of the RT circuit 30, not only the Q' signal and the QB' signal, but also an error of 1 degree propagates to the I' signal and the IB' signal. The average phase errors in the I signal and the Q signal are both 1. The phase error between the I signal and the Q signal is subtracted to become 0.

[0059] <Effect: Detailed Explanation Preparation (Input Side)> In the previous section, the effect summary was explained. In reality, a large number of random errors in combinations are handled. Therefore, next, the formula will be generalized for a detailed explanation.

[0060] FIGS. 17(a) and (b), FIGS. 18(a) and (b) are diagrams for explaining the reduction of IQ phase error by the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. The reduction of the IQ phase error in the case of the high-frequency signal processing circuit shown in FIG. 17(a) will be explained. Before the detailed explanation, as shown in FIG. 17(b), the phase (rise) and the definition of the IQ phase error at the input of the RT circuit 30 are defined. Based on the rising edge of the phase of the I signal, the Q signal, the IB signal, and the QB signal have phase delays of 90, 180, and 270 degrees respectively, and further include phase errors a, b, and c respectively. As shown in FIG. 18(a), the phase error between the I signal and the Q signal can be calculated from the average phase error Iave between the I signal and the IB signal and the average phase error Qave between the Q signal and the QB signal. The phase error between the I signal and the Q signal at the input of the RT circuit 30 will occur by (a + c - b) / 2. Here, as shown in FIG. 18(b), the phases of the respective signals are defined as follows: the phase of the I signal = 0 degrees, the phase of the Q signal = -90 degrees, the phase of the IB signal = -180 degrees, and the phase of the QB signal = -270 degrees.

[0061] <Effect: Detailed Explanation Preparation (Output Side)> As described above, the RT circuit 30 has two input terminals, a terminal 31 and a terminal 32. The rising edge of the output signal takes the rising edge or the falling edge with the larger phase delay in the input signals of the terminal 31 or the terminal 32. The falling edge of the output signal takes the falling edge of the input signal input to the terminal 31. The phase error in the output signal of the RT circuit 30 needs to be case-divided according to the magnitude relationship of the phase errors a, b, and c.

[0062] Figs. 19(a) to (c), Figs. 20(a) to (c), Figs. 21(a) to (c), Figs. 22(a) to (c), and Fig. 23 are diagrams illustrating the classification of phase errors at the output of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1.

[0063] As shown in Fig. 19(a), in the case of the RT circuit 5 where the I signal is input to the first terminal and the QB signal is input to the second terminal, as shown in Figs. 19(b) and 19(c), it is classified according to the phase error c>0 and the phase error c≦0.

[0064] As shown in Fig. 20(a), in the case of the RT circuit 6 where the IB signal is input to the first terminal and the Q signal is input to the second terminal, as shown in Figs. 20(b) and 20(c), it is classified according to the phase error a>phase error b and the phase error a≦phase error b.

[0065] As shown in Fig. 21(a), in the case of the RT circuit 7 where the Q signal is input to the first terminal and the I signal is input to the second terminal, as shown in Figs. 21(b) and 21(c), it is classified according to the phase error a<0 and the phase error a≧0.

[0066] As shown in Fig. 22(a), in the case of the RT circuit 8 where the QB signal is input to the first terminal and the IB signal is input to the second terminal, as shown in Figs. 22(b) and 22(c), it is classified according to the phase error b>phase error c and the phase error b≦phase error c.

[0067] Therefore, as shown by the formula in Fig. 23, the average phases Iave and Qave of the I signal and the Q signal, and the phase error (IQ Phase error) between the I signal and the Q signal can be expressed. The combinations of the IQ phase errors are 4×4 ways. Note that among the average phase errors Iave of the I signal and Qave of the Q signal, in the combinations having the same error term, the IQ phase error becomes 0, which means it is canceled.

[0068] <Effect: Preparation for detailed description (Summary of retiming circuit input / output)> FIG. 24 is a diagram illustrating the relationship of the phase error between the input and output of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. In FIG. 24, the relationship of the phase error between the input and output of the RT circuit 30 derived in FIGS. 18(a) and 23 is summarized. Here, the delay phase (shifted to the right in the timing chart) is defined as the positive polarity. Effects #1 and #2 will be described with reference to FIG. 24 and the timing chart corresponding to FIG. 24.

[0069] <Effect #1: Prerequisites for Error> FIGS. 25(a) and (b) are diagrams illustrating the cancellation effect on the VCO operating phase error in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 25(a), in this case, it is assumed that there is no imbalance in the buffer BUF. As described above, the four phases of the output LOOUT of the retiming circuit 34 are generated from the rising edge of the output VCOOUT.

[0070] As shown in FIG. 25(b), the I signal and the IB signal of the output LOOUT are generated from the pos signal of the output VCOOUT. The Q signal and the QB signal of the output LOOUT are generated from the neg signal of the output VCOOUT. Therefore, ideally, no phase error occurs between the I signal and the IB signal, or between the Q signal and the QB signal. The problem in this case is the component of the phase error d between the I signal and the Q signal, or between the IB signal and the QB signal. This phase error d is determined by 1 / 2 times the amount of the VCO operating phase error. The reason is that the delay times are the same and the signal period is doubled. Hereinafter, it will be shown that for the phase error d at the input of the RT circuit 30, the phase error between the I' signal and the Q' signal, or between the IB' signal and the QB' signal, becomes 0 at the output of the RT circuit 30. Note that this case corresponds to the conditions of a = c = d and b = 0 in FIG. 17(b).

[0071] <Effect #1: Calculation Results of Input / Output Errors of the RT Circuit When an Error Occurs> Based on the I signal, the input / output error of the RT circuit 30 with a phase error d with respect to a 90-degree delay on the Q signal side is calculated using the relational expressions in FIG. 24. FIG. 26 is a diagram illustrating the calculation results in the case of a phase delay (d = 1 degree) greater than 90 degrees in the high-frequency signal processing circuit according to Embodiment 1. FIG. 27 is a diagram illustrating the calculation results in the case of a phase advance (d = -1 degree) greater than 90 degrees in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIGS. 26 and 27, in any case, the phase error + / -1 included in the input signal of the RT circuit 30 becomes 0 in the output signal. Thus, it is shown that the phase error d is canceled by the RT circuit 30.

[0072] <Effect #1: Timing Chart> FIGS. 28 to 30 are timing chart diagrams illustrating the input / output signals of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. FIG. 28 shows no phase error (case 1), FIG. 29 corresponds to FIG. 26 (case 2), and FIG. 30 corresponds to FIG. 27 (case 3). In each case, it is shown that the phase error d between the I signal and the Q signal, and between the IB signal and the QB signal is canceled between the I' signal and the Q' signal, and between the IB' signal and the QB' signal.

[0073] <Supplement: Verification of Effect #1 by Simulation> Next, the IRR simulation results at the RX output with and without the retiming circuit 34 including the RT circuit 30 will be described. FIG. 31 is a block diagram illustrating the configuration used for the simulation of the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 31, VCO19 is an ideal signal source that outputs at 5 GHz. The VCO operating phase error is set to -30 degrees to +30 degrees. The IRR monitor points are the RX outputs of the I channel and the Q channel.

[0074] Figs. 32 to 34 are diagrams illustrating simulation results of the high-frequency signal processing circuit according to Embodiment 1. As shown in Fig. 32, the phase error that is canceled in principle is converted into an amplitude error. Also, as shown in Fig. 33, the phase error is improved by about 1 / 5 by the RT circuit 30. As shown in Fig. 34, even if a large IQ phase error occurs in the VCO 19, the retiming circuit 34 having the RT circuit 30 can set the IRR about 10 dB higher. Thus, even if the VCO operating phase error varies greatly from -30 degrees to +30 degrees, the phase error is almost canceled.

[0075] <Effect #2: Prerequisites for Errors> Next, error reduction due to IQ imbalance of the IQ buffer will be described. Figs. 35(a) and (b) are diagrams illustrating configurations for explaining IQ imbalance error reduction of the IQ buffer BUF in the high-frequency signal processing circuit according to Embodiment 1. As shown in Fig. 35(a), four sets of buffers BUF are arranged before the retiming circuit 34 (after DIV20).

[0076] Assume that the buffers BUF for the IB signal, Q signal, and QB signal give phase errors a, b, and c to the respective signals of the IB signal, Q signal, and QB signal with respect to the buffer BUF for the I signal, as shown in Fig. 35(b). In this case, assume that the phase errors a, b, and c are uncorrelated with each other and have a normal distribution with an average value of 0 and the same standard deviation. Under this prerequisite condition, the phase error reduction effect at the output LOOUT of the retiming circuit 34 will be described below using the equation of Fig. 24. In this case, it is assumed that there is no VCO differential imbalance.

[0077] <Effect #2: Calculation Results of Input / Output Errors of Retiming Circuit When Errors Occur> First, representative ones are shown from among many combinations. For example, consider the case where a phase error of 1 degree in magnitude occurs only in the Q signal. That is, the phase error a = 1, and the phase errors b = c = 0. FIG. 36 is a diagram illustrating the relationship between the input and output phase errors of the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 36, in this case, the 0.5-degree IQ phase error included at the input of the RT circuit 30 becomes 0 degrees at the output of the RT circuit 30.

[0078] FIG. 37 is a diagram illustrating a calculation example of a combination of phase errors in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 37, in the case where a phase error of +1 degree occurs only in one phase (Q) out of the four phases, the conditions are a = 1, b = c = 0. In this case, the average IQ phase error on the input side is 0.5, and the average IQ phase error on the output side is 0, which is improved. In the case where a phase error of -1 degree occurs only in one phase (Q) out of the four phases, the conditions are a = -1, b = c = 0. In this case, the average IQ phase error on the input side is -0.5, and the average IQ phase error on the output side is 0, which is improved.

[0079] In the case where a phase error of +1 degree occurs in two adjacent phases (Q, QB) out of the four phases, the conditions are a = c = 1, b = 0. In this case, the average IQ phase error on the input side is 1, and the average IQ phase error on the output side is 0, which is improved. In the case where phase errors of +1 and -1 degrees occur in two adjacent phases (Q, QB) out of the four phases, the conditions are a = 1, c = -1, b = 0. In this case, the average IQ phase error on the input side is 0, and the average IQ phase error on the output side is 0, which is equivalent.

[0080] In the case where a phase error of +1 degree occurs in two non-adjacent phases (IB, QB) out of the four phases, the conditions are b = c = 1 and a = 0. In this case, the average IQ phase error on the input side is 0, and the average IQ phase error on the output side is -0.5, indicating degradation. However, it is half the amount of the maximum phase error on the input side. In the case where phase errors of +1 and -1 degrees occur in two non-adjacent phases (IB, QB) out of the four phases, the conditions are b = 1, c = -1, and a = 0. In this case, the average IQ phase error on the input side is -1, and the average IQ phase error on the output side is -0, indicating improvement.

[0081] Among the calculation examples of appropriate combinations of phase errors, there are also cases of partial degradation. However, looking at the maximum value of the error amount, for a 1-degree phase error at the input, the output is 0.5. The amplitude is decreasing. Furthermore, to consider random combinations, the calculation results in Excel are shown below.

[0082] <Effect #2: Calculation Results of 1000 Sets Considering Normal Distribution Variation> Figures 38(a) and (b) are graphs illustrating the calculation results of the IQ phase error of the relay buffer in the high-frequency signal processing circuit according to Embodiment 1. As shown in Figures 38(a) and (b), for phase errors a, b, c having a normal distribution with a standard deviation of 3 degrees, the IQ phase error is calculated. Then, in the 1000 combination calculations, the standard deviation of the IQ phase error before the input of the RT circuit 30 is about 2.58 degrees. The output of the RT circuit 30 is 0.71 degrees. In this calculation, the standard deviation value of the phase error is reduced by 72% (there are many near the error 0 due to an increase in the cancellation factor at the output). Also, looking at the maximum amplitude, the output of the RT circuit 30 is less than half that of the input of the RT circuit 30.

[0083] Figure 39 is a graph illustrating the selection frequency for each case in the high-frequency signal processing circuit according to Embodiment 1. As shown in Figure 39, the selection frequency for each case is a number close to 250 for each of the 4 Cases in the average phase errors Iave and Qave. Therefore, each of the 4 Cases is equal.

[0084] <Supplement: Verification of Effect #2 by Simulation> Next, the Monte Carlo simulation results of the IQ phase error in the RX output with and without the retiming circuit 34 including the RT circuit 30 will be described. FIG. 40 is a block diagram illustrating the configuration used for the simulation of the high-frequency signal processing circuit according to Embodiment 1. FIGS. 41(a) and (b) are diagrams illustrating the Monte Carlo simulation results of the IQ phase error in the RX output with and without the RT circuit 30 in the high-frequency signal processing circuit according to Embodiment 1.

[0085] As shown in FIG. 40, the VCO 19 is an ideal signal source that outputs at 5 GHz. The monitor points of the IRR are the RX outputs of the I channel and the Q channel. As shown in FIGS. 41(a) and (b), by providing the retiming circuit 34 including the RT circuit 30, the variation in the phase error can be reduced by about 42%. Note that the actual retiming circuit 34 also includes variation factors other than those assumed in the simulation calculation. Therefore, the reduction effect of the phase error in the actual retiming circuit 34 is considered to be lower than the simulation calculation.

[0086] According to the retiming circuit 34 of the present embodiment, an output signal in which the phase error in the input signal is canceled is output. Therefore, the wireless communication quality can be improved. In addition, the retiming circuit 34 can cancel the phase error regardless of which of the I signal, IB signal, Q signal, and QB signal in the input signal has the phase error. Therefore, an extra configuration such as signal switching is unnecessary, and the size can be reduced.

[0087] The retiming circuit 34 can be composed of an inverter circuit and MOS transistors. Therefore, the configuration and manufacturing process can be simplified, and the cost can be reduced.

[0088] Moreover, even if the input signal does not contain a phase error, it does not affect the input signal. Therefore, the wireless communication quality can be maintained.

[0089] Hereinafter, Examples 1 to 13 will be described.

[0090] <Example 1> FIG. 42 is a block diagram illustrating the configuration of Example 1 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 42, in the circuit of LODIV22 of Example 1, DIV20 that has received the 5 GHz signal of VCO19 outputs signals (I signal, IB signal, Q signal, QB signal) having a 2.5 GHz four-phase with a 25% duty cycle. These signals are input to the RT circuit 30 (retiming buffer) of the retiming circuit 34. At the same time, the signals of the foregoing four-phase are input to the clock terminal CK of the RT circuit 30 for each RT circuit 30. Thereby, the waveforms of the I signal and the Q signal are synthesized. The retiming circuit 34 supplies a waveform synthesis output with a 75% duty cycle as an LO signal to the gate of the PMOS of the reception mixer 21. FIG. 42 shows a circuit example at the transistor level of DIV20 and the mixer 21. DIV20 is, for example, the one described in Non-Patent Document 1.

[0091] In this embodiment, the frequency of each input signal has a duty ratio of approximately 25%. The output signal output from the terminal 33 of each RT circuit 30 (RT circuits 5 to 8) transitions from the second state to the first state in conjunction with the rising edge of the input signal input to the terminal 31 of each RT circuit 30 or the falling edge of the input signal input to the terminal 32. And it transitions from the first state to the second state in conjunction with the falling edge of the input signal input to the terminal 31 of each RT circuit 30.

[0092] Also, in this embodiment, the terminal 31 of the RT circuit 30 is connected to the gates of the PMOS transistor 15 and the NMOS transistor 18. The terminal 32 is connected to the inverter circuit 13. The inverter circuit 13 is connected to the inverter circuit 14 and the gate of the NMOS transistor 17. The inverter circuit 14 is connected to the gate of the PMOS transistor 16. The drain of the PMOS transistor 15 is connected to the source of the PMOS transistor 16. The drain of the NMOS transistor 18 is connected to the source of the NMOS transistor 17. The drains of the PMOS transistor 16 and the NMOS transistor 17 are connected to the terminal 33. Also, the mixer 21 includes a PMOS transistor.

[0093] <Example 2> Next, as Example 2, an example in which the circuit configuration of the mixer 21 in Example 1 is changed will be described. FIG. 43 is a block diagram illustrating the configuration of Example 2 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 43, when the transistor in the LO signal input section of the mixer 21 is changed from a PMOS transistor to an NMOS transistor with respect to the configuration of FIG. 42, an odd number of stages (1 stage in the figure) of the inverter circuit IV1 for inverting the logic is required between the RT circuit 30 and the mixer 21. Thereby, a 25% duty cycle signal is supplied to the mixer 21 input.

[0094] Thus, in this embodiment, the RT circuit 30 further has the inverter circuit IV1. Therefore, the drains of the PMOS transistor 16 and the NMOS transistor 17 are connected to the terminal 33 via the inverter circuit IV1.

[0095] Also, in this embodiment, the output signal output from the terminal 33 of each RT circuit 30 transitions from the first state to the second state in conjunction with the rising edge of the input signal input to the terminal 31 of each RT circuit 30 or the falling edge of the input signal input to the terminal 32. Then, it transitions from the second state to the first state in conjunction with the falling edge of the input signal input to the terminal 31 of each RT circuit 30.

[0096] <Example 3> Next, as Example 3, an example where the duty cycle of the input signal of the retiming circuit 34 in Example 1 is 75% is shown. FIG. 44 is a block diagram illustrating the configuration of Example 3 in the high-frequency signal processing circuit according to Embodiment 1. The example where the duty cycle of the input signal of the retiming circuit 34 is 75% is composed of DIV20 with a 25% duty cycle and odd-stage inverters, etc. In this case, it is necessary to add an odd number of inverters for logical inversion to the input of the RT circuit 30 compared to the configuration of FIG. 42.

[0097] Specifically, the RT circuit 30 further has an inverter circuit IV2. The terminal 31 is connected to the gates of the PMOS transistor 15 and the NMOS transistor 18 via the inverter circuit IV2.

[0098] Also, in this embodiment, the output signal output from the terminal 33 of each RT circuit 30 transitions from the second state to the first state in conjunction with the falling edge of the input signal input to the terminal 31 of each RT circuit 30 or the rising edge of the input signal input to the terminal 32. Then, it transitions from the first state to the second state in conjunction with the rising edge of the input signal input to the terminal 31 of each RT circuit 30.

[0099] <Example 4> Next, as Example 4, an example is shown in which the duty cycle of the input signal of the retiming circuit 34 in Example 1 is 75% and the mixer 21 has an NMOS configuration. FIG. 45 is a block diagram illustrating the configuration of Example 4 in the high-frequency signal processing circuit according to Embodiment 1. In this case, it is necessary to add an odd number of inverters for logic inversion to the input of the RT circuit 30 with respect to FIG. 43.

[0100] Specifically, the RT circuit 30 further includes an inverter circuit IV1 and an inverter circuit IV2. The terminal 31 is connected to the gates of the PMOS transistor 15 and the NMOS transistor 18 via the inverter circuit IV2. Also, the drains of the PMOS transistor 16 and the NMOS transistor 17 are connected to the terminal 33 via the inverter circuit IV1.

[0101] In this embodiment, the output signal output from the terminal 33 of each RT circuit 30 transitions from the first state to the second state in conjunction with the fall edge of the input signal input to the terminal 31 of each RT circuit 30 or the rise edge of the input signal input to the terminal 32. Then, it transitions from the second state to the first state in conjunction with the rise edge of the input signal input to the terminal 31 of each RT circuit 30.

[0102] <Examples 5, 6, 7> Next, as Examples 5, 6, and 7, configuration examples of the RT circuit 30 are shown. FIGS. 46(a) to (c) are block diagrams illustrating the configurations of Examples 5 to 7 in the high-frequency signal processing circuit according to Embodiment 1. In Example 5, as shown in FIG. 46(a), an example is shown in which an even number of inverters are inserted on the IN terminal side of the RT circuit 30 to adjust the timing up to the transistor input on the CK terminal side. Specifically, the RT circuit 30 further includes an inverter circuit IV2 and an inverter circuit IV3. The terminal 31 is connected to the gates of the PMOS transistor 15 and the NMOS transistor 18 via the inverter circuit IV2 and the inverter circuit IV3.

[0103] In Example 6, as shown in FIG. 46(b), an example in which the core part of the RT circuit 30 is configured by a NAND logic circuit is shown. The RT circuit 30 has an inverter circuit IV4 and a NAND circuit. The terminal 31 is connected to one input terminal of the NAND circuit, and the terminal 32 is connected to the other input terminal of the NAND circuit via the inverter circuit IV4. The terminal 33 is connected to the output terminal of the NAND circuit. The function of the RT circuit 30 in Example 6 is equivalent to that in Example 1. However, in the SIM verification, the variation characteristics of the phase error may be inferior.

[0104] In Example 7, as shown in FIG. 46(c), it is a configuration in which the MOS transistors connected to the terminal 31 (IN terminal) and the terminal 32 (CK terminal) of the RT circuit 30 are interchanged, which is the same as FIG. 7(c).

[0105] <Example 8> Next, as Example 8, the detailed circuit configuration of LODIV22 is shown. FIG. 47 is a block diagram illustrating the configuration of Example 8 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 47, in the configuration of Example 1, two-stage inverter circuits IV2 and IV3 are inserted on the IN terminal side in the RT circuit 30 for the purpose of relaying buffer and timing adjustment. In this embodiment, in addition to the signal supply path to the receiving circuit, it also has a function of supplying signals to the transmitter TX and the PLL. Also, LODIV22, the retiming circuit 34, and the RX-mixer 21 are arranged in proximity on the layout as shown in FIG. 8(c).

[0106] <Examples 9, 10, 11, 12> Next, as Examples 9, 10, 11, and 12, an example of a configuration in which an IQ phase adjustment function is added to the RT circuit 30 is shown. FIGS. 48(a) to 48(d) are block diagrams illustrating the configurations of Examples 9 to 12 in the high-frequency signal processing circuit according to Embodiment 1. The configuration for finely adjusting the IQ phase as shown in FIGS. 48(a) to 48(d) is not essential. However, in a wireless system that requires high-precision orthogonality, a configuration for finely adjusting the IQ phase may be required. For example, in a Zero-IF receiver that handles 64QAM modulation, a configuration for finely adjusting the IQ phase may be required. However, since the required variable range is narrow, it is also possible to configure the phase adjustment function with low current and a small area.

[0107] FIG. 48(a) is an example in which a variable capacitor CC capable of independently adjusting the I signal and the Q signal is added to the output of the RT circuit 30. Specifically, the RT circuit 30 further has a variable capacitor CC. The drain of the PMOS transistor 16 and the drain of the NMOS transistor 17 are connected to the terminal 33 via the variable capacitor CC. Thereby, the phase of the I signal and the phase of the Q signal can be adjusted.

[0108] FIG. 48(b) is an example in which a variable capacitor CC capable of independently adjusting the I signal and the Q signal is added to the clock CK input terminal so that the phase of the I signal and the phase of the Q signal can be adjusted. Specifically, the terminal 32 is connected to the inverter circuit 13 via the variable capacitor CC.

[0109] FIG. 48(c) is a modification of FIG. 48(b). FIG. 48(c) is an example in which a variable capacitor CC capable of independently adjusting the I signal and the Q signal is added after the inverter circuit 13 following the clock CK input terminal. For example, as shown in FIG. 48(c), the inverter circuit 13 is connected to the inverter circuit 14 and the variable capacitor CC, and the variable capacitor CC is connected to the gate of the NMOS transistor 17. Note that the variable capacitor CC may be arranged anywhere as long as the timing on the clock CK side can be adjusted.

[0110] FIG. 48(d) is an example in which an inverter circuit group capable of switching the number of stages for extracting a signal is added to the input of the clock CK terminal instead of the variable capacitor CC. Specifically, the RT circuit 30 further has a variable-stage inverter circuit IV5 that adjusts the delay amount by switching the number of stages of a plurality of inverter circuits. The terminal 32 is connected to the inverter circuit 13 via the variable-stage inverter circuit IV5. The extraction port is arranged to output an even number of stages so as not to change the logic. The delay amount is adjusted by switching the number of stages of the inverter. Thereby, the phase of the I signal and the phase of the Q signal can be adjusted.

[0111] <Embodiment 13> Next, as Embodiment 13, an example in which a 25% IQ generator is arranged after DIV17 with a 50% duty cycle output is shown. FIG. 49 is a block diagram illustrating the configuration of Embodiment 13 in the high-frequency signal processing circuit according to Embodiment 1. As shown in FIG. 49, a 25% IQ generator (sometimes also referred to as a Generator, Gen.) is arranged after DIV17 with a 50% duty cycle output in the configuration of Embodiment 1. The 25% IQ generator can generally be realized by a circuit that takes the logical product of the I signal and the Q signal, the logical product of the Q signal and the IB signal, the logical product of the IB signal and the QB signal, and the logical product of the QB signal and the I signal. Note that in Embodiment 13, the error factors may increase compared to Embodiment 1. Therefore, in Embodiment 13, the IQ phase error may be larger than that in Embodiment 1.

[0112] (Embodiment 2) Next, Embodiment 2 will be described. This embodiment is an example of a wireless device including a high-frequency signal processing circuit such as the aforementioned retiming circuit 34. FIG. 50 is a block diagram illustrating the wireless device according to Embodiment 2. As shown in FIG. 50, the wireless device 102 includes an antenna impedance matcher 24, a receiver 25, a transmitter 26, a digital circuit 40, a PLL 41, and an LODIV 22. The receiver 25 has an LNA 27, a mixer 21, a band-pass filter 28, and an ADC 29. The LODIV 22 includes a DIV 20 and a high-frequency signal processing circuit such as a retiming circuit 34. As described above, the high-frequency signal processing circuit such as the retiming circuit 34 is connected between the DIV 20 and the mixer 21. In the wireless device 102 of this embodiment, it is preferable that the connection wiring length between the mixer 21 and the high-frequency signal processing circuit such as the retiming circuit 34 is shorter than the connection wiring between the transmitter 26 and the DIV 20.

[0113] According to this embodiment, since the wireless device 102 includes the above-described high-frequency signal processing circuit, the wireless communication quality can be improved. Other configurations and effects are included in the description of Embodiment 1.

[0114] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof. Also, a combination of the configurations of Embodiments 1 and 2 is also within the scope of the technical idea. Furthermore, the following matters are also within the scope of the technical idea of the embodiments.

[0115] (Appendix 1) A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, Comprising, Each waveform synthesizer, A first terminal and a second terminal to which an input signal is input, A third terminal from which an output signal synthesized from the plurality of input signals is output; having The first terminal of the first waveform synthesizer is connected to the first input terminal; The second terminal of the first waveform synthesizer is connected to the fourth input terminal; The third terminal of the first waveform synthesizer is connected to the first output terminal; The first terminal of the second waveform synthesizer is connected to the second input terminal; The second terminal of the second waveform synthesizer is connected to the third input terminal; The third terminal of the second waveform synthesizer is connected to the second output terminal; The first terminal of the third waveform synthesizer is connected to the third input terminal; The second terminal of the third waveform synthesizer is connected to the first input terminal; The third terminal of the third waveform synthesizer is connected to the third output terminal; The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal; The second terminal of the fourth waveform synthesizer is connected to the second input terminal; The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal; A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal; The frequencies of the respective input signals are equal to each other; With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are values that are respectively 180 degrees delayed, 90 degrees delayed, and 270 degrees delayed; The output signal output from the third terminal of each waveform synthesizer is a digital signal that takes two states, a first state and a second state; The state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, High-frequency signal processing circuit. (Appendix 2) The frequency of each input signal has a duty ratio of approximately 25%, The output signal output from the third terminal of each waveform synthesizer is, In conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal, it transitions from the second state to the first state, In conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer, it transitions from the first state to the second state, The high-frequency signal processing circuit according to Appendix 1. (Appendix 3) The frequency of each input signal has a duty ratio of approximately 25%, The output signal output from the third terminal of each waveform synthesizer is, In conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal, it transitions from the first state to the second state, In conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer, it transitions from the second state to the first state, The high-frequency signal processing circuit according to Appendix 1. (Appendix 4) The frequency of each input signal has a duty ratio of approximately 75%, The output signal output from the third terminal of each waveform synthesizer is, In conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer or the rising edge of the input signal input to the second terminal, it transitions from the second state to the first state, Transitions from the first state to the second state in conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer. The high-frequency signal processing circuit according to Supplementary Note 1. (Supplementary Note 5) The frequency of each input signal has a duty ratio of approximately 75%. The output signal output from the third terminal of each waveform synthesizer is Transitions from the first state to the second state in conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer or the rising edge of the input signal input to the second terminal. Transitions from the second state to the first state in conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer. The high-frequency signal processing circuit according to Supplementary Note 1. (Supplementary Note 6) The waveform synthesizer has a first inverter circuit and a second inverter circuit, a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor, and The high-frequency signal processing circuit according to Supplementary Note 1. (Supplementary Note 7) The first terminal is connected to the gate of the first P-type MOS transistor and the gate of the second N-type MOS transistor. The second terminal is connected to the first inverter circuit. The first inverter circuit is connected to the second inverter circuit and the gate of the first N-type MOS transistor. The second inverter circuit is connected to the gate of the second P-type MOS transistor. The drain of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor. The drain of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor. The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal, The high-frequency signal processing circuit according to Supplementary Note 6. (Supplementary Note 8) The waveform synthesizer further includes a third inverter circuit, The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal via the third inverter circuit, The high-frequency signal processing circuit according to Supplementary Note 7. (Supplementary Note 9) The waveform synthesizer further includes a fourth inverter circuit, The first terminal is connected to the gate of the first P-type MOS transistor and the gate of the second N-type MOS transistor via the fourth inverter circuit, The high-frequency signal processing circuit according to Supplementary Note 7. (Supplementary Note 10) The waveform synthesizer further includes a third inverter circuit and a fourth inverter circuit, The first terminal is connected to the gate of the first P-type MOS transistor and the gate of the second N-type MOS transistor via the fourth inverter circuit, The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal via the third inverter circuit, The high-frequency signal processing circuit according to Supplementary Note 7. (Supplementary Note 11) The waveform synthesizer further includes a fourth inverter circuit and a fifth inverter circuit, The first terminal is connected to the gate of the first P-type MOS transistor and the gate of the second N-type MOS transistor via the fourth inverter circuit and the fifth inverter circuit, The high-frequency signal processing circuit according to Supplementary Note 7. (Supplementary Note 12) The waveform synthesizer, an inverter circuit, a NAND circuit, having, the first terminal is connected to one input terminal of the NAND circuit, the second terminal is connected to the other input terminal of the NAND circuit via the inverter circuit, the third terminal is connected to the output terminal of the NAND circuit, the high-frequency signal processing circuit according to Appendix 1. (Appendix 13) the first terminal is connected to the gate of the second P-type MOS transistor and the gate of the first N-type MOS transistor, the second terminal is connected to the first inverter circuit, the first inverter circuit is connected to the second inverter circuit and the gate of the second N-type MOS transistor, the second inverter circuit is connected to the gate of the first P-type MOS transistor, the drain of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor, the drain of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor, the drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal, the high-frequency signal processing circuit according to Appendix 6. (Appendix 14) the waveform synthesizer further has a variable capacitance, the drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal via the variable capacitance, the high-frequency signal processing circuit according to Appendix 7. (Appendix 15) the waveform synthesizer further has a variable capacitance, the second terminal is connected to the first inverter circuit via the variable capacitance, The high-frequency signal processing circuit described in Supplementary Note 7. (Supplementary Note 16) The waveform synthesizer further has a variable capacitance, The first inverter circuit is connected to the second inverter circuit and the variable capacitance, The variable capacitance is connected to the gate of the first N-type MOS transistor, The high-frequency signal processing circuit described in Supplementary Note 7. (Supplementary Note 17) The waveform synthesizer further includes a variable-stage inverter circuit that adjusts the delay amount by switching the number of stages of a plurality of inverter circuits, The second terminal is connected to the first inverter circuit via the variable-stage inverter circuit, The high-frequency signal processing circuit described in Supplementary Note 7. (Supplementary Note 18) The frequency of each input signal is generated by a generator that generates a 25% duty cycle output arranged after a frequency divider with a 50% duty cycle output, The high-frequency signal processing circuit described in Supplementary Note 2. (Supplementary Note 19) The value close to 180-degree delay, the value close to 90-degree delay, and the value close to 270-degree delay are, respectively, the value including a phase error at 180 degrees, the value including the phase error at 90 degrees, and the value including the phase error at 270 degrees, Among the second input signal, the third input signal, and the fourth input signal, at least any one of them is a value including the phase error, The high-frequency signal processing circuit described in Supplementary Note 1. (Supplementary Note 20) An antenna impedance matcher, a transmitter, a receiver, a digital circuit, a PLL, and an LO frequency divider are provided, At least one of the receiver and the transmitter has an LNA, a mixer, a filter, and an ADC, The LO frequency divider includes a frequency divider and the high-frequency signal processing circuit described in Supplementary Note 1 connected between the frequency divider and the mixer, A wireless device. (Supplementary Note 21) The connection wiring length between the mixer and the high-frequency signal processing circuit is shorter than the connection wiring between the transmitter and the frequency divider. The wireless device according to Addendum 20.

Explanation of Signs

[0116] 1, 2, 3, 4 Input terminals 5, 6, 7, 8 RT circuit 9, 10, 11, 12 Output terminals 13, 14 Inverter circuit 15, 16 PMOS transistor 17, 18 NMOS transistor 19 VCO (Voltage Controlled Oscillator) 20 DIV (Frequency Divider) 21, 21a, 21b Mixer 22 LODIV (Local Oscillator Divider, LO Divider) 23 Antenna 24 Antenna Impedance Matched Unit (MN) 25 Receiver 26 Transmitter 27 Low Noise Amplifier (LNA) 28, 28a, 28b Band Pass Filter (BPF) 28c, 28d Programmable Gain Amplifier (PGA) 29, 29a, 29b Analog-to-Digital Converter (ADC) 30 RT circuit 31, 32, 33 Terminals 34 Retiming Circuit (IQ Retiming Circuit) 40 Digital Circuit 41 PLL (Phase Locked Loop) 51 Transmitter Circuit 52 Receiver Circuit 1001 High-Frequency Signal Processing Circuit 102 Wireless Device BUF Buffer CP Tuning Capacitance LB LO Block

Claims

1. a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal; a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; a first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer; comprising: each waveform synthesizer has a first terminal and a second terminal to which an input signal is input, and a third terminal from which an output signal obtained by synthesizing a plurality of the input signals input thereto is output; having: the first terminal of the first waveform synthesizer is connected to the first input terminal; the second terminal of the first waveform synthesizer is connected to the fourth input terminal; the third terminal of the first waveform synthesizer is connected to the first output terminal; the first terminal of the second waveform synthesizer is connected to the second input terminal; the second terminal of the second waveform synthesizer is connected to the third input terminal; the third terminal of the second waveform synthesizer is connected to the second output terminal; the first terminal of the third waveform synthesizer is connected to the third input terminal; the second terminal of the third waveform synthesizer is connected to the first input terminal; the third terminal of the third waveform synthesizer is connected to the third output terminal; the first terminal of the fourth waveform synthesizer is connected to the fourth input terminal; the second terminal of the fourth waveform synthesizer is connected to the second input terminal; the third terminal of the fourth waveform synthesizer is connected to the fourth output terminal; a first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal; the frequencies of the respective input signals are equal to each other; with respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay; the output signal output from the third terminal of each waveform synthesizer is a digital signal that takes two states, a first state and a second state; the state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal. The state transitions from the other state to one state in conjunction with the input signal input to the first terminal of each waveform synthesizer, The frequency of each input signal has a duty ratio of approximately 25%, The output signal output from the third terminal of each waveform synthesizer is, It transitions from the second state to the first state in conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal, It transitions from the first state to the second state in conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer, High-frequency signal processing circuit.

2. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, Comprising, Each waveform synthesizer, A first terminal and a second terminal to which an input signal is input, A third terminal from which an output signal obtained by synthesizing the plurality of input signals input is output, Having, The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay. The output signal output from the third terminal of each waveform synthesizer is a digital signal that takes two states, a first state and a second state, and the state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal. The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer. The frequency of each input signal has a duty ratio of approximately 25%. The output signal output from the third terminal of each waveform synthesizer is and transitions from the first state to the second state in conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal. It transitions from the second state to the first state in conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer. A high-frequency signal processing circuit.

3. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, a first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, and is provided with Each waveform synthesizer has a first terminal and a second terminal to which an input signal is input, and a third terminal from which an output signal obtained by synthesizing the plurality of input signals input is output, and has The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay, The output signal output from the third terminal of each waveform synthesizer is A digital signal that takes two states, a first state and a second state, The state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, The waveform synthesizer A first inverter circuit and a second inverter circuit, A first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor, having A high-frequency signal processing circuit.

4. The first terminal is connected to the gates of the first P-type MOS transistor and the second N-type MOS transistor, The second terminal is connected to the first inverter circuit, The first inverter circuit is connected to the second inverter circuit and the gate of the first N-type MOS transistor, The second inverter circuit is connected to the gate of the second P-type MOS transistor, The drain of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor, The drain of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor, The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal, The high-frequency signal processing circuit according to claim 3.

5. The waveform synthesizer further includes a third inverter circuit, The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal via the third inverter circuit, The high-frequency signal processing circuit according to claim 4.

6. The waveform synthesizer further includes a fourth inverter circuit, The first terminal is connected to the gates of the first P-type MOS transistor and the second N-type MOS transistor via the fourth inverter circuit, The high-frequency signal processing circuit according to claim 4.

7. The waveform synthesizer further includes a third inverter circuit and a fourth inverter circuit, The first terminal is connected to the gates of the first P-type MOS transistor and the second N-type MOS transistor via the fourth inverter circuit, The drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal via the third inverter circuit, The high-frequency signal processing circuit according to claim 4.

8. The waveform synthesizer further includes a fourth inverter circuit and a fifth inverter circuit, The first terminal is connected to the gates of the first P-type MOS transistor and the second N-type MOS transistor via the fourth inverter circuit and the fifth inverter circuit, The high-frequency signal processing circuit according to claim 4.

9. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal; A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer; Comprising: Each waveform synthesizer A first terminal and a second terminal to which an input signal is input; A third terminal from which an output signal obtained by synthesizing the plurality of input signals is output; Having: The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the respective input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay, The output signal output from the third terminal of each waveform synthesizer is A digital signal that takes two states, a first state and a second state, The state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, The waveform synthesizer An inverter circuit and A NAND circuit, And has The first terminal is connected to one input terminal of the NAND circuit, The second terminal is connected to the other input terminal of the NAND circuit via the inverter circuit, The third terminal is connected to the output terminal of the NAND circuit, A high-frequency signal processing circuit.

10. The first terminal is connected to the gates of the second P-type MOS transistor and the first N-type MOS transistor, The second terminal is connected to the first inverter circuit, The first inverter circuit is connected to the gate of the second inverter circuit and the second N-type MOS transistor. The second inverter circuit is connected to the gate of the first P-type MOS transistor. The drain of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor. The drain of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor. The drains of the second P-type MOS transistor and the first N-type MOS transistor are connected to the third terminal. The high-frequency signal processing circuit according to claim 3.

11. The waveform synthesizer further has a variable capacitance. The drains of the second P-type MOS transistor and the first N-type MOS transistor are connected to the third terminal via the variable capacitance. The high-frequency signal processing circuit according to claim 4.

12. The waveform synthesizer further has a variable capacitance. The second terminal is connected to the first inverter circuit via the variable capacitance. The high-frequency signal processing circuit according to claim 4.

13. The waveform synthesizer further has a variable capacitance. The first inverter circuit is connected to the second inverter circuit and the variable capacitance. The variable capacitance is connected to the gate of the first N-type MOS transistor. The high-frequency signal processing circuit according to claim 4.

14. The values close to 180-degree delay, the values close to 90-degree delay, and the values close to 270-degree delay are, respectively, the values including a phase error at 180 degrees, the values including the phase error at 90 degrees, and the values including the phase error at 270 degrees. Among the second input signal, the third input signal, and the fourth input signal, at least one of them is a value including the phase error. The high-frequency signal processing circuit according to claim 1.

15. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal; A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer; Comprising: Each waveform synthesizer Has a first terminal and a second terminal to which an input signal is input; And a third terminal from which an output signal obtained by synthesizing the plurality of input signals input is output. And has The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the respective input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are values that are respectively 180 degrees delayed, 90 degrees delayed, and 270 degrees delayed, The output signal output from the third terminal of each waveform synthesizer is A digital signal that takes two states, a first state and a second state, The state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, The frequency of each input signal has a duty ratio of approximately 25%, The output signal output from the third terminal of each waveform synthesizer is It transitions from the second state to the first state in conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal, It transitions from the first state to the second state in conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer. High-frequency signal processing circuit.

16. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, Comprising, Each waveform synthesizer, A first terminal and a second terminal to which an input signal is input, A third terminal from which an output signal obtained by synthesizing the plurality of input signals input is output, Having, The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the respective input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are values delayed by 180 degrees, 90 degrees, and 270 degrees respectively, The output signal output from the third terminal of each waveform synthesizer, Is a digital signal that takes two states, a first state and a second state, The state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, The state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, The frequencies of the respective input signals have a duty ratio of approximately 25%, The output signal output from the third terminal of each waveform synthesizer is, In conjunction with the rising edge of the input signal input to the first terminal of each waveform synthesizer or the falling edge of the input signal input to the second terminal, it transitions from the first state to the second state, In conjunction with the falling edge of the input signal input to the first terminal of each waveform synthesizer, it transitions from the second state to the first state, A high-frequency signal processing circuit.

17. A first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, A first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, Comprising: Each waveform synthesizer Has a first terminal and a second terminal to which an input signal is input, And a third terminal from which an output signal obtained by synthesizing the plurality of input signals input is output, And has The first terminal of the first waveform synthesizer is connected to the first input terminal, The second terminal of the first waveform synthesizer is connected to the fourth input terminal, The third terminal of the first waveform synthesizer is connected to the first output terminal, The first terminal of the second waveform synthesizer is connected to the second input terminal, The second terminal of the second waveform synthesizer is connected to the third input terminal, The third terminal of the second waveform synthesizer is connected to the second output terminal, The first terminal of the third waveform synthesizer is connected to the third input terminal, The second terminal of the third waveform synthesizer is connected to the first input terminal, The third terminal of the third waveform synthesizer is connected to the third output terminal, The first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, The second terminal of the fourth waveform synthesizer is connected to the second input terminal, The third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, A first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, The frequencies of the respective input signals are equal to each other, With respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are values that are 180 degrees delayed, 90 degrees delayed, and 270 degrees delayed, respectively. The output signal output from the third terminal of each waveform synthesizer is a digital signal that takes two states, a first state and a second state, the state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, the state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, the waveform synthesizer includes a first inverter circuit and a second inverter circuit, a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor, and has a high-frequency signal processing circuit.

18. The first terminal is connected to the gate of the first P-type MOS transistor and the gate of the second N-type MOS transistor, the second terminal is connected to the first inverter circuit, the first inverter circuit is connected to the second inverter circuit and the gate of the first N-type MOS transistor, the second inverter circuit is connected to the gate of the second P-type MOS transistor, the drain of the first P-type MOS transistor is connected to the source of the second P-type MOS transistor, the drain of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor, the drain of the second P-type MOS transistor and the drain of the first N-type MOS transistor are connected to the third terminal, The high-frequency signal processing circuit according to claim 17.

19. An antenna impedance matcher, a transmitter, a receiver, a digital circuit, a PLL, and a LO frequency divider are provided, at least one of the receiver and the transmitter has an LNA, a mixer, a filter, and an ADC, the LO frequency divider includes a frequency divider and a high-frequency signal processing circuit connected between the frequency divider and the mixer, the high-frequency signal processing circuit has a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, A first waveform synthesizer, a second waveform synthesizer, a third waveform synthesizer, and a fourth waveform synthesizer, comprising: Each waveform synthesizer has a first terminal and a second terminal to which an input signal is input, and a third terminal from which an output signal obtained by synthesizing the plurality of input signals input thereto is output, and has the first terminal of the first waveform synthesizer is connected to the first input terminal, the second terminal of the first waveform synthesizer is connected to the fourth input terminal, the third terminal of the first waveform synthesizer is connected to the first output terminal, the first terminal of the second waveform synthesizer is connected to the second input terminal, the second terminal of the second waveform synthesizer is connected to the third input terminal, the third terminal of the second waveform synthesizer is connected to the second output terminal, the first terminal of the third waveform synthesizer is connected to the third input terminal, the second terminal of the third waveform synthesizer is connected to the first input terminal, the third terminal of the third waveform synthesizer is connected to the third output terminal, the first terminal of the fourth waveform synthesizer is connected to the fourth input terminal, the second terminal of the fourth waveform synthesizer is connected to the second input terminal, the third terminal of the fourth waveform synthesizer is connected to the fourth output terminal, a first input signal, a second input signal, a third input signal, and a fourth input signal are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal, the frequencies of the respective input signals are equal to each other, with respect to the phase of the first input signal, the phases of the second input signal, the third input signal, and the fourth input signal are respectively 180 degrees delayed or values close to the 180-degree delay, 90 degrees delayed or values close to the 90-degree delay, and 270 degrees delayed or values close to the 270-degree delay, the output signal output from the third terminal of each waveform synthesizer is a digital signal that takes two states, a first state and a second state, the state transitions from one to the other in conjunction with the input signal input to the first terminal of each waveform synthesizer or the input signal input to the second terminal, and the state transitions from the other to one in conjunction with the input signal input to the first terminal of each waveform synthesizer, a wireless device.

20. The connection wiring length between the mixer and the high-frequency signal processing circuit is shorter than the connection wiring between the transmitter and the frequency divider. The wireless device according to claim 19.

Images