Data Equalization for Storage within a Memory Device

Abstract

Methods, systems, and devices related to data balancing are described. Data may be communicated using original sets of bits, which may be divided into segments. Each of the original sets of bits may have a first value or a second value, and the weight of the original set of bits may be based on the amount of the set of bits that have the first value. If the weight of the original set of bits is outside a target weight range, a different, coded set of bits may be used to represent the data, and the coded set of bits has a weight within the target weight range. The coded set of bits may be identified based on the inversion of the original set of bits in a one-by-one cumulative manner. The coded set of bits may be stored in place of the original set of bits.

Description

Technical Field

[0001] [Cross - Reference] This patent application claims priority to U.S. Patent Application No. 16 / 865,163, entitled "BALANCING DATA FOR STORAGE IN A MEMORY DEVICE", filed by Laurent et al. on May 1, 2020, which has been assigned to the assignee of the present invention and is hereby expressly incorporated by reference herein.

[0002] The following generally relates to one or more memory systems, and more particularly to balancing data for storage in a memory device.

Background Art

[0003] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells in the memory device into various states. For example, a binary memory cell may be programmed into one of two supported states, often represented by logic 1 or logic 0. In some embodiments, a single memory cell may support three or more states, and any one of them may be stored. To access the stored information, a component may read or sense at least one stored state in the memory device. To store information, a component may write or program a state into the memory device.

[0004] There exist various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selective memory, chalcogenide memory technology, etc. The memory cells may be volatile or non-volatile.

[0005] Improving memory devices may include, among other various metrics, increasing memory cell density, increasing read / write speed, increasing reliability, increasing data retention, decreasing power consumption, or decreasing manufacturing cost.

Brief Description of the Drawings

[0006]

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[0007] A set of data (data packets, data bursts) exchanged between a host device and a memory device may include N bits, each of the N bits being able to represent a logical value (e.g., one of a first logical value or a second logical value). A weight may be assigned to a data packet based on the amount of bits within the data packet that have a first logical value (e.g., 1). A data packet having the same amount of bits with a first logical value and a second logical value (e.g., 0) may be referred to as a “balanced data packet” or “balanced codeword” and have a particular weight (e.g., NUMERICAL VALUES Data packets having weights (or some other specific target weight) may more generally be referred to as "constant weight data packets" or "constant weight codewords". As described herein, data packets may be encoded to have a specific target weight (e.g., to be balanced data packets or another type of constant weight data packet), or to have a weight within a target weight range (e.g., a weight within the range

Number

[0008] Data packets may be encoded to obtain corresponding encoded data packets, and the encoded data packets may then be stored in a memory array. That is, the encoded data packets may be used to represent the same data as the corresponding original data packets and may be stored in the memory array in place of the corresponding original data packets. In some cases, the encoding is a target weight (e.g.,

Number

number

[0009] In some cases, different inversion possibilities may be verified for a data packet to obtain an encoded data packet. For example, in the case of a single data packet, multiple weights may be calculated for a set of possible encoded data packets that may be constructed from the single data packet, each of which may include a different combination of inverted and non-inverted bits of the data packet. In order to verify all possible encoded data packets for a single data packet and to ensure that a desired weight is obtained, up to 2 N The weights of each are up to 2 N A coding bit may be calculated for each of the different coded data packets. After identifying an inversion probability (e.g., equal to a target weight, within a target weight range) associated with a coded data packet having a particular combination of inverted and non-inverted bits, the corresponding bits of the data packet may be inverted to yield a coded data packet. The coded data packet may then be stored in the memory array in place of the original data packet. To support later decoding of the coded data packet that returns the original data packet, a coding bit may be appended to the coded data packet indicating which bits of the data packet have / will have been inverted as a result of the encoding process. N To support indicating N different combinations, N coding bits may be used to indicate which bits of the data packet are / are inverted.

[0010] In some cases, the encoding process used to generate encoded data packets, for example, up to a maximum of 2 N may increase the latency for data storage based on verifying up to a maximum of 2 possible encoded data packets. To reduce the latency impact of generating encoded data packets, the number of possible encoded data packets to be verified may be reduced. To reduce the number of possible encoded data packets to be verified, the data packet may be divided into r segments, and the weight of the possible encoded data packets derived by sequential (or persistent) inversion of each segment of the data packet may be checked until a target weight range is achieved. That is, the memory device may calculate a first weight associated with a first possible encoded data packet assuming that the first segment of the data packet is inverted, a second weight associated with a second possible encoded data packet assuming that the first and second segments of the data packet are inverted, and up to an rth weight associated with a final possible encoded data packet assuming that all segments of the data packet are inverted. Thus, r + 1 hypotheses (rather than 2 N hypotheses) may be verified, and [log2(r + 1)] encoding bits (rather than N encoding bits) may be used to indicate which segments of the data packet were inverted during the encoding process - or, in some cases, r hypotheses may be verified and [log2(r)] encoding bits may be used when, for example, the target weight range is

Number

[0011] Depending on the limits of the target weight range (e.g., lower limit, upper limit, span), the weight of the possible encoded data packets derived by sequential cumulative inversion of segments may fail to identify an encoded data packet that achieves the target weight range. Thus, the limits of the target weight range may be selected to ensure that the weight associated with at least one of the possible encoded data packets falls within the target weight range. For example, the target weight range may be represented as

Number

[0012] The features of the present disclosure are first described in the context of a memory system and die described with reference to FIGS. 1 and 2. The features of the present disclosure are described in the context of data packets, inversion diagrams, memory devices, encoders, and index decoders described with reference to FIGS. 3 through 8. These and other features of the present disclosure are further illustrated and described by apparatus diagrams and flowcharts related to data equalization for storage within a memory device described with reference to FIGS. 9 through 11.

[0013] FIG. 1 is a diagram showing an example of a system 100 that supports data equalization for storage within a memory device according to an example disclosed herein. It should be noted that the following is only one example of how data equalization for storage within a memory device is implemented. The techniques disclosed herein may be implemented with any memory device. For example, the techniques disclosed herein may be implemented with FeRAM, PCM, etc. In this example, system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 that couple host device 105 to memory device 110. System 100 may include one or more memory devices 110, although aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0014] System 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may be shown in aspects such as a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, etc. Memory device 110 may be a component of a system operable to store data for one or more other components of system 100.

[0015] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as, among other examples, a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or some other fixed or portable electronic device. In some examples, host device 105 may refer to hardware, firmware, software, or combinations thereof that implement the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as the host or host device 105.

[0016] Memory device 110 may be an independent device or component operable to provide a physical memory address / space that can be used or referenced by system 100. In some examples, memory device 110 may be configurable to cooperate with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of modulation schemes for modulating signals, different pin designs for communicating signals, various form factors for the physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0017] Memory device 110 may be operable to store data for components of host device 105. In some embodiments, memory device 110 may function as a slave type device with respect to host device 105 (e.g., execute in response to commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0018] Host device 105 may include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output (I / O) controllers. The components of the host device may be coupled to each other using bus 135.

[0019] Processor 125 may be operable to provide control or other functions to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such embodiments, processor 125 may be, among other embodiments, a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-chip (SoC) embodiment. In some embodiments, external memory controller 120 may be implemented by or be a part of processor 125.

[0020] The BIOS component 130 may be a software component including BIOS operating as firmware, which can initialize and operate various hardware components of the system 100 or the host device 105. The BIOS component 130 may also manage the data flow between the processor 125 and various components of the system 100 or the host device 105. The BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or any other non-volatile memory.

[0021] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) supporting a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a set of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), and each memory cell is operable to store at least one bit of data. The memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0022] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controllers 120, one or more memory dies 160, or the processor 125. In some embodiments, the device memory controller 155 may control the operation of the memory device 110 as described herein in connection with the local memory controller 165 of the memory die 160.

[0023] The local memory controller 165 (e.g., local to the memory die 160) may be operable to control the operation of the memory die 160. In some embodiments, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., receive or transmit data or commands or both). In some embodiments, the memory device 110 may not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, or may be operable to communicate with other local memory controllers 165, or may be operable to communicate directly with the external memory controller 120 or the processor 125 or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165 or both.

[0024] The external memory controller 120 may be operable to enable one or more communications of information, data, or commands between a component (e.g., the processor 125) of the system 100 or host device 105 and the memory device 110. The external memory controller 120 may convert or translate the communication between the component of the host device 105 and the memory device 110. In some embodiments, the external memory controller 120 or the system 100 or other components of the host device 105, or its functions described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, software, or some combination thereof implemented by the processor 125 or other components of the system 100 or host device 105. The external memory controller 120 is shown to be external to the memory device 110, but in some embodiments, the external memory controller 120, or its functions described herein, may be implemented by one or more components (e.g., the device memory controller 155, the local memory controller 165) of the memory device 110, or vice versa.

[0025] The components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that conveys information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. The signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal that includes one or more pins or pads in the host device 105 and one or more pins or pads in the memory device 110. The pins may be examples of conductive input or output points of the devices of the system 100, and the pins may be operable to function as part of the channel.

[0026] The channels 115 (and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some embodiments, signaling may be communicated on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered per clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered per clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0027] In some embodiments, the memory device 110 may receive data or commands or both from the host device 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 should store a set of data for the host device 105 or a read command indicating that the memory device 110 should provide data stored in the memory die 160 to the host device. The set of data may be sent on the data channel 190. In some cases, the set of data sent on the data channel 190 may be referred to as a data packet.

[0028] The data packet received by the memory device 110 may include N bits, and each of the N bits may have a respective logical value (e.g., either a first logical value or a second logical value). The memory device 110 may assign a weight to the data packet based on the amount of bits in the data packet having a first logical value (e.g., 1), i.e., based on the number of 1s in the data packet. As described herein, an encoded data packet may be generated based on the data packet, and the encoded data packet may have a weight within a target weight range or equal to a specific target weight, which may support one or more of a variety of benefits understood by those skilled in the art, among other things, advanced read techniques, shorter latency, increased reliability, lower power consumption, and reduced leakage for the memory array 170.

[0029] In one example of an advanced read technique supported by the encoded data packet, the memory device 110 may terminate the read operation before reading all of the memory cells used to store the encoded data packet. That is, a specific weight (e.g.,

Number

Number

[0030] In some cases, as part of the encoding process for obtaining an encoded data packet, the memory device 110 may verify different invertibility for the data packet. That is, in the case of a single data packet, the memory device 110 may calculate weights for a set of possible encoded data packets that can be derived from the single data packet. Each of the possible encoded data packets may include different combinations of inverted bits and may be referred to as a "hypothesis". To verify all of the possible encoded data packets for a single data packet and to ensure that a target weight or weight range is obtained, the memory device 110 may calculate up to 2 N weights for up to 2 N different encoded data packets derived from a single data packet - that is, the memory device 110 may verify 2 N different hypotheses.

[0031] After identifying a hypothesis associated with a target weight or weight range, the memory device 110 may invert corresponding bits of the data packet to produce an encoded data packet. The memory device 110 may then store the encoded data packet in the memory array 170 instead of the originally received data packet. To enable reconstruction of the original data packet, the memory device 110 may generate and store an indication of which bits of the data packet were inverted to form the encoded data packet - such an indication, sometimes alternatively referred to as a set of encoded bits, may be associated with the encoded data packet. In some cases, log2(2 N ) = N encoded bits are used to indicate which bits of the data packet were inverted during the encoding process.

[0032] In some cases, the encoding process for obtaining the encoded data packet may add latency to the process - as a result of verifying, for example, up to 2 N different hypotheses - to store the data. To reduce the added latency, the potential number of hypotheses verified by the memory device 100 may be reduced. In one option for reducing the number of hypotheses verified, the memory device 110 may use a target weight (e.g.,

Number

[0033] In another option to reduce the number of hypotheses to be verified, the memory device 110 may divide the data packet into r1 segments and verify all possible combinations of the segments of the data packet that are inverted until a hypothesis that achieves the target weight range is determined. The target weight range can be expressed as

Number

Number

Number

Number

Number

[0034] In a third option for reducing the number of hypotheses to be verified, which can be associated with a reduction in latency and encoding overhead compared to the first and second options, the memory device 110 divides the data packet into segments of r2 and verifies a set of hypotheses derived by sequential cumulative inversion of each segment of the data packet until a hypothesis that achieves the target weight range is determined. That is, the memory device calculates a first weight associated with a first hypothesis that assumes the first segment of the data packet is inverted, a second weight associated with a second hypothesis that assumes the first and second segments of the data packet are inverted, and up to an r2-th weight associated with a final hypothesis that assumes all segments of the data packet are inverted. Thus, r2 + 1 hypotheses may be verified (including the hypothesis that assumes the segment is not inverted), and [log2(r2 + 1)] encoded bits may be used to indicate which segments of the data packet were inverted during the encoding process. In some cases, each of the r2 segments may contain n2 bits, where in the above formula,

Number

[0035] In contrast, in the case of the first option, N+1 hypotheses may be verified, and [log2(N+1)] encoded bits may be used, where N may be greater than r2 and r1. And in the case of the second option,

Number

[0036] Therefore, to ensure that the sequential cumulative inversion of the segments results in an encoded data packet with an acceptable weight, the memory device 110 may use a target weight range that guarantees that the weight associated with at least one of the hypotheses falls within the target weight range. The target weight range is

Number

Number

[0037] In some cases, while still ensuring that the weight associated with at least one of the hypotheses falls within the target weight range, the target weight range may be offset (e.g.,

Number

Number

Number

Number

Number

[0038] In some embodiments, in the case of the third option, instead of r2 + 1 hypotheses, r2 hypotheses may be verified, and thus [log2(r2)] encoded bits may be used to indicate which segment of the data packet was inverted during the encoding process. For example, when the weight range for the data packet is

Number

Number

Number

[0039] When the memory device 110 receives a read command (from the host device 105) requesting data that was encoded prior to storage in the memory array 170, the memory device 110 may use the encoded bits stored with the encoded data packets to reconstruct the originally received data packets. The process of reconstructing the original data packets from the encoded data packets may be referred to as decoding. After the encoded data packets have been decoded, the memory device 110 may output the originally received data packets to the host device 105. Alternatively, the memory device 110 may output the encoded data packets and associated encoded bits so that an external device (e.g., the host device 105) can decode the encoded data packets.

[0040] The encoding and decoding described herein may be performed at different locations within the system 100 (and thus the associated encoding and decoding circuitry may be located) depending on the embodiment. For example, the encoding and decoding may be performed within the memory die 160 (e.g., by the local memory controller 165), within the memory device 110 (e.g., by the device memory controller 155), or within the host device 105 (e.g., by the external memory controller 120). In some cases, where the encoding and decoding are performed may be based on the location of error correction circuitry within the system 100. For example, when data packets are to be encoded and written to the memory array 170, the encoding for equalization purposes may be performed prior to the associated (e.g., write side) error correction procedure, and when the encoded data packets are to be read and decoded, the associated (e.g., read side) error correction procedure may be performed prior to decoding.

[0041] Encoding and decoding for equalization purposes can be considered high-level functions compared to error correction, and thus, the encoding and decoding may be performed within the same device or on a high-level device compared to error correction. For example, if the error correction circuit is located within the host device 105 (e.g., in the external memory controller 120), the encoding / decoding circuit may be located within the host device 105 (e.g., in the external memory controller 120). If the error correction circuit is located within the memory device 110 (e.g., in the device memory controller 155), the encoding / decoding circuit may be located within the memory device 110 (e.g., in the device memory controller 155) or within the host device 105 (e.g., in the external memory controller 120). And when the error correction circuit is located on the memory die 160 (e.g., in the local memory controller 165), the encoding / decoding circuit for performing the equalization procedure may be located within any of the memory die 160 (e.g., in the local memory controller 165), the memory device 110 (e.g., in the device memory controller 155), or the host device 105 (e.g., in the external memory controller 120).

[0042] FIG. 2 is a diagram showing an embodiment of a memory die 200 that supports data equalization for storage within a memory device according to an embodiment disclosed herein. It should be noted that the following is only one example of how data equalization for storage within a memory device is implemented. The techniques disclosed herein may be implemented with any memory device. For example, the techniques disclosed herein may be implemented with FeRAM, PCM, etc. In this embodiment, the memory die 200 may be an embodiment of the memory die 160 described with reference to FIG. 1.

[0043] In some embodiments, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 each programmable to store different logical states (e.g., programmed ones of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information (e.g., logical 0 or logical 1) at a time. In some embodiments, the memory cell 205 (e.g., a multi-level memory cell 205) may be operable to store more than one bit of information (e.g., logical 00, logical 01, logical 10, or logical 11) at a time. In some embodiments, the memory cells 205 may be arranged in an array such as the memory array 170 described with reference to FIG. 1.

[0044] In some cases, the memory cell 205 may store a logical state using a configurable material, which may be referred to as a memory element, a memory storage element, a material element, a material storage element, a material portion, or a polar writing material portion, among other things. The configurable material of the memory cell 205 may refer to a chalcogenide-based memory component. For example, a chalcogenide memory element may be used within a phase change memory (PCM) cell, a threshold processing memory cell, or a self-selective memory cell.

[0045] The memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern such as a grid pattern. The access lines may be formed from one or more conductive materials. In some embodiments, the row lines 210 may be referred to as word lines. In some embodiments, the column lines 215 may be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, are interchangeable without loss of understanding or operation. The memory cells 205 may be positioned at intersections of the row lines 210 and the column lines 215.

[0046] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting one or more access lines such as one or more of the row lines 210 or column lines 215. By biasing the row lines 210 and column lines 215 (for example, applying a voltage to the row lines 210 or column lines 215), access to a single memory cell 205 can be achieved at their intersection. In either a two-dimensional or three-dimensional configuration, the intersection of the row lines 210 and column lines 215 may be referred to as the address of the memory cell 205. The access lines may be conductive lines coupled to the memory cell 205 and may be used to perform access operations on the memory cell 205.

[0047] Access to the memory cell 205 may be controlled via the row decoder 220 or column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the row lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the column lines 215 based on the received column address.

[0048] The sensing component 230 may be operable to detect the state of the memory cell 205 (e.g., material state, resistance, threshold state) and determine the logical state of the memory cell 205 based on the stored state. The sensing component 230 may include one or more sense amplifiers that amplify or convert a signal resulting from accessing the memory cell 205. The sensing component 230 may compare the signal detected from the memory cell 205 with a reference signal 235 (e.g., a reference voltage). The detected logical state of the memory cell 205 may be provided as the output of the sensing component 230 (e.g., to the input / output 240) and the detected logical state may be indicated to another component of the memory device including the memory die 200.

[0049] The local memory controller 260 may control access to the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sense component 230). The local memory controller 260 may be an example of the local memory controller 165 described with reference to FIG. 1. In some embodiments, one or more of the row decoder 220, column decoder 225, and sense component 230 may be co-located with the local memory controller 260. The local memory controller 260 may receive one or more of commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate this command or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and be operable to communicate data from the memory die 200 to the host device 105 based on having performed the one or more operations. The local memory controller 260 may generate row signals and column address signals to activate the target row line 210 and target column line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current considered herein is changeable and may be different for the various operations considered when operating the memory die 200.

[0050] The local memory controller 260 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include, among others, write operations, read operations, refresh operations, precharge operations, or activation operations. In some embodiments, the access operations may be performed or coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be operable to perform other access operations not enumerated herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0051] The local memory controller 260 may be operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 for performing the write operation. The local memory controller 260 can identify the target row line 210 and the target column line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target row line 210 and the target column 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the column line 215 during the write operation to store a specific state in the memory element of the memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

[0052] The local memory controller 260 may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cell 205 of the memory die 200 may be determined. The local memory controller 260 can identify a target memory cell 205 for performing the read operation. The local memory controller 260 may identify a target word line 210 and a target bit line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target column 215 (e.g., apply a voltage to the word line 210 or the bit line 215) to access the target memory cell 205. The sense component 230 can detect a signal received from the memory cell 205 based on a pulse applied to the word line 210, a pulse applied to the column line, and / or the resistance or threshold characteristics of the memory cell 205. The sense component 230 can amplify the signal. The local memory controller 260 can activate the sense component 230 (e.g., latch the sense component), whereby the signal received from the memory cell 205 can be compared to a reference signal 235. Based on the comparison, the sense component 230 can determine the logical state stored on the memory cell 205. The pulse used as part of the read operation may include one or more voltage levels over a duration.

[0053] Before executing, or as part of executing, a write operation to store a received data packet, local memory controller 260 may be operable to encode the received data packet and write the encoded data packet, rather than the received data packet, to the memory array. Local memory controller 260 may include a data encoder 265 operable to execute an encoding operation before or as part of the write operation. Data encoder 265 may divide the data packet into r segments and determine which segments of the data packet should be inverted to obtain an encoded data packet having a weight within a target range. Data encoder 265 may be configured to determine the weights of r + 1 encoded data packets that may be derived from the data packet (including the encoded data packet that is the same as the original data packet) and identify possible encoded data packets having weights that fall within a target weight range. The target weight range may be stored within data encoder 265 and may span values

Number

[0054] Data encoder 265 may also construct an encoded segment indicating which of the segments of the encoded data packet are inverted. Data encoder 265 may also construct a padding segment used to increase the weight of the constant weight encoded data packet so that the final weight of the constant weight encoded data packet is equal to and / or balanced with a particular target weight. The encoded data packet stored within the memory array may include the encoded segment and the padding segment.

[0055] After performing a read operation to provide the requested data packet to the host device, or as part of performing the read operation, the local memory controller 260 may be operable to decode an encoded version of the requested data packet. The local memory controller 260 may include a data decoder 270 that is operable to perform a decoding operation after or as part of the read operation. The data decoder 270 may be configured to determine which segments of the encoded data packet were inverted during the encoding process - for example, using the encoded bits stored within the encoded data packet. After the encoded data packet has been decoded, the original data packet may be reconstructed and transmitted to the host device.

[0056] In some cases, the data encoder 265 and the data decoder 270 are located external to the local memory controller 260 - for example, based on the location of the error correction circuitry. For example, the data encoder 265 and the data decoder 270 may be located external to the local memory controller 260 if the error correction circuitry is located external to the local memory controller 260 - for example, if the error correction circuitry is located in the device memory controller or the host device. As discussed herein, the location of the data encoder 265 and the data decoder 270 may be selected such that the error correction procedure is performed after the encoding procedure and before the associated decoding procedure.

[0057] FIG. 3 is a diagram illustrating an example of a data structure 300 that supports data equalization for storage within a memory device, according to an embodiment disclosed herein. The data structure 300 may include an encoded data packet 305 and an encoded segment 325.

[0058] The symbolized data packet 305 may include N symbolized data bits stored in a memory array (e.g., the memory array 170 of FIG. 1). The symbolized data packet 305 may be a symbolized version of a data packet received from a host device in relation to a single read command (e.g., as a single data burst). Thus, the data packet 310 may include N changed (e.g., symbolized) data bits as compared to the N bits of the received data packet.

[0059] A weight may be assigned to the symbolized data packet 305 based on the amount of bits in the symbolized data packet 305 having a given logical value (e.g., logical value 1). For example, if the symbolized data packet 305 includes 100 bits having a logical value of 1, the symbolized data packet 305 may have a weight of 100. In some cases, the weight of the symbolized data packet 305 may be expressed in terms of the ratio of the amount of bits in the symbolized data packet 305 having a given logical value to the total amount of bits in the symbolized data packet 305 - for example, if there are a total of 264 bits in the symbolized data packet 305 and 64 of those bits have a logical value of 1, the symbolized data packet 305 may have a weight of 25%. If the symbolized data packet includes the same amount of bits having a first logical value as bits having a second logical value, the symbolized data packet 305 may be considered a balanced data packet. If the weight of the symbolized data packet 305 is the target weight (e.g.,

Number

Number

[0060] The encoded data packet 305 may be divided (virtually or physically) into a plurality of segments 310. In some cases, the encoded data packet 305 is divided into r segments 310. In some cases, each segment 310 may contain n bits. In other cases, each segment 310 may contain various numbers of bits. The weight may be assigned to the segment 310 based on the amount of bits contained in the segment 310 having a given logical value (e.g., logical value 1). In some cases, each segment 310 may be associated with a unique index. In some embodiments, the index may be assigned to the segment 310 in the order of appearance. For example, until segment 310-r can be associated with index r, segment 310-a may be associated with index 1, segment 310-b may be associated with index 2, and so on - for example, this can be represented as {1,2,3,4,5,6,7,8} when r = 8. In other embodiments, the index may be assigned to the segment 310 with the order of appearance scrambled. For example, until segment 310-r can be associated with index 4, segment 310-a may be associated with index 3, segment 310-b may be associated with index 1, and so on - for example, this can be represented as {3,1,2,7,5,6,8,4} when r = 8. In either case, the index need not be repeated more than once.

[0061] Segment 310 of the symbolized data packet 305 may correspond to a segment of the received data packet. To obtain the symbolized data packet 305, the weights of a set of possible symbolized data packets (including the symbolized data packet 305) can be calculated by sequentially accumulating the inversions of the corresponding segments of the received data packet. The sequential cumulative inversion of the corresponding segments involves calculating the weight for the unchanged version of the data packet, the weight for the version of the data packet when the first segment associated with the first index is inverted, the weight for the version of the data packet when the first segment and the second segment associated with the second index are inverted, and so on, until a weight that satisfies the target weight range is obtained.

[0062] The encoded segment 325 may include a certain amount of encoded bits that collectively indicate which segments 310 of the symbolized data packet 305 are inverted as a result of the encoding operation performed on the data packet. The amount of encoded bits included in the encoded segment 325 may be derived from the received data packet according to the encoding scheme used to equalize the received data packet, based on the number of combinations of bits that are inverted and bits that are not inverted. For example, if N 2 N combinations are possible, the encoded segment 325 may include log2(2

[0063] In some embodiments, the memory device receives data packets from a host device. Before storing the data packets in the memory array, the memory device may encode the data to obtain an encoded data packet 305, which may be a balanced data packet or another type of constant-weight data packet and may have a weight within a target weight range. To obtain the encoded data packet 305, the weight of a possible encoded version of the data packet may be verified by a segment of the data packet by non-repeating (e.g., sequential) cumulative inversion until the encoded data packet 305 is identified, and the encoded data packet 305 may have a weight equal to or within the target weight range. That is, the memory device may determine a first weight for a first encoded version of the data packet assuming that the segment corresponding to segment 310-a is inverted, and check whether the first weight is within the target weight range. If so, the memory device may invert the segment that results in the encoded data packet 305 having the first segment 310-a inverted and may configure the encoded segment 325 to indicate that the segment 310-a is inverted. The memory device may then store the encoded data packet 305 and the encoded segment 325 in the memory array. Otherwise, the memory device may determine a second weight for a second encoded version of the data packet assuming that the segments corresponding to segment 310-a and segment 310-b are inverted, and check whether the second weight is within the target weight range. If so, the memory device may invert the segment that results in the encoded data packet 305 having the first segment 310-a and the second segment 310-b inverted. Otherwise, the memory device may continue to verify the weights for possible encoded versions of the encoded data packet 305 until a weight within the target weight range is determined.

[0064] In some embodiments, the limits of the target weight range (e.g., lower bound, upper bound, span, or any combination thereof) may be selected to ensure that sequential cumulative inversion of segments of a data packet results in an encoded version of the data packet having a weight within the target weight range (e.g., the target weight range may be equal to the range

Number

[0065] In some cases, the data structure 300 may also include a padding segment 320, which may support obtaining a specific target weight for a set of bits configured according to the data structure 300. The padding segment 320 may include some amount of padding (dummy, filler) bits. When the weight of the encoded data packet 305 satisfies a target weight range (e.g., a weight between 49% and 51% or between 128 and 135), the padding segment 320 may be used to adjust (fine-tune) the combined weight of the encoded data packet 305 and the padding segment 320 to be equal to a specific target weight (e.g., 50%, or an exact weight of 128). The specific target weight may be 50%, a power of 2, or any other weight that supports advanced read techniques or provides other benefits. The padding segment 320 may include any amount of bits, depending on the embodiment. In some cases, the padding segment 320 may include an amount of bits equal to an amount smaller than the span of the target weight range (e.g., when the target range is 128 - 135, the padding segment 320 may include 7 bits, and the span of 128 - 135 is 8 (including all)), but one of ordinary skill in the art will understand that other amounts of bits for the padding segment 320 are possible. In some cases, the span of the target range may be equal to n, and thus the padding segment 320 may include n - 1 bits.

[0066] As an illustrative example, the encoded data packet 305 may include a total of 256 bits and have a target weight range between 121 and 128. Also, the padding segment 310 may include seven bits. After the weight of the encoded data packet 305 is determined to be within the target weight range, one or more of the bits within the padding segment 320 may be inverted to achieve a specific target weight of 128 (e.g., 128 is half of 256 and is a power of two) for the combination of the encoded data packet 305 and the encoded segment 325 using the segment unit encoding scheme described herein. For example, if the encoded data packet 305 has a weight of 122, the padding segment 320 may be configured such that six of the seven bits included in the padding segment 320 have a first logical value (e.g., 1). In this way, the combined weight of the encoded data packet 305 and the padding segment 320 may be equal to 128. It should be understood that this and any other specific numerical examples herein are provided for illustrative clarity only and are not limitations of the claims.

[0067] In some embodiments, the memory device includes an amount of bits within padding segment 320 for the purpose of encoding and decoding the operations described herein to a total amount of bits N'. For example, the encoded data packet 305 may include a total of 256 bits, and the padding segment 320 may include 7 bits to result in a total amount of bits N' of 263 bits. The target weight range of the encoded data packet 305 may be between 124 and 131 such that after the target weight range is achieved, bits from the padding segment 320 can be inverted to achieve a specific target weight of 131 for the combined weight of the encoded data packet 305 and the padding segment 320. In some cases, the encoded bits within the encoding segment 325 and the padding bits within the padding segment 320 may be included in a total amount of bits N''. In such cases, the padding bits may likewise be used to achieve a target weight for the combined weight of the encoded data packet 305, the encoding segment 325, and the padding segment 320 - that is, taking into account the number of bits within the encoding segment 325 having a first logical value.

[0068] FIG. 4 is an inversion diagram 400 that supports data equalization for storage within a memory device, according to an embodiment disclosed herein. The inversion diagram 400 may be an example of an encoding operation (e.g., a series of segment unit inversions) performed on a data packet that results in an encoded data packet 305, where the weight of the encoded data packet is within a target weight range. The inversion diagram 400 can show the weights of different encoded versions of the data packet, where N is shown on the vertical access and r is shown on the horizontal axis. The inversion diagram 400 may show the inversion of segment 310 and the target weight range 445. Additionally, the inversion diagram 400 may show the change in the weight of the page when the memory device inverts a first segment 310-a, a second segment 310-b, a third segment 310-c, etc.

[0069] As described herein, the memory device may perform an encoding operation to obtain an encoded data packet (e.g., encoded data packet 305) having a weight equal to and / or within a target weight range 445 (e.g.,

Number

[0070] The memory device may assign a unique index to each segment 310. In some embodiments, the weight for the encoded version of the data packet may be determined according to a one-by-one inversion of the segments based on the index of each segment. For example, if the data packet is divided into 8 segments 310, the page may be inverted according to a sequential non-repeating index pattern of {1, 2, 3, 4, 5, 6, 7, 8}. Alternatively, a non-repeating index pattern with a scrambled order of {1, 5, 3, 2, 4, 6, 8, 7} may be used as long as the segment 310 is not inverted more than once.

[0071] Additionally, the inverted diagram 400 can show the weights (W) of different encoded versions of the data packet before and after each segment 310 is inverted. For example, weight 425-a can represent the weight of the data packet before the first segment 310-a is inverted. Weight 425-b can represent the weight of the data packet after the first segment 310-a is inverted but before the second segment 310-b is inverted, and so on. Since each (or maximum) segment 310 may contain n bits, the inversion of an individual segment 310 may change the weight of the encoded data packet 305 by some amount within range 440, and the span of range 440 may be equal to 2n. That is, at most, the weight of the page may increase by amount n or decrease by amount n after the inversion of segment 310. For example, if segment 310-a contains 8 bits, the weight 425-a of the data packet may increase by at most 8 (e.g., if all bits within segment 310-a were in logical state 0 before inversion) or decrease by at most 8 (e.g., if all bits of 310-a were in logical state 1 before inversion). Thus, the span of range 440 may be 16 (e.g., equal to 2n). In some embodiments, when the weight of the data packet is

Number

Number

[0072] However, after dividing the data packet into r segments 310 and before performing any inversions, the memory device can calculate an initial weight 425-a of the page and determine whether the initial weight 425-a is within a target weight range 445. If the initial weight 425-a is within the target weight range 445, the memory device stops calculating weights for any combination of inversions. In the embodiment shown in FIG. 4, the initial weight 425-a may be outside the target weight range 445, and thus, the memory device can calculate a weight for the data packet assuming that segment 310-a is inverted, and inverting segment 310-a can change the weight of the data packet from weight 425-a to weight 425-b. FIG. 4 shows weight 425-b near the upper part of the range associated with the first segment 310-a, but weight 425-b may be anywhere within range 440 with respect to the initial weight 425-a.

[0073] After inverting the first segment 310-a, the memory device may calculate the weight 425-b of the modified data packet and determine whether the weight 425-b is within the target weight range 445. Generally, the memory device may determine the weight of different versions of the data packet after each assumed inversion of a subsequent segment 310 and determine whether the target weight range 445 has been achieved. If the weight of the encoded data packet 305 is within the target weight range 445, the memory device may stop determining additional weights for the remaining set of inversion combinations for the data packet. As long as the weight remains outside the target weight range 445, the memory device may continue to calculate additional weights for versions of the data packet having additional inverted segments 310 until the target weight range 445 is achieved, and the additional segments 310 may be determined in sequential order. In this example, the weight 425-b is outside the target weight range 445, and the memory device may therefore continue to calculate additional weights based on the inversion of additional segments 310 in sequential order until a weight 425-f within the target weight range 445 is achieved. In the example of FIG. 4, the weight 425-f is achieved after inverting the fifth segment 310-e of the data packet.

[0074] After identifying a version of the data packet having a weight within the target weight range 445, the memory device may generate an encoded data packet corresponding to the identified version of the data packet. In some cases, the memory device stores a unique index associated with the last inverted segment associated with the identified version of the data packet. For example, if the version of the data packet is identified after inverting a segment having an index of 5, the memory device may set a set of bits in the encoded segment equal to 5. When the memory device later decodes the encoded data packet, the memory device may determine that segments having an index less than or equal to 5 were inverted during the encoding process.

[0075] As described herein, the target weight range 445 may be selected such that performing sequential non-repeating inversions may ensure that a weight within the target weight range 445 is achieved at some point. For example, if each of the segments 310 contains the same amount n of bits, the target weight range 445 may have a span that is the same as or larger than n. As another example, if at least some of the segments 310 contain different amounts of bits, the target weight range 445 may have a span that is the same as or larger than the amount of bits in the largest segment 310. Since the weight of the encoded data packet 305 can increase or decrease below n following the inversion of the segment 310, selecting the target weight range 445 to be the same as or larger than n can ensure that sequential inversion operations will eventually achieve the target weight range 445 when a single inversion operation does not completely bypass the range. In some cases, the target weight range 445 may be based on the following equation.

Number

[0076] Selecting the target weight range 445 to be the same as or larger than n may ensure that sequential non-repeating inversions achieve the target weight range 445 after some amount k of inversions. For example, let w i = W(X i ) be the weight of segment i. When the memory device uses a non-repeating cumulative encoding scheme, there may be r + 1 possible inversion patterns, including an inversion pattern that includes zero inverted segments. Setting Y0 to Y r represents r + 1 possible inversions. That is,

Number

Number

Number

Number

[0077] S i 's weight moves in an amount not greater than n. So when the target weight range 445 is n or greater, non - repetitive (e.g., sequential) cumulative inversion of segments can ensure that the target weight range 445 is satisfied. That is, - n ≤ S k - S k-1 ≤ n. Additionally, the memory device can reduce the latency associated with generating an encoded data packet by calculating the possible weights of the data packet using the weight w i of individual segments. That is, after determining the initial weight of the data packet and the weights of individual segments 310, the memory device uses the formula Sk =S k-1 +n-2w k can be used to calculate all possible weights for data packets (assuming all different inversion patterns), where 0 ≦ k ≦ r in the above formula. The memory device can then determine which of the weights are within the target weight range - for example, the weight of the encoded version of the data packet has the smallest number of inverted segments - and may generate the corresponding encoded data packet.

[0078] In some cases, the memory device may select a target weight range 445 that includes a weight of 50% or N / 2 (for example, to support one or more advanced read techniques). Additionally, if the initial weight 425-a on page 305 is low (as shown in the embodiment of FIG. 4), sequentially inverting segment 310 tends to increase the weight of page 305, but instead if the initial weight 425-a is high (for example, close to or equal to N), sequentially inverting segment 310 tends to decrease the weight of the page. Thus, encoding page 305 as described herein tends towards N / 2 and ultimately falls within a range that includes N / 2 regardless of the initial weight 425-a of page 305. Additionally, in some embodiments, when the initial weight 430 has a value of W, the final weight 435 - for example, the weight of the page when each segment 310 is inverted - may be equal to N - W. Thus, the generalized Knuth algorithm may be symmetric and may start from either the weight 430 or the weight 435.

[0079] As discussed herein, padding segments are for a particular target weight (for example,

Number

[0080] FIG. 5 is an inversion diagram 500 that supports data equalization for storage within a memory device, according to an embodiment disclosed herein. The inversion diagram 500 may be an example of an encoding operation performed on a data packet or page to achieve a target weight or target weight range.

[0081] Segment 510 may be an example of segment 310, weights 525, 530, and 535 may be examples of weights 425, 430, and 435, range 540 may be an example of range 440, and target weight range 545-a may be an example of target weight range 445 (e.g., the target weight range described with reference to FIG. 3).

[0082] As described herein, the memory device may perform an encoding operation to obtain an encoded data packet having a target weight or target weight range (e.g., target weight range 545) before storing the data received within the data packet. The memory device may perform the encoding operation by dividing the page into r segments having n bits and determining weights for different inversion patterns derived according to a non-repeating cumulative sequence.

[0083] In some embodiments, the initial target weight range 545-a may be shifted relative to the embodiment shown in FIG. 4. For example, the initial target weight range 545-a may still be

Number

Number

Number

Number

Number

Number

Number

[0084] In some cases, the memory device can be configured to use any of a set of supported target weight ranges 545 (e.g., based on fuse settings or mode register settings). In some embodiments, the value of m may be stored in a register within the memory device, and the memory device may offset an initial target weight range 545-a according to the stored value. In other cases, the memory device may be configured to select a different value for m - e.g., based on a configured operating mode, the operating lifetime of the memory device, etc.

[0085] FIG. 6 shows a memory device 600 that supports data equalization for storage within a memory device, according to an embodiment disclosed herein. The memory device 600 can perform aspects of an encoding operation to achieve a target weight or target weight range, as described herein. The memory device 600 can also perform aspects of a decoding operation, as described herein. The memory device 600 may include an encoding circuit 605, which may be an embodiment of the data encoder 265 described with reference to FIG. 2, and may include a weight evaluation circuit 615, an inversion circuit 620-a, and an index encoder 625. The memory device 600 may also include a decoding circuit 610, which may be an embodiment of the data decoder 270 described with reference to FIG. 2, and may include an index decoder 630 and an inversion circuit 620-b. In some embodiments, the encoding circuit 605 and the decoding circuit 610 may share the inversion circuit 620. Additionally, the memory device 600 may include a memory array 670, which may be an embodiment of the memory array 170 described with reference to FIG. 1.

[0086] The locations of the encoding circuit 605 and the decoding circuit 610 may be based on the location of the error correction circuit used for the memory array 670. For example, the encoding circuit 605 and the decoding circuit 610 may be disposed on the same die as the memory array 670 - for example, when the error correction circuit is disposed on the same die as the memory array 670. Or, the encoding circuit 605 and the decoding circuit 610 may be external to the die including the memory array 670 - for example, when the error correction circuit is not disposed on the same die as the memory array 670. For example, the locations of the encoding circuit 605 and the decoding circuit 610 may be selected such that encoding by the encoding circuit 605 is performed before write-side error correction and decoding by the decoding circuit 610 is performed after read-side error correction.

[0087] In some embodiments, the encoding circuit 605 may receive data from a host device (e.g., host device 105) for storage in the memory array 670. In some embodiments, the data may be included in data packets that are divided into r segments. In other embodiments, the encoding circuit 605 may divide a page into r segments. As described herein, each bit in a data packet can have a given logical state (e.g., logical state 1 or 0). The weight evaluation circuit 615 can determine the weight of the data packet - either upon reception or after the segments of the data packet are inverted - and calculate whether the weight is within a target weight range or equal to a target weight as described herein.

[0088] In some embodiments, the weight evaluation circuit 615 may first calculate all weights of invertibility. For example, a page may be divided into 8 segments, and the weight evaluation circuit 615 may calculate the initial weight of the page, the weight of the page after inverting the first segment, the weight of the page after inverting the first and second segments, etc. until it calculates the weight of inverting all 8 segments. The weight evaluation circuit 615 may then determine which possible combination of inversions is the first possible combination to achieve the target weight range (for example, inverting segments 1 to 5). The weight evaluation circuit 615 may then send a command indicating which segments should be inverted to the inversion circuit 620-a.

[0089] In some cases, after identifying that the version of the data packet associated with the inversion pattern satisfies the target weight range, the weight evaluation circuit 615 may use the padding segment 320 - for example, by setting one or more bits in the padding segment 320 to a given logical value - to equalize the combined weight of the identified version of the data packet and the padding segment to a specific target weight. For example, the weight evaluation circuit 615 may determine the difference between the weight of the identified versions of the data packet, and the specific target weight is equal to the value 2. The weight evaluation circuit 615 may then configure the padding segment such that two bits in the padding segment 320 have a given logical value (for example, 1) - the remaining bits in the padding segment 320 may have another logical value (for example, 0).

[0090] As described herein, the index encoder 625 may generate an encoded segment 325 that includes an index signature (value) associated with the last segment inverted by the inverter circuit 620-a (if any), which led to the page weight being within the target weight range. When applicable, the signature generated by the index decoder 630 may indicate that the segment was not inverted.

[0091] After the encoding circuit 605 encodes data to achieve a target weight range or target weight, the encoding circuit 605 may send the encoded data packet, encoded bits, and / or padding bits to the memory array 670. The memory array 670 may store the data in memory cells within the memory array 670.

[0092] In some embodiments, the memory device 600 may output data to the host device based on a read request sent by the host device. The memory array 670 may output an encoded version of the data to the decoding circuit 610 in response to a request sent by the host device. The index decoder 630 may decode a flag stored within the encoded segment to determine which segments were inverted. For example, the index decoder 630 may decode the flag and determine that the first five of eight segments were inverted. The index decoder 630 may then send the decoded flag to the inversion circuit 620-b. The inversion circuit 620-b may then re-invert (and thereby de-invert) the segments that were inverted during the encoding process (e.g., segments 1-5). The memory device 600 may then send the decoded data packet (e.g., the originally received data packet) to the host device. In some embodiments, the memory device 600 may directly send an encoded data packet (e.g., stored within the memory array 670 and having a weight within or equal to a target weight range) to the host device or another external device, along with a flag of the last segment that was inverted (or that no segments were inverted), and an index decoder and / or inversion circuit located at the host may be used to read the encoded data packet.

[0093] FIG. 7 is a diagram illustrating the operation of an encoder 700 that supports data equalization for storage within a memory device, according to an embodiment disclosed herein. The encoder 700 may be, for example, an embodiment of the encoding circuit 605 described with reference to FIG. 6. For example, the weight evaluation circuit 715 may be an embodiment of the weight evaluation circuit 615, the inversion circuit 720 may be an embodiment of the inversion circuit 620, and the memory array 770 may be an embodiment of the memory array 170 and / or the memory array 670 described with reference to FIGS. 1 and 6. Additionally, the weight evaluation circuit 715 may include a weight counter 725, an inverter calculator 735, and a range identifier 745.

[0094] Encoder 700 may receive data packet 705-a transmitted by a host device and encode the data so that a target weight or target weight range is achieved. In some embodiments, encoder 700 may (e.g., virtually or physically) divide data packet 705-a into segments 710-a through 710-h that become data packet 705-b. In other embodiments, the encoder may receive data packet 705-b - for example, the host device may send data packet 705-b as already divided into segments 710-a through 710-h as described herein and with reference to FIG. 6.

[0095] Data packet 705-b may be sent to weight evaluation circuit 715 and weight counter 725. Weight counter 725 may calculate the weight of each segment 710 - for example, the weight of segment 730-a may be the weight associated with segment 710-a, and the weight of segment 730-h may be the weight associated with segment 710-h. Weight counter 725 may also calculate the weight of data packet 705-b. Weight counter 725 may then send the weights of segments 730 to inverter calculator 735.

[0096] The inverter computer 735 can calculate the calculated weights 740 associated with each invertibility for the data packet 705-b. That is, if there are 8 segments in the data packet 705-b, there can be 8 different invertibilities - for example, until all 8 segments are inverted, only the first segment is inverted, the first segment and the second segment are inverted, and so on. The calculated weight 740-a can be the weight associated with the first invertibility (for example, only the first segment is inverted), and the calculated weight 740-h can be the weight associated with the last invertibility (for example, all 8 segments are inverted). Thus, the inverter computer 735 can calculate the weight associated with each possibility and send that information to the range identifier 745.

[0097] Before receiving information from the inverter computer 735, the range identifier 745 may be configured with a target weight range or a target weight. In some cases, the target weight may be equal to N / 2 or a power of 2. In some cases, the target weight range may be configured to ensure that a non-repeating inversion operation is guaranteed to achieve the range. After receiving information from the inverter computer 735 and / or the weight evaluation circuit 715, the range identifier 745 can determine whether any of the calculated weights 740 are within the target weight range or satisfy the target weight. That is, the range identifier 745 can first check whether the data packet 705-b is within the range, then whether the calculated weight 740-a is within the range, and then whether the calculated weight 740-b is within the range (for example, the possibility of inverting the first segment and the second segment), and so on.

[0098] The range identifier 745 can then determine which possibility is the first to achieve the target weight or target weight range. For example, the range identifier 745 may determine that inverting the first five segments 710, as described herein with reference to FIG. 4, may achieve the target weight range. The range identifier 745 may then send information regarding the first possibility (e.g., inverting the first five segments) to the inversion circuit 720. In some cases, the range identifier 745 sends an index associated with the fifth segment to indicate that when the first five segments are inverted, the weight of the encoded data packet falls within the target weight range. The inversion circuit 720 can then invert the segment, as described herein with reference to FIG. 4.

[0099] The inversion circuit 720 can also append to the encoded data packet an indicator of the index associated with the last segment inverted (e.g., the fifth segment), or an indicator that the segment was not inverted. The memory device can store the indicator within the encoded segment, as described herein with reference to FIGS. 3 and 4. The inversion circuit 720 can store the index in binary format such that [log2r] bits are required to store the index within the encoded segment to encapsulate all inversion possibilities. Additionally, the value of index i can be between 1 and r + 1 or between 0 and r. For example, if a page is divided into seven segments, r = 7, and the formula [log2(r + 1)] calculates that the memory device requires 3 bits to uniquely identify each of the indices along with the possibility that the segment was not inverted.

[0100] For example, when a page is divided into seven segments and 3 bits are used to store information, the following table (e.g., Table 1) can be an example of how each index is represented. [Table 1]

[0101] The variables i1, i2, and i3 can represent binary values associated with the index i, where i1 can represent the most significant bit. For example, when none of the segments are inverted, the index bits i1, i2, and i3 may all have a value of 0. When the first segment is inverted, the index bits i1 and i2 may have a value of 0, and the index bit i3 may have a value of 1. When the first and second segments are inverted, the index bits i1 and i3 may have a value of 0, and the index bit i2 may have a value of 1, and so on. The inversion circuit 720 can then send the encoded data and the encoded bits (e.g., the index) to the memory array 770, as described herein with reference to FIG. 6. In some embodiments, the encoder 700 may be included in the memory array 770.

[0102] FIG. 8 is a diagram illustrating an embodiment of a decoder 800 that supports data balancing for storage within a memory device, according to an embodiment disclosed herein. The decoder 800 may include aspects of the decoding circuit 610 described with reference to FIG. 6, or may be an embodiment thereof. The decoder 800 may receive index bits 810-a, index bits 810-b, and index bits 810-c (e.g., the index bits i1, i2, and i3 described with reference to FIG. 7). The decoder 800 may include an index decoder 825 (e.g., an embodiment of the index decoder 630 described with reference to FIG. 6) and may generate inversion signals 815. The index decoder 825 may also generate outputs 820 associated with each inversion signal 815 - for example, output 820-e may be associated with inversion signal 815-e.

[0103] As described with reference to FIGS. 3 through 7 herein, the memory device may encode data received from a host device (e.g., host device 105) before storing the data in the memory array. That is, the memory device may implement a generalized Knuth algorithm and select a target weight or target weight range such that performing a non-repeating inversion may guarantee that the target weight or target weight range is achieved. The memory device may also store an indication of the segment that was last inverted or an indication that the segment was not inverted before the target weight or target weight range was achieved, and the indication may include index bits i1, i2, and i3. As described with reference to FIG. 6 herein, the memory device may also receive a read command from the host device and may decode the encoded data before outputting the data to the host device. The memory device may use a decoder 800 to decode the data.

[0104] As described with reference to FIG. 7 herein, the memory device may store an index associated with the segment that was last inverted before a target weight range is achieved using an encoded data packet - e.g., by indexing the end of the data packet. For example, when a page (e.g., a data packet received from the host) is split into seven segments, the memory device may store three index bits within the encoded segment. In other embodiments, the memory device may use a different amount of bits to represent the index based on the amount of segments and amount r.

[0105] In this embodiment, a page may be divided into seven segments and a label may be stored using three index bits. As described herein with reference to FIG. 6 (e.g., index decoder 630), index decoder 825 may receive index bits 810 and decode them such that an encoded version of the data results in the originally received page being modifiable. Index bits 810 may have values shown in Table 1 with reference to FIG. 7. In some embodiments, index decoder 825 may be an AND gate that combines index bits 810 to produce an output 820 that passes through some OR gates that produce inversion signals 815. Each inversion signal 815 may indicate whether the corresponding segment needs to be inverted or is not part of the decoding operation - for example, when inversion signal 815-a signals a logical value of 1, inversion signal 815-a may indicate that the first segment should be inverted, and when inversion signal 815-b signals a logical value of 1, inversion signal 815-b may indicate that the second segment should be inverted, and so on. When a segment is not inverted during the encoding phase, each output 820 of index decoder 825 may signal a logical value of 0, and each inversion signal 815 produced by the decoder may signal a logical value of 0.

[0106] In another embodiment, when the fifth segment is the last segment to be inverted, as described with reference to FIG. 7, index bit 810-a may have a value of 1, and index bits 810-b and 810-c may have a value of 0. Index decoder 825 may generate output 820-e by obtaining the AND value of index bit 810-a, inverted index bit 810-b, and inverted index bit 810-c, and thus, output 820-e may represent a logical value of 1. The other outputs 820 may be generated and output such that they all represent a logical value of 0. This may generate a logical value of 1 with inversion signal 815-e via an OR gate connected to output 820-e. When the output in inversion signal 815-e is 1, the values of inversion signals 815-a to 815-d may also be logical value 1 based on the OR gate embodiment. Since the logical values are 0 for the other outputs 820, the values of inversion signals 815-f and 815-g may also be logical value 0. Thus, decoder 800 may generate a signal indicating that the first segment to the fifth segment of the data packet should be inverted. Using a similar approach to decode all other possible index bits 810, the following table (e.g., Table 2) may be an example of how each inversion signal 815 is calculated.

Table 2

[0107] The inverted values of each index are

Number

Number

Number

[0108] FIG. 9 is a diagram showing a block diagram 900 of a memory device 905 that supports data balancing for storage within a memory device, according to an embodiment disclosed herein. The memory device 905 may be an embodiment of the aspects of the memory device described with reference to FIGS. 1-8. The memory device 905 may include a bit identifier component 910, a bit evaluation component 915, an inversion component 920, a range identifier component 925, an inversion manager 930, a storage component 935, a data output component 940, an index component 945, a target weight component 950, a decoding component 955, and a segment component 960. Each of these modules can communicate with each other, directly or indirectly (for example, via one or more buses).

[0109] The bit identifier component 910 can receive data that includes a set of bits and is divided into a set of segments in a device including a memory array, each bit of the set of bits has one of a first value or a second value, and a set of indexes is assigned to the set of segments. In some embodiments, receive data that includes a set of bits and is divided into a set of segments for storage within a memory array, each bit of the set of bits has a first value or a second value, and a set of indexes is assigned to the set of segments.

[0110] The bit evaluation component 915 can determine that the data includes a first amount of bits having a first value, and this first amount of bits is outside a range based on the amount of bits in the set of bits and the amount of segments in the set of segments. In some embodiments, a bit evaluation component that determines that the data includes an initial amount of bits having a first value. In some cases, the bit evaluation component 915 may determine that the data includes respective amounts of bits having a first value after each inversion of one segment of the set of segments. In some examples, the bit evaluation component 915 may determine the initial amount of bits having a first value based on counting each bit having a first value within the set of bits.

[0111] The inversion component 920 can invert the first segment of the set of segments according to the set of indexes based on the fact that the first amount of bits is outside the range, and the data includes the second amount of bits having the first value after the first segment is inverted. In some embodiments, based on the initial amount being outside the range, until the data includes the adjusted set of bits including the adjusted amount of bits having the first value according to the set of indexes, one segment of the set of segments is inverted at a time, and this adjusted amount of bits is within the range. In some cases, based on the third amount of bits being outside the range, the third segment of the set of segments is inverted according to the set of indexes, and the data includes the fourth amount of bits having the first value after the third segment is inverted, and the fourth amount of bits is within the range.

[0112] The range identifier component 925 can determine that the second amount of bits is outside the range. In some embodiments, the range identifier component 925 may determine that the initial amount of bits is outside the range based on the amount of bits in the set of bits and the amount of segments in the set of segments. In some cases, determining that the third amount of bits is within the range, the data includes the third set of bits after the second segment is inverted. In some examples, determining that the third amount of bits is within the range, the data includes the third set of bits after the second segment is inverted. In some embodiments, determining that the third amount of bits is outside the range, the data includes the third set of bits after the second segment is inverted. In some cases, the range identifier component 925 may configure the span of the range to ensure that inverting at least a subset of the set of segments results in the data including the adjusted amount of bits having the first value within the range. In some examples, the limits of the range are shifted, and the range includes a value equal to half of the amount of bits in the set of bits based on the shift.

[0113] In some embodiments, the range identifier component 925 may compare the amount of each bit with a range after each inversion of one segment of a set of segments, and subsequent segments of the set of segments are inverted based on the amount of each bit being outside the range. In some embodiments, the range identifier component 925 may determine the span of the range based on the amount of bits included in each segment of the set of segments, and inverting the set of segments according to the set of indices results in an adjusted amount of bits being within the range based on the span of the range. In some cases, the range is shifted, and the shifted range includes a value equal to half the amount of bits within the set of bits based on which the shift is made. In some examples, the span of the range is based on the amount of bits included in each segment of the set of segments. In some embodiments, the upper limit of the range is based on the amount of bits within the set of bits and the amount of segments within the set of segments.

[0114] The inversion manager 930 may invert a second segment of the set of segments according to the set of indices based on the second amount of bits being outside the range, and the data includes a third amount of bits having a first value after the second segment is inverted.

[0115] The memory component 935 may write the adjusted set of bits to the memory array based on the adjusted amount of bits being within the range. In some embodiments, the memory component 935 may store a third set of bits within the memory array based on the third amount being within the range. In some cases, the memory component 935 may receive a data request. In some examples, the memory component 935 may receive a data request.

[0116] Based on a request, the data output component 940 may output a third set of bits and a value corresponding to an index for the second segment from the memory array. In some embodiments, the data output component 940 may output a set of bits from the device in response to a request for data. In some cases, the data output component 940 may output an adjusted set of bits and an index identifier for the last inverted segment from the memory array based on a request. In some examples, the data output component 940 may output a set of bits from a device including the memory array in response to a request for data.

[0117] The index component 945 may store a value corresponding to an index for the second segment within the memory array.

[0118] In some embodiments, the index component 945 may identify a value corresponding to an index for the second segment based on an output. In some cases, the index component 945 may store an index identifier for the last inverted segment within the memory array based on an adjusted amount of bits being within a range. In some examples, the index component 945 may order the indexes such that the order may include a sequential ordering of a set of indexes including a single instance of each index of the set of indexes or a non - sequential ordering of a set of indexes including a single instance of each index of the set of indexes. In some cases, inverting is performed according to an ordering of a set of indexes, which includes a single instance of each index of the set of indexes.

[0119] The target weight component 950 can determine the difference between the target amount of bits and the third amount of bits based on the third amount of bits being within a range, where the target amount of bits is equal to half the amount of bits in the set of bits. In some embodiments, based on the difference between the target amount of bits and the third amount of bits, the amount of bits in the third segment having a first value is increased or decreased, and the data includes the target amount of bits having the first value based on the increase or decrease.

[0120] The decoding component 955 can invert the first segment and the second segment to obtain a set of bits based on a value for a third set of bits. In some embodiments, the decoding component 955 may invert each of one or more additional segments each having an index between the index for the first segment and the index for the second segment according to the order of the set of indexes, and the set of bits is obtained based on inverting the one or more additional segments. In some cases, the decoding component 955 may invert each segment of a set of segments having an index that matches or is earlier than the index for the last inverted segment according to the order of the set of indexes for an adjusted set of bits, and the set of bits is obtained based on the inversion.

[0121] The segment component 960 can determine the amount of segments in a set of segments. In some embodiments, the segment component 960 can divide data into a set of segments based on the amount of segments in the set of segments.

[0122] FIG. 10 is a flowchart showing one or more methods 1000 for supporting data balancing for storage within a memory device according to an aspect of the present disclosure. The operations of method 1000 may be performed by the memory device or components thereof described herein. For example, the operations of method 1000 may be executed by the memory device described with reference to FIG. 9. In some embodiments, the memory device may execute a set of instructions that control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use special purpose hardware to perform aspects of the described functions.

[0123] At 1005, the memory device can receive data that includes a set of bits and is divided into a set of segments in a device that includes a memory array, where each bit of the set of bits has one of a first value or a second value, and a set of indexes is assigned to the set of segments. The operation of 1005 may be performed by the methods described herein. In some embodiments, aspects of the operation of 1005 may be performed by the bit identifier component described with reference to FIG. 9.

[0124] At 1010, the memory device can determine that the data includes a first amount of bits having a first value, where the first amount of bits is outside a range based on the amount of bits in the set of bits and the amount of segments in the set of segments. The operation of 1010 may be performed by the methods described herein. In some embodiments, aspects of the operation of 1010 may be performed by the bit evaluation component described with reference to FIG. 9.

[0125] In 1015, the memory device can invert the first segment of the set of segments according to the set of indexes based on the fact that the first amount of bits is outside the range, and the data includes the second amount of bits having the first value after the first segment is inverted. The operation of 1015 may be performed by the method described herein. In some embodiments, the manner of operation of 1015 may be performed by the inversion component described with reference to FIG. 9.

[0126] In 1020, the memory device can determine that the second amount of bits is outside the range. The operation of 1020 may be performed by the method described herein. In some embodiments, the manner of operation of 1020 may be performed by the range identifier component described with reference to FIG. 9.

[0127] In 1025, the memory device can invert the second segment of the set of segments according to the set of indexes based on the fact that the second amount of bits is outside the range, and the data includes the third amount of bits having the first value after the second segment is inverted. The operation of 1025 may be performed by the method described herein. In some embodiments, the manner of operation of 1025 may be performed by the inversion manager described with reference to FIG. 9.

[0128] In some embodiments, the apparatus described herein may execute one or more methods, such as method 1000. The apparatus may be a device including a memory array, and may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving data including a set of bits that is divided into a set of segments, where each bit of the set of bits has one of a first value or a second value, and a set of indices is assigned to the set of segments. The apparatus may include features, means, or instructions for determining that the data includes a first amount of bits having the first value, where the first amount of bits is outside a range based on the amount of bits in the set of bits and the amount of segments in the set of segments, and for inverting a first segment of the set of segments according to the set of indices based on the first amount of bits being outside the range, where the data includes a second amount of bits having the first value after the first segment is inverted. The apparatus may further include features, means, or instructions for determining that the second amount of bits is outside the range, and for inverting a second segment of the set of segments according to the set of indices based on the second amount of bits being outside the range, where the data includes a third amount of bits having the first value after the second segment is inverted.

[0129] Some embodiments of method 1000 and the apparatus described herein may further include operations, features, means, or instructions for determining that the third amount of bits may be within the range, where the data includes a third set of bits after the second segment may be inverted, and for storing the third set of bits in the memory array based on the third amount being within the range.

[0130] In some cases of method 1000 and the apparatuses described herein, it may further include operations, features, means, or instructions for storing in a memory array a value corresponding to an index for a second segment, receiving a data request, and based on this request, outputting from the memory array a value corresponding to an index for a third set of bits and the second segment.

[0131] Some examples of method 1000 and the apparatuses described herein may further include operations, features, means, or instructions for identifying, based on outputting, a value corresponding to an index for a second segment, for a third set of bits, inverting a first segment and a second segment based on the value to obtain a set of bits, and outputting the set of bits from a device in response to a data request.

[0132] Some embodiments of method 1000 and the apparatuses described herein may further include operations, features, means, or instructions for inverting each of one or more additional segments each having a respective index that may be between an index for a first segment and an index for a second segment in accordance with an order of a set of indexes, wherein the set of bits may be obtained based on inverting the one or more additional segments.

[0133] In some cases of method 1000 and the apparatuses described herein, the third segment of the set of segments may be a padding bit or may include this, and the method or apparatus is to determine that the third amount of bits can be within a range, where the data includes the third set of bits after the second segment can be inverted, and based on the third amount of bits being within the range, to determine the difference between the target amount of bits and the third amount of bits, where the target amount of bits is equal to half of the amount of bits within the set of bits, and based on the difference between the target amount of bits and the third amount of bits, to increase or decrease the amount of bits within the third segment having a first value, where the data includes the target amount of bits having a first value based on the increase or decrease, and may further include operations, features, means, or instructions for the increase or decrease.

[0134] Some examples of method 1000 and the apparatuses described herein are to determine that the third amount of bits is outside the range, where the data includes the third set of bits after the second segment can be inverted, and based on the third amount of bits being outside the range, to invert the third segment of the set of segments according to the set of indexes, where the data includes the fourth amount of bits having a first value after the third segment can be inverted, and this fourth amount of bits is within the range, and may further include operations, features, means, or instructions for the inversion.

[0135] In some embodiments of method 1000 and the apparatuses described herein, the inversion may be performed according to the ordering of a plurality of indexes, and this ordering may be a consecutive ordering of the set of indexes including a single instance of each index of the set of indexes, or the ordering may be a non - consecutive ordering of the set of indexes including a single instance of each index of the set of indexes.

[0136] In some cases of method 1000 and the devices described herein, in order to ensure that inverting at least a subset of a set of segments results in data that includes an adjusted amount of bits having a first value within a range, operations, features, means, or instructions for configuring the span of the range may further be included.

[0137] In some examples of method 1000 and the devices described herein, the span of the range may be based on the amount of bits included in each segment of the set of segments.

[0138] Some embodiments of method 1000 and the devices described herein are to shift the limits of the range, and this range may further include operations, features, means, or instructions for shifting, which includes a value equal to half the amount of bits in the set of bits based on the shifting.

[0139] FIG. 11 shows a flowchart illustrating one or more methods 1100 for supporting data balancing for storage within a memory device, according to aspects of the present disclosure. The operations of method 1100 may be performed by the memory device or components thereof described herein. For example, the operations of method 1100 may be executed by the memory device described with reference to FIG. 9. In some embodiments, the memory device may execute a set of instructions that control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use special-purpose hardware to perform aspects of the described functions.

[0140] In 1105, the memory device can receive data, which includes a set of bits and is divided into a set of segments, for storage in the memory array. Each bit in the set of bits has a first value or a second value, and a set of indexes is assigned to the set of segments. The operation of 1105 may be performed by the methods described herein. In some embodiments, the operation mode of 1105 may be performed by the bit identifier component described with reference to FIG. 9.

[0141] In 1110, the memory device may determine that the data includes an initial amount of bits having a first value. The operation of 1110 may be performed by the methods described herein. In some embodiments, the operation mode of 1110 may be performed by the bit evaluation component described with reference to FIG. 9.

[0142] In 1115, the memory device may determine that the initial amount of bits is outside the range based on the amount of bits in the set of bits and the amount of segments in the set of segments. The operation of 1115 may be performed by the methods described herein. In some embodiments, the operation mode of 1115 may be performed by the range identifier component described with reference to FIG. 9.

[0143] In 1120, according to the set of indexes, the memory device can invert one segment of the set of segments at a time based on the fact that the initial amount is outside the range until the data includes an adjusted set of bits that includes an adjusted amount of bits having a first value, and this adjusted amount of bits is within the range. The operation of 1120 may be performed by the methods described herein. In some embodiments, the operation mode of 1120 may be performed by the inversion component described with reference to FIG. 9.

[0144] At 1125, the memory device may write an adjusted set of bits to the memory array based on the adjusted amount of bits being within a range. The operation of 1125 may be performed by the methods described herein. In some embodiments, aspects of the operation of 1125 may be performed by the storage component described with reference to FIG. 9.

[0145] In some embodiments, the apparatus described herein may perform one or more methods such as method 1100. The apparatus includes a set of bits and receives data divided into a set of segments for storage within a memory array, where each bit of the set of bits has a first value or a second value and a set of indices is assigned to the set of segments, and may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving. The apparatus determines that the data includes an initial amount of bits having the first value, determines that the initial amount of bits is outside a range based on the amount of bits in the set of bits and the amount of segments in the set of segments, and based on the initial amount being outside the range, reverses one segment of the set of segments at a time according to the set of indices until the data includes an adjusted set of bits including an adjusted amount of bits having the first value, where the adjusted amount of bits is within the range, and may further include features, means, or instructions for writing the adjusted set of bits to the memory array based on the adjusted amount of bits being within the range.

[0146] Some embodiments of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for determining, after each inversion of one segment of a set of segments, that the data includes a respective amount of bits having a first value, and for comparing, after each inversion of one segment of a set of segments, the respective amount of bits to a range, wherein a subsequent segment of the set of segments is inverted based on the respective amount of bits being outside the range.

[0147] In some cases of method 1100 and the apparatus described herein, storing an index label for the last inverted segment based on an adjusted amount of bits being within a range in a memory array, receiving a data request, and outputting from the memory array an adjusted set of bits and the index label for the last inverted segment based on the request may further be included.

[0148] Some examples of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for inverting each segment of a set of segments having respective indices that match or precede the index for the last inverted segment, in order of the set of indices, for an adjusted set of bits, wherein the set of bits may be obtained based on the inverting, and for outputting the set of bits in response to a data request from a device including the memory array.

[0149] Some embodiments of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for determining a span of a range based on an amount of bits included in each segment of a set of segments, wherein inverting the set of segments according to a set of indices results in an adjusted amount of bits being within the range based on the span of the range.

[0150] In some cases of method 1100 and the apparatus described herein, an upper limit of a range may be based on an amount of bits in a set of bits and an amount of segments in a set of segments.

[0151] Some examples of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for shifting a range, wherein the shifted range includes a value equal to half of an amount of bits in a set of bits based on the shifting.

[0152] Some embodiments of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for determining an initial amount of bits having a first value based on counting, wherein within a set of bits, each bit has the first value.

[0153] In some cases of method 1100 and the apparatus described herein, the inverting may be performed according to an ordering of a set of indices, and the ordering includes a single instance of each index of the set of indices.

[0154] Some examples of method 1100 and the apparatus described herein may further include operations, features, means, or instructions for determining an amount of segments in a set of segments and for dividing data into the set of segments based on the amount of segments in the set of segments.

[0155] The methods described above illustrate possible embodiments, and it should be noted that the operations and steps may be rearranged or modified, and other embodiments are possible. Moreover, portions from two or more of the methods may be combined.

[0156] An apparatus is described. The apparatus may include a memory array and a memory controller coupled to the memory array. The memory controller is to cause the apparatus to receive data including a set of bits divided into a set of segments, each bit of the set of bits having one of a first value or a second value, and an index set assigned to the set of segments; determine that the data includes a first amount of bits having the first value, the first amount of bits being outside a range based on an amount of bits in the set of bits and an amount of segments in the set of segments; invert a first segment of the set of segments according to the index set based on the first amount of bits being outside the range, the data including a second amount of bits having the first value after the first segment is inverted; determine that the second amount of bits is outside the range; invert a second segment of the set of segments according to the index set based on the second amount of bits being outside the range, the data including a third amount of bits having the first value after the second segment is inverted; and be operable to cause the inversion to be performed.

[0157] In some embodiments, the memory controller is further configured to cause the apparatus to determine that a third amount of bits is within the range and store the data in the memory array based on the third amount of bits being within the range, the data including a third set of bits after the second segment is inverted.

[0158] In some embodiments, the memory controller may further be configured to cause the device to store in the memory array a value corresponding to an index for a second segment, receive a data request, and based on this request, output a value corresponding to a third set of bits and an index for the second segment.

[0159] In some embodiments, the memory controller may further be configured to cause the device to determine that a third amount of bits is outside a range, where the data includes a third set of bits after the second segment is inverted, and based on the third amount of bits being outside the range, invert a third segment of a set of segments according to a set of indexes, where the data includes a fourth amount of bits having a first value after the third segment is inverted and the fourth amount of bits is within the range.

[0160] A device is described. The device may include a memory array and a memory controller coupled to the memory array. The memory controller may be operable to cause the device to receive data including a set of bits and divided into a set of segments for storage in the memory array, where each bit of the set of bits has one of a first value or a second value and a set of indexes is assigned to the set of segments, determine that the data includes an initial amount of bits having the first value, determine that the initial amount of bits is outside a range based on the amount of bits in the set of bits and the amount of segments in the set of segments, and based on the initial amount of bits being outside the range, invert one segment of the set of segments at a time according to the set of indexes until the data includes an adjusted set of bits including an adjusted amount of bits having the first value, where the adjusted amount of bits is within the range, and based on the adjusted amount of bits being within the range, write the adjusted set of bits to the memory array.

[0161] In some embodiments, the memory controller causes the device to determine that after each inversion of one segment of the set of segments, the data includes a respective amount of bits having a first value, and to compare the respective amount of bits with a range after each inversion of one segment of the set of segments, wherein a subsequent segment of the set of segments can be inverted based on the respective amount of bits being outside the range.

[0162] In some embodiments, the memory controller further configures the device to store an index identifier assigned to the last inverted segment based on the adjusted amount of bits being within a range in the memory array, receive a data request, and output an adjusted set of bits and the index identifier based on the request.

[0163] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced through the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Although some of the figures may show a signal as a single signal, those skilled in the art will appreciate that the signal can represent a bus of signals, and the bus can have various bit widths.

[0164] The terms "electronically communicating", "in conductive contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electronically communicating with each other (or in conductive contact or connected or coupled) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given point in time, the conductive path between components that are electronically communicating with each other (or in conductive contact or connected or coupled) can be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between connected components can be a direct conductive path between the components, or alternatively, the conductive path between connected components can be an indirect conductive path that includes intermediate components such as switches, transistors, or other components. In some embodiments, the flow of signals between connected components can be temporarily interrupted using one or more intermediate components such as switches or transistors.

[0165] The term "coupled" refers to a state of transition from an open circuit relationship between components, where signals cannot currently communicate between the components via a conductive path, to a closed circuit relationship between the components, where signals can communicate between the components via a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not allow signals to flow.

[0166] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that causes signals not to flow between the components using a conductive path that previously allowed signals to flow.

[0167] Devices including the memory arrays discussed in this specification can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some embodiments, the substrate is a semiconductor wafer. In other embodiments, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a sub-region of the substrate, can be controlled via doping using various species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0168] The switching components or transistors discussed in this specification can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements via a conductive material, such as metal. The source and drain can be conductive and can include highly doped, for example, degenerate semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. When the channel is n-type (i.e., the majority carriers are electrons), the FET can be called an n-type FET. When the channel is p-type (i.e., the majority carriers are holes), the FET can be called a p-type FET. The channel can be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can result in the channel becoming conductive. The transistor will turn “on” or be “activated” when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. The transistor will turn “off” or be “deactivated” when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

[0169] The description set forth herein in connection with the accompanying drawings is illustrative of exemplary configurations and does not represent all examples that are implementable or within the scope of the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration” and does not mean “preferred” or “advantageous over other examples.” The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0170] In the accompanying drawings, like components or mechanisms can have the same reference labels. Further, various components of the same type can be distinguished by attaching a dash followed by a second label that distinguishes within like components after the reference label. If only the first reference label is used in the specification, the description may apply to any one of the like components having the same first reference label, regardless of the second reference label.

[0171] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0172] The various exemplary blocks and modules described in connection with the disclosure herein can be implemented or executed by a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors associated with a DSP core, or any other such configuration).

[0173] The functions described herein may be implemented in hardware, software executable by a processor, firmware, or any combination thereof. When implemented within software executed by a processor, the functions can be stored or transmitted as one or more instructions or code on a computer-readable medium. Other examples and embodiments are included in the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanisms implementing the functions may be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein, including in the claims, the "or" used in a listing of items (e.g., a listing of items preceded by a phrase such as "at least one of" or "one or more") indicates an inclusive listing, such that, for example, a listing of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, the phrase "based on" as used herein should not be construed to represent a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, when used herein, the phrase "based on" should be construed in the same manner as the phrase "at least partially based on".

[0174] A computer-readable medium includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. The non-transitory storage media may be any available media that is accessible by a general purpose computer or a special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code means in the form of instructions or data structures and that is accessible by a general purpose computer or a special purpose computer, or a general purpose processor or a special purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, the terms disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray (registered trademark) disc, where disk typically magnetically reproduces data, and discs optically reproduce data using a laser. Combinations of the above are also included within the scope of computer-readable media.

[0175] The description in this specification is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure is not limited to the examples and designs described herein, but rather is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. Receiving, in a device comprising a memory array, data that includes a plurality of bits and is divided into a plurality of segments, wherein each bit of the plurality of bits has one of a first value or a second value, and wherein a plurality of indexes are assigned to the plurality of segments; Determining that the data includes a first quantity of bits having the first value, wherein the first quantity of bits is outside a range that is at least partially based on the quantity of bits in the plurality of bits and the quantity of segments in the plurality of segments; Inverting a first segment of the plurality of segments according to the plurality of indexes, at least partially based on the first quantity of bits being outside the range, wherein the data includes a second quantity of bits having the first value after the first segment is inverted; Determining that the second quantity of bits is outside the range; Inverting a second segment of the plurality of segments according to the plurality of indexes, at least partially based on the second quantity of bits being outside the range, wherein the data includes a third quantity of bits having the first value after the second segment is inverted; A method comprising the above.

2. Determining that the third quantity of bits is within the range, wherein the data includes a third plurality of bits after the second segment is inverted; Storing the third plurality of bits in the memory array, at least partially based on the third quantity of bits being within the range; The method according to claim 1, further comprising the above.

3. Storing a value corresponding to an index for the second segment in the memory array; Receiving a request for the data; Outputting from the memory array the third plurality of bits and the value corresponding to the index for the second segment, at least partially based on the request; The method according to claim 2, further comprising the above.

4. Identifying the value corresponding to the index for the second segment, at least partially based on the outputting; For the third plurality of bits, inverting the first segment and the second segment to obtain the plurality of bits based at least in part on the value; outputting the plurality of bits from the device in response to the request for the data; The method of claim 3, further comprising.

5. Inverting each of one or more additional segments having each index between the index for the first segment and the index for the second segment according to the order of the plurality of indexes, wherein the plurality of bits are obtained based at least in part on inverting the one or more additional segments; The method of claim 4, further comprising.

6. A third segment of the plurality of segments includes padding bits, and the method includes: determining that a third amount of the bits is within the range, wherein the data includes a third plurality of bits after the second segment is inverted; determining a difference between a target amount of bits and the third amount of bits based at least in part on the third amount of bits being within the range, wherein the target amount of bits is equal to half of the amount of bits in the plurality of bits; increasing or decreasing an amount of bits in the third segment having the first value based at least in part on the difference between the target amount of bits and the third amount of bits, wherein the data includes the target amount of bits having the first value based at least in part on the increasing or decreasing; The method of claim 1, further comprising.

7. determining that a third amount of the bits is outside the range, wherein the data includes a third plurality of bits after the second segment is inverted; Reversing a third segment of the plurality of segments according to the plurality of indexes, at least in part based on the third quantity of the bits being outside the range, wherein the data includes a fourth quantity of bits having the first value after the third segment is reversed, and the fourth quantity of the bits is within the range; The method of claim 1, further comprising. **Claim 8** The reversing is performed according to an ordering of the plurality of indexes, the ordering being a sequential ordering of the plurality of indexes including a single instance of each index of the plurality of indexes, or a non-sequential ordering of the plurality of indexes including a single instance of each index of the plurality of indexes The method of claim 1, including. **Claim 9** Configuring a span of the range to ensure that reversing at least a subset of the plurality of segments results in the data including an adjusted quantity of bits having the first value within the range The method of claim 1, further comprising. **Claim 10** The method of claim 9, wherein the span of the range is at least partially based on the quantity of bits included in each segment of the plurality of segments. **Claim 11** Shifting a limit of the range, wherein the range includes a value equal to half of the quantity of the bits within the plurality of bits, at least in part based on the shifting The method of claim 9, further comprising. **Claim 12** Receiving data including a plurality of bits and divided into a plurality of segments for storage in a memory array, wherein each bit of the plurality of bits has a first value or a second value, and wherein a plurality of indexes are assigned to the plurality of segments; Determining that the data includes an initial quantity of bits having the first value; Determining that the initial quantity of the bits is outside a range at least partially based on the quantity of bits within the plurality of bits and the quantity of segments within the plurality of segments; Based at least in part on the initial amount being outside the range, reversing one segment of the plurality of segments at a time until the data includes an adjusted plurality of bits including an adjusted amount of bits having the first value, wherein the adjusted amount of bits is within the range; Based at least in part on the adjusted amount of bits being within the range, writing the adjusted plurality of bits to the memory array; A method comprising.

13. After each reversal of one segment of the plurality of segments, determining that the data includes respective amounts of bits having the first value; After each reversal of one segment of the plurality of segments, comparing the respective amounts of bits to the range, wherein subsequent segments of the plurality of segments are reversed based at least in part on the respective amounts of bits being outside the range; The method of claim 12, further comprising.

14. Storing an index label for the last reversed segment in the memory array based at least in part on the adjusted amount of bits being within the range; Receiving a request for the data; Based at least in part on the request, outputting the adjusted plurality of bits and the index label for the last reversed segment from the memory array; The method of claim 12, further comprising.

15. For the adjusted plurality of bits, reversing each segment of the plurality of segments having an index that matches or is earlier than the index for the last reversed segment, in the order of the plurality of indexes, wherein the plurality of bits are obtained based at least in part on the reversing; Outputting the plurality of bits in response to the request for the data from a device including the memory array; The method of claim 14, further comprising.

16. Determining the span of the range based at least in part on the amount of bits included within each segment of the plurality of segments, wherein reversing the plurality of segments according to the plurality of indexes results in the adjusted amount of bits being within the range based at least in part on the span of the range The method of claim 12, further comprising. **Claim 17** The method of claim 16, wherein an upper limit of the range is based at least in part on the amount of bits within the plurality of bits and the amount of segments within the plurality of segments. **Claim 18** Shifting the range, wherein the shifted range includes a value equal to half of the amount of bits within the plurality of bits based at least in part on the shifting. The method of claim 16, further comprising. **Claim 19** Determining an initial amount of bits having the first value based at least in part on counting, wherein within the plurality of bits, each bit has the first value. The method of claim 12, further comprising. **Claim 20** The method of claim 12, wherein the reversing is performed according to an ordering of the plurality of indexes, the ordering including a single instance of each index of the plurality of indexes. **Claim 21** Determining the amount of segments within the plurality of segments; and Dividing the data into the plurality of segments based at least in part on the amount of segments within the plurality of segments. The method of claim 12, further comprising. **Claim 22** A memory array; Coupled to the memory array, causing the device to Receive data including a plurality of bits and divided into a plurality of segments, wherein each bit of the plurality of bits has one of a first value or a second value, and wherein a plurality of indexes are assigned to the plurality of segments; Determining that the data includes a first amount of bits having the first value, the first amount of bits being outside of a range based at least in part on the amount of bits within the plurality of bits and the amount of segments within the plurality of segments. Based at least in part on the first quantity of the bits being outside the range, invert the first segment of the plurality of segments according to the plurality of indexes, where the data includes a second quantity of bits having the first value after the first segment is inverted. Cause it to be determined that the second quantity of the bits is outside the range. Based at least in part on the second quantity of the bits being outside the range, invert the second segment of the plurality of segments according to the plurality of indexes, where the data includes a third quantity of bits having the first value after the second segment is inverted. A memory controller operable to An apparatus comprising. **Claim 23** The memory controller causes the apparatus to Cause it to be determined that the third quantity of the bits is within the range. Based at least in part on the third quantity of the bits being within the range, store the data in the memory array, where the data includes a third plurality of bits after the second segment is inverted. The apparatus according to claim 22, further operable to **Claim 24** The memory controller causes the apparatus to Store a value corresponding to the index for the second segment in the memory array. Receive a request for the data. Based at least in part on the request, output the third plurality of bits and the value corresponding to the index for the second segment. The apparatus according to claim 23, further operable to **Claim 25** The memory controller causes the apparatus to Cause it to be determined that the third quantity of the bits is outside the range, where the data includes a third plurality of bits after the second segment is inverted. Based at least in part on the third quantity of the bits being outside the range, invert the third segment of the plurality of segments according to the plurality of indexes, where the data includes a fourth quantity of bits having the first value after the third segment is inverted, and the fourth quantity of the bits is within the range. The apparatus according to claim 22, further operable to **Claim 26** A memory array and Coupled to the memory array, to the apparatus Receive data that includes a plurality of bits and is divided into a plurality of segments for storage in a memory array, where each bit of the plurality of bits has one of a first value or a second value, and where a plurality of indexes are assigned to the plurality of segments. Determine that the data includes an initial amount of bits having the first value. Determine that the initial amount of bits is outside a range that is at least partially based on the amount of bits within the plurality of bits and the amount of segments within the plurality of segments. Based at least in part on the initial amount of bits being outside the range, invert one segment of the plurality of segments at a time according to the plurality of indexes until the data includes an adjusted plurality of bits that includes an adjusted amount of bits having the first value, where the adjusted amount of bits is within the range. Based at least in part on the adjusted amount of bits being within the range, cause the adjusted plurality of bits to be written to the memory array. A memory controller operable to An apparatus comprising.

27. The memory controller causes the apparatus to After each inversion of one segment of the plurality of segments, determine that the data includes respective amounts of bits having the first value. After each inversion of one segment of the plurality of segments, compare each respective amount of bits to the range, where subsequent segments of the plurality of segments are inverted based at least in part on each respective amount of bits being outside the range. The apparatus according to claim 26, further operable as described above.

28. The memory controller causes the apparatus to Within the memory array, store an indication of an index assigned to the last segment inverted, based at least in part on the adjusted amount of bits being within the range. Receive a request for the data. Based at least in part on the request, output the adjusted plurality of bits and the indication of the index from the memory array. The apparatus according to claim 22, further operable as described above.

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