Search for the Optimal Read Reference Voltage of 3D NAND Memory

Abstract

The memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage relative to a first default read reference voltage and configured to determine an anchor read reference voltage having the same offset as the first best read offset relative to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range may be determined based on the anchor read reference voltage. A second best read offset of the second best read reference voltage relative to the second read reference voltage may be determined by searching in the first scan range. A read process may be performed to read the page from the set of MLCs based on the first and second best read reference voltages.

Description

Technical Field

[0001] This application relates to 3-dimensional (3D) NAND flash memory operation techniques.

Background Art

[0002] 3-dimensional (3D) NAND flash memory employs state-of-the-art multi-level cell (MLC) technology to provide high storage density. A read-retry mechanism is used to improve the reliability of 3D NAND flash memory. For example, multiple retry steps with adjusted read reference voltage values can be performed to read a target page multiple times before an encoded page can be accurately decoded. A large number of read-retry operations can significantly increase the read latency and may degrade the performance of the memory system.

Summary of the Invention

Means for Solving the Problems

[0003] Aspects of the present disclosure provide a method for a memory system. The method may include determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determining an anchor read reference voltage having the same offset as the first best read offset with respect to a second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set for reading pages from a set of multi-level cells (MLCs) in a semiconductor memory device of the memory system. A first scanning range may be determined based on the anchor read reference voltage. An upper limit of the first scanning range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scanning range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset may be positive voltage values or negative voltage values. A second best read offset of a second best read reference voltage with respect to the second read reference voltage may be determined based on the first scanning range.

[0004] In an embodiment, the step of determining the first best read offset is a step of determining a second scanning range, where the second scanning range has an upper limit obtained by adding an upper offset to the first default read reference voltage and a lower limit obtained by adding a lower offset to the first default read reference voltage, the step of scanning the second scanning range based on a coarse step voltage by performing a series of first single read operations within the second scanning range, where each first single read operation corresponds to a first read reference voltage and each first single read operation generates a bit count of either 1 or 0, the step of determining, for each first single read operation, if available, a first bit count difference between the bit count of each first single read operation and the bit count of the previous first single read operation, and, if available, a second bit count difference between the bit count of each first single read operation and the bit count of the subsequent first single read operation, and the step of determining the first read reference voltage of the first single read operation having the minimum value among the series of first single read operations such that the sum of each first bit count difference and each second bit count difference is the minimum value as the coarse best read reference voltage.

[0005] In an embodiment, the method may further include, when there are two or more first single read operations having the same value for the sum of each first bit count difference and each second bit count difference, determining the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations such that the minimum value of each first bit count difference and each second bit count difference is the coarse best read reference voltage.

[0006] In an embodiment, the method includes a step of determining a third scanning range, where the third scanning range has an upper limit which is the sum of a coarse best read reference voltage and a coarse step voltage, and a lower limit which is the difference between the coarse best read reference voltage and the coarse step voltage; a step of scanning the third scanning range based on a fine step voltage by performing a series of second single read operations within the third scanning range, where each second single read operation corresponds to a second read reference voltage and each second single read operation generates a bit count of either 1 or 0; a step of determining, for each second single read operation, if available, a first bit count difference between the bit count of each second single read operation and the bit count of the previous second single read operation, and a second bit count difference between the bit count of each second single read operation and the bit count of the subsequent second single read operation; and a step of determining the second read reference voltage of the second single read operation having the minimum value among the series of second single read operations as the first best read reference voltage, where the offset of the first best read reference voltage with respect to the first default read reference voltage is the first best read offset.

[0007] In an embodiment, the step of determining a second best read reference voltage offset of a second best read reference voltage with respect to a second default read reference voltage based on a first scan range includes: scanning the first scan range by performing a series of third single read operations within the first scan range, where each third single read operation corresponds to a third read reference voltage and each third single read operation generates a bit count of either 1 or 0; for each third single read operation, when available, determining a first bit count difference between the bit count of each third single read operation and the bit count of the previous third single read operation, and when available, determining a second bit count difference between the bit count of each third single read operation and the bit count of the subsequent third single read operation; determining the third read reference voltage of the third single read operation having the minimum value among the total of each first bit count difference and each second bit count difference as the second best read reference voltage, where the offset of the second best read reference voltage with respect to the second default read reference voltage is the second best read offset. In the example, the first single read operation, the second single read operation, and the third single read operation are partial page read operations.

[0008] In an embodiment, the method comprises a step of collecting a first set of first optimal read offsets, wherein each first optimal read offset is a voltage shift of an optimal read reference voltage from a first default read reference voltage, each first optimal read offset corresponds to a memory cell condition for causing each memory cell in a set of memory cells to have a respective first optimal read offset, and the first set of first optimal read offsets each have a positive value or a negative value; a step of setting a maximum value of the first set of first optimal read offsets to be an upper offset of a second scan range; and a step of setting a minimum value of the first set of first optimal read offsets to be a lower offset of the second scan range.

[0009] In an embodiment, the method comprises a step of collecting a second set of second optimal read offsets, wherein each second optimal read offset corresponds to a first set of first optimal read voltages and one of respective memory cell conditions, each second optimal read offset is a voltage shift of an optimal read reference voltage from a second default read reference voltage, and the second set of second optimal read offsets each have a positive value or a negative value; a step of determining a difference between each pair of a first optimal read offset and a respective second optimal read offset, the difference being equal to subtracting each first optimal read offset from a respective second optimal read offset; a step of setting a maximum value of the differences between each pair of a first optimal read offset and a respective second optimal read offset to be an upper offset of a first scan range; and a step of setting a minimum value of the differences between each pair of a first optimal read offset and a respective second optimal read offset to be a lower offset of the first scan range.

[0010] In an embodiment, the method may further include determining that an error correction code (ECC) decoding process has failed to read a page, before determining a first best read reference offset of a first best read reference voltage with respect to a first default read reference voltage. In an embodiment, an ECC software decoding process is performed to read a page from a set of multi-level cells (MLCs) based on a first best read reference voltage and a second best read reference voltage. In an embodiment, the first or second default read reference voltage corresponds to a default read reference voltage of an MLC.

[0011] Aspects of the present disclosure provide a non-transitory computer-readable medium storing instructions. When executed by a processor, the instructions cause the processor to perform a method.

[0012] Aspects of the present disclosure provide a memory system. The memory system may include a semiconductor memory device and a memory controller that operates the semiconductor memory device. The memory controller may include circuitry. The circuitry is configured to determine a first best read reference offset of a first best read reference voltage with respect to a first default read reference voltage, and is configured to determine an anchor read reference voltage having the same offset as the first best read reference offset with respect to a second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set to read a page from a set of multi-level cells (MLCs) in the semiconductor memory device in the memory system. A first scanning range may be determined based on the anchor read reference voltage. An upper limit of the first scanning range is obtained by adding an upper limit offset to the anchor read reference voltage, and a lower limit of the first scanning range is obtained by adding a lower limit offset to the anchor read reference voltage. The upper limit offset and the lower limit offset may be positive or negative voltage values. A second best read reference offset of a second best read reference voltage with respect to a second read reference voltage may be determined based on the first scanning range.

[0013] The disclosure of the present invention can be understood from the following detailed description when read together with the accompanying drawings. It should be noted that the various features are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be increased or reduced for clarity of consideration.

Brief Description of the Drawings

[0014]

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[0015] Although specific configurations and arrangements are considered, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be used in various other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and changed with each other in a manner not clearly depicted in the drawings so that such combinations, adjustments, and changes are within the scope of the present disclosure.

[0016] Generally, terms can be understood at least in part from their use in context. For example, as used herein, the term "one or more" can be used, at least in part depending on the context, to describe a feature, structure, or property in the singular sense, or to describe a combination of features, structures, or properties in the plural sense. Similarly, terms such as "one" or "the" can also be understood, at least in part depending on the context, to convey a singular use or a plural use. Also, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and instead, depending at least in part on the context, may allow for the presence of additional factors that are not necessarily explicitly recited.

[0017] The present disclosure is not limited to 3D NAND memory devices, but 3D NAND devices can be used in some examples to illustrate the concepts of the present invention. For example, the techniques described herein can be applied to planar NAND memory devices.

[0018] Aspects of the present disclosure provide methods and techniques for exploring a best read reference voltage (best read level). The best read level can subsequently be used for read retry or software decoding processes. In embodiments, corresponding to the read level, a scan process can be performed over a plurality of scan points in a scan voltage range (scan range). A series of single read operations can be performed at each scan point over a word line memory cell string that stores one or more pages of data. Each single read operation can output a bit count. The best read level can be determined based on the bit count difference between two consecutive single read operations. Thus, the exploration process does not rely on known data stored in the memory cells.

[0019] Also, a scanning range optimization method is provided to accelerate the search process for the best level. For example, data on a first best read offset with respect to a first default read reference voltage and a second best read offset with respect to a second default read reference voltage can be collected corresponding to different memory cell conditions. A range of voltage differences between the voltage value of the first best read offset and the voltage values of the respective second best read offsets can be determined. The best read level resulting from the first search process at the first read level can be used as an anchor voltage for the second search process at the second read level. The search range for the second search process can be determined based on the range of voltage differences around the anchor voltage.

[0020] FIG. 1 shows a block diagram of a system 100 having a memory device according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As shown in FIG. 1, system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be an electronic device such as a central processing unit (CPU), or a processor of a system on chip (SoC) such as an application processor (AP). Host 108 can be configured to transmit data to memory device 104 or receive data from memory device 104. Memory device 104 can be any memory device disclosed in the present disclosure.

[0021] According to some embodiments, the memory control device 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory control device 106 can manage the data stored in the memory device 104 and can communicate with the host 108. In some embodiments, the memory control device 106 is designed to operate in a low duty cycle environment such as a Secure Digital (SD) card, a CompactFlash (CF) (registered trademark) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones. In some embodiments, the memory control device 106 is designed to operate in a high duty cycle environment such as a solid state drive (SSD) or an embedded multimedia card (eMMC) used as a data storage device for portable devices such as smart phones, tablets, laptop computers, and enterprise storage arrays.

[0022] The memory control device 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory control device 106 can also be configured to manage various functions with respect to the data stored in, or to be stored in, the memory device 104, including but not limited to bad block management, garbage collection, translation from logical addresses to physical addresses, wear leveling, etc. In some embodiments, the memory control device 106 is further configured to process an error correction code (ECC) with respect to the data read from, or written to, the memory device 104. For example, any other suitable function, such as formatting the memory device 104, can also be performed by the memory control device 106. Consistent with some aspects of the present disclosure, in some embodiments, the memory control device 106 is configured to perform the best read reference voltage search method, in whole or in part, as described herein.

[0023] The memory control device 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory control device 106 can communicate with the external device through at least one of various interface protocols such as USB protocol, MMC protocol, PCI (Peripheral Component Interconnect) protocol, PCI-Express (PCI-E) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0024] The memory control device 106 and the one or more memory devices 104 can be incorporated into various types of storage devices and can be included in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0025] In one example, as shown in FIG. 2A, the memory control device 106 and a single memory device 104 can be incorporated into a memory card 202. The memory card 202 can be a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can further include a memory card connector 204 that connects the memory card 202 to a host (e.g., the host 108 in FIG. 1). In another example, as shown in FIG. 2B, the memory control device 106 and a plurality of memory devices 104 can be incorporated into an SSD 206. The SSD 206 can further include an SSD connector 208 that connects the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or the operating speed of the SSD 206 are greater than the storage capacity and / or the operating speed of the memory card 202.

[0026] FIG. 3 shows a schematic circuit diagram of a memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in FIG. 1. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 connected to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array provided in the form of an array of NAND memory strings 308 in which memory cells 306 each extend vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 connected in series and stacked vertically. Each memory cell 306 can hold a continuous analog value such as a voltage or charge that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 can be either a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0027] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can store 1-bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than single-bit of data in more than four memory states. For example, an MLC can store 2 bits per cell (also known as a double-level cell (DLC)), 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, when each MLC stores 2 bits of data, the MLC can be programmed to take on one of three possible programming levels out of an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0028] As shown in FIG. 3, each NAND memory string 308 may include a source select gate (SSG) 310 (or referred to as a source select transistor) at its source end and a drain select gate (DSG) 312 (or referred to as a drain select transistor) at its drain end. The SSG 310 and the DSG 312 may be configured to activate the selected NAND memory string 308 (a column of the array) during a read operation and a program operation. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are connected through the same source line 314, such as a common SL (Source Line) for example. In other words, all the NAND memory strings 308 in the same block 304 have an array common source (ACS) according to some embodiments. According to some embodiments, the DSG 312 of each NAND memory string 308 is connected to respective bit lines 316 through which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a non-select voltage (e.g., 0V) to respective DSG 312 through one or more DSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a non-select voltage (e.g., 0V) to respective SSG 310 through one or more SSG lines 315.

[0029] As shown in FIG. 3, the NAND memory string 308 can be organized into a plurality of blocks 304 each having a common source line 314, such as being connected to the ACS. In some embodiments, each block 304 is a basic data unit for an erase operation, that is, all the memory cells 306 in the same block 304 are erased simultaneously. To erase the memory cells 306 in the selected block 304, the source line 314 connected to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or more). In some examples, the erase operation can be performed at the half-block level, the quarter-block level, or at a level having any suitable number of blocks or any suitable fragment of a block.

[0030] The memory cells 306 of adjacent NAND memory strings 308 are connected through word lines 318 that select which rows of the memory cells 306 are affected by read and program operations. In some embodiments, each word line 318 is connected to a page 320 of memory cells 306 that is a basic data unit for a program operation. The size of one page 320 in bits can be related to the number of NAND memory strings 308 connected by the word lines 318 in one block 304. For ease of description, the memory cells 306 in one page 320 can be connected to the same word line 318, and the terms "page" and "word line" can be used interchangeably in this disclosure. However, in some examples, the memory cells 306 in one page 320 may be connected to two or more word lines 318. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in each respective page 320 and a gate line connecting the control gates to each other. In some embodiments, each word line 318 can be connected to a plurality of pages (or some pages) of memory cells based on the control of the SSG and DSG.

[0031] The peripheral circuit 302 can be connected to the memory cell array 301 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 can include any suitable analog circuits, digital circuits, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to respective target memory cells 306 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and by sensing voltage signals and / or current signals from the respective target memory cells 306. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0032] For example, FIG. 4 shows some of the peripheral circuits including a page buffer / sense amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, a control logic 412, a register 414, an interface 416, and a data bus 418. It is understood that in some examples, additional peripheral circuits not shown in FIG. 4 may also be included.

[0033] The page buffer / sense amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 may store one page of program data (write data) to program one page 320 of the memory cell array 301. In other examples, the page buffer / sense amplifier 404 may perform a program verification operation to ensure that data is properly programmed to the memory cell 306 connected to the selected word line 318. In still other examples, the page buffer / sense amplifier 404 may sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify a small voltage amplitude to a logic level recognizable in the read operation. The column decoder / bit line driver 406 can be configured to be controlled by the control logic 412 and to select one or more NAND memory strings 308 by applying the bit line voltage generated from the voltage generator 410.

[0034] The row decoder / word line driver 408 can be configured to be controlled by the control logic 412 and to select / deselect the block 304 of the memory cell array 301 and to select / deselect the word line 318 of the block 304. The row decoder / word line driver 408 can be further configured to drive the word line 318 using the word line voltage generated from the voltage generator 410. In some embodiments, the row decoder / word line driver 408 can also select / deselect and drive the SSG line 315 and the DSG line 313. As will be described in detail later, the row decoder / word line driver 408 is configured to apply a read voltage to the selected word line 318 in the read operation of the memory cell 306 connected to the selected word line 318. The read voltage can be either a read voltage corrected by a read offset based on the empty block when the read voltage is applied to the word line 318 in the empty block, or a default read voltage without a read offset based on the empty block when the read voltage is applied to the word line 318 in the full block.

[0035] The voltage generator 410 can be controlled by the control logic 412 and configured to generate a word line voltage (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), a bit line voltage, and a source line voltage supplied to the memory cell array 301. As will be described in detail later, depending on whether the read operation is performed on an empty block or a full block, the control logic 412 can control the voltage generator 410 to provide a default read voltage or a corrected read voltage having an offset from the default read voltage to the row decoder / word line driver 408.

[0036] The control logic 412 can be connected to each of the peripheral circuits described above and can be configured to control the operation of each peripheral circuit. The register 414 can be connected to the control logic 412 and can include a status register, an instruction register, and an address register for storing status information, instruction operation codes (OP codes), and instruction addresses for controlling the operation of each peripheral circuit. As will be described in detail later, the status register of the register 414 can include one or more registers configured to store information on free blocks indicating free blocks of all the blocks 304 in the memory cell array 301, such as having an ADSV list. In some embodiments, the information on free blocks also indicates the last programmed page of each free block.

[0037] FIG. 5 shows a schematic diagram of a threshold voltage distribution of memory cells according to an embodiment of the present disclosure. The horizontal axis represents the threshold voltage of the memory cells (indicated by Vth). The vertical axis represents the number of memory cells corresponding to different threshold voltages.

[0038] In FIG. 5, the memory cells can be memory cells in a 3D NAND memory device corresponding to pages, codewords, word line memory cell strings, blocks, planes, dies, and the like. The memory cells are TLC and can be programmed (or erased) to be in one of eight states (memory states) indicated by S0 to S7. The memory cells programmed (or erased) to be in a specific state can have threshold voltages distributed within a voltage range. Thus, in FIG. 5, each state (S0 to S7) is shown as having a threshold voltage distribution. In some examples, these distributions can be modeled using a Poisson distribution respectively.

[0039] A TLC memory cell can represent three bits depending on the state of the memory cell. In other words, three bits can be encoded in one of eight states. The mapping between the states and the respective three bits can vary in different embodiments. In FIG. 5, the eight states S0 to S7 are mapped to 111, 110, 100, 000, 010, 011, 001, and 101 respectively. The least significant bit (LSB) in the eight states can belong to the lower page. The middle significant bit (CSB) in the eight states can belong to the middle page. The most significant bit (MSB) in the eight states can belong to the upper page.

[0040] In FIG. 5, seven default read reference voltages V1 to V7 are positioned between the respective memory cell threshold voltage distributions. Ideally, each memory cell threshold voltage distribution can be included within two adjacent default read reference voltages. In other words, it is desired that a programmed or erased memory cell can maintain its intended state and thereby maintain the three bits it represents. However, the memory cell threshold distribution may shift or expand from one distribution to another due to, for example, program / erase (P / E) cycles, retention periods, write disturb or read disturb, temperature changes, etc. Such changes in the memory cell threshold distribution cause read errors.

[0041] Corresponding to a specific default read reference voltage, if a memory cell has a threshold voltage less than the default read reference voltage, it can be said that the memory cell is in a lower state. If a memory cell has a threshold voltage greater than the default read reference voltage, it can be said that the memory cell is in an upper state. Also, in FIG. 5, the states to the right of the default read reference voltage are called upper states with respect to the default read reference voltage. The states to the left of the default read reference voltage are called lower states with respect to the default read reference voltage.

[0042] Depending on different MLC technologies, different sets of default read reference voltages can be used. For example, SLC can use one default read reference voltage to distinguish two states. DLC can use three default read reference voltages to distinguish four states. QLC can use fifteen default read reference voltages to distinguish sixteen states.

[0043] Figure 6 shows a situation where the memory cell threshold voltage distributions are shifted. Distributions D1 and D2 (dashed lines) represent the ideal memory cell threshold voltage distributions corresponding to two adjacent states (such as S1 and S2 in Figure 5). V default The default read reference voltage 601 shown is positioned between distribution D1 and distribution D2. Corresponding to the ideal threshold voltage distribution, the memory cell is in a state where it accurately represents or maps the encoded bits of the data programmed into the memory cell. Typically, the state of the memory cell over time of the programmed memory cell can be the ideal distribution. In other words, the memory cell at the time of being programmed can have an ideal distribution of threshold voltages (or states).

[0044] Corresponding to distributions D1 and D2, when a single read operation is performed using the default read reference voltage 601, the memory cells belonging to distribution D2 are detected to be in a state of, for example, 0 (indicating having a threshold voltage greater than V default ), resulting in a bit of 0. The memory cells belonging to distribution D1 are in a state of, for example, 1 (V defaultIt is detected to have a smaller threshold voltage (indicating having a smaller threshold voltage), resulting in a bit of 1. Those detected bits correspond to the ideal threshold voltage distribution or the state of the memory cells at the programmed time. Therefore, those bits are referred to as the original bits or ideal bits with respect to the corresponding default read reference voltage 601. When the data programmed into a set of memory cells is known, it should be noted that the ideal state of the set of memory cells (e.g., states S0 to S7 in FIG. 5) can be determined based on the data without a read operation. Therefore, the original bits can be derived or calculated when the associated data is known. Thus, the original bits can also be used to refer to the derived bits or calculated bits in situations where error bits are determined based on the known data.

[0045] Compared with a page read operation in which multiple read operations occur at multiple different read reference voltages, a read operation at a single read reference voltage (such as a default or non - default read reference voltage) is referred to as a single - read operation.

[0046] Distributions D1’ and D2’ represent the threshold voltage distributions of the actual memory cells when the results of the ideal distributions D1 and D2 are shifted. Under the actual distribution, when a single - read operation is performed using the default read reference voltage 601, it belongs to distribution D2’, but V default Memory cells each having a smaller threshold voltage are detected, for example, to indicate having a smaller threshold voltage, resulting in a bit of 1. Therefore, the original bit 0 represented by these memory cells is inverted to be 1. These inverted bits are referred to as inverted bits of the upper state when each memory cell changes its state from an upper state to a lower state. default It is detected to have a smaller threshold voltage (indicating having a smaller threshold voltage), resulting in a bit of 1. Therefore, the original bit 0 represented by these memory cells is inverted to be 1. These inverted bits are referred to as inverted bits of the upper state when each memory cell changes its state from an upper state to a lower state.

[0047] Belonging to distribution D1’, but V defaultMemory cells each having a larger threshold value are detected, for example, to be in a state of 0 (indicating that they have a larger threshold voltage), resulting in bit 0. Therefore, the original bit 1 represented by these memory cells is inverted to 0. These inverted bits are referred to as lower-state inverted bits when each memory cell changes its state from a lower state to a higher state. In addition to the memory cells associated with the lower-state or higher-state inverted bits, other memory cells belonging to distributions D1’ and D2’ can still be accurately detected to be in states 1 and 0, respectively. default During a page read operation (including multiple single read operations), inverted bit errors from multiple single read operations may result in bit errors in the page's parity word. When the raw bit error rate (RBER) of the parity word reaches a level exceeding the ECC correction ability, the associated data (e.g., corresponding to the page) cannot be retrieved, resulting in a failure of ECC decoding. To achieve successful ECC correction, it is desirable to reduce the number of inverted bits in a single read operation.

[0048] This disclosure provides techniques and methods for searching for an optimal read reference voltage to minimize or reduce the number of inverted bits. FIG. 6 shows the optimal read reference voltage 602 as shown in V

[0049] The optimal read reference voltage 602 can be a read reference voltage whose magnitude of inverted bits (including inversion from 1 to 0 or from 0 to 1) is the smallest compared to other read reference voltages within the search range 610. The best read reference voltage 603 can be the output of the search process and is near the optimal read reference voltage 602. The discrepancy between the best read reference voltage 603 and the optimal read reference voltage 602 can be limited to within the accuracy set in each search process. opt

[0050] ​As shown, the search range 610 may have an upper offset 612 and a lower offset 611 defined with respect to the default read reference voltage 601. Thus, the upper limit of the search range 610 can be the default read reference voltage 601 plus the upper offset 612. The lower limit of the search range 610 can be the default read reference voltage 601 plus the lower offset 611 (which has a negative value).

[0051] FIG. 7 shows a read process 700 according to an embodiment of the present disclosure. The process 700 can be performed by the memory controller 106 to read data (such as a page or an upper page) from the 3D NAND memory device 104. The process 700 starts from S711.

[0052] In S711, a read operation can be performed, for example, to read a page from the memory device 104. The page can be one of the lower page, the middle page, or the upper page stored in the set of TLCs. Thus, a plurality of single read operations each based on a default read reference voltage can be performed on the memory cells storing the page. For example, corresponding to the mapping between the three bits and the eight states (S0 to S7) in FIG. 5, three single read operations at the default read reference voltages V2, V4, and V6 can be performed to read the middle page. The bits resulting from each single read operation can be processed to generate the raw bits of the codeword belonging to the page.

[0053] In S712, ECC decoding can be performed based on the raw bits of the codeword. Various types of ECC (low density parity check code (LDPC)) can be used in various embodiments. In S713, it is determined whether the ECC decoding was successful. When the RBER of the codeword exceeds the ECC correction capability, the ECC decoding of the page will fail. When the ECC decoding fails, the process 700 proceeds to S714. Otherwise, the process 700 proceeds to S716 and ends in S716.

[0054] In S714, the synchronization of the read reference voltage is performed to determine a new read reference voltage. In S715, a read retry is performed based on the new read reference voltage. The operation in S715 can be similar to the operation in S711, but with an updated read reference voltage. Based on the raw bit of the codeword generated from S715, a second repetition of ECC decoding can be performed in S712. The read retry can be repeated until process 700 reaches S716 or until the available read reference voltages for the read retry are exhausted.

[0055] When a read error occurs (at S713), in various embodiments, there can be various ways for read error handling. In some examples, a read - retry table is used for the read - retry process. A list of one or more read reference voltages for read - retry can be provided in the read - retry table, for example, by the producer of each 3D NAND memory device or memory system (such as an SSD). Typically, the read - retry table is constructed based on the consideration of a limited number of factors such as retention period, read disturb, cross - temperature, problems with the first read, etc. Therefore, the read - retry table may not be comprehensive for all situations.

[0056] In some embodiments, the best read reference voltage search method disclosed herein can be employed as an alternative or in addition to the use of a read - retry table to determine the next read retry reference voltage.

[0057] In some embodiments, after a failure in ECC decoding, a best read reference voltage search method is launched to find the best read reference voltage. Next, the best read reference voltage can be used as the base voltage for software LDPC decoding processing. In an example of software LDPC decoding processing, multiple read - retry read reference voltages can be set around the best read reference voltage. Thus, multiple read retry operations can be performed in a (step - by - step) manner to obtain the log - likelihood ratio (LLR). The LLR can be fed into an ECC engine (which can be separate from the memory controller 106 or can be part of the memory controller 106) to software - decode the codeword.

[0058] FIG. 8 shows a best read level search process 800 based on a failed bit count (FBC) according to an embodiment of the present disclosure. The term best read level herein refers to the best read reference voltage level. Process 800 can be executed in an experimental environment where known data is programmed into a block of memory cells in a memory device.

[0059] Process 800 can include multiple coarse or fine scanning processes. Each scanning process can cover the search range of the read reference voltage with a step voltage. At each scanning point (corresponding to a specific read reference voltage level or read level), the read bits resulting from a single read operation can be compared with the original bits to determine the FBC (the magnitude of the inverted bits from 0 to 1 or from 1 to 0). The original bits can be derived based on the known data. The read level with the minimum FBC can be determined to be the best read level for each scanning process. The search range can be defined with respect to each default read reference voltage (or referred to as the default voltage). The best read level can be represented as the best read offset with respect to the default voltage.

[0060] Process 800 may include one step of coarse scanning (S810) and two steps of fine scanning (S820 and S830). TLC is used as an example for the description of process 800.

[0061] In S810, the coarse scanning is performed at a default voltage on the word line cell string. The default voltage can be, for example, V1 to V7 which are all the default voltages configured for TLC. The word line cell string may include memory cells controlled by word lines. The word line cell string can store three pages of known data. Therefore, the initial state or the original bits of the word line cell string can be calculated based on the known data. The block under test may include multiple layers of word lines.

[0062] A scanning range and a step voltage can be provided for each coarse scanning. For example, a lower limit offset of -300 mV and an upper limit offset of 300 mV can be provided for each default voltage. Therefore, the scanning range can be {-300 mV, +300 mV} with each default voltage at the center point. For example, a coarse step voltage of 100 mV can be provided. Therefore, seven scanning points, namely, -300 mV, -200 mV, -100 mV, 0, 100 mV, 200 mV, and 300 mV are provided.

[0063] For each coarse scan, the read level at the scan point having the minimum FBC can be determined such that it becomes the best read level. In some examples, for each scan point, the read bits from the word line memory cell string can include bits of a plurality of codewords. The FBC for each codeword can be determined. The maximum FBC for each codeword can be determined for each scan point or read level. Thus, the read level at which the maximum FBC for each codeword is minimum is determined as the best read level (referred to as the coarse best read level) for each coarse scan. Thus, the best read offset (referred to as the coarse best read offset) can be determined for each coarse scan.

[0064] If multiple read levels of a certain coarse scan have the same maximum FBC for each codeword, the total FBC of all codewords for each read level is considered. The read level having the minimum total FBC is determined to be the best read level. If multiple read levels of a certain coarse scan have the same minimum total FBC, the read level having a smaller offset is determined to be the best read level.

[0065] In S820, a first fine scan is performed at a coarse best read level for the word line memory cell strings in a block. For example, for each of the word line memory cell strings, seven first fine scans can be performed at seven coarse best read levels. For each first fine scan, a scan range {-200 ms, 200 ms} with each respective coarse best read level in the middle can be provided. Assuming that the offset of the coarse best read level from S810 is -100 ms, when the lower limit offset and the upper limit offset for each respective default voltage are used to define the scan range, the scan range becomes {-300 ms, 100 ms}. For each first fine scan, for example, a fine step voltage of 20 ms smaller than a coarse step voltage of 100 mV can be provided. In the same way as in S810, based on the FBC, a fine best read level and a corresponding fine best read offset can be found for each first fine scan.

[0066] In S830, a second fine scan is performed at a fine optimal read level for the word line memory cell strings in the block. For example, for each of the word line memory cell strings, seven second fine scans can be performed at seven fine optimal read levels. For each second fine scan, a scan range {-10ms, 10ms} with a fine optimal read level in the middle can be provided. Assuming that the offset of the fine optimal read level from S820 is -120ms, when the lower limit offset and the upper limit offset for each default voltage are used to define the scan range, the scan range becomes {-130ms, -110ms}. For each second fine scan, for example, a fine step voltage of 10ms (or less than 10ms) smaller than a 20mV fine step voltage can be provided. In the same way as in S810 or S820, based on FBC, the final fine optimal read level and the corresponding final fine optimal read offset can be found for each second fine scan. Finally, for the block of memory cells, in each word line memory cell string, the optimal read level is obtained corresponding to each of the seven default voltages. In various examples, the results can be used as a basis for various evaluations or experiments. For example, the results can be used to evaluate the performance of the LDPC algorithm.

[0067] The FBC-based method described in this specification can typically be used for test or experimental environments. The FBC-based method depends on known data programmed into the memory cells. For an actual memory system, the data stored in the memory device may not be known. The FBC-based method can scan all word line memory cell strings. For an actual memory system, the search for the optimal level is performed in one word line memory cell string in response to a failed page read operation for the word line memory cell string. In the FBC-based method, the scan for the word line memory cell string may be too time-consuming and thus may not be suitable for an actual memory system.

[0068] In some embodiments, a best read level search method based on bit count difference (BCD) is used. In the BCD-based method, the bit count difference between adjacent read levels (scanning points) is calculated and used to determine the best read level. Thus, the BCD-based method does not rely on known data programmed in memory devices that may not be available in an actual memory system.

[0069] Also, the BCD-based method is used to find the best read level for reading a page. Thus, the scanning operation is performed at a limited number of default voltages instead of all default voltages of the word line memory cell string. For example, for reading the middle page, the scanning operation can be performed around three default voltages (e.g., V2, V4, and V6) to find three best read levels. Also, the scanning operation is not performed on all word line memory cell strings throughout the block.

[0070] In some examples, in the BCD-based method, for each read level (scanning point), partial page reading is used instead of full page reading during a single read operation. For example, a page stored in a word line memory cell string can be 16k bytes in length. The page can include four codewords each 4k bytes in length. Thus, the BCD-based method can read from memory cells corresponding to codewords instead of pages. The bits resulting from a single read operation can be reduced. Thus, the delay in data transmission from the memory device to the memory controller can be reduced.

[0071] In some examples, the scan range used in the BCD-based method is optimized based on some of the worst-case observed read level offsets. Accordingly, the scan time can be reduced. In some examples, the BCD-based method can use one coarse scan and one fine scan. The scan process is simplified compared to one coarse scan and two fine scans in the search process 800. In some examples, hardware support is available to calculate the bit count for BCD. The time to calculate the bit count can be reduced compared to the FBC calculation implemented using software.

[0072] FIG. 9 shows a BCD table 900 for determining the best read level from a series of read levels (scan points) during a scan process. The scan process can be part of a BCD-based best read level search process. The first column of the BCD table 900 includes a series of scan points covered by the scan process. The scan points are represented by a scan point offset (or read level offset). A step voltage of 10 mV is used. At each scan point, a single read operation can be performed. Bits can be read from a set of memory cells belonging to a word line memory cell string. For example, a memory cell with a threshold voltage lower than the read level of the scan point is read as 1. A memory cell with a threshold voltage higher than the read level of the scan point is read as 0.

[0073] Considering the current scanning point, two BCDs can be calculated. The first BCD, denoted as BCD-L, can be the BCD between the current scanning point and the left scanning point adjacent to the current scanning point. The second BCD, denoted as BCD-R, can be the BCD between the current scanning point and the right scanning point adjacent to the current scanning point. The left or right position can be with respect to the search range along the axis of the threshold voltage. Typically, a larger read level is on the right side of a smaller read level. For read levels close to the left or right boundary of the search range, the left or right scanning points are not available. Each BCD-L or BCD-R is not calculated and is unavailable. Typically, read levels close to the boundary of the search range can be excluded from the candidate scanning points for selecting the best read level.

[0074] For the above BCD-L and BCD-R corresponding to each scanning point, the best read level can be selected from a series of scanning points. First, the read level at the scanning point having the smallest sum of BCD-L and BCD-R (denoted as Sum(BCD-L, BCD-R)) can be determined to be the best read level. If multiple scanning points have the same sum of BCD-L and BCD-R, the read level at the scanning point having the smallest minimum value of BCD-L or BCD-R (denoted as Min(BCD-L, BCD-R)) is determined to be the best read level among these multiple scanning points. If there are still multiple scanning points having the same minimum value of BCD-L or BCD-R, the scanning point closest to the midpoint of the scanning range can be determined as the best scanning point with the best read level. Corresponding to the best read level, the corresponding scanning point offset can be determined to be the best read offset with respect to each default voltage.

[0075] Figures 10A - 10B illustrate a search process 1000 for the best read level based on BCD according to an embodiment of the present disclosure. The search process 1000 based on BCD can be implemented to find the best read reference voltage for the page read operation. The process 1000 may include two parts, namely, a coarse search part from S1002 to S1016 and a fine search part from S1024 to S1036.

[0076] In S1002, the ECC decoding fails for the page read operation. For example, the raw codeword bits of the target page are obtained based on the data read from the memory device by one or more single read operations. The LDPC hardware decoding based on the raw codeword bits may fail due to a high RBER. The search process 1000 based on BCD can then be launched to find the best read level for a read retry of the target page or for software LDPC decoding.

[0077] In S1004, the read level corresponding to the default voltage can be initialized. Depending on which MLC technology the target page uses, what kind of target page it is (e.g., a lower page or an upper page), and how the bits are encoded by the memory cell states, the number of read levels to be covered can be determined. For example, for SLC, a single read operation at a certain read level can be performed. For DLC, one read level is covered for reading a lower page, and two read levels are covered for reading an upper page. For TLC, two read levels, three read levels, and two read levels are respectively covered for reading a lower page, a middle page, and an upper page. The coarse search and the fine search cover the read levels determined in S1004.

[0078] In S1006, it is determined whether the following read levels are available. If all the read levels determined in S1004 are completed and the next read level is not available, process 1000 proceeds to S1024 and enters the detailed search part. Otherwise, process 1000 proceeds to S1008 with the selection of a read level among the read levels determined in S1004. The read levels can be selected in any order.

[0079] In S1008, the scan point offset can be initialized corresponding to the selected read level. For example, the number and position (voltage value) of each scan point can be determined based on the scan range (or scan voltage range) and the step voltage. The scan points can be indicated in the form of a scan point offset with respect to the respective default voltage corresponding to the selected read level. For example, an upper limit offset and a lower limit offset with respect to the default voltage can be provided to indicate the scan range.

[0080] In S1010, it is determined whether the next scan point offset is available. If all the scan point offsets determined in S1008 are completed and the next scan point offset is not available, process 1000 proceeds to S1016. Otherwise, process 1000 proceeds to S1012. In S1012, a scan point offset is selected from the scan point offsets determined in S1008. The scan point offsets can be selected in any order.

[0081] In S1014, a single read operation can be performed at the scan point of the selected scan point offset on the memory cell that stores the target page. The bits resulting from the single read operation can be stored in the memory. If the read bits of adjacent scan points are available in the memory, the BCD-L or BCD-R between the current scan point and the adjacent scan points can be calculated and stored in a BCD table such as the table shown in FIG. 9. Process 1000 can return to S1010 to process the next scan point offset if available.

[0082] In S1016, at the current stage, for each scanning point offset, BCD-L and BCD-R are put into the BCD table corresponding to the current read level selected in S1006. Based on the BCD table, a rough best read offset can be determined for the current read level. The rough best read offset can be used as the central scanning point offset for a detailed search corresponding to the current read level. The process 1000 can proceed to S1006 to process the next read level if available.

[0083] In S1024, the detailed search part of the process 1000 starts based on the rough best read offset of each read level. Specifically, in S1024, the read level corresponding to the default voltage is initialized in the same way as in S1004. The same set of read levels can be determined. In S1026, it can be determined whether the next read level is available. When all read levels are covered, the process 1000 can proceed to S1038 and end in S1038. Otherwise, the process 1000 proceeds to S1028 at the selected read level.

[0084] In S1028, the scanning point offset for the detailed search corresponding to the selected read level can be initialized. For example, the number and position of the scanning point offsets for the detailed search can be determined based on the detailed scanning range and the detailed step voltage. For example, the detailed scanning range can use each rough best read level as the central point. The upper and lower limits can be provided relative to the central location.

[0085] In S1030, it may be determined whether the following scan point offsets are available. If all scan point offsets are covered, process 1000 proceeds to S1036. Otherwise, process 1000 proceeds to S1032. In S1032, the next scan point offset is selected. In S1034, a single read operation is performed at the selected scan point offset to read bits from the memory cells storing the target page. The BCD-L or BCD-R of the current scan point offset or adjacent scan point offsets can be calculated to fill the BCD table. Process 1000 can return to S1030 to process the next available scan point offset.

[0086] In S1036, the BCD table corresponding to the current read level is filled. A fine best read offset can be determined for the current read level. Process 1000 can proceed to S1026 to process the next available read level. When process 1000 ends in S1038, the best read levels corresponding to the fine best read offsets are available for each read level. In some examples, the obtained best read levels can subsequently be used in LDPC software decoding processing.

[0087] FIG. 11A shows two tables 1110 and 1120 for showing how to optimize the scan range used for rough search in the BCD-based search process 1000 according to an embodiment of the present disclosure. In the example of FIG. 11A, an optimized scan range (referred to as an optimized rough scan range) for rough search at a specific read level corresponding to each default voltage can be determined based on the set of data provided in table 1110. Table 1110 includes seven columns. Each column corresponds to one of seven read levels (or seven default voltages) for TLC. The seven read levels are shown as RD1 to RD7. Table 1110 includes a plurality of rows.

[0088] Each row includes a set of best read offsets corresponding to one of seven read levels, RD1 to RD7. Each best read offset has an offset value (in units of mV) with respect to its respective default voltage (such as V1 to V7 in FIG. 5). For example, for read level RD1, the first best read offset is -130 mV, and the last best read offset is -60 mV with respect to the default voltage V1.

[0089] Each row of best read offsets can correspond to a memory cell condition that causes or indicates that the set of memory cells have their respective best read offsets. For example, the condition can be a combination of multiple factors. The factors can include the type of workload, the temperature of the environment, the retention period, read disturb, cross temperature, first read problems, fabrication process, etc. Different conditions can correspond to different values of the factors. For example, the set of memory cells can be placed under the conditions in an experimental environment. The best read offsets can be measured from these memory cells. In some embodiments, the conditions being considered can be a set of extreme conditions associated with worst-case scenarios. Thus, some of the best read offsets can each represent the maximum change in the best read offset under extreme conditions.

[0090] Table 1120 shows the optimized coarse search range derived based on the best read offsets collected in Table 1110. As shown, for each read level (RD1, RD2, and RD3), the minimum value in each column of the best read offsets is used as the lower offset, while the maximum value in each column of the best read offsets is used as the upper offset. The lower offset and the upper offset together can define the optimized coarse search range for each read level with respect to each default voltage. For example, the lower boundary voltage of the optimized coarse search range is the default voltage plus the lower offset. The upper boundary voltage of the optimized coarse search range is the default voltage plus the upper offset.

[0091] In Table 1120, the offsets in the first, second, and third columns can be used respectively for the coarse search at each read level RD1, RD2, and RD3. If necessary, other upper and lower offsets for other read levels can be derived similarly.

[0092] FIG. 11B shows two tables 1130 and 1140 for showing how to optimize the scanning range used for fine search in the BCD-based search process 1000 according to an embodiment of the present disclosure. Table 1130 includes a row of values equal in number to the row of the best read offset in Table 1110. The first column of Table 1130 includes a list of the best read offset differences between columns RD2 and RD4. Each such best read offset difference can be the difference between two best offset values in different columns RD2 and RD4 but in the same row in Table 1110. For example, considering the last row of Table 1110, the difference between the value of column RD2 and the value of column RD4 is -40 mV - (-30) mV = -10 mV (subtracting the lower level value from the higher read level value). Similarly, the second column of Table 1130 includes a list of the best read offset differences between columns RD4 and RD6.

[0093] Table 1140 shows the optimized fine search range for read levels RD4 and RD6. The optimized search range can be derived based on the best read offset difference in Table 1130. Specifically, for the fine search range of RD4 in Table 1140, the lower limit offset of -80 mV can be the minimum of the best read offset differences listed in the first column of Table 1130, and the upper limit offset of 50 mV can be the maximum of the best read offset differences listed in the first column of Table 1130. These lower limit and upper limit offsets can be offsets with respect to the anchor voltage when used in the fine search process. For example, the anchor voltage for RD4 can have an anchor offset with respect to the default voltage of RD4. The anchor offset can be made equal to the fine best read offset of read level RD2. The fine best read offset of RD2 can be found, for example, in the optimized coarse search range {-190 mV, 70 mV} of RD2 as indicated in Table 1120. Two iterations of search (coarse search and fine search) can be performed to find the fine best read for the set of RD2, such as in the example of FIGS. 10A - 10B.

[0094] Similarly, for the fine search range of RD6 in Table 1140, a lower offset of -160 mV can be the minimum of the best read offset differences listed in the second column of Table 1130, and an upper offset of 60 mV can be the maximum of the best read offset differences listed in the second column of Table 1130. These lower and upper offsets can be offsets with respect to the anchor voltage for RD6. The anchor voltage for RD6 can have an anchor offset with respect to each default voltage of RD6. The anchor offset of RD6 can be made equal to the fine best read offset of read level RD4. The fine best read offset of RD4 can be found, for example, in the optimized fine search range {-80 mV, 50 mV} of RD2 indicated in Table 1140. Table 1140 also lists a fine search range {-100 mV, 100 mV} for RD2. This fine search range can be set based on any other method.

[0095] In the previous description, the combination of the coarse search and the fine search is first performed in the coarse search range of RD2 in Table 1120 to find the fine best read offset of RD2. When using the fine best read offset of RD2 as the anchor offset, the fine search is performed in the fine search range of RD4 in Table 1140 to find the fine best read offset of RD4. The fine best read offset of RD4 is used as the anchor offset, and the fine search range of RD6 can be determined in the fine search range of RD6 in Table 1140. In this way, three best read offsets can be determined for read levels RD2, RD4, and RD6 and can be used to read the middle page in the example of FIG. 5.

[0096] In other examples, the above order (from RD2 to RD6) may be changed to any order. For example, the above search can take any order, such as the order of RD6, RD2, and RD4. A combination of a coarse search and a fine search may start from RD6 and be continued by two fine searches at RD2 and RD4. In this order, the corresponding coarse search range and fine search range at each level can be adjusted accordingly. For example, the fine best offset of RD6 can be used as the anchor offset of RD2. Thus, the fine search range of RD2 can be determined based on the best read offset difference between the best read offset of RD2 and the best read offset of RD6. Also, the fine best offset of RD6 can be used as the anchor offset of RD4. Alternatively, the fine best offset of RD2 is used as the anchor offset of RD4.

[0097] The previous description has used the read levels RD2, RD4, and RD6 of the middle page of the TLC as examples to illustrate the method of optimizing the coarse search range or the fine search range. However, the search optimization method can be used for any type of MLC with one, two, three, four, or more pages saved.

[0098] Compared with setting the search range indiscriminately, the search range (or scanning range) obtained by using the search range optimization method disclosed in this specification can be made shorter, and thus the best read level search process can be accelerated. Also, when the search range optimization method disclosed in this specification is used, some coarse search processes can be skipped, and the best read level search process can be further accelerated. Furthermore, the search range optimization method disclosed in this specification does not depend on a specific search method. The search range optimization method can be used to provide an optimized countermeasure range for any best read search method.

[0099] Figures 12A to 12C show the best read level search process according to an embodiment of the present disclosure. The best read levels corresponding to the default voltages V2 and V4 for reading the middle page from the TLC can be determined during the process. Optimized coarse search ranges and fine search ranges are used during the process.

[0100] Figure 12A shows a coarse search range 1210. The coarse search range 1210 has an upper limit offset 1212 of 70 mV and a lower limit offset 1211 of -190 mV with respect to the default voltage 1213 of V2. The coarse search range 1210 can be an optimized coarse search range determined using the coarse search range optimization method described in the examples of Figures 11A to 11B. A coarse search with a step voltage of 100 mV can be performed across the coarse search range 1210 to find a coarse best read level 1214 having a coarse best read offset 1215 of -30 mV with respect to the default voltage 1213 of V2.

[0101] Figure 12B shows a fine search range 1220 defined with the coarse best read level 1214 as the central scan point 1214. The fine search range 1220 can have a lower limit offset 1221 of -100 mV and an upper limit offset 1222 of 100 mV with respect to the central scan point 1214. Following the coarse search in Figure 12A, a fine search with a step voltage of 10 mV can be performed across the fine search range 1220 to find a fine best read level 1223. The fine best read level can have a fine best read offset 1224 of -50 mV with respect to the default voltage 1213 of V2.

[0102] FIG. 12C shows another detailed search range 1230 for the read level corresponding to the default voltage 1235 of V4. The detailed search range 1230 can be defined based on other scan points (anchor voltages) 1233. The anchor scan points 1233 are for the default voltage 1235 of V4, but may have the same offset value as the fine best read offset 1224 of -50 mV. The detailed search range 1230 may have a lower limit offset 1231 of -80 mV and an upper limit offset 1232 of 50 mV with respect to the anchor scan points 1233. Following the detailed search in FIG. 12B, another detailed search can be performed on the detailed search range 1230 in voltage steps of 10 mV to find the best read level 1236. The best read level 1236 may have a best read offset 1237 for the default voltage V4.

[0103] FIG. 13 shows a best read level search process 1300 according to an embodiment of the present disclosure. The process 1300 can start from S1310.

[0104] In S1310, a first best read offset of the first best read reference voltage with respect to the first default read reference voltage can be determined. For example, to determine the first best read offset, a second scan range can be determined. The second scan range may have an upper limit that is the first default read reference voltage plus an upper limit offset and a lower limit that is the first default read reference voltage plus a lower limit offset. The second scan range can be scanned based on a coarse step voltage by performing a series of first single read operations within the second scan range. Each first single read operation generates a bit count of either 1 or 0. Each first single read operation corresponds to the first read reference voltage.

[0105] For example, for each first single read operation, if available, a first bit count difference between the bit count of each first single read operation and the bit count of the previous first single read operation can be determined. If available, a second bit count difference between the bit count of each first single read operation and the bit count of a subsequent first single read operation can be determined. The first read reference voltage of the first single read operation having the minimum value among a series of first single read operations can be determined such that the sum of each first bit count difference and each second bit count difference becomes the rough best read reference voltage.

[0106] In an example, when there are two or more first single read operations in which the sum of each first bit count difference and each second bit count difference has the same value, the minimum value of each first bit count difference and each second bit count difference can be determined such that the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations becomes the rough best read reference voltage.

[0107] In some examples, a third scanning range can be subsequently determined. The third scanning range can have an upper limit that is the rough best read reference voltage plus a rough step voltage and a lower limit that is the rough best read reference voltage minus the rough step voltage. The third scanning range can be scanned based on a fine step voltage by performing a series of second single read operations within the third scanning range. Each second single read operation corresponds to a second read reference voltage. Each second single read operation generates a bit count of either 1 or 0.

[0108] For each second single read operation, if available, a first bit count difference between the bit count of each second single read operation and the bit count of the previous second single read operation can be determined. Also, if available, a second bit count difference between the bit count of each second single read operation and the bit count of a subsequent second single read operation can be determined. Accordingly, the second read reference voltage of the second single read operation having the minimum value among a series of second single read operations can be determined such that the sum of each first bit count difference and each second bit count difference becomes the first best read reference voltage. The offset of the first best read reference voltage with respect to the first default read reference voltage is the first best read offset.

[0109] In S1320, an anchor read reference voltage having the same offset as the first best read offset can be determined with respect to the second default read reference voltage. The first default read reference voltage and the second default read reference voltage are set to read a page from a set of MLCs in the semiconductor memory device.

[0110] In S1330, a first scanning range can be determined based on the anchor read reference voltage. For example, the upper limit of the first scanning range is the anchor read reference voltage plus an upper limit offset. The lower limit of the first scanning range is the anchor read reference voltage plus a lower limit offset. The upper limit offset and the lower limit offset can be positive voltage values or negative voltage values.

[0111] In S1340, the second best read reference offset of the second best read reference voltage with respect to the second default read reference voltage can be determined by searching within the first scan range. For example, the first scan range can be scanned by performing a series of third single read operations within the first scan range. Each third single read operation corresponds to a third read reference voltage. Each third single read operation generates a bit count of either 1 or 0.

[0112] For each third single read operation, if available, a first bit count difference between the bit count of each third single read operation and the bit count of the previous third single read operation can be determined. If available, a second bit count difference between the bit count of each third single read operation and the bit count of the subsequent third single read operation can be determined. Thus, the third read reference voltage of the third single read operation having the minimum value among the series of third single read operations, where the sum of each first bit count difference and each second bit count difference, can be determined to be the second best read reference voltage. The offset of the second best read reference voltage with respect to the second default read reference voltage is the second best read offset. In some examples, the first single read operation, the second single read operation, and the third single read operation are partial page read operations.

[0113] In S1350, a read process can be performed to read a page from a set of MLCs based on the first best read reference voltage and the second best read reference voltage. Process 1300 can end.

[0114] Figures 14A to 14B show a performance comparison between a first best read search process and a second best read search process according to an embodiment of the present disclosure. The first best read search process can be a search process for a best read level based on FBC, such as in the example of FIG. 8. The second best read search process can be a search process for a best read level based on BCD, such as the process in the examples of FIGS. 9 to 13.

[0115] FIG. 14A shows the total time for completing the first best read level search process for a word line memory cell string. The word line memory cell string can include an MLC having (n + 1) states. Therefore, there are n read levels to be processed. The total time indicated by T is T = SUM(K, M, N)*(tR + tDMA + tOH)*n levels (1) and can be. In Equation (1), n levels represents the number of read levels to be processed. K, M, and N respectively indicate the number of scan steps performed between a rough scan, a first fine scan, and a second fine scan when processing each read level. The time for each scan step includes a page read time tR, a data transfer time (e.g., between a memory device and a memory controller), tDMA, and a firmware (FW) processing overhead time tOH.

[0116] FIG. 14B shows the total time for completing the second best read level search process for a word line memory cell string. The word line memory cell string can also include an MLC having (n + 1) states. However, the number of read levels to be processed is smaller than n. For example, to read the middle page of a TLC, the search process can be performed at three read levels (e.g., RD2, RD4, and RD4). Therefore, the total time indicated by T' is T' = K'*(tR' + tDMA' + tOH') + ΣM[i]*(tR' + tDMA' + tOH') (2) This is possible. In Equation (2), K’ represents the number of scan steps performed during a rough scan at the first read level among the read levels to be processed. M’[i] represents the number of scan steps performed during a detailed scan for each read level indexed by i. The time for each scan step includes the single read operation time tR’, the data transfer time (e.g., between the memory device and the memory controller), tDMA’, and the firmware (FW) processing overhead time tOH’.

[0117] Comparing the example of FIG. 14B with the example of FIG. 14A, since the single read operation can be used instead of the normal page read operation, the read time tR’ can be made smaller than tR. The data transfer time tDMA’ can be made smaller than tDMA because partial page reads can be used instead of full page reads and the amount of data to be transferred is reduced. The FW processing overhead tOH’ can be made smaller than tOH because the bit count (in each scan step) in the second search method can have hardware acceleration support while the FBC (comparison between the read bit and the original bit) can be performed using FW. The number of scan steps K’ and M’[i] can also be reduced from K and M due to the adoption of the search range optimization technique. The second detailed search is excluded from the second search method, and thus N does not appear in Equation (2). Also, as shown in FIG. 14B, the rough scan (including K’ scan steps) is performed only at the first read level. The other read levels each include only a detailed scan. Performing the rough scan once can also save time.

[0118] In various embodiments, the best read level search methods disclosed herein may be implemented in a memory controller (such as memory controller 106) or in a memory device (such as memory device 104). These methods may be initiated in response to an ECC decoding failure or may be executed in the background. In some embodiments, the methods disclosed herein may be implemented in hardware, software, or a combination thereof. By way of example, the best read level search methods disclosed herein may be implemented with instructions stored on a non-transitory computer-readable medium. A processor or processing circuit can execute the instructions to implement the respective methods.

[0119] Aspects of the present disclosure provide a memory controller that implements the techniques disclosed herein. For example, the memory controller may include circuitry configured to implement the method. The method may include determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading pages from a set of multi-level cells (MLCs) in a semiconductor memory device in a memory system; determining a first search range based on the anchor read reference voltage, wherein an upper limit of the first search range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first search range is the anchor read reference voltage plus a lower limit offset, and the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read offset of a second best read reference voltage with respect to a second read reference voltage by searching within the first search range; and performing a read process for reading pages from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

[0120] Aspects of the present disclosure provide a non-transitory computer-readable medium that stores instructions for implementing the techniques disclosed herein. For example, the instructions, when executed by a processor (or processing circuitry), can cause the processor (or processing circuitry) to implement a method. The method includes determining a first best read reference voltage offset of a first best read reference voltage with respect to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read reference voltage with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in a semiconductor memory device in a memory system; determining a first scan range based on the anchor read reference voltage, wherein an upper limit of the first scan range is the anchor read reference voltage plus an upper limit offset, and a lower limit of the first scan range is the anchor read reference voltage plus a lower limit offset, and the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read reference voltage offset of a second best read reference voltage with respect to a second read reference voltage by searching within the first scan range; and performing a read process for reading a page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

[0121] The above has outlined the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures in order to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alternatives can be made herein without departing from the spirit and scope of the present disclosure.

Description of Reference Numerals

[0122] 100 System 102 Memory System 104 Memory Device 106 Memory Controller 108 Host 202 Memory Card 204 Memory Card Connector 206 SSD 208 SSD Connector 300 Memory Device 301 Memory Cell Array 302 Peripheral Circuit 304 Block 306 Memory Cell 308 NAND Memory String 310 Source Select Gate, SSG 312 Drain Select Gate, DSG 314 Source Line 316 Bit Line 318 Word Line 320 Page 404 Page Buffer / Sense Amplifier 406 Column Decoder / Bit Line Driver 408 Row Decoder / Word Line Driver 410 Voltage Generator 412 Control Logic 414 Register 416 Interface 418 Data Bus 601 Default Read Reference Voltage 602 Optimal Read Reference Voltage 603 Best Read Reference Voltage 610 Search Range 611 Lower Limit Offset 612 Upper Limit Offset 700 Read Process 800 Search Process for Best Read Level 900 BCD Table 1000 Search Process for Best Read Level Based on BCD 1110, 1120 Tables for Coarse Search 1130, 1140 Tables for Fine Search 1210 Coarse Search Range 1211 Lower Limit Offset 1212 Upper Limit Offset 1213 Default Voltage 1214 Coarse Best Read Level, Central Scanning Point 1215 Coarse Best Read Offset 1220 Fine Search Range 1221 Lower Limit Offset 1222 Upper Limit Offset 1223 Fine Best Read Level 1224 Fine Best Read Offset 1230 Fine Search Range 1231 Lower Limit Offset 1232 Upper Limit Offset 1233 Scanning Point, Anchor Voltage 1235 Default Voltage 1236 Best Read Level 1237 Best Read Offset D1, D2, D1’, D2’ Distributions S0, S1, S2, S3, S4, S5, S6, S7 States V1, V2, V3, V4, V5, V6, V7 Default Read Reference Voltages Vth Threshold Voltage

Claims

1. A method for a memory system, comprising: determining a first best read reference offset of a first best read reference voltage with respect to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read reference offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading pages from a set of multi-level cells (MLCs) in a semiconductor memory device in the memory system; determining a first scanning range based on the anchor read reference voltage, wherein an upper limit of the first scanning range is obtained by adding an upper limit offset to the anchor read reference voltage, and a lower limit of the first scanning range is obtained by adding a lower limit offset to the anchor read reference voltage, and the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read reference offset of a second best read reference voltage with respect to the second default read reference voltage based on the first scanning range; and a method comprising the steps of:

2. The step of determining the first best read reference offset comprises: determining a second scanning range, wherein the second scanning range has an upper limit obtained by adding an upper limit offset to the first default read reference voltage and a lower limit obtained by adding a lower limit offset to the first default read reference voltage; scanning the second scanning range based on a coarse step voltage by performing a series of first single read operations within the second scanning range, wherein each first single read operation corresponds to a first read reference voltage and each first single read operation generates a bit count of either 1 or 0; for each first single read operation, when available, determining a first bit count difference between the bit counts of the first single read operation and the previous first single read operation, and when available, determining a second bit count difference between the bit counts of the first single read operation and the subsequent first single read operation; and a step of determining; Determining the first read reference voltage of the first single read operation among the series of first single read operations, where the sum of each of the first bit count differences and each of the second bit count differences has a minimum value, to be the rough best read reference voltage; The method according to claim 1, comprising: **Claim 3** When there are two or more first single read operations in which the sum of each of the first bit count differences and each of the second bit count differences has the same value, further comprising determining the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations, where the minimum value of each of the first bit count differences and each of the second bit count differences is to be the rough best read reference voltage; **Claim 4** Determining a third scanning range, where the third scanning range has an upper limit that is the sum of the rough best read reference voltage and the rough step voltage, and a lower limit that is the difference between the rough best read reference voltage and the rough step voltage; Scanning the third scanning range based on a fine step voltage by performing a series of second single read operations within the third scanning range, where each second single read operation corresponds to a second read reference voltage and each second single read operation generates a bit count of either 1 or 0; For each second single read operation, Determining, if available, a first bit count difference between the bit count of each second single read operation and the bit count of the previous second single read operation, and Determining, if available, a second bit count difference between the bit count of each second single read operation and the bit count of the subsequent second single read operation ; A step of determining, as the first optimal read reference voltage, the second read reference voltage of the second single-shot read operation having the minimum value among the series of second single-shot read operations, where the sum of each of the first bit count differences and each of the second bit count differences is the offset of the first optimal read reference voltage with respect to the first default read reference voltage being the first optimal read offset, and The method according to claim 2, further comprising.

5. Based on the first scanning range, the step of determining the second optimal read offset of the second optimal read reference voltage with respect to the second default read reference voltage is A step of scanning the first scanning range by performing a series of third single-shot read operations within the first scanning range, each third single-shot read operation corresponding to a third read reference voltage, and each third single-shot read operation generating a bit count of either 1 or 0, and For each of the third single-shot read operations If available, a first bit count difference between the bit count of each of the third single-shot read operations and the bit count of the previous third single-shot read operation, and If available, a second bit count difference between the bit count of each of the third single-shot read operations and the bit count of the subsequent third single-shot read operation And a step of determining A step of determining, as the second optimal read reference voltage, the third read reference voltage of the third single-shot read operation having the minimum value among the series of third single-shot read operations, where the sum of each of the first bit count differences and each of the second bit count differences is the offset of the second optimal read reference voltage with respect to the second default read reference voltage being the second optimal read offset, and The method according to claim 4, comprising.

6. The method according to claim 5, wherein the first single-shot read operation, the second single-shot read operation, and the third single-shot read operation are partial page read operations.

7. Collecting a first set of first best read offsets, each first best read offset being a voltage shift of a best read reference voltage from the first default read reference voltage, each first best read offset corresponding to a memory cell condition that causes a respective one of the first best read offsets to be applied to a set of memory cells, the first set of first best read offsets each having a positive or negative value; Setting the maximum value of the first set of first best read offsets to be the upper offset of the second scan range; Setting the minimum value of the first set of first best read offsets to be the lower offset of the second scan range The method of claim 2, further comprising.

8. Collecting a second set of second best read offsets, each second best read offset corresponding to one of the first set of first best read offsets and one of the respective memory cell conditions, each second best read offset being a voltage shift of a best read reference voltage from the second default read reference voltage, the second set of second best read offsets each having a positive or negative value; Determining the difference between each pair of the first best read offset and the respective second best read offset, the difference being equal to subtracting each first best read offset from the respective second best read offset; Setting the maximum value of the differences between each pair of the first best read offset and the respective second best read offset to be the upper offset of the first scan range; Setting the minimum value of the differences between each pair of the first best read offset and the respective second best read offset to be the lower offset of the first scan range The method of claim 7, further comprising.

9. Before the step of determining the first best read reference offset of the first best read reference voltage with respect to the first default read reference voltage, the method further includes a step of determining that error correction code (ECC) decoding processing has failed to read the page, according to the method of claim 1.

10. The method according to claim 1, further including a step of performing ECC software decoding processing to read the page from the set of MLCs based on the first best read reference voltage and the second best read reference voltage.

11. The method according to claim 1, wherein the first or second default read reference voltage corresponds to the default read reference voltage of the MLC.

12. A semiconductor memory device, determining a first best read reference offset of a first best read reference voltage with respect to a first default read reference voltage; determining an anchor read reference voltage having the same offset as the first best read reference offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading a page from a set of multi-level cells (MLCs) in the semiconductor memory device; determining a first scanning range based on the anchor read reference voltage, wherein an upper limit of the first scanning range is obtained by adding an upper limit offset to the anchor read reference voltage, and a lower limit of the first scanning range is obtained by adding a lower limit offset to the anchor read reference voltage, and the upper limit offset and the lower limit offset are positive or negative voltage values; determining a second best read reference offset of a second best read reference voltage with respect to the second default read reference voltage based on the first scanning range A memory control device comprising a circuit configured to perform the above operations A memory system comprising the same.

13. The circuit determining a second scanning range, wherein the second scanning range has an upper limit obtained by adding an upper limit offset to the first default read reference voltage and a lower limit obtained by adding a lower limit offset to the first default read reference voltage. Performing a series of first single read operations within the second scanning range to scan the second scanning range based on a coarse step voltage, wherein each first single read operation corresponds to a first read reference voltage and each first single read operation generates a bit count of either 1 or 0, and scanning; For each of the first single read operations, when available, a first bit count difference between the bit count of each of the first single read operations and the bit count of the previous first single read operation, and when available, a second bit count difference between the bit count of each of the first single read operations and the bit count of the subsequent first single read operation are determined; determining the first read reference voltage of the first single read operation having the minimum value among the series of first single read operations such that the sum of each of the first bit count differences and each of the second bit count differences becomes the coarse best read reference voltage; The memory system according to claim 12, further configured to perform the above.

14. The circuit is when there are two or more first single read operations in which the sum of each of the first bit count differences and each of the second bit count differences has the same value, the minimum value of each of the first bit count differences and each of the second bit count differences is such that the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations is determined to be the coarse best read reference voltage. The memory system according to claim 13, further configured as above.

15. The circuit is determining a third scanning range, wherein the third scanning range has an upper limit which is the sum of the coarse best read reference voltage and the coarse step voltage and a lower limit which is the difference between the coarse best read reference voltage and the coarse step voltage, and determining; By performing a series of second single read operations within the third scan range, scanning the third scan range based on a fine step voltage, where each second single read operation corresponds to a second read reference voltage and each second single read operation generates a bit count of either 1 or 0, the scanning; For each second single read operation, When available, a first bit count difference between the bit count of each said second single read operation and the bit count of the previous second single read operation, and When available, a second bit count difference between the bit count of each said second single read operation and the bit count of the subsequent second single read operation To determine; Determining the second read reference voltage of the second single read operation having the minimum value among the series of second single read operations as the first best read reference voltage such that the offset of the first best read reference voltage with respect to the first default read reference voltage is the first best read offset, the determining; The memory system according to claim 13, further configured to perform.

16. A non - transitory computer - readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising: Determining a first best read offset of a first best read reference voltage with respect to a first default read reference voltage; Determining an anchor read reference voltage having the same offset as the first best read offset with respect to a second default read reference voltage, wherein the first default read reference voltage and the second default read reference voltage are set for reading pages from a set of multi - level cells (MLCs) in a semiconductor memory device; A step of determining a first scanning range based on the anchor reading reference voltage, wherein an upper limit of the first scanning range is obtained by adding an upper limit offset to the anchor reading reference voltage, a lower limit of the first scanning range is obtained by adding a lower limit offset to the anchor reading reference voltage, and the upper limit offset and the lower limit offset are positive voltage values or negative voltage values, the step and A step of determining a second best reading offset of the second best reading reference voltage with respect to the second default reading reference voltage based on the first scanning range A non-transitory computer-readable medium including

17. The step of determining the first best reading offset A step of determining a second scanning range, wherein the second scanning range has an upper limit obtained by adding an upper limit offset to the first default reading reference voltage and a lower limit obtained by adding a lower limit offset to the first default reading reference voltage, the step and A step of scanning the second scanning range based on a coarse step voltage by performing a series of first single-read operations within the second scanning range, wherein each first single-read operation corresponds to a first reading reference voltage, and each first single-read operation generates a bit count of either 1 or 0, the step and For each first single-read operation If available, a first bit count difference between the bit count of each first single-read operation and the bit count of the previous first single-read operation, and If available, a second bit count difference between the bit count of each first single-read operation and the bit count of the subsequent first single-read operation The step of determining The step of determining the first reading reference voltage of the first single-read operation having the minimum value among the series of first single-read operations as the coarse best reading reference voltage based on the sum of each first bit count difference and each second bit count difference The non-transitory computer-readable medium according to claim 16, including

18. The method When there are two or more first single read operations in which the sum of each of the first bit count differences and each of the second bit count differences has the same value, the minimum value of each of the first bit count differences and each of the second bit count differences is the first read reference voltage of the first single read operation having the minimum value among the two or more first single read operations. The non-transitory computer-readable medium according to claim 17, further comprising a step of determining so as to be the rough best read reference voltage.

19. The method includes a step of determining a third scanning range, wherein the third scanning range has an upper limit which is the sum of the rough best read reference voltage and the rough step voltage, and a lower limit which is the difference between the rough best read reference voltage and the rough step voltage. a step of scanning the third scanning range based on a fine step voltage by performing a series of second single read operations within the third scanning range, each second single read operation corresponding to a second read reference voltage, and each second single read operation generating a bit count of either 1 or 0. For each second single read operation, when available, a first bit count difference between the bit count of each of the second single read operations and the bit count of the previous second single read operation, and when available, a second bit count difference between the bit count of each of the second single read operations and the bit count of the subsequent second single read operation are determined. a step of determining the second read reference voltage of the second single read operation having the minimum value among the series of second single read operations such that the sum of each of the first bit count differences and each of the second bit count differences is the minimum value, wherein the offset of the first best read reference voltage with respect to the first default read reference voltage is the first best read offset. The non-transitory computer-readable medium according to claim 17, further comprising.

20. Based on the first scanning range, the step of determining the second best read reference offset of the second best read reference voltage with respect to the second default read reference voltage is: Scanning the first scanning range by performing a series of third single read operations within the first scanning range, each third single read operation corresponding to a third read reference voltage, and each third single read operation generating a bit count of either 1 or 0; For each third single read operation, When available, a first bit count difference between the bit count of each third single read operation and the bit count of the previous third single read operation, and When available, a second bit count difference between the bit count of each third single read operation and the bit count of the subsequent third single read operation Determining; Determining the third read reference voltage of the third single read operation having the minimum value among the series of third single read operations as the second best read reference voltage, such that the offset of the second best read reference voltage with respect to the second default read reference voltage is the second best read offset; A non-transitory computer-readable medium according to claim 19, comprising.

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