3D NOR Memory String Array of Thin Film Ferroelectric Transistors

Abstract

The memory structure of the present disclosure includes storage transistors configured as horizontal NOR memory strings, where the storage transistors are thin-film ferroelectric field effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent to a semiconductor channel. In some embodiments, the semiconductor channel is formed of an oxide semiconductor material, and the ferroelectric storage transistors are junctionless transistors that do not have a p / n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, where the first conductive layer and the second conductive layer are electrically connected to the semiconductor channel. The ferroelectric storage transistors in multiple NOR memory strings are arranged to form a semi-autonomous three-dimensional memory array (tile), where each tile is individually addressed and controlled by circuitry in the semiconductor substrate below each tile in cooperation with a memory controller.

Description

Technical Field

[0001] The present invention relates to high-density memory structures. In particular, the present invention relates to high-density and low read latency memory structures formed by interconnected thin-film memory elements (e.g., three-dimensional arrays of thin-film storage transistors), including those configured as NOR-type memory strings (“NOR memory strings”).

Background Art

[0002] A NOR-type memory string includes storage transistors that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. U.S. Patent No. 10,121,553 (Patent Document 1) titled "Capacitively Coupled Nonvolatile Thin Film Transistor NOR String in a Three-Dimensional Array" issued on November 6, 2018 discloses storage transistors or memory transistors configured as a three-dimensional array of NOR memory strings formed on the upper side of the plane of a semiconductor substrate. Patent Document 1 is hereby incorporated by reference in its entirety for all purposes. In Patent Document 1, a NOR memory string includes a number of thin film storage transistors that share a common bit line and a common source line. In particular, Patent Document 1 discloses a NOR memory string including (i) a common source region and a common drain region extending longitudinally along the horizontal direction and (ii) gate electrodes of each storage transistor extending along the vertical direction. In Patent Document 1, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to a direction parallel to the surface of the semiconductor substrate. In a three-dimensional array, the NOR memory strings are provided on a plurality of planes (e.g., 8 or 16 planes) above the semiconductor substrate, and the NOR memory strings on each plane are arranged in columns. In the case of a charge trap type storage transistor, data is stored in a charge storage film within each storage transistor. For example, the charge storage film can include a tunnel dielectric layer, a charge trap layer, and a blocking layer, and can be realized as a multilayer film with silicon oxide, silicon nitride, and silicon oxide arranged in this order, and is referred to as an ONO layer. An electric field applied across the entire charge storage film adds or removes charges to the charge traps in the charge trap layer, changes the threshold voltage of the storage transistor, and encodes a given logic state in the storage transistor.

[0003] Advances in electrically polarizable materials ("ferroelectric materials"), particularly materials used in semiconductor manufacturing processes, suggest new potential applications for ferroelectric memory circuits. For example, the document "Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors," by T.S. Boscke et al., published in the 2011 International Electron Devices Meeting (IEDM), pp. 24.5.1-24.5.4, discloses a ferroelectric field effect transistor (FeFET) that uses hafnium oxide as a gate dielectric material. By controlling the polarization direction of the ferroelectric gate dielectric layer, the FeFET can be programmed to have either of two threshold voltages. Each threshold voltage of the FeFET constitutes a state representing a specified logical value, such as, for example, a "program" state or an "erase" state. Such FeFETs can be applied to high-density memory circuits. For example, U.S. Patent Application No. 13 / 897,037 (U.S. Patent No. 9,281,044) (Patent Document 2) titled "Apparatus Having a Ferroelectric Field Effect Transistor Memory Array and Related Methods," filed on May 17, 2013, discloses a three-dimensional array of FeFETs.

[0004] However, conventional FeFETs have had the problem of low durability. For example, the paper "Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory," by K. Florent et al., published in the 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 2.5.1-2.5.4, discloses that the durability is 10 4 cycles. Such low durability makes the memory circuit substantially unsuitable for many memory applications.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Means for Solving the Problems

[0006] According to the present disclosure, there is provided a three-dimensional memory structure formed on a plane of a semiconductor substrate, including a plurality of stacks of thin-film ferroelectric field-effect transistors (FeFETs) configured as a plurality of stacks of NOR memory strings extending along a first direction substantially parallel to the plane of the semiconductor substrate. Each stack of NOR memory strings is provided in a stacked manner along a second direction substantially orthogonal to the plane. Each thin-film ferroelectric field-effect transistor (FeFET) of each NOR memory string shares a common source layer and a common drain layer extending along the first direction.

[0007] In some embodiments, each stack of NOR memory strings includes a plurality of pairs of memory strings formed in a stacked manner along the second direction, and each pair of memory strings is insulated from other pairs of memory strings by a first insulating layer. Each pair of memory strings includes a first common drain layer, a first common source layer, and a second common drain layer, and each layer is spaced apart from each other in the second direction by a second insulating layer. Each pair of memory strings is composed of a first NOR memory string formed by the first common drain layer and the first common source layer, and a second NOR memory string formed by the second common drain layer and the first common source layer.

[0008] The memory structure of the present disclosure further includes a semiconductor layer provided adjacent to each stack of the NOR memory string and in contact with the common source layer and the common drain layer of each stack. A semiconductor layer provided between the common source layer and the common drain layer adjacent to each other in the second direction forms a channel region for a thin-film ferroelectric field-effect transistor (FeFET) of each NOR memory string. Further, the memory structure of the present disclosure further includes a ferroelectric gate dielectric layer provided adjacent to the semiconductor layer and along the second direction. Further, the memory structure of the present disclosure further includes a plurality of conductors provided adjacent to the ferroelectric gate dielectric layer between adjacent stacks of the NOR memory string and along the second direction. Each conductor functions as a common gate electrode for each thin-film ferroelectric field-effect transistor (FeFET) of the NOR memory strings of adjacent stacks. In some embodiments, the memory structure of the present disclosure further includes an interface layer provided between the ferroelectric gate dielectric layer and the semiconductor layer that forms the channel.

[0009] In some embodiments, the ferroelectric gate dielectric layer includes a ferroelectric polarization layer provided as a continuous layer adjacent to each conductor in the second direction.

[0010] In yet another embodiment, it is provided as a continuous layer along the sidewalls of each stack of the NOR memory string.

[0011] In some embodiments, the ferroelectric gate dielectric layer is formed from a doped hafnium oxide material, and the semiconductor layer forming the channel region is an oxide semiconductor layer formed from an amorphous oxide semiconductor material.

[0012] In some embodiments, the first common drain layer, the second common drain layer, and the first common source layer are formed from a partial or substantially metal conductor material.

[0013] The above and other advantages, aspects, and novel features of the present invention, as well as the details of its illustrated embodiments, will be more fully understood by reference to the following description and the accompanying drawings.

Brief Description of the Drawings

[0014] Various embodiments of the present invention are disclosed in the following detailed description and the accompanying drawings. Although various examples of the present invention are depicted in the drawings, the present invention is not limited by the depicted examples. In the drawings, it should be understood that like reference numerals indicate like structural elements. Also, the depictions in the figures are not necessarily drawn to scale.

[0015]

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DETAILED DESCRIPTION OF THE INVENTION

[0016] According to an embodiment of the present invention, the memory structure of the present disclosure includes a storage transistor configured as a horizontal NOR memory string, and the storage transistor is a thin-film ferroelectric field-effect transistor (FeFET) having a ferroelectric gate dielectric layer formed adjacent to an oxide semiconductor channel region. The ferroelectric storage transistor thus formed is a junctionless transistor that does not have a p / n junction in the channel and in which the mobile carrier density in the channel is modulated by the polarization of the ferroelectric gate dielectric layer. In an embodiment of the present invention, the ferroelectric storage transistors in each NOR memory string share a first conductive layer that functions as a common source line and a second conductive layer that functions as a common bit line, and the first conductive layer and the second conductive layer are electrically connected to the oxide semiconductor channel region. The ferroelectric storage transistors in the NOR memory string are controlled by individual control gate electrodes, and each storage transistor can be individually addressed and accessed. In some embodiments, the ferroelectric gate dielectric layer is formed from a doped hafnium oxide material, and the oxide semiconductor channel region is formed from an amorphous oxide semiconductor material.

[0017] In some embodiments, the memory structure of the present disclosure includes a plurality of NOR memory strings configured as a three-dimensional array to form a high-density memory structure. The three-dimensional array of NOR memory strings is configured as a stack of NOR memory strings in a first direction, and the NOR memory strings are formed overlapping each other in the stack in the first direction. Also, the three-dimensional array of NOR memory strings is configured as a column of NOR memory strings in a second direction forming a plane, and the columns of NOR memory strings are arranged in one or more parallel planes in the first direction. In some embodiments, a pair of adjacent NOR memory strings in the stack share a common source line. The voltage on each shared common source line can be directly applied separately from one or both ends of each source line in the three-dimensional structure. In some embodiments, the shared common source line is electrically floating, and the source voltage is applied from the through-bit line using a precharge transistor to alleviate the congestion of the connector lines at the end staircase of the bit line / source line in the three-dimensional structure. Further, in some embodiments, the oxide semiconductor channel region is formed as a continuous layer at least in a first direction across a plurality of NOR memory strings formed in the stack. In this way, the NOR memory strings can be constructed using a simplified manufacturing process step that reduces the aspect ratio for anisotropic etching of trenches through multiple layers of the memory strings, resulting in a compact-sized and high-density memory structure.

[0018] The ferroelectric storage transistor described in this specification provides high durability, long-term data retention, and relatively low voltage operation in both the erase operation (less than 5.0 volts) and the programming (e.g., less than -5.0 volts) operation. By combining the ferroelectric or polarization characteristics with a three-dimensional structure (e.g., as a thin film NOR memory string described in this specification), the memory structure of the ferroelectric storage transistor of the present invention can achieve the advantages of the low read latency of a high-speed random access memory circuit and the additional advantages of a high-density and low-cost memory array. The above and other advantages of the memory structure of the present invention will be further described below.

[0019] In this description, for ease of reference to the drawings, as shown in the figures, a Cartesian coordinate reference system is used in which the Z direction is orthogonal to the plane of the semiconductor surface, and the X and Y directions are orthogonal to the Z direction.

[0020] Furthermore, the drawings provided in this specification are idealized depictions for explaining the embodiments of the present disclosure and are not intended to be actual depictions of specific components, structures, or devices. The drawings are not drawn to scale, and the thicknesses and dimensions of some layers may be exaggerated for clarity. Deformations from the illustrated shapes are also expected. For example, regions illustrated as box-shaped may generally have rough and / or non-linear features. The sharp angles illustrated may be rounded. Like reference numerals refer to like components throughout.

[0021] Memory structure

[0022] FIG. 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in an embodiment of the present invention. The memory structure of the present disclosure can be used, in some examples, to implement a part of a semiconductor memory device. Referring to FIG. 1, the memory structure 10 includes a number of alternately stacked conductive layers and insulating layers formed on the plane of a semiconductor substrate 12. For example, in some embodiments, the insulating layer can be an insulating dielectric layer. In the present specification, a combination of a pair of conductive layers and an insulating layer sandwiched therebetween is referred to as an active layer 11. A buffer layer 14 may be provided between the semiconductor substrate 12 and the active layer 11 formed on the semiconductor substrate 12. In some embodiments, the buffer layer 14 can be a silicon oxycarbide (SiOC) layer or a silicon dioxide (SiO2) layer. The active layer 11 including alternately stacked conductive layers and insulating layers is formed by stacking in the Z direction (i.e., along the direction perpendicular to the plane of the semiconductor substrate 12). The active layer 11 is divided in the X direction into narrow strips (“active strips”) 24, and these narrow strips (active strips) 24 are stacked to form a stack of active strips (“active stack”) extending in the Y direction. Each active strip 24 thus formed forms a NOR memory string of a ferroelectric storage transistor 20 extending in the Y direction.

[0023] Each active layer 11 includes a first conductive layer 16 that functions as a common bit line of the NOR memory string and a second conductive layer 18 that functions as a common source line of the NOR memory string. In some embodiments, the first conductive layer 16 and the second conductive layer 18 are separated by an insulating layer 17 that can be a dielectric layer. For example, in some embodiments, the insulating layer 17 can be a silicon oxide layer. In the memory structure shown in FIG. 1, eight active layers 11 (11-0 to 11-7) are provided. A remarkable feature of the memory structure 10 of the present disclosure is that in a memory structure having N active layers, a pair of adjacent active layers 11 share a common source line 18. As a result, a memory structure having N active layers includes N common bit lines but only N / 2 common source lines. For example, a pair of adjacent active layers 11-0 and 11-1 includes (i) a first conductive layer 16a that forms a common bit line of the first NOR memory string, (ii) an insulating layer 17a, (iii) a second conductive layer 18 that forms a common source line of the first NOR memory string and the second NOR memory string, (iv) an insulating layer 17b, and (v) a first conductive layer 16b that forms a common bit line of the second NOR memory string. With such a configuration, in the memory structure 10 of the present disclosure, a pair of adjacent active layers forms a pair of NOR memory strings that share a common source line 18. A pair of adjacent active layers is separated from other pairs of active layers by an insulating layer 15 such as an insulating dielectric layer.

[0024] Subsequent processing steps form an oxide semiconductor channel region 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28 within the narrow trench 22 between the active stacks separated from each other. Another notable feature of the memory structure 10 of the present disclosure is that each oxide semiconductor channel region 25 is formed as a continuous layer along the sidewalls of the active stack, sandwiching a plurality of NOR memory strings of the active stack in the X direction. In some embodiments, each oxide semiconductor channel region 25 is a continuous layer along the sidewalls of a pair of adjacent active stacks sharing the narrow trench 22. The oxide semiconductor channel region 25 is insulated from another oxide semiconductor channel region 25 formed in another narrow trench 22.

[0025] In an embodiment of the present invention, the gate electrode 28 and the ferroelectric gate dielectric layer 26 are formed as columnar structures extending in the Z direction. In this embodiment, the ferroelectric gate dielectric layer 26 surrounds the gate electrode 28 to form a columnar structure. In this specification, the gate electrode 28 is also referred to as a "local word line", and the combination of the gate electrode 28 and the ferroelectric gate dielectric layer 26 surrounding it is collectively referred to as a "local word line (LWL) structure". The local word line structures (LWL structures) formed in each trench 22 are insulated from each other by the dielectric material 23. The ferroelectric storage transistor 20 is formed at the intersection of the active strip 24, the oxide semiconductor channel region 25, and the LWL structure. Therefore, the ferroelectric storage transistors 20 are formed on both sides of the active strip 24. In the memory structure shown in FIG. 1, the LWL structures are formed alternately (in a staggered manner) in adjacent trenches 22 such that the ferroelectric storage transistors 20 formed on both sides of the active strip are offset from each other in the Y direction along the NOR memory string. In particular, the insulating layer 15 between a pair of NOR memory strings (active strip 24), and the insulating layers 17a and 17b between the adjacent common source lines 18 and common bit lines 16 provide insulation for separating the ferroelectric storage transistors 20 formed on both sides of the same active strip 24. With such a configuration, the ferroelectric storage transistors 20 sharing the common source line 18 and the common bit line 16 form a NOR memory string (also referred to as a "horizontal NOR memory string" or "HNOR memory string") along each active strip 24 (in the Y direction).

[0026] In the three-dimensional array of NOR memory strings formed in this way, the ferroelectric storage transistor 20 is a junctionless transistor that does not include a p / n junction as a drain region or a source region in the channel. Instead, the first conductive layer 16 (common bit line) functions as the drain region of the ferroelectric storage transistor 20, and the second conductive layer 18 functions as the source region of the ferroelectric storage transistor 20. Accordingly, the NOR memory string includes ferroelectric storage transistors 20 that share a common drain region (common bit line 16) and a common source region (common source line 18).

[0027] In some embodiments, the first conductive layer 16 and the second conductive layer 18 are each formed using a metal layer or a low-resistivity metal conductive material such as molybdenum (Mo), tungsten (W), tungsten nitride (WN), ruthenium, or a titanium tungsten alloy (TiW). In some embodiments, the insulating layer 15 and the insulating layer 17 may be formed as a silicon oxide layer (SiO2). In other embodiments, the insulating layer 15 may be formed of another insulating dielectric material such as silicon nitride. In some embodiments, the ferroelectric gate dielectric layer may be formed from a doped hafnium oxide material such as zirconium-doped hafnium oxide (HfZrO or "HZO"). In some embodiments, hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the oxide semiconductor channel region is formed of an amorphous oxide semiconductor material such as indium gallium zinc oxide (IGZO).

[0028] To complete the memory circuit, various types of circuits that support the memory operation of the HNOR memory string are formed inside or on the surface of the semiconductor substrate 12. Such circuits are referred to as "circuits under the array" ("CuA") and may include analog circuits and digital circuits. For example, the memory operation may include a read operation and a write operation. In this specification, the write operation to the memory circuit includes an erase operation and a program operation, and refers to changing the polarization state or polarization direction of the ferroelectric gate dielectric layer 26 from one polarization state to another. Further, in some embodiments, the memory operation includes a refresh operation. In some embodiments, the circuits under the array support the memory operations of the memory circuit, such as an erase operation, a program operation, a read operation, and a refresh operation.

[0029] In some embodiments, the circuits under the array include various voltage sources or voltage generators for generating operating voltages such as a power supply voltage, a ground voltage, a programming voltage, an erase voltage, a read voltage, or a reference voltage. The circuits under the array may further include a word line driver circuit, a bit line driver circuit, and an input / output driver circuit. The circuits under the array may further include an address decoder for decoding an address signal for selecting a specified storage transistor, a sense amplifier for reading data stored from the selected storage transistor, latches and registers such as shift registers, or other memory elements. The circuits under the array may further include various logic circuits such as inverters, NAND, NOR, exclusive OR, and other logic gates. In some embodiments, the circuits under the array include a state machine, a microsequencer, and a data processing circuit. For example, in one embodiment, the circuits under the array include a state machine for managing the memory operations (e.g., read operation, erase operation, program operation, and refresh operation) in the memory circuit.

[0030] In some embodiments, the other conductive layer may be disposed above or below the memory structure 10 to supply control signals, such as word line signals, to the array of ferroelectric storage transistors 20. In some embodiments, the conductive layer may be arranged to connect the under-array circuitry to the common bit lines of the NOR memory string and the local word lines that support the memory operation. In one embodiment, the conductive layer may be provided to route control signals and data signals between the NOR memory string and the under-array circuitry. With such a configuration, the under-array circuitry supports the memory operation of the NOR memory string and autonomously performs the erase, program, and read operations of the NOR memory string in response to the erase, program, and read commands provided to the memory structure 10. In one example, the write operation to the ferroelectric storage transistor 20 includes an erase operation and a subsequent program operation.

[0031] In some embodiments, the memory structure 10 is connected to a memory controller that is a separate semiconductor substrate and is electrically connected using one or more integration techniques such as hybrid bonding, TSV, exposed contacts, and other suitable interconnection techniques. The memory controller typically provides commands such as erase, program, and read commands, along with accompanying information such as memory cell addresses and write data for write operations, to the under-array circuitry. The memory structure 10 uses the under-array circuitry to autonomously perform memory operations in response to the received commands.

[0032] In embodiments of the present disclosure, the memory structure 10 represents a modular memory unit referred to as a "tile", and the memory device is formed using an array of modular memory units. In an exemplary embodiment, the memory device is configured as a two-dimensional array of tiles, and each tile includes a three-dimensional array of ferroelectric storage transistors having support circuitry for each tile formed thereunder. More specifically, the support circuitry for the ferroelectric storage transistors of each tile is provided for modularization in a portion of the semiconductor substrate under each tile. In this way, each modular memory unit (or tile) operates semi-autonomously to perform memory operations such as erase, program, read, and refresh operations. As a result, the memory device includes an array of tiles, and each tile can be individually addressed and controlled by an array-under circuit (CuA) formed under each tile. In particular, each tile of the tile array can perform memory operations on multiple tiles simultaneously and access them independently by means of the tile-based CuA provided for each tile. In some embodiments, the tile-based array-under circuit (CuA) is formed on the semiconductor substrate using a first manufacturing process, and then the semiconductor substrate on which the tile-based support circuitry is formed thereon is subjected to a second manufacturing process for forming thin-film storage transistors.

[0033] A memory module is formed by connecting a memory device to a memory controller. The memory controller may be a controller integrated circuit, also referred to as a "chiplet". Alternatively, the memory controller may be incorporated or implemented in a general-purpose integrated circuit (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The memory controller implements the management functions of the memory device. In some embodiments, the memory controller provides commands such as startup, read, erase, program, commit, and refresh, and accompanying command information such as memory addresses and write data, to the memory device. Also, the memory controller can provide a memory interface for host access and a host interface function that implements other system functions, if applicable. The memory controller operates in cooperation with the underlying circuit of each tile, enabling semi-autonomous memory operations in each tile and simultaneous memory operations for a large number of tiles. The memory device formed by the tile array realizes a high-speed large-capacity memory with a parallel access function to the storage transistors of multiple tiles.

[0034] In the embodiment shown in FIG. 1, the memory structure 10 includes an oxide semiconductor channel region 25 formed as a continuous layer in the Y direction along the sidewalls of the active stack of the NOR memory string (active strip 24). In other embodiments, as shown in FIG. 2, the oxide semiconductor channel regions 25 may be separated from each other between adjacent local word line (LWL) structures. FIG. 2 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in another embodiment of the present invention. Similar elements in FIGS. 1 and 2 are given similar reference numerals for simplicity of explanation. Referring to FIG. 2, the memory structure 30 is configured substantially the same as the memory structure 10 of FIG. 1, except for the formation of the oxide semiconductor channel region 25. In the memory structure 30, the oxide semiconductor channel regions 25 formed in the narrow trenches 22 are separated or unified by each LWL structure, as indicated by the dotted circle 32. That is, the oxide semiconductor channel regions 25 are provided so as to be adjacent only to the columnar structures composed of the ferroelectric gate dielectric layer 26 and the gate electrode 28. The oxide semiconductor channel regions 25 are removed between adjacent LWL structures, thereby removing parasitic devices that may be formed in the regions between the LWL structures.

[0035] FIG. 3 is a partial cross-sectional view of the memory structure of FIG. 1 including a three-dimensional array of NOR memory strings in an embodiment of the present invention. Similar elements in FIGS. 1 and 3 are given similar reference numerals for simplicity of explanation. Referring to FIG. 3, the memory structure 10 includes a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed on a semiconductor substrate (omitted for simplicity in FIG. 3). In this embodiment, the active stacks of a pair of NOR memory strings (active strips 24) adjacent to the same narrow trench 22 share a common oxide semiconductor channel region 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28 in each local word line (LWL) structure. That is, the oxide semiconductor channel region 25 is continuous along the bottom of the narrow trench 22. In adjacent narrow trenches 22, the oxide semiconductor channel region 25 formed in one narrow trench 22 is insulated from the oxide semiconductor channel region 25 formed in the other narrow trench 22. Each active stack 24 has ferroelectric storage transistors 20 formed on both sides of the active stack 24. When the LWL structures are staggered (in a checkerboard pattern) in the Y direction, in adjacent narrow trenches 22, the ferroelectric storage transistors 20 are formed offset from each other in the Y direction so as not to face each other in the X direction. The dielectric material 23 is formed in the trench 22 between the LWL structures.

[0036] The oxide semiconductor channel region realizes many advantages in the three-dimensional array of the NOR memory strings of the present invention. First, the oxide semiconductor channel region generally has high mobility, high switching performance, and no concern about electron or hole tunneling. Second, the storage transistors of the NOR memory strings having an oxide semiconductor channel region become junctionless transistors, thereby eliminating the need to provide polysilicon source-drain layers in the memory structure. As a result, the stack height of the three-dimensional array of NOR memory strings is significantly reduced as compared with a conventional memory array having the same number of planar or layers of NOR memory strings. Further, in an embodiment of the present invention, the stack height of the NOR memory strings is further reduced by sharing a common source line between adjacent active layers. As a result, a high-density and compact memory structure is realized.

[0037] In the memory structure 10, each pair of active layers (in the Z direction) includes a first common bit line (first conductive layer 16a) and a common source line (second conductive layer 18) separated from each other by an insulating layer 17a, and a second common bit line (first conductive layer 16b) separated from the common source line 18 by an insulating layer 17b, thereby forming a first NOR memory string and a second NOR memory string. Each pair consisting of the first NOR memory string and the second NOR memory string is separated from other pairs in the Z direction by an insulating layer 15.

[0038] In this embodiment, the insulating layer 15 has a thickness of d1 in the Z direction, and the insulating layers 17a and 17b have a thickness of d2 in the Z direction. The thickness d1 is selected so as to sufficiently insulate adjacent common bit lines of the active stack. The thickness d2 between the common bit line and the common source line defines the channel length of the ferroelectric storage transistor 20. In this embodiment, the first conductive layer 16 and the second conductive layer 18 have the same thickness d3 in the Z direction. In other embodiments, the first conductive layer 16 and the second conductive layer 18 have different thicknesses in the Z direction. Further, in this embodiment, the oxide semiconductor channel region 25 has a thickness d4 in the X direction between the ferroelectric gate dielectric layer 26 and the source line / bit line of the active stack 24, and the depth of the channel region is defined by the thickness d4.

[0039] In some embodiments, the thickness d1 is in the range of 30 to 50 nm, and in one example, it has a value of 30 nm. In some embodiments, the thickness d2 is in the range of 30 to 80 nm, and in one example, it has a value of 50 nm. In some embodiments, the thickness d3 is in the range of 30 to 40 nm, and in one example, it has a value of 40 nm. In one embodiment, the stack height of a pair of adjacent NOR memory strings is 250 nm. A memory structure including a stack of eight NOR memory strings can be formed with a stack height of only 1000 nm, and the stack height is significantly reduced as compared with a conventional memory structure formed using, for example, a polysilicon channel. The reduction in the stack height has the effect of reducing the aspect ratio of the etching process for forming narrow trenches between the active stacks during the manufacturing process, as will be described in more detail below.

[0040] In some embodiments, the oxide semiconductor channel region 25 has a thickness d4 of 8 to 15 nm in the X direction. In one example, the oxide semiconductor channel region 25 has a thickness of 10 nm. In some embodiments, the ferroelectric gate dielectric layer 26 has a thickness of 3 to 7 nm in the X direction. In one example, the ferroelectric gate dielectric layer 26 has a thickness of 4 nm. In some embodiments, the active stack 24 has a width of 60 nm in the X direction, and the narrow trench in which the LWL structure is formed has a width of 70 nm in the X direction. In some embodiments, the gate electrode has a thickness of about 55 nm in the X direction. In this specification, the dimensions are provided for illustrative purposes only and are not intended to be limiting. In actual implementation, any suitable thickness or dimension may be used.

[0041] In the memory structure 10 of FIG. 3, the three-dimensional array of NOR memory strings includes ferroelectric storage transistors 20 formed at both side ends along the length (Y direction) of each active strip 24, and the vertical local word lines 28 are alternately (in a staggered pattern) arranged in the Y direction along both side ends. By sharing each vertical local word line 28 between adjacent active stacks, high density is achieved. Each vertical local word line 28 functions as a gate electrode for the ferroelectric storage transistors 20 aligned in the vertical direction of the active strip 24 of each active stack. The vertical local word lines 28 can be connected to each other by an interconnect conductor 42 (also referred to as a "global word line") provided above or below the three-dimensional array of NOR memory strings. In one embodiment, the global word line 42 extends along a lateral direction (X direction) orthogonal to the length direction (Y direction) of the connected active strip 24. The global word line 42 connects the local word lines 28 to a support circuit, such as a word line driver circuit, formed in the array undercircuit (CuA) of the semiconductor substrate 12.

[0042] Memory Circuit and Operation

[0043] FIG. 4 is a circuit diagram of a three-dimensional array of NOR memory strings in an embodiment of the present invention. In particular, FIG. 4 shows a part of a NOR memory string that can be constructed from the memory structure described with reference to FIGS. 1 to 3. Referring to FIG. 4, the memory array 90 includes ferroelectric storage transistors 92 disposed in a NOR memory string 95 that includes NOR memory strings 95-0 to 95-5. Each NOR memory string 95 includes ferroelectric storage transistors 92 connected across a common bit line BL94 (e.g., BLk to BLk+5) and a common source line SL96 (e.g., SLm to SLm+2), and each ferroelectric storage transistor 92 of each NOR memory string 95 is controlled by a respective word line WL98 (e.g., WLn to WLn+6). More specifically, each ferroelectric storage transistor 92 in the NOR memory string 95 has a gate terminal connected to the word line WL98, a drain terminal connected to the bit line BL94, and a source terminal connected to the source line SL96.

[0044] The memory array 90 includes NOR memory strings formed in an active stack, and each of the NOR memory strings 95-0 to 95-5 is disposed on a different plane of the three-dimensional memory structure. Ferroelectric storage transistors 92 in a column across multiple NOR memory strings are controlled by a common word line WL98, also referred to as a local word line or LWL. FIG. 4 shows a part of a NOR memory string that includes ferroelectric storage transistors 92 connected to word lines WLn to WLn+6. In practice, the memory array may be provided with thousands of word lines (e.g., 4096 word lines), and as a result, the NOR memory string may be provided with thousands of randomly accessible ferroelectric storage transistors. The memory array 90 includes a control circuit for controlling read, write, and refresh operations of the memory array. For example, the control circuit can be formed on a semiconductor substrate 12 under the memory array as shown in FIG. 1, and is referred to as a circuit under array or CuA.

[0045] In the memory array 90, adjacent NOR memory strings 95 share a common source line SL. For example, NOR memory strings 95-0 and 95-1 share a common source line SLm, and NOR memory strings 95-2 and 95-3 share a common source line SLm+1. By sharing a common source line between adjacent pairs of NOR memory strings, it is possible to reduce the number of conductive layers for forming an active stack compared to the case where each NOR memory string has its own common source line. In other embodiments, the memory array may be constructed by each NOR memory string 95 having its own common source line and common bit line without sharing the common source line with another NOR memory string.

[0046] In some embodiments, the memory array 90 may be composed of memory pages, where a memory page refers to a group of storage transistors that are accessed together for read and write operations. In this embodiment, the memory page 97 is arranged in columns across multiple planes of the memory array 90 and includes storage transistors that share a common word line 98. That is, the memory page 97 includes storage transistors within the active stack of NOR memory strings 95-0 to 95-5 connected to the same word line 98 (e.g., word line WLn). In an actual implementation, the memory page may be associated with the same continuous oxide semiconductor channel and include one or more columns of ferroelectric storage transistors 92 across multiple planes of NOR memory strings that share the same word line.

[0047] In the memory array 90, the source line 96 is electrically floating, that is, the source line 96 is not directly connected to any potential. In practice, for example, the source line 96 maintains a relatively constant voltage through the parasitic capacitance of the source terminal, such as the parasitic capacitance between the source terminal and the gate terminal of the storage transistor. More specifically, the parasitic capacitance specific to each NOR memory string (for example, the distributed capacitance between the common source terminal of the NOR memory string and its plurality of local word lines) may be used as a virtual voltage source that provides a common power supply voltage under certain operating conditions. In this description, the source line 96 may be referred to as being connected to virtual ground. In some examples, the power supply voltage may be set to a desired voltage value through a precharge operation, and the source line may be left floating after the precharge operation. In one embodiment, the precharge operation sets the common bit line to a desired voltage, then instantaneously turns on the precharge transistor to short the common bit line to the common source line, and transfers the bit line voltage to the source line. As a result, the common source line is charged to a voltage equal to the voltage supplied to the bit line from the voltage of the common bit line. When the precharge operation is completed, the precharge transistor is turned off. The common source line maintains a relatively constant voltage through the parasitic capacitance of the source terminal, such as the parasitic capacitance between the source terminal and the gate terminal of the storage transistor of the NOR memory string. In other embodiments, a predetermined potential, such as a ground voltage, may be supplied to the source line 96 by a voltage source.

[0048] In an embodiment of the present invention, the ferroelectric storage transistor 92 is a thin-film ferroelectric field-effect transistor. More specifically, a ferroelectric field-effect transistor (also referred to as FeFET) is formed by using a ferroelectric material as a gate dielectric layer between a gate conductor (usually a metal layer) and a channel of the field-effect transistor. In some embodiments, the ferroelectric storage transistor may further include an interfacial dielectric layer adjacent to the channel and the ferroelectric gate dielectric layer. The ferroelectric storage transistor realizes a memory function by storing data as a polarization state in the ferroelectric gate dielectric layer. In particular, a voltage applied between the gate conductor and the channel induces an electric polarization in the ferroelectric gate dielectric layer, and this polarization can be reversed by applying a voltage of the opposite polarity. The ferroelectric gate dielectric layer retains the induced polarization state even after the applied gate voltage is removed, realizing the memory function of the ferroelectric storage transistor. For example, by applying a ferroelectric storage transistor, it is possible to form a nonvolatile memory cell in which data is stored in the ferroelectric gate dielectric layer as two stable residual polarization states.

[0049] The induced polarization state of the ferroelectric gate dielectric layer changes the threshold voltage of the ferroelectric storage transistor. By utilizing the change or shift in the threshold voltage of the ferroelectric storage transistor due to different polarization states, it becomes possible to represent data in different logical states. For example, as a result of two induced electric polarization states in the ferroelectric gate dielectric layer, two logical states (e.g., "0" and "1") can be represented by the high and low threshold voltages of the ferroelectric storage transistor. In other embodiments, it is possible to induce two or more polarization states in the ferroelectric gate dielectric layer, such as by applying two or more different ranges of voltages to the ferroelectric gate dielectric layer. In this way, the ferroelectric storage transistor can be operated to store data in two or more logical states. For example, a tri-state provides three threshold voltage states corresponding to 1.5 bits stored in each cell, or a continuum of analog states such as a quad-state (00, 01, 10, and 11) corresponding to 2 bits stored in one ferroelectric memory cell. This continuum of analog states will be advantageous for applications in artificial intelligence and machine learning applications.

[0050] In an embodiment of the present invention, a three-dimensional array of NOR memory strings of ferroelectric storage transistors can be applied to the implementation of non-volatile memory devices or quasi-non-volatile memory devices. For example, the average retention time of quasi-volatile memory is 100 milliseconds or more, such as about 10 minutes, or several hours, while the minimum data retention time of non-volatile memory devices can exceed several days to several years. In one embodiment, the ferroelectric storage transistor has a data retention time longer than 1 hour and a program / erase cycle durability exceeding 10 8 program / erase cycles. For example, the data retention time of the ferroelectric storage transistor is several hours, and the program / erase cycle durability is about 10 11This is the case. By using such a ferroelectric storage transistor, the refresh interval becomes about several hours, so that it is possible to form a quasi-volatile memory device having a much longer refresh interval than that of a DRAM that requires more frequent refreshing, such as several tens of milliseconds. In some embodiments, it is possible to form a quasi-volatile memory device having a high storage capacity by using a plurality of three-dimensional arrays of ferroelectric storage transistors ("tiles").

[0051] The ferroelectric storage transistor stores data in the ferroelectric gate dielectric layer. During operation, for example, when a voltage of a first polarity is applied to the gate terminal with respect to the source terminal, the applied electric field of the first polarity induces the ferroelectric gate dielectric layer to be in a first polarization state. On the other hand, for example, when a voltage of a second polarity is applied to the gate terminal with respect to the source terminal, by applying an electric field of a second polarity opposite to the first polarity, the ferroelectric gate insulating layer is induced to be in a second polarization state. The first polarization state shifts the threshold voltage V t of the ferroelectric storage transistor to a lower value, and this can be used to encode a first logic state such as a logic "1" state. Alternatively, the second polarization state shifts the threshold voltage V t of the ferroelectric storage transistor to a higher value, and this can be used to encode a second logic state such as a "0" state. In this specification, shifting the threshold voltage Vt of the ferroelectric storage transistor to a higher value (logic "0") is referred to as a program operation, and shifting the threshold voltage V t of the ferroelectric storage transistor to a lower value (logic "1") is referred to as an erase operation.

[0052] In some embodiments, by using the above-described precharge operation, it is possible to set the voltages of the source line and the bit line of the NOR memory string to a voltage that is negative relative to the voltage of the local word line (e.g., during an erase operation), or to a voltage that is positive relative to the voltage of the local word line (e.g., during a program operation). Since the ferroelectric storage transistor's erase or program polarization state reverses the voltage of the local word line using the voltage of one of the source and drain terminals as an electrode and the voltage of the local word line as a second electrode, it is somewhat contrasting and advantageous in that the polarization of the cell can be easily reversed. In some embodiments, each string of ferroelectric storage transistors is a thin film transistor, as opposed to single crystal transistors formed within a semiconductor substrate, and thus does not require a wiring connection to the ground potential of the semiconductor substrate in any of the common source, common drain, or common channel. Instead, by applying only a positive voltage (or only a negative voltage) to the local word line or the common source / common drain, it becomes possible to impart both polarization states to the FeFET. This single voltage polarity function simplifies the process flow of the control / logic transistors formed within the substrate, and since ferroelectric polarization states typically have a voltage hysteresis that changes from a negative voltage (erase state) to a positive voltage (programmed state), optimized operation becomes possible.

[0053] In an embodiment of the present invention, the ferroelectric storage transistor is formed using an oxide semiconductor channel. For example, the oxide semiconductor channel can be formed using an amorphous oxide semiconductor material such as indium gallium zinc oxide (InGaZnO or "IGZO"). The channel region of the oxide semiconductor has the advantage of having a high mobility that improves switching performance without concern for electron or hole tunneling. For example, the electron mobility of the IGZO film depends on the relative composition of indium, gallium, and zinc, but is 10.0 to 100.0 cm 2 / V. The oxide semiconductor channel forms an N-type unipolar channel region, and the conductive layers 16a, 18, 16b (FIG. 1) that form the source terminal and the drain terminal are in direct contact with the channel region. The ferroelectric storage transistor thus formed is normally in the on state and is a depletion-mode device that can be turned off by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric storage transistor is a function of the thickness d4 (FIG. 3) of the oxide semiconductor channel region 25. That is, the threshold voltage of the ferroelectric storage transistor is the amount of voltage required to deplete the thickness d4 of the oxide semiconductor channel region and thereby cut off the ferroelectric storage transistor.

[0054] Next, with reference to FIGS. 5 to 7, exemplary operating conditions of a three-dimensional NOR memory string of a ferroelectric storage transistor will be described. In an embodiment of the present invention, the write operation to the NOR memory string is performed by first executing an erase operation and then executing a program operation. In this embodiment, the erase operation is applied to all the storage transistors in a memory page to set all the storage transistors to a first logical state, and then the subsequent program operation is applied to the selected storage transistor in the memory page to program the selected memory storage to a second logical state.

[0055] FIG. 5 is a diagram showing an erasure operation that can be implemented in a three-dimensional array of NOR memory strings according to an embodiment of the present invention. Referring to FIG. 5, a memory array 50 is shown that includes a first portion of a set of NOR memory strings belonging to a selected global word line (GWL) 42a and a second portion of the same set of NOR memory strings belonging to a non-selected global word line (GWL) 42b. In an actual implementation, the first and second portions of the NOR memory strings are formed on the same set of NOR memory strings (the same set of active stacks), but show ferroelectric storage transistors associated with different local word lines 28. That is, the first and second portions of the NOR memory strings show ferroelectric storage transistors arranged at different positions in the Y direction along the NOR memory strings.

[0056] As described above, the global word lines 42a, 42b are interconnecting conductors that connect word line signals to one or more local word lines 28 coupled to a NOR memory string formed in one or more active stacks. A first portion of the NOR memory string shows ferroelectric storage transistors that belong to a selected global word line 42a and are arranged in the same plane in the X direction. The ferroelectric storage transistors of the first portion belong to memory pages 52a and 54a which are memory pages formed at different positions in the same plane and in the X direction. A second portion of the NOR memory string shows ferroelectric storage transistors that belong to a non-selected global word line 42b and are arranged in the same plane in the X direction. The ferroelectric storage transistors of the second portion belong to memory pages 52b and 54b which are memory pages formed at different positions in the same plane and in the X direction. In particular, the ferroelectric storage transistors within page 52b belong to a non-selected page within the same NOR memory string as the selected page 52a. That is, memory pages 52a and 52b belong to the same set of the NOR memory string but are arranged at different positions in the Y direction. Accordingly, the bit lines and source lines of pages 52a, 52b are biased to the same voltage level, but page 52b is associated with the non-selected global word line 42b. On the other hand, memory pages 54a and 54b are associated with the same NOR memory string but are arranged at different positions in the Y direction. Memory page 54a is connected to the selected global word line 42a, and memory page 54b is connected to the non-selected global word line 42b.

[0057] In this embodiment, a memory page includes ferroelectric storage transistors in two stacks adjacent to each other of a NOR memory string that share a common word line and further share the same continuous oxide semiconductor channel region. In one embodiment, the memory array 50 includes eight layers of NOR memory strings, and a memory page includes at least 16 ferroelectric storage transistors (or 16 bits) that span two adjacent active stacks of the NOR memory strings. In other embodiments, the oxide semiconductor channels can be separated at the bottom of each narrow trench 22. In that case, the ferroelectric storage transistors in each stack of the NOR memory string form a unique memory page. For example, when the oxide semiconductor channels are separated at the bottom of the narrow trenches, the memory array 50 may include memory pages of eight ferroelectric storage transistors (or 8 bits) that span one active stack of the eight layers of NOR memory strings.

[0058] In this embodiment, the memory page of the ferroelectric storage transistor is erased by an erase operation. In some examples, this is referred to as a block erase operation. For example, the erase operation erases all ferroelectric storage transistors associated with the selected global word line 42a within the selected page 52a. To erase the ferroelectric storage transistors within the selected page 52a, a word line voltage that is positive relative to the voltages of the source line and the bit line is used. In some embodiments, both the source line voltage and the bit line voltage are set to 0V, and the selected global word line 42a is driven to 2 - 3V. In this example, the selected global word line 42a is driven to 2.2V. To suppress the erasure of other non - selected ferroelectric storage transistors, the non - selected global word line 42b is biased to a positive voltage that is lower than the voltage of the selected global word line 42a. For example, the non - selected global word line 42b is biased to half of the voltage of the selected global word line 42a, e.g., 1.1V. The source line voltage and the bit line voltage of the non - selected pages 54a, 54b are driven to the same voltage (e.g., 1.1V) as the non - selected global word line 42b, and as a result, the gate - source voltage across these non - selected ferroelectric storage transistors becomes 0V. For the ferroelectric storage transistors within page 52b, since they belong to the same NOR memory string set as the selected page 52a, the source line and the bit line are biased to 0V. However, since their gate terminals are biased to the non - selected global word line voltage (e.g., 1.1V), and the gate - source voltage across these non - selected ferroelectric storage transistors is not sufficient to invert the polarization state of the transistors, they are not erased. As a result, only the ferroelectric storage transistors of page 52a are erased. In the present disclosure, the erased ferroelectric storage transistors hold the first logic state "1".

[0059] FIG. 6 is a diagram showing a program operation that can be performed in a three-dimensional array of a NOR memory string following the erasure operation of FIG. 5 in an embodiment of the present invention. Referring to FIG. 6, after the ferroelectric storage transistors in the selected page 52a are erased (logical state "1"), some of the ferroelectric storage transistors in the page will be programmed to a second logical state "0" based on the write data. In FIG. 6, it is assumed that the transistor indicated by the dashed box 44 is programmed. The other transistors are not programmed and retain the logical state associated with the erased state ("1").

[0060] To program the selected ferroelectric storage transistor in the selected page 52a, a word line voltage that is negative with respect to the voltages of the source line and the bit line is used. Alternatively, the source line voltage and the bit line voltage of the ferroelectric storage transistor to be programmed may be made positive with respect to the word line voltage. In the embodiments of the present disclosure, the program operation of the ferroelectric storage transistor realizes asymmetric programming. Asymmetric programming refers to using different source line voltages and bit line voltages in the program operation. In this embodiment, to program the selected ferroelectric storage transistor (indicated by the dashed box 44) in the selected page 52a, the selected global word line 42 is set to 0V. The bit line voltage of the selected ferroelectric storage transistor to be programmed is set to 1.8V, and the bit line voltage of the non-selected ferroelectric storage transistor is set to 0.8V. The source line voltage of all ferroelectric storage transistors is also set to 0.8V. With such a configuration, a sufficiently high electric field is applied at the drain terminal only to the ferroelectric storage transistor in which the gate-source voltage is negative (e.g., 0.8V) and the gate-drain voltage is sufficiently large and negative (e.g., -1.8V) to invert the polarization state of the transistor to the programmed state (logical "0"). The other ferroelectric storage transistors in the selected page 52a have a gate-drain voltage of only -0.8V and retain the previously erased state (e.g., logical "1").

[0061] To suppress the programming of other non-selected ferroelectric storage transistors, the non-selected global word line 42b is biased to a voltage higher than the voltage of the selected global word line 42a. For example, the non-selected global word line 42b is biased to 0.8V. The source line voltage and bit line voltage of the non-selected pages 54a, 54b are driven to the same voltage as the non-selected global word line 42b (e.g., 0.8V). As a result, a gate-source voltage of 0V is applied across the non-selected ferroelectric storage transistors in the non-selected page 54b, and these transistors are not programmed. For the ferroelectric storage transistors in the non-selected page 54a, although the negative gate-source voltage is -0.8V, the gate-drain voltage is only -0.8V, which is insufficient to change the polarization state of these ferroelectric storage transistors. For the non-selected ferroelectric storage transistors in the page 52b, since they belong to the same set of NOR memory strings as the selected page 52a, the voltages of the source line and bit line are biased to the same values as the transistors in the page 52a. However, since their gate terminals are biased to the non-selected global word line voltage (e.g., 0.8V) and the gate-source voltage across these non-selected ferroelectric storage transistors is 0V, these transistors are maintained off and thus not programmed. As a result, only the selected ferroelectric storage transistors (shown by box 44) in the page 52a are programmed.

[0062] In the memory array 50 of FIG. 6, parasitic transistor devices are formed in the regions between two bit lines of two ferroelectric storage transistors adjacent to each other in the Z direction, as indicated by the dashed ellipses 45a to 45f in FIG. 6, by the continuous channels. Each of these parasitic transistor devices includes a ferroelectric gate dielectric layer, a channel region, and two bit lines that function as conductive source / drain terminals. The memory array 50 includes such parasitic transistor devices, but they do not affect the memory operation. In particular, the parasitic transistor devices 45a to 45f are erased during the erase operation. And during the program operation, the parasitic transistor devices (e.g., 45d) arranged between two non-selected ferroelectric storage transistors are not programmed, and the parasitic transistor devices having at least one adjacent ferroelectric storage transistor selected for programming (e.g., 45a to c and 45e to f) are programmed simultaneously. On the other hand, the programming of the parasitic transistor devices increases the threshold voltage of the parasitic transistor devices, which has the effect of turning off the parasitic transistor devices programmed for the read operation. Therefore, the incidental programming of the parasitic transistor devices during the program operation does not affect the operation of the memory array 50.

[0063] FIG. 7 is a diagram showing a read operation that can be performed in a three-dimensional array of a NOR memory string following the write operations of FIGS. 5 and 6 in an embodiment of the present invention. Referring to FIG. 7, a small positive gate-source voltage is applied to read a ferroelectric storage transistor from the selected page 52a, and a small positive bit line voltage is applied. In the present embodiment, the read operation is performed by setting the selected global word line 42a to a positive voltage of 0.7 V, setting the source line voltage to 0 V, and setting the bit line voltage to 0.5 V. When biased in this way, the ferroelectric storage transistor in the erased state conducts, and an "on" current Ion flows between the bit line and the source line of the erased storage transistor. On the other hand, the ferroelectric storage transistor in the programmed state becomes non-conductive, and no current flows between the bit line and the source line of the programmed storage transistor except for a small leakage current called an "off" current Ioff.

[0064] During the read operation, the non-selected global word line 42b is set to 0 V. Similarly, the bit line voltage and the source line voltage of the non-selected memory pages 54a and 54b are set to 0 V. For the non-selected ferroelectric storage transistors in the page 52b belonging to the same NOR memory string as the selected page 52a, the voltages of the source line and the bit line are biased to the same values as the transistors in the page 52a. However, since the gate terminals of these non-selected ferroelectric storage transistors are biased to the non-selected global word line voltage (e.g., 0 V), and the gate-source voltage across these non-selected ferroelectric storage transistors is 0 V, these transistors are maintained off, and thus no read is performed.

[0065] When biased in this way, the ferroelectric storage transistors of the selected page 52a that have been erased conduct a current Ion, while the programmed ferroelectric storage transistors of the selected page 52a that have been programmed conduct a current Ioff. By connecting the bit lines of the ferroelectric storage transistors to a sense amplifier and detecting the cell current, an output logic value indicating the cell current is generated. Parasitic transistor devices between the two bit lines do not affect the read operation even if the parasitic devices are erased or programmed. This is because the source / drain terminals of the parasitic transistor devices are biased to the same bit line voltage (0.5V), so no current flows through these parasitic transistor devices.

[0066] In some embodiments, the ferroelectric storage transistors of a three-dimensional array of NOR memory strings may be induced to store data in multiple states, i.e., data in two or more polarization states corresponding to two or more logic states. In one embodiment, the ferroelectric storage transistor is erased to a low threshold voltage level representing one polarization state, and then programmed to two or more intermediate states, so as to operate to store multiple states or multiple levels of data, and each state has a threshold voltage level higher than the threshold voltage level associated with the erased state and different threshold voltage levels.

[0067] In some embodiments, the ferroelectric storage transistors are erased using the bias conditions described above with reference to FIG. 5. For example, the selected global word line is driven to 2.2V, and the selected bit line and source line are driven to 0V. The non-selected global word line, non-selected bit line, and non-selected source line are driven to 1.1V. Under this bias condition, the selected ferroelectric storage transistor is erased at a first threshold voltage that is the lower, or lowest, threshold voltage of the ferroelectric storage transistor.

[0068] In some embodiments, ferroelectric storage transistors within the same page (e.g., page 52a) are programmed to multiple logical states in a single program operation. That is, the threshold voltages of ferroelectric storage transistors within the same page increase from an erased threshold voltage level to different higher threshold voltage levels by the same program operation. Therefore, only two write cycles (one erase and one program) are required to store multiple (or two or more) logical states in the ferroelectric storage transistors.

[0069] In one example, the bias conditions used to program all ferroelectric storage transistors within the same page into two program states include driving the selected global word line to 0V and the selected bit line to 1.6V or 2V, depending on the desired program state of each ferroelectric storage transistor. In this way, the selected ferroelectric storage transistor can be programmed into two program states having different program threshold voltage levels by a single programming operation, and as a result, together with the erased state, three logic states are stored in the ferroelectric storage transistors of the selected page. In another example, the bias conditions used to program all ferroelectric storage transistors within the same page into three program states include driving the selected global word line to 0V and the selected bit line to 1.6V, 1.8V, or 2V, depending on the desired program state of each ferroelectric storage transistor. In this way, the selected ferroelectric storage transistor can be programmed into three program states having different program threshold voltage levels by a single programming operation, and as a result, together with the erased state, four logic states are stored in the ferroelectric storage transistors of the selected page. In this example, during the multi-state programming operation, all source lines, non-selected bit lines, and non-selected global word lines may be set to 0.8V. In another example, the selected ferroelectric storage transistor within a memory page can be programmed into any number of program states with the same programming operation by applying different program voltages, such as voltage values from 1.6V to 2.0V, to the bit line. The selected ferroelectric storage transistor within a memory page is programmed to continuous threshold voltage values by applying a program voltage over a continuous voltage range, such as a continuous program voltage value from 1.6V to 2.0V.

[0070] In other embodiments, ferroelectric storage transistors within the same page (e.g., page 52a) are programmed to multiple logical states with separate program operations. That is, after an erase operation, the selected ferroelectric storage transistor is programmed to increase to different levels of threshold voltage by separate program operations. In one example, the selected global word line is driven to 0V. Then, in the first program operation, the first group of selected bit lines is driven to 1.6V (VPP voltage), and the associated ferroelectric storage transistor is programmed to the second logical state (the erased state being the first logical state). All source lines, non-selected bit lines, and non-selected global word lines are set to a voltage value of 0.44 * VPP, i.e., 0.7V. To program another logical state by the second program operation, the second group of selected bit lines is driven to 2.0V (VPP voltage), and the associated ferroelectric storage transistor is programmed to the third logical state. All source lines, non-selected bit lines, and non-selected global word lines are set to a voltage value of 0.44 * VPP, i.e., 0.88V. By performing successive program operations and using different VPP voltage values, it becomes possible to program the selected ferroelectric storage transistor to any number of logical states.

[0071] In the above description, voltage bias conditions are described and exemplary voltage values are given to explain the erase, program, and read operations of the memory array of ferroelectric storage transistors. The voltages described above are for illustrative purposes only and are not intended to be limiting. In other embodiments, other voltage values may be used to implement the voltage bias conditions for the erase, program, and read operations.

[0072] As described above, in the embodiments of the present disclosure, the common source line of the memory structure may remain floating or may not be electrically connected to any potential. Instead, the common source line can be pre-charged using one or both of the bit lines of the NOR memory string pair before the erase, program, and read operations. In one embodiment, the pre-charge operation sets the bit line to a desired voltage via a pre-charge transistor, and then the source line is charged from the bit line to a voltage equal to the bit line voltage.

[0073] Bit Line Selection of Sense Amplifier

[0074] Returning to FIG. 1, the memory structure 10 is shown as including four active stacks each having four bit lines on each layer or plane of an eight-layer three-dimensional memory structure. Ferroelectric storage transistors 20 are formed on both sides of each active stack to form a NOR memory string along each active strip. In an actual implementation, the memory structure 10 may be formed of thousands of bit lines per layer (e.g., 2048 bit lines) where each bit line is coupled to thousands of LWL structures to form thousands of ferroelectric storage transistors 20 (e.g., 4096 transistors) along the active strip as a NOR memory string.

[0075] In some embodiments, the storage transistors within the memory structure 10 are accessed in units of memory pages having a given byte size, and the support circuitry formed within the semiconductor substrate 12 below the memory array includes sense amplifier circuitry for outputting the byte-sized read data of the memory page. In one example, the memory structure 10 may be accessed with a memory page size of 64 bytes or 512 bits. In that case, the support circuitry below the memory array may include 512 sense amplifiers to output 512 bits of read data. In some embodiments, a bit line selector is used to multiplex thousands of bit lines within the memory structure to a given number of sense amplifiers, thereby enabling page access to the memory data. For example, 16k bit lines may be multiplexed to 512 sense amplifiers using a bit line selector.

[0076] FIG. 8 is a diagram showing a bit line selector that can be implemented within a three-dimensional array of NOR memory strings in an embodiment of the present invention. In the above-described embodiment, the ferroelectric storage transistors formed within the active stack belong to the same memory page and are accessed together. Referring to FIG. 8, the bit line selector circuit 80 is configured to enable selection of bit lines across all layers of the memory array belonging to the same active stack, thereby selecting the storage transistors belonging to the same memory page.

[0077] In this embodiment, the bit line selector circuit 80 includes a plurality of bit line selectors SEL0 to SEL31. In this figure, for simplicity, only two selectors SEL0 and SEL31 are shown. Each bit line selector SELn includes a multiplexer 82 (for example, multiplexer circuits 82-1, 82-2, etc.), and each multiplexer 82 selects one column of bit lines from 32 columns. The multiplexer 82 may be referred to as a 32:1 multiplexer (mux) or a 32:1 selector. In this embodiment, the multiplexer 82 receives selection signals S0 to S31 and selects or activates one of the 32 output terminals, output terminal 88. For example, multiplexer 82-1 selects one of the 32 output terminals 88-0 to 88-31. On the other hand, multiplexer 82-31 selects one of the 32 output terminals 88-992 to 88-1023. Each output terminal 88 is coupled to the gate terminal of a bank of pass transistors. Each bank of pass transistors receives, at a first terminal, bit line signals of the same column across all layers of the memory array. When the pass transistors are activated by output terminal 88, the bit line signals are passed to the respective second terminals of the banks of pass transistors. The second terminals of the banks of pass transistors are connected to the respective sense amplifier circuits via metal interconnects or the like.

[0078] For example, in the bit line selector SEL0, each output terminal 88-0 to 88-31 is connected to a bank of pass transistors, and the pass transistors of each bank are connected to respective sense amplifier circuits SA00 to SA07. Each output terminal 88-0 to 88-31 is connected to different pages of ferroelectric storage transistors. For example, output terminal 88-0 is connected to bit line B0 that crosses layers L0 to L7 of the memory array, and output terminal 88-31 is connected to bit line B31 that crosses layers L0 to L7 of the memory array. On the other hand, the bit line selector SEL31 includes a 32:1 multiplexer 82-31 having output terminals 88-992 to 88-1023, and the pass transistors of each bank are connected to respective sense amplifier circuits SA248 to SA255. Each output terminal 88-992 to 88-1023 is connected to different pages of ferroelectric storage transistors. For example, output terminal 88-992 is connected to bit line B992 that crosses layers L0 to L7 of the memory array, and output terminal 88-1023 is connected to bit line B1023 that crosses layers L0 to L7 of the memory array.

[0079] As thus configured, in the bit line selectors SEL0 to SEL31, the multiplexers 82-0 to 82-31 select one output terminal 88 according to the selection signals S0 to S31. As a result, one column of bit lines associated with each multiplexer is selected, and each selected column includes the bit lines of all layers of the array. Accordingly, a total of 32 columns of bit lines are selected, and each column is coupled to a respective sense amplifier circuit. In this example, the selected 32 columns of bit lines are connected to 256 sense amplifier circuits SA0 to SA255, providing 256-bit read data.

[0080] The bit line selector circuit 80 described in this specification is for illustrative purposes only and is not intended to be limiting. Although various circuit configurations can be used to implement the bit line selection described herein, the bit line selector circuit 80 is disclosed here as an exemplary embodiment.

[0081] Manufacturing process

[0082] Figures 9A - 9N are diagrams showing a process for manufacturing a memory structure including a three - dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. Figures 9A - 9H are diagrams showing a partial vertical cross - sectional view (i.e., the X - Z plane) of a three - dimensional array of NOR memory strings. Each of Figures 9I - 9N includes two diagrams. Diagram (i) is a horizontal cross - sectional view (i.e., the X - Y plane) along line A - A' shown in diagram (ii). Diagram (ii) is a vertical cross - sectional view (i.e., the X - Z plane) along line A - A' of diagram (i).

[0083] Referring to Figure 9A, first, a memory structure 100 is formed by continuously depositing (i) an insulating dielectric layer 104 and (ii) a sacrificial layer 106 on the upper side of the flat surface of a semiconductor substrate 101 to form a multilayer structure. In some embodiments, a buffer layer 102 may be provided on the upper side of the surface of the semiconductor substrate 101 before the insulating dielectric layer 104 and the sacrificial layer 106 are formed on the upper side of the substrate 101. In some embodiments, the buffer layer 102 may be a silicon oxycarbide (SiOC) layer or a silicon dioxide (SiO2) layer. In this embodiment, the insulating dielectric layer 104 is a silicon oxide layer and may have a thickness of 30 nm. The sacrificial layer 106 is a silicon nitride layer and may have a thickness of 40 nm. The sacrificial layer 106 is replaced by a conductive layer in a metal replacement process in subsequent processing. Figure 9A is a diagram showing the memory structure 100 after the deposition of the initial layer of the thin film. As described above, in this description, the dimensions are provided for illustrative purposes and are not intended to be limiting. In actual implementation, any appropriate thickness and dimensions can be used. Also, the figures are not necessarily to scale.

[0084] Referring to FIG. 9B, a first set of trenches 108 are formed within the memory structure 100 using, for example, anisotropic etching after a patterning step by photolithography. In some examples, the width of each trench 108 may be 70 nm and the spacing between them may be 190 nm. Referring to FIG. 9C, an amorphous metal oxide semiconductor layer 120 is conformally deposited on the exposed sidewalls of the trenches 108. The amorphous metal oxide semiconductor layer 120 (the "oxide semiconductor layer 120") may be deposited using, for example, atomic layer deposition (ALD) techniques, plasma enhanced ALD techniques, or physical vapor deposition (PVD). In particular, the oxide semiconductor layer 120 can be formed at a low processing temperature such as less than 400 °C. In the present embodiment, the oxide semiconductor layer 120 is an indium gallium zinc oxide (InGaZnO, or "IGZO") layer. For example, IGZO deposition using thermal ALD or plasma enhanced ALD can be performed at a low processing temperature of 200 °C. Other oxide semiconductor materials that can be used include indium zinc oxide (InZnO, or "IZO"), indium aluminum zinc oxide (IAlZnO), or indium tin zinc oxide (ITZO). In one embodiment, the thickness of the oxide semiconductor layer 120 is 10 nm. The oxide semiconductor layer 120 forms the channel region of the ferroelectric storage transistor.

[0085] In the present embodiment, the deposited oxide semiconductor layer 120 is a continuous layer provided along the exposed sidewalls of the trenches 108. In some embodiments, after the oxide semiconductor layer 120 is deposited, an etching process can be performed to etch away the oxide semiconductor layer 120 provided at the bottom of the trenches 108, thereby separating the oxide semiconductor layer formed on the sidewalls of the trenches. The etching of the oxide semiconductor layer 120 from the bottom of the trenches 108 is optional and may be included, for example, when a specific memory page size is desired as described above.

[0086] Referring to FIG. 9D, the trench 108 is then filled with a dielectric material 110. In some embodiments, the dielectric material 110 is a silicon oxide material such as SiO2. The excess dielectric material may be removed from the top of the memory structure 100 using, for example, chemical mechanical polishing (CMP). FIG. 9D is a diagram showing the resulting memory structure 100.

[0087] Referring to FIG. 9E, the second set of trenches 109 are then cut using substantially the same technique as described with reference to FIG. 9B above, with mechanical support by the dielectric material 110. In some examples, the width of the trenches 109 may be 70 nm. Each of the second set of trenches 109 is cut between pairs of the first set of trenches 108 adjacent to each other, and each of the second set of trenches 109 is cut at substantially equal distances from each other between pairs of the first set of trenches 108 adjacent to each other. As a result of cutting the trenches 108 and 109 across each other within the multilayer structure, stacks within the multilayer structure are formed, which are referred to herein as "active stacks". In some examples, the width of each of the active stacks is about 60 nm. The narrow strips of the layers 104 and 106 within the resulting active stacks are referred to herein as "active strips".

[0088] Next, the sacrificial silicon nitride layer 106 is removed, for example, using wet etching, thereby forming a cavity between the insulating dielectric layers 104 as shown in FIG. 9F. As shown in FIG. 9G, the cavity is filled with the conductive layer 112. In some embodiments, the conductive layer 112 is a high melting point metal layer such as molybdenum (Mo) or tungsten (W). In other embodiments, the conductive layer 112 may be a metal layer selected from molybdenum, titanium, tungsten, lanthanum, tantalum, ruthenium, any silicide thereof, any nitride thereof, and any combination thereof. For example, the conductive layer 112 may be formed using, for example, atomic layer deposition (ALD) technology. The etching step removes all of the material deposited from the sidewalls of the trench 109. In some examples, isotropic wet etching is used to remove the material deposited from the sidewalls of the trench 109. In this embodiment, the conductive layer 112 is a molybdenum layer and forms the source and drain terminals of the ferroelectric storage transistor to be formed.

[0089] Next, the amorphous metal oxide semiconductor layer 120 is conformally deposited on the exposed sidewalls of the trench 109, for example, using an ALD process. The thickness of the oxide semiconductor layer 120 may be 10 nm. Next, the trench 109 is filled with a dielectric material 110 such as SiO2. The excess deposited material may be removed from the top of the memory structure 100, for example, by CMP. The resulting memory structure 100 is shown in FIG. 9H.

[0090] Referring to FIG. 9I, thereafter, the vias 114 are patterned and the dielectric material 110 exposed by the vias 114 is etched, for example, using anisotropic etching. The vias 114 are masked in an elliptical shape as shown in the horizontal cross-sectional view (i) of FIG. 9I. In some examples, the elliptical mask opening may have a major axis of 100 nm along the X direction and a minor axis of 60 nm along the Y direction. The vias 114 are later filled with a dielectric material to insulate the storage transistors adjacent to each other within the NOR memory string to be formed.

[0091] Referring to FIG. 9J, the via 114 is then filled with a sacrificial silicon nitride liner 115 and a sacrificial amorphous silicon layer 116. The excess material on the memory structure 100 may be removed, for example, using CMP. After filling the via 114, residues of the dielectric material 110 in the trenches 108 and 109, as shown in FIG. 9K, are removed, for example, using a wet etching step. As a result, cavities 118 are formed in the trenches 108 and 109 outside the via 114, which are then filled with the sacrificial layers of the silicon nitride liner 115 and the amorphous silicon layer 116.

[0092] Referring to FIG. 9L, the ferroelectric gate dielectric layer 122 is then conformally deposited on the exposed sidewalls of the cavity 118. In some embodiments, the ferroelectric gate dielectric layer 122 is deposited by any one of suitable deposition methods including, but not limited to, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Other deposition methods such as evaporation and electrodeposition can also be used. In some embodiments, the ferroelectric gate dielectric layer 122 is a doped hafnium oxide (HfO2) layer. In one embodiment, hafnium oxide is doped with zirconium oxide (ZrO2) to form a hafnium zirconium oxide layer (HfZrO or "HZO"). In other embodiments, hafnium oxide is doped with silicon (Si), iridium (Ir), and lanthanum (La). In some embodiments, the ferroelectric gate dielectric layer 122 is selected from materials including zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0093] In one embodiment, the thickness of the ferroelectric gate dielectric layer 122 is 4 nm. In some embodiments, an interfacial dielectric layer (also referred to as an "interface layer") is formed between the oxide semiconductor layer 120 and the ferroelectric gate dielectric layer 122. In some embodiments, the interfacial dielectric layer is formed using a material having a high dielectric constant (K) (also referred to as a "high-K" material). In one example, when an interfacial dielectric layer is provided, it may be a silicon nitride (Si3N4) layer having a thickness of 1 nm. To form a ferroelectric phase in the ferroelectric material, the ferroelectric gate dielectric layer 122 may be deposited and then annealed. The ferroelectric gate dielectric layer 122 forms the gate dielectric layer of the ferroelectric storage transistor.

[0094] After annealing the deposited ferroelectric gate dielectric layer 122, the cavity 118 is then filled with a conductive layer 124 including a continuously deposited titanium nitride (TiN) liner and a tungsten (W) layer. The TiN liner may be formed, for example, using atomic layer deposition (ALD) technology. In each of the cavities 118, the conductive layer 124 provides a vertical local word line (LWL) that functions as the gate electrode of each ferroelectric storage transistor aligned in the vertical direction within the same active stack with respect to the vias 114 (filled with the sacrificial materials 115, 116) adjacent to each other. The structure obtained from the combination of the ferroelectric gate dielectric layer 122 and the conductive layer 124 is referred to herein as a local word line (LWL) structure. The excess deposited material may be removed from the top of the memory structure 100 by CMP or the like. FIG. 9L is a diagram showing the resulting memory structure 100.

[0095] It is advantageous for the memory structure 100 to include a normally-sized cavity 118a in the central portion of the memory structure and an extended-sized cavity 118b at the end of the memory structure (FIG. 9K). As a result, the memory structure 100 includes an LWL structure formed within the normally-sized cavity 118a used to form ferroelectric storage transistors of the NOR memory string. The structure formed in the extended-sized cavity 118b at the end of the memory structure 100 may be a dummy structure or, if applicable, may be converted into a non-memory transistor such as a precharge transistor. The detailed configuration of the memory structure 100 at the end of the memory string is not important for the implementation of the present invention.

[0096] Referring to FIG. 9M, after the LWL structure is formed, then, when the sacrificial material formed in the via 114 is removed, a cavity 126 is formed. In this embodiment, the amorphous silicon layer 116 is removed, for example, by using a wet etching step. The silicon nitride liner 115 remains within the cavity 126. In other embodiments, the silicon nitride liner 115 may also be removed, for example, by using a wet etching step.

[0097] Referring to FIG. 9N, next, the via 126 exposing the dielectric material 130 is filled. In some embodiments, the dielectric material 130 is silicon oxide such as SiO2. The extra material on the memory structure 100 may be removed by CMP. The resulting memory structure 100 includes a NOR memory string of ferroelectric storage transistors formed in a plurality of active stacks in multiple layers, realizing a high-capacity memory device. In particular, the ferroelectric storage transistors in the NOR memory string are formed by a conductive layer 112 functioning as source and drain terminals, an oxide semiconductor layer 120 functioning as a channel region, a ferroelectric gate dielectric layer 122 functioning as a gate dielectric layer, and a conductive layer 124 functioning as a gate terminal or gate conductor. The memory structure 100 includes an oxide semiconductor layer 120 that is a continuous layer across all layers of the active stack in the Z direction. Further, the conductive layers 112 are arranged such that NOR memory string pairs share a common source line.

[0098] In the memory structure 100 of FIG. 9N, the oxide semiconductor layer 120 is formed as a continuous layer across the active stack and is further a continuous layer provided along the NOR memory string in the Y direction. Since the region between the LWL structures is filled only with the dielectric material, leaving the oxide semiconductor layer 120 between the LWL structures does not affect the memory device. On the other hand, in some embodiments, as shown by the memory structure 30 of FIG. 2, the oxide semiconductor layer 120 may be separated between the LWL structures.

[0099] FIGS. 10A - 10B are diagrams showing another process for manufacturing a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. Referring to FIG. 10A, the memory structure 200 is constructed in the same manner as described above with reference to FIGS. 9A - 9H, and the resulting structure includes active stacks separated by trenches lined with an oxide semiconductor layer 120 and filled with a dielectric material 110, with insulating dielectric layers 104 and conductive layers 112 alternately arranged as shown in FIG. 9H.

[0100] Next, the via 114 is patterned, and the dielectric material 110 exposed by the via 114 is etched, for example, using anisotropic etching. In this embodiment, after removing the dielectric material 110 from the via 114, the exposed oxide semiconductor layer 120 within the via 114 is also removed by performing an anisotropic dry etching or wet etching process or the like. As a result, the oxide semiconductor layer 120 remains only outside the via 114, and each segment of the oxide semiconductor layer 120 is separated in the Y direction along the formed NOR-type memory string. By executing the subsequent processing steps described above with reference to FIGS. 9J to 9N, the manufacturing of the memory structure 200 is completed. Referring to FIG. 10B, an LWL structure is formed in the cavity between the vias 114. The LWL structure includes a ferroelectric gate dielectric layer 122 and a conductive layer 124. The sacrificial material formed within the via 114 is replaced with a dielectric material 130 such as silicon oxide. As shown in the horizontal view (i) of FIG. 10B, the oxide semiconductor layer 120 is separated in the Y direction along the NOR memory string and is provided only in the portion adjacent to each LWL structure.

[0101] In an embodiment of the present invention, it is possible to construct a memory structure using an air gap as an insulator disposed between NOR memory string pairs sharing a common source line. The dielectric constant of the air gap is approximately 1.0, which is significantly lower than most dielectric materials, so the parasitic capacitance between the bit lines of the NOR memory string pair adjacent to the bit lines of the NOR memory string pair in the Z direction is effectively reduced. The air gap improves the insulation between adjacent NOR memory string pairs, thereby improving the performance of the formed memory device. FIG. 11 is a cross-sectional view of a part of a memory structure including a three-dimensional array of NOR memory strings insulated by an air gap cavity in an embodiment of the present invention. For simplicity of explanation, the same reference numerals are assigned to similar elements in FIGS. 1, 3, and 11. Referring to FIG. 11, the memory structure 300 includes a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed on the upper side of a semiconductor substrate (not shown in FIG. 11). In this embodiment, the active stack pairs of NOR memory strings 24 in contact with the same narrow trench 22 share a common oxide semiconductor channel region 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28. The oxide semiconductor channel region 25 formed in one narrow trench 22 is insulated from the oxide semiconductor channel region 25 formed in the other narrow trench 22. Each active stack 24 has ferroelectric storage transistors formed on both sides of the stack. When the LWL structures are arranged alternately (in a staggered pattern) in the Y direction, the adjacent narrow trenches 22 have storage transistors formed so as to be offset from each other in the Y direction. As a result, the active stack 24 does not include a storage transistor formed directly across the active stack in the X direction. The local word line structures formed in each trench 22 are insulated from each other by a dielectric material 23.

[0102] In the memory structure 300, each pair of active layers includes a first common bit line (first conductive layer 16a) and a common source line (second conductive layer 18) separated by an insulating layer 17a, and a second common bit line (third conductive layer 16b) separated from the common source line 18 by an insulating layer 17b, forming first and second NOR memory strings. In embodiments of the present disclosure, each pair of the first and second NOR memory strings is separated from the other pairs in the Z direction by an air gap or cavity 315, also referred to herein as an "air gap cavity". In this way, the air gap 315 insulates the bit lines adjacent to each other within each active stack of the memory structure. The three-dimensional array of NOR memory strings may include a bottom insulating layer 305 formed at the bottom of the memory array to insulate the first conductive layer 16a from the semiconductor substrate. The three-dimensional array of NOR memory strings may further include an upper insulating layer 325 formed on the three-dimensional array to insulate the memory array from the conductive connectors formed above the memory array.

[0103] As used herein, an air gap refers to a cavity formed within a memory structure that is free of any material. In some embodiments, the air gap 315 can be formed by replacing a portion of an insulating dielectric layer with an air gap sacrificial layer during a multi-layer continuous deposition process as shown in FIG. 9A. For example, in the multi-layer structure of FIG. 9A, every three layers of the insulating dielectric layer 140, except for the bottommost insulating dielectric layer, can be replaced with an air gap sacrificial layer. In some embodiments, the air gap sacrificial layer is a material that has a high etching selectivity with respect to the conductive materials used to form the source and bit lines 16a, 16b, 18, and also has selectivity with respect to the insulating materials 17a, 17b used to insulate the source and bit lines within the memory string. In some embodiments, the air gap sacrificial layer may be a material selected from germanium (Ge), silicon germanium (SiGe), or carbon (C).

[0104] Subsequently, after forming a local word line structure in the trench 22, for example, after the process of FIG. 9N in which a memory structure 300 including an oxide semiconductor channel 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28 is formed, then the air gap sacrificial layer can be etched away through one or more shafts formed at a specified position within the narrow trench 22. The air gap sacrificial layer can be etched using isotropic dry etching or wet etching, or ashing in the case of a carbon sacrificial layer. The dielectric material 23 formed within the trench 22 between the local word line structure and the active stack 24 supports the active stack 24. The air gap sacrificial layer along the Y-direction length of the NOR memory string is removed by etching to form an elongated cavity 315 bounded by adjacent bit line conductors, referred to herein as an "air gap" or "air gap cavity". When formed in this manner, the memory structure 300 includes periodic air gaps 315 formed within the array between each pair of adjacent bit line conductors 16b and 16a. These periodic air gaps 315 have a dielectric constant of about 1.0, which is much lower than the dielectric constant of the insulating dielectric material used for bit line insulation. For example, the dielectric constant of silicon dioxide (SiO2) is 4.0, while the dielectric constant of the air gap is 1.0. By using the cavity or air gap 315 as an insulating layer between adjacent bit lines, the parasitic capacitance between adjacent bit line pairs in the Z direction is significantly reduced.

[0105] In some embodiments, after the air-gap sacrificial layer is removed, an air-gap liner layer can be deposited to seal the surface exposed by the air gap 315. For example, the air-gap liner layer can be employed to seal the exposed conductive material forming the common bit lines 16a and 16b and the exposed surface of the oxide semiconductor channel region 25. In some embodiments, the air-gap liner layer is a dielectric material, and in some examples, the air-gap liner layer is a silicon nitride layer or a silicon oxide layer that lines the exposed surface formed by the air-gap cavity 315.

[0106] In other embodiments, the cavity or air gap 315 can be advantageously employed to segment the oxide semiconductor channel 25 in the region between adjacent pairs of NOR memory strings. Further, in some embodiments, the cavity or air gap 315 can be further employed to segment the ferroelectric gate dielectric layer 26, thereby insulating the ferroelectric gate dielectric layer from each pair of NOR memory strings. FIG. 12 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings in which ferroelectric transistors are insulated from each other by air gap cavities, according to another embodiment of the present invention. For simplicity of explanation, like elements in FIGS. 11 and 12 are labeled with like reference numerals. Referring to FIG. 12, the memory structure 400 is formed in substantially the same manner as the memory structure 300 of FIG. 11 and includes air gaps or air gap cavities 315 between adjacent pairs of NOR memory strings. In the memory structure 400, the formation of the air gap cavity 315 provides access means for further etching away the exposed sidewalls of the oxide semiconductor channel 25. In some embodiments, the air gap 315 is further used to etch away the exposed sidewalls of the ferroelectric gate dielectric layer 26. In some embodiments, the oxide semiconductor channel sidewalls and the ferroelectric gate dielectric layer sidewalls are etched or removed by wet etching or isotropic dry etching. The etching process of the oxide semiconductor channel sidewalls and the ferroelectric gate dielectric layer sidewalls may be selective with respect to the bit line conductor layers 16a, 16b such that the bit line conductor layers 16a, 16b are minimally affected by the etching process. After the etching process, the oxide semiconductor channel region and the ferroelectric gate dielectric layer disposed between a pair of adjacent bit line conductors 16b, 16a, as indicated by the dashed circle 355, are removed. As a result, the oxide semiconductor channel 25 and the ferroelectric gate dielectric layer 26 are insulated from each pair of NOR memory strings in the active stack 24.Such insulation is not only beneficial for reducing parasitic capacitance but also for removing interference between adjacent pairs (i.e., in the Z direction) of NOR memory strings within the active stack 24. In embodiments of the present disclosure, it is possible to use an air-gap cavity to remove or segment only the oxide semiconductor channel 25 and leave the ferroelectric gate dielectric layer 26 as a continuous layer.

[0107] As described with reference to FIG. 11, by depositing an air-gap liner layer, it is possible to seal the surfaces exposed by the air gap 315. In particular, the air-gap liner layer can be applied to seal the exposed conductive materials forming the common bit lines 16a and 16b, the exposed surfaces of the oxide semiconductor channel regions, and the exposed surfaces of the ferroelectric gate dielectric layer 26 within the air-gap cavity 315. In some embodiments, the air-gap liner layer may be a dielectric material such as silicon nitride or silicon oxide.

[0108] In some embodiments, the memory structures 300, 400 of FIGS. 11 and 12 can be formed using a sacrificial layer instead of the insulating layers 17a, 17b, and the sacrificial layer can be replaced by a cavity or an air gap in a subsequent processing step. In that case, the memory structure is formed with a cavity or an air gap between each pair of source lines and bit lines. In this way, the parasitic capacitance between adjacent source line and bit line conductors is reduced. When the sacrificial layer is replaced by a cavity, the oxide semiconductor channel 25 and the ferroelectric gate dielectric layer 26 are maintained to form the channel region and the gate dielectric of the ferroelectric storage transistor. In some embodiments, it is possible to apply an air-gap liner layer to seal the exposed surfaces of the air-gap cavity.

[0109] In the above-described embodiments, the ferroelectric storage transistor of the three-dimensional array of NOR memory strings uses an oxide semiconductor material to form the channel region. In still other embodiments of the present invention, it is possible to form a NOR memory string using a polysilicon material for the channel region. That is, it is also possible to replace the oxide semiconductor channel region 25 of any of the above embodiments with a polysilicon channel. In that case, an interfacial dielectric layer is added between the polysilicon channel region and the ferroelectric gate dielectric layer. In one embodiment, the interfacial dielectric layer is a silicon oxide layer (SiO2), a silicon nitride layer (SiN), or an aluminum oxide layer.

[0110] In some embodiments, the source layer and the drain layer can each be formed using a conductive layer (e.g., metal) that includes or does not include a polysilicon layer doped at a high concentration as a source region or a drain region. In one embodiment, the polysilicon channel is an N-type layer doped at a high concentration to form a junctionless channel. The highly doped N-type channel region forms a depletion-mode ferroelectric transistor in the same manner as an oxide semiconductor channel. In one embodiment, the polysilicon channel is doped with an N-type dopant at a dopant concentration of about 2 - 5×10 18 cm -3 . The highly doped N-type channel region enables direct contact with the metal conductor forming the source layer and the drain layer, eliminating the need for a polysilicon source / drain layer.

[0111] In other aspects of the present disclosure, the air gap cavity can be applied to a memory structure for insulating individual NOR memory strings within an active stack. FIG. 13 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings in which ferroelectric transistors are insulated by an air gap cavity, in another embodiment of the present invention. For simplicity of explanation, like elements in FIGS. 1, 3, and 13 are given like reference numerals. Referring to FIG. 13, a memory structure is shown that includes a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed on an upper side (not shown in FIG. 13) of a semiconductor substrate. The memory structure 500 is constructed using conductive layers alternately arranged as common bit lines and common source lines. Thus, like the embodiments described above, adjacent NOR memory string pairs do not share a common source line. Thus, the memory structure 500 includes an active stack formed by individual NOR memory strings 11-0 to 11-7, and each NOR memory string has its own common bit line 16 and common source line 18 separated from each other by an insulating layer 17. In this embodiment, each NOR memory string is formed adjacent to respective oxide semiconductor channel regions 25 and ferroelectric gate dielectric layers 26. An active stack pair of NOR memory strings 24 in contact with the same narrow trench 22 shares a gate conductor 28. Each active stack 24 includes ferroelectric storage transistors formed on both sides of the stack. When the LWL structures are arranged alternately (in a staggered pattern) in the Y direction, adjacent narrow trenches 22 have storage transistors formed offset from each other in the Y direction, such that the active stack 24 does not include storage transistors formed so as to directly cross the active stack in the X direction. Local word line structures formed within each trench 22 are insulated from each other by a dielectric material 23.

[0112] In the memory structure 500, each active layer, such as 11-0 to 11-7, includes a common bit line (first conductive layer 16) and a common source line (second conductive layer 18) separated by an insulating layer 17, forming a NOR memory string. In an embodiment of the present disclosure, each NOR memory string is separated from other NOR memory strings in the Z direction by an air gap or an air gap cavity 415. In this way, the air gap cavity 415 insulates adjacent ferroelectric storage transistors within each active stack of the memory structure from each other. The three-dimensional array of NOR memory strings may include a bottom insulating layer 405 formed at the bottom of the memory array to insulate the conductive layer 18 from the semiconductor substrate. The three-dimensional array of NOR memory strings may further include an upper insulating layer 425 formed on the three-dimensional array to insulate the memory array from conductive connectors formed on the memory array.

[0113] The memory structure 500 is formed in substantially the same manner as the memory structure 300 of FIG. 11 and includes an air gap or cavity for insulating the NOR memory string. In some embodiments, the air gap 415 within the memory structure 500 can be formed by replacing a portion of the insulating layer with an air gap sacrificial layer during a multi-layer continuous deposition process as shown in FIG. 9A. For example, in the multi-layer structure of FIG. 9A, it is possible to replace all other layers of the insulating dielectric layer 140 with an air gap sacrificial layer except for the bottom insulating dielectric layer. Then, after the formation of the local word line structure into the trench 22, for example, after the process of FIG. 9N in which the memory structure 500 including the oxide semiconductor channel 25, the ferroelectric gate dielectric layer 26, and the gate electrode 28 is formed, the air gap sacrificial layer can be etched away through, for example, one or more shafts formed in the narrow trench 22 at a designated position. The air gap sacrificial layer can be etched using isotropic dry etching, wet etching, or ashing in the case of a carbon sacrificial layer. The local word line structure and the dielectric material 23 formed in the trench 22 between the active stacks 24 support the active stacks 24. The air gap sacrificial layer along the length of the NOR memory string in the Y direction is etched away to form an elongated air gap cavity 415 bounded by adjacent bit line / source line conductors. Further, in this embodiment, the air gap cavity 415 is used as an access means for further etching away the exposed sidewalls of the oxide semiconductor channel 25And the ferroelectric gate dielectric layer 26 is insulated for each NOR memory string. When formed in this way, the memory structure 500 includes a periodic air gap 415 formed in the array between each adjacent bit line 16 and source line 18 of adjacent NOR memory strings within the active stack. The periodic air gap 415 has a low dielectric constant and has the advantage of reducing the parasitic capacitance between the bit lines and source lines of adjacent NOR memory strings (in the Z direction) within the active stack. Further, by using the air gap cavity 415 to segment the oxide semiconductor channel and the ferroelectric gate insulating layer for each NOR memory string, the parasitic capacitance is further reduced and the interference between adjacent NOR memory strings (i.e., in the Z direction) within the active stack is minimized. In some embodiments, it is possible to apply an air gap liner layer to seal the exposed surfaces of the air gap cavity.

[0114] In this detailed description, process steps described in one embodiment can be used in another embodiment even if not explicitly described in that other embodiment. When referring to a method that includes two or more defined steps herein, the defined steps can be performed in any order or simultaneously, unless the context indicates otherwise or specific instructions are provided otherwise herein. Further, unless the context indicates otherwise or explicit instructions are provided otherwise, the method can also include one or more other steps that are performed before any of the defined steps, between two of the defined steps, or after all of the defined steps.

[0115] In this detailed description, various embodiments or examples of the present invention can be implemented in various forms, such as processes, apparatuses, systems, and compositions of matter. A detailed description of one or more embodiments of the present invention has been provided above, together with the accompanying drawings that illustrate the principles of the present invention. Although the present invention has been described in connection with such embodiments, the present invention is not limited to any particular embodiment. Various changes and modifications are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternative forms, modifications, and equivalents. To provide a complete understanding of the present invention, numerous specific details are set forth herein. These details are provided for illustrative purposes only, and the present invention can be practiced without some or all of these specific details, in accordance with the claims. Technical matters known in the art related to the present invention are not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. A three-dimensional memory structure formed on a plane of a semiconductor substrate, including a plurality of stacks of thin-film ferroelectric field-effect transistors (FeFETs) configured as a plurality of stacks of NOR memory strings extending along a first direction substantially parallel to the plane of the semiconductor substrate, each stack of the NOR memory strings being provided in a stacked manner along a second direction substantially orthogonal to the plane, the thin-film ferroelectric field-effect transistors (FeFETs) of each NOR memory string sharing a common source layer and a common drain layer extending along the first direction, (i) each stack of the NOR memory strings includes a plurality of memory string pairs formed in a stacked manner along the second direction, and each memory string pair is insulated from other memory string pairs by a first insulating layer; (ii) each memory string pair includes a first common drain layer, a first common source layer, and a second common drain layer, and each layer is spaced apart from each other in the second direction by a second insulating layer; (iii) each memory string pair is composed of a first NOR memory string formed by the first common drain layer and the first common source layer, and a second NOR memory string formed by the second common drain layer and the first common source layer; (iv) a semiconductor layer is provided adjacent to each stack of the NOR memory strings and in contact with the common source layer and the common drain layer of each stack, and a channel region for the thin-film ferroelectric field-effect transistors (FeFETs) of each NOR memory string is formed by the semiconductor layer provided between the common source layer and the common drain layer adjacent to each other in the second direction; (v) a ferroelectric gate dielectric layer is provided adjacent to the semiconductor layer and along the second direction; (vi) a plurality of conductors are provided adjacent to the ferroelectric gate dielectric layer between adjacent stacks of the NOR memory strings and along the second direction, and each conductor functions as a common gate electrode for the thin-film ferroelectric field-effect transistors (FeFETs) of the NOR memory strings of the adjacent stacks, a memory structure.

2. The memory structure according to claim 1, wherein the ferroelectric gate dielectric layer includes a ferroelectric polarization layer provided as a continuous layer adjacent to each conductor in the second direction, the memory structure.

3. The memory structure according to claim 1, wherein the semiconductor layer includes a doped N-type polysilicon layer, each of the thin-film ferroelectric field-effect transistors (FeFETs) includes a depletion-mode transistor, and the memory structure further includes an interfacial dielectric layer provided between the N-type polysilicon layer and the ferroelectric gate dielectric layer, the memory structure.

4. The memory structure according to claim 3, wherein the interfacial dielectric layer includes one or more of a silicon nitride layer and an aluminum oxide layer, the memory structure.

5. The memory structure according to claim 1, wherein the semiconductor layer includes an oxide semiconductor layer, the memory structure.

6. The memory structure according to claim 5, wherein the oxide semiconductor layer includes one of an indium zinc oxide (IZO) layer and an indium gallium zinc oxide (IGZO) layer, the memory structure.

7. The memory structure according to claim 5, wherein the ferroelectric gate dielectric layer is in substantial direct contact with the oxide semiconductor layer without an intervening interfacial dielectric layer, the memory structure.

8. The memory structure according to claim 1, wherein the semiconductor layer is provided as a continuous layer along the sidewalls of each stack of the NOR memory string, the memory structure.

9. The memory structure according to claim 8, wherein the semiconductor layer includes a continuous layer formed on the opposing sidewalls of adjacent stacks of the NOR memory string, the memory structure.

10. The memory structure according to claim 9, wherein the NOR memory string is provided as rows of the NOR memory string along a third direction substantially orthogonal to both the first direction and the second direction, and the semiconductor layer associated with a first set of the plurality of conductors functioning as the common gate electrode provided between adjacent stacks of the NOR memory string is spaced apart from the semiconductor layer associated with another set of the plurality of conductors functioning as the common gate electrode provided between other adjacent stacks of the NOR memory string in the third direction, the memory structure.

11. The memory structure according to claim 1, wherein the semiconductor layer and the ferroelectric gate dielectric layer are formed adjacent to each conductor between adjacent stacks, the semiconductor layer is insulated in the first direction from the semiconductor layer associated with other conductors provided between the stacks, the memory structure. **Claim 12** The memory structure according to claim 1, wherein the first insulating layer includes an air gap cavity, the memory structure. **Claim 13** The memory structure according to claim 12, wherein the air gap cavity extends to the ferroelectric gate dielectric layer of the thin film ferroelectric field effect transistor (FeFET) within the stack of the NOR memory strings, the semiconductor layer is provided adjacent only to each pair of NOR memory strings within the stack and is segmented by the air gap cavity between adjacent pairs of NOR memory strings, the memory structure. **Claim 14** The memory structure according to claim 13, wherein the air gap cavity extends to the conductor forming the common gate electrode of the thin film ferroelectric field effect transistor (FeFET) within the stack of the NOR memory strings, the semiconductor layer and the ferroelectric gate dielectric layer are provided adjacent only to each pair of memory strings within the stack and are segmented by the air gap cavity between adjacent pairs of NOR memory strings, the memory structure. **Claim 15** The memory structure according to claim 12, wherein the second insulating layer includes an air gap cavity, the memory structure. **Claim 16** The memory structure according to claim 1 or 12, wherein the first insulating layer has a first dimension in the second direction, the second insulating layer has a second dimension in the second direction, the second dimension is the channel length of the thin film ferroelectric field effect transistor (FeFET), the memory structure. **Claim 17** The memory structure according to claim 16, wherein the first dimension of the first insulating layer is smaller than the second dimension of the second insulating layer, the memory structure. **Claim 18** The memory structure according to claim 16, wherein the first dimension of the first insulating layer is 30 nm, the second dimension of the second insulating layer is 30 to 80 nm, the memory structure.

19. The memory structure according to claim 1, wherein the common source layer and the common drain layer each include a metal layer, the memory structure.

20. The memory structure according to claim 19, wherein the semiconductor layer related to the thin-film ferroelectric field-effect transistor (FeFET) of each NOR memory string is connected to the metal layer forming the common source layer and the common drain layer, and provides a channel region without bonding for each thin-film ferroelectric field-effect transistor (FeFET), the memory structure.

21. The memory structure according to claim 19, wherein the metal layer includes one or more of molybdenum, titanium, tungsten, lanthanum, tantalum, ruthenium, any silicide thereof, any nitride thereof, and any combination thereof, the memory structure.

22. The memory structure according to claim 1, wherein the common drain layer of each NOR memory string functions as a common bit line of each NOR memory string, the memory structure.

23. The memory structure according to claim 1, wherein each conductor includes a titanium nitride layer, the memory structure.

24. The memory structure according to claim 23, wherein each conductor includes the titanium nitride layer formed adjacent to the ferroelectric gate dielectric layer and a tungsten layer formed adjacent to the titanium nitride layer, the memory structure.

25. The memory structure according to claim 1, wherein the ferroelectric gate dielectric layer includes a doped hafnium oxide layer, the memory structure.

26. The memory structure according to claim 25, wherein the doped hafnium oxide layer includes one or more of zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities, the memory structure.

27. The memory structure according to claim 1, Each of the thin-film ferroelectric field-effect transistors (FeFETs) is electrically placed in a first polarization state by applying a first voltage to both the common source layer and the common drain layer and applying a second voltage to the associated common gate electrode; Each of the thin-film ferroelectric field-effect transistors (FeFETs) is a memory structure that is electrically placed in a second polarization state by applying a third voltage to the common drain layer, applying a fourth voltage different from the third voltage to the common source layer, and applying a fifth voltage to the associated common gate electrode.

28. The memory structure according to claim 1, Each of the thin-film ferroelectric field-effect transistors (FeFETs) is electrically placed in a first polarization state by applying a first voltage to both the common source layer and the common drain layer and applying at least a second voltage to the associated common gate electrode; Each of the thin-film ferroelectric field-effect transistors (FeFETs) is a memory structure that is electrically placed in two or more polarization states by applying voltages having different voltage ranges for each of the two or more polarization states to the common drain layer, the common source layer, and the associated common gate electrode.

29. The memory structure according to claim 28, The two or more polarization states include a series of analog states, the memory structure.

30. The memory structure according to claim 27, The thin-film ferroelectric field-effect transistors (FeFETs) formed in the columns in the second direction in each stack of the NOR memory string are grouped to form a page of memory cells, The page of memory cells is a memory structure that is placed together in the first polarization state by applying the first voltage to the common source layer and the common drain layer and applying the second voltage to the common gate electrode.

31. The memory structure according to claim 27, The common source layer of the NOR memory string is electrically floating, The common source layer is biased to a given voltage during a precharge period and then left floating, the memory structure.

32. The memory structure according to claim 1, Each stack of the NOR memory string includes the thin-film ferroelectric field-effect transistors (FeFETs) formed on sidewalls on both sides of the stack, and is a memory structure.

33. The memory structure according to claim 1, wherein a circuit for supporting memory operations is formed on the plane of the semiconductor substrate under the plurality of stacks of the thin-film ferroelectric field-effect transistors (FeFETs).

34. The memory structure according to claim 33, wherein the circuit for supporting memory operations includes both analog circuits and digital circuits.

35. The memory structure according to claim 33, wherein the circuit for supporting memory operations executes erase, program, or read operations on the plurality of stacks of the thin-film ferroelectric field-effect transistors (FeFETs) in response to erase, program, or read commands provided to the memory structure.

36. The memory structure according to claim 33, further including a layer of interconnecting conductors formed above the NOR memory string and the circuit for supporting memory operations and electrically connected to the NOR memory string and the circuit for supporting memory operations, wherein the layer of interconnecting conductors is provided for routing control signals and data signals between the NOR memory string and the circuit for supporting memory operations.

37. The memory structure according to claim 36, wherein the circuit for supporting memory operations includes two or more of a word line driver circuit, a bit line driver circuit, an input / output driver circuit, an address decoder, a sense amplifier, a voltage source for generating an operating voltage for memory operations, a latch, a register, other memory elements, and a state machine for managing memory operations in the thin-film ferroelectric field-effect transistors (FeFETs) of the NOR memory string.

38. The memory structure according to claim 35, wherein the circuit for supporting memory operations is connected to a memory controller formed on a separate semiconductor substrate and receives the commands and data signals from the memory controller.

39. The memory structure according to claim 1, wherein each of the thin-film ferroelectric field-effect transistors (FeFETs) has a data retention time of more than 1 hour and a program / erase cycle durability of more than 108 cycles, the memory structure.

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