Clock signal generation circuit

Abstract

To provide a clock signal generation circuit capable of generating clock signals so as to guarantee an order of ON / OFF timings of both of a switched capacitor signal and a chopping signal.SOLUTION: In a switched capacitor system 1, first and second synchronization clock circuits 4(1 and 2) generate clock signals synchronized with an ADC operation frequency signal and a chopping frequency signal, respectively, by a master clock. An ON / OFF edge generator 6 delays the ADC operation frequency signal to generate a plurality of rising and falling edge signals. For a switched capacitor signal generated at a clock generator 7, its frequency is prescribed by the first synchronization clock circuit 4(1), and its rising and falling edges are prescribed by the ON / OFF edge generator 6. For a chopping signal generated at a clock generator 8, its frequency is prescribed by the second synchronization clock circuit 4(2), and its rising and falling edges are prescribed by the ON / OFF edge generator 6.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit that generates a clock signal to be supplied to a switched capacitor circuit having a function of chopping a signal.

Background Art

[0002] For example, in Non-Patent Document 1, as shown in FIG. 10, in a ΔΣ type A / D converter using a switched capacitor circuit, a configuration for performing chopping to reduce an offset voltage is disclosed. Since there is also a switch inside the A / D converter, a configuration for merging the internal switch and the chopping switch by merging the timing signal for turning ON / OFF the internal switch and the timing signal for turning ON / OFF the chopping switch is also disclosed.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the configuration disclosed in Non-Patent Document 1, since the respective signals are not created from circuits that generate the same edge, the ON / OFF timing in the switched capacitor and the ON / OFF timing of the chopping signal may be out of order, and the order of the ON / OFF timings of both is not guaranteed. When configuring a ΔΣ type A / D converter, if the ON / OFF timings of both are out of order, it will affect the output error of the A / D converter.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a clock signal generation circuit that can generate a clock signal so as to guarantee the order of the ON / OFF timings of a switched capacitor signal and a chopping signal.

Means for Solving the Problems

[0006] According to the clock signal generation circuit described in claim 1, the first and second synchronous clock circuits generate first and second synchronous clock signals in which first and second operating frequency signals are synchronized by a master clock, respectively. The edge signal generation circuit generates one or more rise and fall edge signals by delaying the first synchronous clock signal. The first clock signal group generated by the first clock generator has a frequency is defined by the first synchronous clock circuit, and its rise and fall edges are defined by the edge signal generation circuit. Also, the second clock signal group generated by the second clock generator has a frequency defined by the second synchronous clock circuit, and its rise and fall edges are defined by the edge signal generation circuit.

[0007] With such a configuration, since the frequencies of the first clock signal group mainly for driving the switch capacitor circuit and the second clock signal group for driving the chopping functional unit are individually defined by the first and second synchronous clock circuits, respectively, each frequency can be set flexibly. And since the rise and fall edges of the first and second clock signal groups are both defined by the edge signal generation circuit, the edge timings of both signal groups can be synchronized according to the rise and fall edge signals.

[0008] Further, according to the clock signal generation circuit described in claim 3, it is the same as the clock signal generation circuit described in claim 1 except that the edge signal generation circuit generates one or more rise and fall edge signals by delaying the second synchronous clock signal. Therefore, the same effects as those of claim 1 can be obtained.

Brief Description of the Drawings

[0009]

Figure 1

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Figure 10

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (First Embodiment) As shown in FIGS. 1 and 2, the switched capacitor system 1 of this embodiment is configured to generate and supply a clock signal for driving each part to a switched capacitor circuit 2 having a chopping function part. The switched capacitor circuit 2 is applied, for example, to constitute a ΔΣA / D converter. Details of the operation of the ΔΣA / D converter are described, for example, in Japanese Patent No. 6753330 and the like.

[0011] The output terminal of the operational amplifier OP constituting the switched capacitor circuit 2 is connected to the inverting input terminal of the operational amplifier OP via the integration capacitor Cf. The non-inverting input terminal of the operational amplifier OP is connected to the ground. One end of the sampling capacitor Cs is connected to the input terminal of the analog signal Vin via the switch SS1 and is also connected to the ground via the switch SS2. The other end of the sampling capacitor Cs is connected to the ground via the switch SS3 and is also connected to the inverting input terminal of the operational amplifier OP via the switch SS4.

[0012] The DAC indicates a reference voltage for operating as a D / A converter. The DAC is applied to one end of the DAC capacitor Cd via the switch SD1, and the other end of the DAC capacitor Cd is connected to the common connection point of the sampling capacitor Cs and the switch SS4. The chopping switch CSW1, which is a chopping function part, is arranged on the input terminal side of the operational amplifier OP, and the chopping switch CSW2 is arranged on the output terminal side of the operational amplifier OP.

[0013] The master clock signal is input to the first frequency division circuit 3 and the synchronization circuit 4. The clock signal frequency-divided in the first frequency division circuit 3 becomes a clock signal having a frequency required for the operation of the ΔΣ A / D converter in the switch capacitor circuit 2 (see FIGS. 3(1) and (2)). Hereinafter, the operation of the A / D converter is referred to as the "ADC operation". Also, a clock signal having a frequency required for the ADC operation is referred to as an ADC operation frequency signal. The ADC operation frequency signal is the first operation frequency signal.

[0014] The ADC operation frequency signal is input to the synchronization circuit 4 and the second frequency division circuit 5. The clock signal frequency-divided in the second frequency division circuit 5 becomes a clock signal having a frequency required for the chopping operation in the switch capacitor circuit 2 (see FIG. 3(3)). This clock signal is referred to as a chopping frequency signal. The chopping frequency signal is also input to the synchronization circuit 4. The chopping frequency signal is the second operation frequency signal.

[0015] The synchronization circuit 4 synchronizes and outputs the ADC operation frequency signal and the chopping frequency signal with the master clock signal, respectively (see FIGS. 3(4) and (5)). The synchronized ADC operation frequency signal is input to the ON / OFF edge generator 6 and the switch capacitor clock generator 7, and the synchronized chopping frequency signal is input to the chopping clock generator 8.

[0016] Note that the synchronization circuit 4 is actually divided into two. The side that synchronizes the ADC operation frequency signal is the first clock synchronization circuit 4(1), and the side that synchronizes the chopping frequency signal is the second clock synchronization circuit 4(2). The ADC operation frequency signal synchronized with the master clock signal is the first synchronization clock signal, and the chopping frequency signal synchronized with the master clock signal is the second synchronization clock signal.

[0017] The ON / OFF edge generator 6, which is an edge signal generation circuit, outputs the input ADC operation frequency signal as it is, and uses the signal obtained by delaying the said signal step by step as an ON / OFF edge signal (refer to Fig. 3(6)), and outputs them to the switched-capacitor clock generator 7 and the chopping clock generator 8, which are the first clock generator and the second clock generator respectively. In these clock generators 7 and 8, signals for operating the switched-capacitor circuit 2 and signals for operating the chopping functional unit are generated respectively (refer to Fig. 3(7), (8)) and supplied to the switched-capacitor circuit 2.

[0018] Φ1, Φ1d, Φ2, Φ2d of the switched-capacitor signal (7) shown in Fig. 4 are signals for controlling the ON / OFF of switches SS3, SS1, SS4, SD1 respectively, and correspond to the first clock signal group. Also, the chopping signal (8) shown in the same figure is a signal for controlling the ON / OFF of chopping switches CSW1, CSW2, and corresponds to the second clock signal group.

[0019] As described above, according to this embodiment, in the switched-capacitor system 1, the first synchronous clock circuit 4(1) and the second synchronous clock circuit 4(2) generate clock signals obtained by synchronizing the ADC operation frequency signal and the chopping frequency signal with the master clock respectively. The ON / OFF edge generator 6 generates a plurality of rise and fall edge signals by delaying the ADC operation frequency signal. The switched-capacitor signal generated by the switched-capacitor clock generator 7 has its frequency defined by the first synchronous clock circuit 4(1), and its rise and fall edges defined by the ON / OFF edge generator 6. Also, the chopping signal generated by the chopping clock generator 8 has its frequency defined by the second synchronous clock circuit 4(2), and its rise and fall edges defined by the ON / OFF edge generator 6.

[0020] With such a configuration, since the switched capacitor signal for driving the switch capacitor circuit 2 and the chopping signals for driving the chopping switches CSW1 and CSW2 have their respective frequencies individually defined by the first and second synchronous clock circuits, each frequency can be flexibly set. And since the rise and fall edges of the switched capacitor signal and the chopping signals are both defined by the ON / OFF edge generator 6, the edge timings of both signals can be synchronized according to the rise and fall edge signals. And by synchronizing the edge timings of both signals as described above, the ON / OFF timing order of the switched capacitor signal and the chopping signal becomes as expected, so that the A / D conversion operation can be correctly performed.

[0021] (Second Embodiment) Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted, and the different parts will be described. In the switched capacitor system 11 of the second embodiment shown in FIG. 5, the arrangement of the ON / OFF edge generator 6 between the synchronous circuit 4 and the clock generators 7 and 8 is different from that of the switched capacitor system 1. That is, the ADC operation frequency signal synchronized in the synchronous circuit 4(1) is directly input to the switched capacitor clock generator 7. And the chopping frequency signal synchronized in the synchronous circuit 4(2) is input to the ON / OFF edge generator 6 and the chopping clock generator 8.

[0022] As a result, as shown in FIG. 6, the ON / OFF edge signal (6) output by the ON / OFF edge generator 6 is the chopping frequency signal and the signal obtained by delaying the signal step by step. Also in the case of the second embodiment configured as above, the same effects as those of the first embodiment can be obtained.

[0023] (Third Embodiment) In the first embodiment, the ADC operation frequency signal is generated by the second frequency division circuit 5 dividing the ADC operation frequency signal to generate a chopping frequency signal. However, in the third embodiment shown in FIG. 7, the second frequency division circuit 5 divides the master clock signal to generate a chopping frequency signal.

[0024] (Fourth Embodiment) The fourth embodiment shows a variation in the arrangement of the chopping functional unit in the switched capacitor circuit. In the switched capacitor system 12 shown in FIG. 8, a chopping switch CSW1 is arranged between the DAC and the DAC capacitor Cd, and a chopping switch CSW2 is arranged between the input voltage Vin and the sampling capacitor Cs. Further, chopping switches CSW3 and CSW4 are arranged at both ends of the integrating capacitor Cf, and a chopping switch CSW5 is arranged at the output terminal of the operational amplifier OP.

[0025] (Fifth Embodiment) The fifth embodiment shown in FIG. 9 also shows a variation in the arrangement of the chopping functional unit, similar to the fourth embodiment. In the switched capacitor system 13 of the fifth embodiment, the reference voltage DAC is generated by the bandgap reference voltage circuit 14. A series circuit of a current source 15, resistor elements R1 and R2, and diode D1 is connected between the power supply and the ground. Also, a series circuit of resistor element R3 and diode D2 is connected in parallel to the series circuit.

[0026] Here, let the operational amplifier constituting the switched capacitor circuit 2 be OP1, and the operational amplifier used in the reference voltage circuit 14 be OP2. The common connection point of the resistor elements R1 and R2 is connected to the inverting input terminal of the operational amplifier OP2, and the anode of the diode D2 is connected to the non-inverting input terminal of the operational amplifier OP2. The output terminal of the operational amplifier OP2 is connected to the common connection point of the resistor elements R1 and R3 and serves as the terminal for supplying the reference voltage DAC. And the chopping switches CSW1 and CSW2 are arranged on the input terminal side and the output terminal side of the operational amplifier OP2, respectively, instead of the operational amplifier OP1.

[0027] (Other embodiments) The switched capacitor circuit is not limited to constituting a ΔΣ A / D converter. The rising and falling edge signals generated by the edge signal generation circuit may each be one or more. The chopping frequency signal is not limited to being a frequency-divided-by-two signal of the ADC operation frequency signal. An external clock signal may be used instead of the master clock signal.

[0028] Although the present disclosure has been described based on embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

Description of reference numerals

[0029] In the drawings, 1 is a switched capacitor system, 2 is a switched capacitor circuit, 3 is a first half-cycle generation circuit, 4(1) is a first clock synchronization circuit, 4(2) is a second clock synchronization circuit, 5 is a second half-cycle generation circuit, 6 is an ON / OFF edge generator, 7 is a clock generator for the switched capacitor, 8 is a clock generator for chopping, and CSW1 and CSW2 indicate chopping switches.

Claims

1. A clock signal generation circuit that generates a clock signal for driving each part of a switched capacitor circuit (2) having a chopping function unit (CSW1, CSW2, CSW3, CSW4, CSW5) for chopping a signal, A first synchronous clock circuit (4(1)) that generates a first synchronous clock signal by synchronizing a first operating frequency signal with a master clock, A second synchronous clock circuit (4(2)) that generates a second synchronous clock signal by synchronizing a second operating frequency signal with a master clock, An edge signal generation circuit (6) that generates one or more rise and fall edge signals by delaying the first synchronous clock signal, A first clock generator (7) that generates a first group of clock signals mainly for driving the switched capacitor circuit, A second clock generator (8) that generates a second group of clock signals for driving the chopping function unit, and The first group of clock signals has a frequency defined by the first synchronous clock circuit, and its rise and fall edges are defined and output by the edge signal generation circuit, The second group of clock signals has a frequency defined by the second synchronous clock circuit, and its rise and fall edges are defined and output by the edge signal generation circuit. The clock signal generation circuit.

2. The clock signal generation circuit according to claim 1, wherein the edge signal generation circuit generates the rise and fall edge signals by using one or more phase-shifted clock signals obtained by phase-shifting the first synchronous clock signal by a predetermined phase amount.

3. A clock signal generation circuit that generates a clock signal for driving each part of a switched capacitor circuit (2) having a chopping function unit (CSW1, CSW2, CSW3, CSW4, CSW5) for chopping a signal, A first synchronous clock circuit (4(1)) that generates a first synchronous clock signal by synchronizing a first operating frequency signal with a master clock, A second synchronous clock circuit (4(2)) that generates a second synchronous clock signal by synchronizing a second operating frequency signal with a master clock, An edge signal generation circuit (6) that generates one or more rise and fall edge signals by delaying the second synchronous clock signal, A first clock generator (7) that generates a first group of clock signals mainly for driving the switched capacitor circuit, A second clock generator (8) for generating a second clock signal group for driving the chopping function unit is provided. The first clock signal group has its frequency defined by the first synchronous clock circuit, and its rising and falling edges are defined and output by the edge signal generation circuit. The second clock signal group is a clock signal generation circuit whose frequency is defined by the second synchronous clock circuit, and whose rising and falling edges are defined and output by the edge signal generation circuit.

4. The clock signal generation circuit according to claim 3, wherein the edge signal generation circuit also uses one or more phase-shifted clock signals obtained by phase-shifting the second synchronous clock signal by a predetermined phase amount to generate the rising and falling edge signals.

5. The clock signal generation circuit according to any one of claims 1 to 4, wherein the chopping function unit (CSW1, CSW2) is disposed on the input terminal side and the output terminal side of the operational amplifier constituting the switch capacitor circuit.

6. The clock signal generation circuit according to any one of claims 1 to 4, wherein the chopping function unit (CSW1 to CSW5) is disposed on the input side of the input capacitor constituting the switch capacitor circuit, across both ends of the feedback capacitor of the operational amplifier constituting the switch capacitor circuit, and at the subsequent stage of the output terminal of the operational amplifier.

7. The clock signal generation circuit according to any one of claims 1 to 4, wherein the chopping function unit (CSW1, CSW2) is disposed on the input terminal side and the output terminal side of the operational amplifier constituting the reference voltage circuit for applying a reference voltage to the switch capacitor circuit.

8. The clock signal generation circuit according to any one of claims 1 to 7, wherein the second operating frequency signal is generated by integer-dividing the first operating frequency signal.

9. The clock signal generation circuit according to any one of claims 1 to 7, further comprising a frequency division circuit (3, 5) for frequency-dividing an external clock signal or the master clock signal to generate the first operating frequency signal and the second operating frequency signal.

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