Plating method for printed circuit board and printed circuit board using the same

Abstract

A method for plating a printed circuit board and a printed circuit board using the same are provided. [Solution] A method for plating a printed circuit board according to an embodiment of the present invention includes the steps of contacting a substrate having through holes formed therein with a plating solution and positioning the substrate so that the substrate faces an electrode, and applying pulse currents to both sides of the substrate, wherein pulse currents of opposite polarity are applied to both sides of the substrate at least once and pulse currents of positive polarity are applied to both sides of the substrate at least once, thereby forming plating that fills the through holes from the middle to the ends.

Description

Technical Field

[0001] The present invention relates to a plating method for a printed circuit board and a printed circuit board using the same.

Background Art

[0002] As the integration degree of electronic components and printed circuit boards increases, higher requirements are placed on high-speed signal transmission and high heat dissipation characteristics in printed circuit boards.

[0003] In a printed circuit board, through vias in the form of PTH (Plated Through Hole) are formed for signal transmission. However, due to the limitations of current plating technology, only the wall surface of the hole is plated, and the rest is generally filled with insulating resin ink. However, in the case of vias formed in this way, due to the difference in the coefficient of thermal expansion (CTE) between different materials (for example, copper and insulating resin), the quality reliability is low, the heat dissipation characteristics are insufficient, and it is difficult to apply to products that require high-speed signal transmission and high heat dissipation characteristics such as 5G antenna modules.

[0004] On the other hand, in order to improve the heat dissipation characteristics of a printed circuit board, staggered vias in which a plurality of vias are stacked so that a part overlaps, or stacked vias in which they are stacked so as to completely overlap are used. Although the heat dissipation characteristics can be improved through such vias, defects such as cracks and delamination of the interlayer vias generated when stacking the vias occur, and problems such as signal noise caused by the stacked vias also occur.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention provides a plating method for a printed circuit board capable of forming vias ensuring high-speed signal transmission and high heat dissipation characteristics, and a printed circuit board using the same.

Means for Solving the Problems

[0007] The plating method for a printed circuit board according to one aspect of the present invention includes a step of bringing a substrate with through holes formed into contact with a plating solution and arranging the substrate facing an electrode, and a step of applying a pulsed current to both surfaces of the substrate, wherein a pulsed current of opposite polarities is applied to both surfaces of the substrate at least once, and a pulsed positive current is applied to both surfaces of the substrate at least once, and plating can be formed from the middle to the end of the through hole.

[0008] On the other hand, a printed circuit board according to another aspect of the present invention includes a substrate with through holes formed, and vias filling the through holes and extending to both surfaces of the substrate. The vias include a first plating layer formed inside the through holes and having a concave groove portion formed on the surface of the substrate, and a second plating layer filling the groove portion, coupled to the first plating layer, and formed to extend on the substrate. The first plating layer can have crystal grains with a larger area in a region disposed at the lower part of the groove portion than in a region disposed at the central part of the through hole.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] Examples of the printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings. When explaining with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and duplicate explanations thereof are omitted.

[0011] Also, terms such as "first" and "second" used below are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are not limited by terms such as first and second.

[0012] Further, the term "coupling" does not only mean physical direct contact between each component in the contact relationship between each component, but is used as a concept that includes cases where other components are interposed between each component and each component is in contact with the other components.

[0013] <Method for plating a printed circuit board> FIG. 1 is a flowchart showing a method for plating a printed circuit board according to an embodiment of the present invention, and FIGS. 2 to 5 are diagrams illustrating the method for plating a printed circuit board according to an embodiment of the present invention.

[0014] Referring to FIG. 1, the method for plating a printed circuit board according to an embodiment of the present invention includes a step S110 of arranging a substrate 10 and a step S120 of applying a pulsed current to both sides of the substrate 10.

[0015] In the step S110 of arranging the substrate 10, the substrate 10 is arranged for electroplating. Through holes 13 are formed in the substrate 10, and vias by plating can be formed inside the through holes 13.

[0016] The substrate 10 in which the through holes 13 are formed is brought into contact with a plating solution so that plating can be performed. For example, the substrate 10 can be arranged in a plating tank (not shown) containing the plating solution, and the substrate 10 can be immersed in the plating solution.

[0017] Further, the substrate 10 can be arranged so as to face an electrode (not shown) for plating. The electrode can form a potential difference with the surface of the opposed substrate 10 and apply a current to the substrate 10. For example, the substrate 10 can be positioned between a pair of electrodes, and the substrate 10 can be arranged such that both sides of the substrate 10 face the electrodes respectively. Further, a seed layer 13a for plating can be formed on both sides of the substrate 10 and the inner wall of the through hole 13.

[0018] In step S120 of applying a pulsed current to both sides of the substrate 10, a current is applied to one surface 10a and the other surface 10b of the substrate 10 to perform electrolytic plating. At this time, a pulsed current can be applied to the substrate 10. In this embodiment, the current can be applied to the substrate 10 by the PPR (periodic pulse reverse) method. That is, in the plating process, the electrode can form not only a forward current but also a reverse current with respect to the substrate 10.

[0019] In particular, the plating method according to this embodiment includes at least once the process in which pulsed currents of opposite polarities are applied to both sides of the substrate 10. For example, when a first pulsed current is applied to one surface 10a of the substrate 10 and a second pulsed current is applied to the other surface 10b of the substrate 10, the first pulsed current and the second pulsed current can have different polarities from each other for a certain period of time. Specifically, the first pulsed current has a first cycle C1 including a section for applying a reverse current, and the second pulsed current can have a second cycle C2 that temporally overlaps with the section for applying the reverse current of the first pulsed current and includes a section for applying a forward current.

[0020] Here, being temporally overlapped means that two target sections coexist for a predetermined period of time. In other words, it is sufficient if there is a temporal region where the two sections exist simultaneously, and the temporal length, start and end points, etc. of each section can be set without limitation.

[0021] On the other hand, the first cycle C1 of the first pulsed current and the second cycle C2 of the second pulsed current can have a repeated period, but the cycle may end in one time. Also, the first cycle C1 and the second cycle C2 preferably have the same period, but are not limited thereto, and may be cycles having different periods from each other.

[0022] In addition, the plating method according to this embodiment includes at least one process of applying a pulsed positive current to both sides of the substrate 10. For example, on both sides of the substrate 10, the first pulsed current and the second pulsed current can have the same polarity in which plating is formed during a certain period of time. Specifically, the first cycle C1 of the first pulsed current also includes a section where a positive current is applied, and can be temporally overlapped with the section where a positive current is applied in the second cycle C2 of the second pulsed current.

[0023] Referring to FIGS. 2 and 3, on one surface 10a of the substrate 10, opposed first electrodes are arranged, and the first electrodes form a potential difference with one surface 10a of the substrate 10, and a first pulsed current can be applied. At this time, in the first cycle C1 of the first pulsed current, a first - 1 section where a reverse current is applied and a first - 2 section where a positive current is applied can occur.

[0024] Also, on the other surface 10b of the substrate 10, opposed second electrodes are arranged, and the second electrodes form a potential difference with the other surface 10b of the substrate 10, and a second pulsed current can be applied. At this time, in the second cycle C2 of the second pulsed current, a second - 1 section where a positive current with a high current density is applied and a second - 2 section where a positive current with a lower current density than the second - 1 section is applied can occur.

[0025] At this time, referring to FIG. 2, in order to apply pulses of opposite polarities to both sides of the substrate 10, the first - 1 section of the first cycle C1 and the second - 1 section of the second cycle C2 can be temporally overlapped. In other words, during a predetermined period of time, a reverse current can be applied to one surface 10a of the substrate 10 by the first pulsed current, and at the same time, a positive current can be applied to the other surface 10b of the substrate 10 by the second pulsed current.

[0026] On the other side 10b of the substrate 10 to which a positive current is applied, plating is formed. On the contrary, on one side 10a of the substrate 10 to which a reverse current is applied, plating may be decomposed. In addition, a reverse current is applied to one side 10a of the substrate 10, and plating additives such as a plating accelerator 2 and a plating inhibitor 4 may be separated on the other side 10b of the substrate 10 on the surface. At this time, the plating accelerator 2 and the plating inhibitor 4 may also be separated on the inner wall of the through hole 13.

[0027] On the other hand, overall, the first electrode facing one side 10a of the substrate 10 becomes the cathode, and the second electrode facing the other side 10b of the substrate 10 becomes the anode. Therefore, a flow in which cations 6 such as metal ions in the plating solution move toward the first electrode can be formed. As a result, a flow of cations 6 such as metal ions toward the first electrode can also be formed inside the through hole 13 of the substrate 10.

[0028] At this time, in order to adjust the plating decomposition on one side 10a of the substrate 10, the separation of the plating additive, and / or the flow of cations 6 such as metal ions inside the through hole 13, the value of the reverse current of the first pulsed current and the value of the positive current of the second pulsed current can be adjusted. In this embodiment, the reverse current of the first pulsed current and the positive current of the second pulsed current are set to have similar current values with respect to the surface of the substrate 10 to which each is applied, and they are set to have opposite polarities but similar current values. In addition, it can be set to have a higher current value compared to when a positive current is applied to both sides of the substrate 10 (for example, the first-second section and the second-second section).

[0029] Referring to FIG. 3, in order to apply positive current pulses of the same polarity to both sides of the substrate 10, the first-second section of the first cycle C1 and the second-second section of the second cycle can be temporally overlapped. In other words, during a predetermined time, a positive current can be applied to both sides of the substrate 10 simultaneously by the first pulsed current and the second pulsed current.

[0030] On both sides of the substrate 10 to which a positive current is applied, plating is formed. In particular, when a positive current is applied to both sides of the substrate 10 after applying opposite polarities to both sides of the substrate 10, plating can be formed that fills the through hole 13 from the middle to the end. Specifically, as described above, when a pulsed current of opposite polarities is applied to both sides of the substrate 10, the plating accelerator 2 and the plating inhibitor 4 may separate on the surface of the substrate 10 to which the reverse current is applied and on the inner wall of the through hole 13. Thereafter, when a pulsed positive current is applied to both sides of the substrate 10, the density of the plating accelerator 2 is concentrated in the middle of the through hole 13, and plating can be formed that fills the through hole 13 from the middle to the end.

[0031] The plating accelerator 2 contained in the plating solution is known to play a role in accelerating the plating rate in a specific region / portion, etc. The plating solution contains a plating inhibitor 4 together with the plating accelerator 2. However, the lower the concentration of the plating inhibitor 4, the easier the adsorption of the plating accelerator 2 to the substrate 10, and the greater the effect of plating acceleration can be.

[0032] The plating solution contains a plating accelerator 2 and a plating inhibitor 4, and the plating inhibitor 4 can have a molecular weight larger than that of the plating accelerator 2. For example, the plating accelerator 2 can be an organic substance containing a disulfide bond (-S-S) or a mercapto group (-SH), such as bis(sodiumsulfopropyl)disulfide (SPS), mercaptopropylsulfonic acid (MPS), 3-N,N-Dimethylaminodithiocarbamoyl-1-propanesulfonic acid (DPS), 3-S-isothiuronium propyl sulfonate (UPS), 3-(benzothiazolyl-2-mercapto)-propyl-sulfonic acid sodium salt (ZPS), etc. Also, for example, the plating inhibitor 4 can be an organic substance having a polyether series polymer substance and a functional group containing a nitrogen atom. Thereby, the plating inhibitor 4 may be a polymer substance having a larger molecular weight and size than the plating accelerator 2.

[0033] As shown in FIG. 3, after applying opposite polarities to both sides of the substrate 10, when a positive current is applied to both sides of the substrate 10, plating additives such as the plating accelerator 2 and the plating inhibitor 4 can be adsorbed onto the substrate 10 again.

[0034] On one hand, inside the through-hole 13 of the substrate 10, the flow of the plating solution is obstructed more than on the surface of the substrate 10. As a result, on the surface of the substrate 10, a relatively faster flow rate is formed compared to the inside of the through-hole 13, the re-adsorption of the plating inhibitor 4 occurs quickly, and the action of the plating accelerator 2 is relatively reduced. On the contrary, inside the through-hole 13 where the flow rate is slow, the re-adsorption process of the plating inhibitor 4 becomes slow, and the adsorption of the plating accelerator 2 with a small molecular weight or size may be relatively easy. Thereby, the density of the plating accelerator 2 increases inside the through-hole 13, the accelerating effect of plating becomes large, and plating growth inside the through-hole 13 can occur intensively. At this time, on the surface of the substrate 10, since the density of the plating inhibitor 4 increases, the plating on the surface of the substrate 10 can also be minimized at the same time.

[0035] Also, in the plating method according to this embodiment, a reverse current can be applied to the other surface 10b of the substrate 10 and a positive current that overlaps the reverse current temporally can be applied to one surface 10a of the substrate 10 so that uniform plating is formed on both sides of the substrate 10.

[0036] That is, with the surface of the substrate 10 reversed, plating can be performed symmetrically to the above-described plating process. Specifically, the second cycle C2 of the second pulse current includes a section where a reverse current is applied, and the first cycle C1 of the first pulse current temporally overlaps with the section where the reverse current of the second pulse current is applied and can include a section where a positive current is applied. Also, the first cycle C1 of the first pulse current and the second cycle C2 of the second pulse current each include a section where a second positive current is applied, and the sections where the second positive current is applied can be temporally overlapped.

[0037] Referring to FIGS. 4 and 5, in the first cycle C1, a first - 3 section in which a positive current with a high current density higher than that in the first - 2 section is applied, and a first - 4 section in which a positive current with a low current density lower than that in the first - 3 section can further occur. Also, in the second cycle C2, a second - 3 section in which a reverse current is applied, and a second - 4 section in which a positive current with a low current density lower than that in the second - 1 section can further occur. At this time, the first - 3 section of the first cycle C1 and the second - 3 section of the second cycle can be temporally overlapped so that pulse currents with opposite polarities are applied to both sides of the substrate 10. Here, the current situation occurring on one surface 10a and the other surface 10b of the substrate 10 shows a direction opposite to the current situation described with reference to FIGS. 2 and 3. That is, the current situation occurring on one surface 10a of the substrate 10 in FIGS. 2 and 3 occurs on the other surface 10b of the substrate 10 in FIGS. 4 and 5, and the current situation occurring on the other surface 10b of the substrate 10 in FIGS. 2 and 3 occurs on one surface 10a of the substrate 10 in FIGS. 4 and 5. However, inside the through - hole 13, the density of the plating accelerator 2 increases, the plating acceleration effect becomes large, and the plating growth inside the through - hole 13 can occur in the same manner regardless of the direction.

[0038] Therefore, when the first pulse current and the second pulse current each having the first cycle C1 and the second cycle C2 shown in FIGS. 2 to 5 are applied to both sides of the substrate 10, symmetrically uniform plating is formed on both sides of the substrate 10, and inside the through - hole 13, the plating can be filled from the middle to both side ends. At this time, the plating on both sides of the substrate 10 can be maintained such that the growth of the thickness is continuously suppressed and does not grow thick even in the process of filling the through - hole 13 with plating.

[0039] On the one hand, in this embodiment, although it has been exemplified that the corresponding sections in the first cycle C1 and the second cycle C2 coincide temporally, it is not limited thereto. It is sufficient if the corresponding sections in the first cycle C1 and the second cycle C2 can be overlapped within a certain period of time, and the temporal lengths, start and end points of each section can also be set differently.

[0040] <Printed circuit board>

[0041] FIG. 6 is a diagram showing a printed circuit board according to an embodiment of the present invention.

[0042] Referring to FIG. 6, a printed circuit board 110 according to an embodiment of the present invention includes a substrate 110 and a via V, and the via V can include a first plating layer 120 and a second plating layer 130.

[0043] The substrate 110 is a portion where a circuit is formed and includes an insulating layer that electrically insulates the circuit pattern. In order to form a via V that connects the circuit patterns on both sides of the substrate 110, a through hole 113 is formed in the substrate 110.

[0044] Referring to FIG. 6, the substrate 110 in this embodiment can be made of an insulating material 112 without an internal circuit layer. For example, a thick core insulating material with a thickness of 0.3 mm or more can constitute the substrate 110. At this time, the through hole 113 has a diameter of 150 μm or more and can be formed by mechanical processing such as drilling.

[0045] The via V is a part of the circuit and is a part that connects the circuit patterns formed on both sides of the substrate 110. The via V can be made of a conductive material and include a metal such as copper, fill the through hole 113 formed in the substrate 110, and can have a structure extending to both sides of the substrate 110.

[0046] Via V includes a first plating layer 120 and a second plating layer 130. The first plating layer 120 is formed inside the through hole 113, and a concave groove portion 121 is formed on the surface of the substrate 110. For example, both ends of the first plating layer 120 extend up to both surfaces of the substrate 110, but concave groove portions 121 are formed at both ends of the first plating layer 120, and the bottom of the groove portion 121 can be formed lower than the surfaces 110a and 110b of the substrate 110.

[0047] FIG. 7 is a diagram showing the first plating layer of a printed circuit board according to an embodiment of the present invention. FIG. 7 is a diagram showing the formed shape of the first plating layer 120 before the second plating layer 130 is formed in FIG. 6.

[0048] Referring to FIGS. 6 and 7, the first plating layer 120 can be formed in a form that fills the inside of the through hole 113 without a gap except for a part at both ends of the through hole 113. Also, the end portion of the first plating layer 120 can have a form that extends on the surface of the substrate 110 along the inner wall of the through hole 113. That is, the first plating layer 120 can extend up to the land of the via V.

[0049] At this time, a seed layer 113a is formed on the inner wall of the through hole 113, and the first plating layer 120 can be an electrolytic plating layer formed on the seed layer 113a. As described in the above plating method, the seed layer can be formed on the surface of the substrate 110 and the through hole 113 for electrolytic plating. Also, the first plating layer 120 is an electrolytic plating layer and can be formed from the middle to both ends of the through hole 113 by the above plating method.

[0050] The second plating layer 130 is filled in the groove portion 121, formed on the first plating layer 120, and extended and formed on the substrate 110. For example, after the first plating layer 120 is formed, secondary additional plating is performed to form the second plating layer 130 on the first plating layer 120, and the groove portion 121 can be filled by the second plating layer 130.

[0051] Referring to FIGS. 6 and 7, the second plating layer 130 can be formed to fill the ends of the through holes 113 remaining after the first plating layer 120 is filled and extend to the lands of the vias V, having a flat upper surface on the first plating layer 120. That is, the second plating layer 130 can be formed in the form of a blind via on the first plating layer 120 having the concave groove portion 121 to form an integrated via V.

[0052] At this time, a circuit pattern (not shown) connected to the via V is formed on the substrate 110. In the first plating layer 120, the depth d of the groove portion 121 is 150 μm or less, and the thickness of the circuit pattern can be 30 μm or less (in this embodiment, since the thickness of the circuit pattern is similar to the thickness of the via V land, it is indicated by the thickness t of the via V land instead of the thickness of the circuit pattern). Thus, as shown in FIG. 7, after the first plating layer 120 is formed, the groove portion 121 with a depth of 150 μm or less can be filled by one plating to form a fine circuit pattern with a thickness of 30 μm or less. The second plating layer 130 can be formed by a plating process for forming the circuit pattern.

[0053] Also, on the surface of the substrate 110, the thickness of the first plating layer 120 can be formed to be greater than the thickness of the second plating layer 130. For example, when growing the plating layer inside the through hole 113 by the above-described plating method, the thickness of the first plating layer 120 formed on the substrate 110 can be adjusted by adjusting current conditions and the like.

[0054] In particular, the first plating layer 120 of this embodiment is formed by the above-described plating method, and regions with different crystal grain sizes can be formed in the plating layer. Specifically, the region 126 disposed at the lower part of the groove portion 121 in the first plating layer 120 can have larger crystal grains than the regions 122 and 124 disposed at the central part of the through hole 113.

[0055] Figures 8 to 10 are photographs showing the via V of the printed circuit board 110 according to an embodiment of the present invention. FIG. 9 shows the formed shape of the first plating layer 120 before the second plating layer 130 is formed in FIG. 8, and FIG. 10 is a magnified photograph of the first plating layer 120 shown in FIG. 9.

[0056] Referring to FIGS. 8 to 10, the first plating layer 120 can be formed to include fine crystal grain regions 122 and 124 and a coarse crystal grain region 126. Crystal grains are an aggregate of crystal lattices grown from one crystal nucleus, and when the cross-section of a metal or alloy is viewed with a microscope or the like, they can be identified as particle forms. The first plating layer 120 can be roughly divided into two regions where the sizes of the crystal grains are clearly distinguishable.

[0057] The fine crystal grain regions 122 and 124 are formed at the center of the through hole 113 and on the inner wall of the through hole 113, and can have a form that extends from the center of the through hole 113 to the inner wall side of the through hole 113. That is, most of the first plating layer 120 near the inner wall of the through hole 113 is the fine crystal grain regions 122 and 124, and only the middle portion of the first plating layer 120 near the center of the through hole 113 can be the fine crystal grain regions 122 and 124 in the thickness direction of the substrate 110.

[0058] Referring to FIG. 9, the fine crystal grain regions 122 and 124 can have a structure that extends along the inner wall of the through hole 113 to the surface of the substrate 110.

[0059] The coarse crystal grain region 126 is formed with metal particles larger than the metal particles in the fine crystal grain regions 122 and 124. The coarse crystal grain region 126 can be formed below the groove portion 121. Also, it can have a structure surrounded by the fine crystal grain regions 122 and 124.

[0060] Also, the fine crystal grain regions 122 and 124 in this embodiment can be further divided into two regions where the sizes of the crystal grains are distinguishable again.

[0061] Referring to FIG. 10, in this embodiment, at the end of the first plating layer 120, the fine crystal grain regions 122 and 124 can be divided into two regions. Specifically, the fine crystal grain regions 122 and 124 include a first fine crystal grain region 122 that extends toward the inner wall side at the center of the through hole 113, and a second fine crystal grain region 124 that is disposed between the first fine crystal grain region 122 and the coarse crystal grain region 126 and extends along the inner wall of the through hole 113 to the surface of the substrate 110. At this time, the metal particles in the second fine crystal grain region 124 can be formed smaller than the metal particles in the first fine crystal grain region 122. That is, most of the fine crystal grain regions 122 and 124 are formed in the first fine crystal grain region 122, and in the vicinity of the boundary between the fine crystal grain regions 122 and 124 that contact the coarse crystal grain region 126, the second fine crystal grain region 124 with smaller particle size can be formed.

[0062] FIG. 11 is a diagram showing a printed circuit board according to another embodiment of the present invention.

[0063] The printed circuit board according to this embodiment is different from the above-described embodiment in that the structure of the substrate 210 in which the through hole 213 is formed is different. That is, the seed layer 213a, the first plating layer 220, the second plating layer 230, etc. are similar to the above-described embodiment.

[0064] Referring to FIG. 11, the substrate 210 according to this embodiment includes a build-up layer in which a plurality of circuit layers are formed inside. The build-up layer includes a plurality of insulating layers 212, and the plurality of insulating layers 212 are laminated in order, and an internal circuit pattern 214 can be formed between the insulating layers 212.

[0065] FIG. 12 is a diagram showing a printed circuit board according to still another embodiment of the present invention.

[0066] The printed circuit board according to this embodiment is different from the above-described embodiment in that a copper foil layer 316 is formed on the substrate 310. That is, the seed layer 313a, the first plating layer 320, the second plating layer 330, etc. are similar to the above-described embodiment.

[0067] Referring to FIG. 12, the substrate 310 of this embodiment can be formed using a copper-clad laminate in which copper foils are formed on both sides of an insulating material. The insulating material of the copper-clad laminate becomes the substrate 310, and the copper foils of the copper-clad laminate can remain as the copper foil layers 316 to form part of the via V or the circuit pattern.

[0068] Specifically, a copper foil layer 316 is formed on the substrate 310, and the seed layer 313a of the first plating layer 320 can be formed on the copper foil layer 316. That is, the seed layer 313a of the first plating layer 320 can have a structure formed on the inner wall of the through hole 313 and the copper foil layer 316. The first plating layer 320 can be formed on the seed layer 313a in the same manner as in the above-described embodiment.

[0069] FIG. 13 is a diagram showing a printed circuit board according to another embodiment of the present invention.

[0070] The structure of the substrate 410 having the through hole 413 in the printed circuit board according to this embodiment is different from that of the above-described embodiment (the embodiment of FIG. 12). That is, the seed layer 413a, the copper foil layer 416, the first plating layer 420, the second plating layer 430, etc. are similar to those of the above-described embodiment.

[0071] Referring to FIG. 13, the substrate 410 according to this embodiment includes a build-up layer including a plurality of insulating layers 412. The plurality of insulating layers 412 are laminated in order, and an internal circuit pattern 414 can be formed between the insulating layers 412.

[0072] FIG. 14 is a diagram showing a printed circuit board according to another embodiment of the present invention, and FIG. 15 is a diagram showing a printed circuit board according to another embodiment of the present invention.

[0073] These embodiments illustrate a modified example of the groove portion 121 of the first plating layer 120. In the above-described embodiment, the groove portion 121 of the first plating layer 120 presented a structure similar to the groove in which a general blind via is formed, but the form of the groove portion 121 is not limited thereto.

[0074] Referring to FIG. 14, in the first plating layer 120', the side wall of the groove portion 121' can be formed very steeply and can be formed in a substantially perpendicular structure to the bottom of the groove portion 121' (see A1).

[0075] Also, referring to FIG. 15, in the first plating layer 120", the groove portion 121" can be formed in a pointed structure and can also be formed in a structure where the bottom of the groove portion 121" is hardly formed (see A2). For example, the groove portion 121" can have a structure in which the inner diameter becomes thinner and converges to a single point as it goes downward so that the second plating layer 130 filled therein has an inverted conical structure.

[0076] As described above, an embodiment of the present invention has been explained. However, those having ordinary knowledge in the technical field can variously modify and change the present invention by adding, changing, deleting, or adding components, etc., within the scope not departing from the idea of the present invention described in the claims, and this can also be said to be included within the scope of the rights of the present invention.

Explanation of Reference Numerals

[0077] C1 First cycle C2 Second cycle V Via 2 Plating accelerator 4 Plating inhibitor 10, 110, 210, 310, 410 Substrate 13, 113, 213, 313, 413 Through hole 120, 120', 120", 220, 320, 420 First plating layer 122 First fine crystal grain region 124 Second fine crystal grain region 126 Coarse crystal grain region 121, 121', 121" Groove portion 130, 230, 330, 430 Second plating layer

Claims

1. A substrate with a through hole formed therein, and a via filling the through hole and extending to both sides of the substrate, wherein the via includes a first plating layer formed inside the through hole, extending to both sides of the substrate, and having concave groove portions formed on the surface of the substrate at both ends; and a second plating layer filled in the groove portions, formed on the first plating layer, and extending and formed on the substrate, wherein the first plating layer has larger crystal grains in a region disposed below the groove portion than in a region disposed at the center of the through hole, in the printed circuit board.

2. The first plating layer includes a fine crystal grain region expanding toward the inner wall side at the center of the through hole, and a coarse crystal grain region formed below the groove portion and surrounded by the fine crystal grain region, wherein metal particles of the coarse crystal grain region are formed larger than metal particles of the fine crystal grain region, in the printed circuit board according to Claim 1.

3. The fine crystal grain region extends along the inner wall of the through hole to the surface of the substrate, in the printed circuit board according to Claim 2.

4. The fine crystal grain region includes a first fine crystal grain region expanding toward the inner wall side at the center of the through hole, and a second fine crystal grain region disposed between the first fine crystal grain region and the coarse crystal grain region and extending along the inner wall of the through hole to the surface of the substrate, wherein metal particles of the second fine crystal grain region are formed smaller than metal particles of the first fine crystal grain region, in the printed circuit board according to Claim 3.

5. In the first plating layer, the depth of the groove portion is 150 μm or less, and a circuit pattern connected to the via is formed on the substrate, and the thickness of the circuit pattern is 30 μm or less, in the printed circuit board according to any one of Claims 1 to 4.

6. further includes a seed layer formed on the inner wall of the through hole and the surface of the substrate, and the first plating layer is an electrolytic plating layer formed on the seed layer, in the printed circuit board according to any one of Claims 1 to 5.

7. a copper foil layer is formed on the substrate, further includes a seed layer formed on the inner wall of the through hole and the copper foil layer, and the first plating layer is an electrolytic plating layer formed on the seed layer, in the printed circuit board according to any one of Claims 1 to 6.

8. The substrate is an insulating material without an internal circuit layer, in the printed circuit board according to any one of Claims 1 to 6.

9. The printed circuit board according to any one of claims 1 to 8, wherein the substrate includes a build-up layer in which a plurality of circuit layers are formed inside.

10. The printed circuit board according to any one of claims 1 to 9, wherein the thickness of the first plating layer on the surface of the substrate is formed to be greater than the thickness of the second plating layer.

11. A substrate in which through holes are formed, and vias that fill the through holes and extend to both sides of the substrate, wherein the via includes a first plating layer formed inside the through hole and a second plating layer formed on the first plating layer, the first plating layer includes a fine crystal grain region disposed at the center of the through hole and a coarse crystal grain region disposed on the second plating layer side, and metal particles in the coarse crystal grain region are larger than metal particles in the fine crystal grain region. The printed circuit board.

12. The printed circuit board according to claim 11, wherein the first plating layer extends on both surfaces of the substrate, and concave grooves are formed on the surface of the substrate at both ends.

13. The printed circuit board according to claim 12, wherein the second plating layer fills the groove and extends on the substrate.

14. The printed circuit board according to any one of claims 11 to 13, wherein the fine crystal grain region extends along the inner wall of the through hole to the surface of the substrate.

15. The fine crystal grain region includes a first fine crystal grain region that expands toward the inner wall side at the center of the through hole, and a second fine crystal grain region that is disposed between the first fine crystal grain region and the coarse crystal grain region and extends along the inner wall of the through hole to the surface of the substrate, The printed circuit board according to any one of claims 11 to 14, wherein metal particles in the second fine crystal grain region are smaller than metal particles in the first fine crystal grain region.

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