Staging of Memory Access Requests

Abstract

Staging the memory access request includes receiving a memory access request for a dynamic random access memory, storing the memory access request in a staging buffer, and moving the memory access request from the staging buffer to a command queue.

Description

Background Art

[0001] The command queue stores memory access requests before execution. When the arbitration and storage load on the command queue increases, it leads to performance degradation.

Brief Description of the Drawings

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[0003] In some embodiments, a method of staging memory access requests includes receiving a memory access request for a dynamic random access memory, storing the memory access request in a staging buffer, and moving the memory access request from the staging buffer to a command queue.

[0004] In some embodiments, the method includes selecting a memory access request from the command queue and executing the memory access request. In some embodiments, the method includes receiving another memory access request, identifying that the staging buffer is full, and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the method includes selecting, based on one or more arbitration rules, a memory access request to move from a plurality of memory access requests in the staging buffer to the command queue. In some embodiments, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of an open page of the dynamic random access memory, bank group rotation, a request type of the memory access request, or sub-channel balancing.

[0005] In some embodiments, a memory management unit for staging memory access requests performs steps including receiving a memory access request for a dynamic random access memory, storing the memory access request in a staging buffer, and moving the memory access request from the staging buffer to a command queue.

[0006] In some embodiments, the steps include selecting a memory access request from the command queue and executing the memory access request. In some embodiments, the steps include receiving another memory access request, identifying that the staging buffer is full, and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the steps include selecting, based on one or more arbitration rules, a memory access request to move from a plurality of memory access requests in the staging buffer to the command queue. In some embodiments, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of an open page of the dynamic random access memory, bank group rotation, a request type of the memory access request, or sub-channel balancing.

[0007] In some embodiments, a processor for staging memory access requests includes a memory management unit, and the memory management unit performs steps including receiving a memory access request for a dynamic random access memory, storing the memory access request in a staging buffer, and moving the memory access request from the staging buffer to a command queue.

[0008] In some embodiments, the step includes selecting a memory access request from a command queue and executing the memory access request. In some embodiments, the step includes receiving another memory access request, identifying that the staging buffer is full, and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the step includes selecting, based on one or more arbitration rules, a memory access request to move from a plurality of memory access requests in the staging buffer to the command queue. In some embodiments, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of an open page of a dynamic random access memory, bank group rotation, a request type of the memory access request, or sub-channel balancing.

[0009] In some embodiments, a system for staging memory access requests comprises an apparatus including a processor, the processor including a memory management unit, the memory management unit performing steps including receiving a memory access request for a dynamic random access memory, storing the memory access request in a staging buffer, and moving the memory access request from the staging buffer to a command queue.

[0010] In some embodiments, the steps include selecting a memory access request from a command queue and executing the memory access request. In some embodiments, the steps include receiving another memory access request, identifying that the staging buffer is full, and storing the other memory access request in the command queue without storing the other memory access request in the staging buffer. In some embodiments, the steps include selecting, based on one or more arbitration rules, a memory access request to move from a plurality of memory access requests in the staging buffer to the command queue. In some embodiments, selecting a memory access request based on one or more arbitration rules includes selecting the memory access request based on one or more of an open page of a dynamic random access memory, bank group rotation, a request type of the memory access request, or sub-channel balancing.

[0011] FIG. 1 is a block diagram of an exemplary non-limiting processor 100 according to some embodiments. The exemplary processor 100 can be implemented in various computing devices including, for example, mobile devices, personal computers, peripheral hardware components, gaming devices, and set-top boxes. The processor 100 includes a memory management unit 102. The memory management unit 102 receives memory access requests (e.g., data read requests and / or data write requests for a particular region of memory). The memory management unit 102 also translates a virtual memory address in the memory access request to a physical memory address in order to execute the memory access request.

[0012] The memory management unit 102 includes a command queue 104. When a memory access request is received (e.g., from the central processing unit or other components of the processor 100), the command queue 104 stores the memory access request before the memory access request is executed to access the dynamic random access memory 106. Although the dynamic random access memory 106 is shown separately from the processor 100, it should be understood that the dynamic random access memory 106 may include an on-chip dynamic random access memory 106 (e.g., as a component of the processor 100). If the dynamic random access memory 106 includes multiple banks, the memory management unit 102 may include multiple command queues 104 corresponding to each bank respectively.

[0013] The memory management unit 102 selects memory access requests to execute from the command queue 104 using one or more schemes such as first-come, first-served (FCFS), ready-to-complete first-come, first-served (FR-FCFS), first-in, first-out (FIFO), etc. The memory management unit 102 includes a command queue arbiter 108 that selects memory access requests to execute from the command queue 104 using one or more rules. For example, the one or more rules are based on timing or clock information (e.g., the elapsed time of the memory access request). As another example, the one or more rules are based on the page table 110. For example, memory access requests that result in a hit in the page table 110 are preferentially selected from the command queue 104 for execution.

[0014] In existing techniques, a memory access request received by the memory management unit 102 is directly placed in the command queue 104 and then executed. To improve performance and reduce the load on the command queue 104, the memory management unit 102 includes a staging buffer 112. A memory access request received by the memory management unit 102 is placed in the staging buffer 112. Next, the staging buffer arbiter 114 selects, based on one or more arbitration rules, a memory access request to move from the staging buffer 112 to the command queue 104.

[0015] In some embodiments, the arbitration rules are based on the page of the dynamic random access memory 106 targeted by the memory access request. For example, a memory access request targeting an open page of the dynamic random access memory 106 is preferentially selected for transfer to the command queue 104 because the overhead required to close and open the page is reduced. As another example, if a memory access request targets a page of the dynamic random access memory 106 and another memory access request in the command queue 104 also targets this page, such that the page will be in an open state when the selected memory access request is executed, this memory access request is preferentially selected.

[0016] In some embodiments, the arbitration rules are based on bank group rotation or rank rotation. For example, if the dynamic random access memory 106 includes multiple banks, memory access requests to be added from the staging buffer 112 to the command queue 104 are selected so that sequentially added requests do not target the same bank. As an example, a memory access request targeting the first bank is moved to the command queue 104, and then a memory access request targeting the second bank is moved to the command queue 104. Next, another memory access request targeting the first bank is added to the command queue 104, and so on. In some embodiments, memory access requests targeting different ranks within the same or different banks are selected, or memory access requests that alternatively target different sub-channels of the dynamic random access memory 106 (e.g., for sub-channel balancing) are selected.

[0017] In some embodiments, the arbitration rules are based on the request type of the memory access request (e.g., read or write). Since there is an operation overhead for switching between reading and writing of the dynamic random access memory 106, read requests and / or write requests are grouped together as part of a "burst" of requests to be moved to the command queue 104. Thus, groups of read requests and / or groups of write requests can be executed sequentially.

[0018] In some embodiments, the memory management unit 102 determines that the staging buffer 112 is full. Thus, the memory management unit 102 directly stores the received memory access request in the command queue 104 without storing the received memory access request in the staging buffer 112.

[0019] For further explanation, FIG. 2 explicitly shows a flowchart illustrating an exemplary method for staging memory access requests according to an embodiment of the present disclosure. The method includes receiving 202 a memory access request 204 for the dynamic random access memory 106 (e.g., by the memory management unit 102 of the processor 100). The memory access request 204 includes a request for data read or data write to the dynamic random access memory 106. The memory access request 204 is received via a data fabric or other interconnection that connects the memory management unit 102 to the central processing unit or other components.

[0020] Also, the method of FIG. 2 includes storing 206 the memory access request 204 in the staging buffer 112 (e.g., by the memory management unit 102). Also, the method of FIG. 2 includes moving 208 the memory access request 204 from the staging buffer 112 to the command queue 104. Moving 208 the memory access request 204 includes removing the memory access request 204 from the staging buffer 112 and storing the memory access request 204 in the command queue 104. In some embodiments, the memory access request 204 is moved in response to some memory access requests 204 within the staging buffer 112 meeting a threshold. In some embodiments, the memory access request 204 is moved in response to some memory access requests 204 within the command queue 104 falling below a threshold. In some embodiments, the memory access request 204 is moved in response to the elapsed time of the memory access request 204 (e.g., the time when the memory access request 204 was received) meeting a threshold. In some embodiments, the memory access request 204 is moved in response to one or more arbitration rules being satisfied.

[0021] For further explanation, FIG. 3 shows a flowchart illustrating an exemplary method for staging memory access requests according to an embodiment of the present disclosure. The method includes receiving 202 a memory access request 204 for the dynamic random access memory 106 (e.g., by the memory management unit 102 of the processor 100), storing 206 the memory access request 204 in the staging buffer 112, and moving 208 the memory access request 204 from the staging buffer 112 to the command queue 104.

[0022] The method of FIG. 3 differs from FIG. 2 in that it also includes selecting 302 a memory access request 204 from the command queue 104 (e.g., by the memory management unit 102 of the processor 100). The memory access request 204 is selected from the command queue 104 using one or more schemes such as first-come, first-served (FCFS), first-ready, first-served (FR-FCFS), first-in, first-out (FIFO), etc. In some embodiments, the memory management unit 102 includes a command queue arbiter 108 that uses one or more rules to select a memory access request to execute from the command queue 104. For example, the one or more rules are based on timing or clock information (e.g., the elapsed time of the memory access request). As another example, the one or more rules are based on the page table 110. For example, a memory access request that results in a hit in the page table 110 is preferentially selected from the command queue 104 for execution.

[0023] The method of FIG. 3 differs from FIG. 2 in that it also includes executing 304 the memory access request 204 (e.g., by the memory management unit 102). Executing 304 the memory access request 204 includes reading data from the address of the dynamic random access memory 106 specified by the memory access request 204 and / or writing data to the address of the dynamic random access memory 106 specified by the memory access request 204.

[0024] For further explanation, FIG. 4 shows a flowchart illustrating an exemplary method for staging memory access requests according to an embodiment of the present disclosure. The method includes receiving 202 a memory access request 204 for the dynamic random access memory 106 (e.g., by the memory management unit 102 of the processor 100), storing 206 the memory access request 204 in the staging buffer 112, and moving 208 the memory access request 204 from the staging buffer 112 to the command queue 104.

[0025] The method of FIG. 4 differs from FIG. 2 in that it also includes receiving 402 another memory access request 404. The method of FIG. 4 further differs from FIG. 2 in that it also includes identifying 406 that the staging buffer 112 is full. The staging buffer 112 includes a predetermined amount of memory for storing a predetermined maximum number of memory access requests. Thus, identifying 406 that the staging buffer 112 is full includes identifying that the staging buffer 112 is storing a predetermined maximum number of memory access requests.

[0026] The method of FIG. 4 further differs from FIG. 2 in that it also includes storing 408 another memory access request 404 in the command queue 104 without storing the other memory access request 404 in the staging buffer 112. Thus, the staging buffer 112 is bypassed when it is full.

[0027] For further explanation, FIG. 5 shows a flowchart illustrating an exemplary method for staging memory access requests according to an embodiment of the present disclosure. The method includes receiving 202 a memory access request 204 for the dynamic random access memory 106 (e.g., by the memory management unit 102 of the processor 100), storing 206 the memory access request 204 in the staging buffer 112, and moving 208 the memory access request 204 from the staging buffer 112 to the command queue 104.

[0028] The method of FIG. 5 differs from FIG. 2 in that it also includes selecting 502 (e.g., by memory management unit 102, by staging buffer arbiter 114 of memory management unit 102) a memory access request 204 to move from a plurality of memory access requests in staging buffer 112 to command queue 104 based on one or more arbitration rules.

[0029] In some embodiments, the arbitration rules are based on the page of dynamic random access memory 106 targeted by the memory access request. For example, a memory access request targeting an open page of dynamic random access memory 106 is preferentially selected for transfer to command queue 104 because the overhead required to close and open the page is reduced. As another example, if a memory access request targets a page of dynamic random access memory 106 and another memory access request in command queue 104 also targets this page, and thus this page will be in an open state when the selected memory access request is executed, then this memory access request is preferentially selected.

[0030] In some embodiments, the arbitration rules are based on bank group rotation or rank rotation. For example, if dynamic random access memory 106 includes multiple banks, a memory access request to be added from staging buffer 112 to command queue 104 is selected so that consecutively added requests do not target the same bank. As an example, a memory access request targeting the first bank is moved to command queue 104, and then a memory access request targeting the second bank is moved to command queue 104. Next, another memory access request targeting the first bank is added to command queue 104, and so on. In some embodiments, memory access requests targeting different ranks within the same or different banks are selected. Also, memory access requests that alternatively target different subchannels of dynamic random access memory 106 (e.g., for subchannel balancing) are selected.

[0031] In some embodiments, the arbitration rules are based on the request type of the memory access request (e.g., read or write). Since there is an operation overhead for switching between reading and writing of the dynamic random access memory 106, read requests and / or write requests are grouped together as part of a "burst" of requests to be moved to the command queue 104. Thus, groups of read requests and / or groups of write requests are executed sequentially.

[0032] For further illustration, FIG. 6 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure, the method including storing 602 a plurality of memory access requests in a staging buffer 112 (e.g., by a memory management unit 102 of a processor 100). The memory access requests include requests for data reading or data writing of the dynamic random access memory 106. The memory access requests are via a data fabric or other interconnection that connects the memory management unit 102 to a central processing unit or other component.

[0033] Also, the method of FIG. 6 includes selecting 606, based on one or more arbitration rules, any one of the plurality of memory access requests 608 from the staging buffer 112. For example, the staging buffer arbiter 114 selects the memory access request 608 based on one or more arbitration rules. The arbitration rules are applied to various attributes of the memory access requests stored in the staging buffer 112, the memory access requests stored in the command queue 104, the page table 110, and / or other attributes. For example, the arbitration rules are based on the request type of the memory access requests in the staging buffer 112 and / or the command queue 104, the currently open page of the dynamic random access memory 106, the bank group targeted by the memory access requests in the staging buffer 112 and / or the command queue 104, the refresh state of the bank or page targeted by the memory access requests in the staging buffer 112 and / or the command queue 104, and / or the subchannel targeted by the memory access requests in the staging buffer 112 and / or the command queue 104.

[0034] The method of FIG. 6 also includes moving 610 the memory access request 608 from the staging buffer 112 to the command queue 104. Moving 610 the memory access request 608 includes deleting the memory access request 608 from the staging buffer 112 and / or freeing the portion of the staging buffer 112 storing the memory access request 608 for subsequent overwriting. Moving 610 the memory access request 608 also includes adding the memory access request 608 to the command queue 104. Accordingly, the memory access request 608 is later executed by the memory management unit 102 from the command queue 104.

[0035] For further explanation, FIG. 7 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing 602 (e.g., by the memory management unit 102 of the processor 100) a plurality of memory access requests in the staging buffer 112, selecting 606, based on one or more arbitration rules, any memory access request 608 from among the plurality of memory access requests from the staging buffer 112, and moving 610 the memory access request 608 from the staging buffer 112 to the command queue 104.

[0036] Selecting 606, based on one or more arbitration rules, any memory access request 608 from among the plurality of memory access requests from the staging buffer 112 is different from FIG. 6 in that it includes selecting 702 a burst of memory access requests of the same request type that includes the memory access request 608. A burst of memory access requests includes a plurality of memory access requests of the same type (e.g., read or write). A burst of memory access requests that are to be moved to the command queue 104 continuously and / or at least partially simultaneously is selected, whereby the memory access requests of the burst of memory access requests are later executed continuously and / or at least partially simultaneously. For example, the execution of a burst of read requests is performed without executing intervening write requests. As another example, the execution of a burst of write requests is performed without executing intervening read requests. Since switching between the execution of read requests and write requests for the dynamic random access memory 106 causes operation overhead, this operation overhead is avoided by executing a plurality of memory access requests of the same request type. Accordingly, the memory access request 608 is selected based on other memory access requests of the same request type added to the command queue 104 and / or based on other memory access requests of the same request type stored in the staging buffer 112 and later to be added to the command queue 104 as part of a burst of memory access requests.

[0037] For further explanation, FIG. 8 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing a plurality of memory access requests in the staging buffer 112 (e.g., by the memory management unit 102 of the processor 100) at 602, selecting at 606 any one of the plurality of memory access requests 608 from the staging buffer 112 based on one or more arbitration rules, and moving the memory access request 608 from the staging buffer 112 to the command queue 104 at 610.

[0038] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is different from FIG. 6 in that it includes selecting 802 the memory access request 608 based on one or more of a bank targeted by another memory access request, a rank targeted by another memory access request, or a memory sub-channel targeted by another memory access request. For example, in some embodiments, memory accesses are added to the command queue 104 such that the memory access requests being executed alternately target different ranks or banks of the dynamic random access memory 106 (e.g., rank balancing, bank balancing). In another embodiment, memory access requests are added to the command queue 104 such that the memory access requests being executed target the sub-channels of the dynamic random access memory 106 in a balanced manner. Accordingly, the memory access request 608 is selected based on the rank, bank, or sub-channel targeted by the memory access request already added to the command queue 104 (e.g., the queued memory access commands target another rank, bank, or sub-channel). Also, the memory access request 608 is selected based on the rank, bank, or sub-channel targeted by the memory access request that exists in the staging buffer 112 and will be added to the command queue 104 later (e.g., the staged memory access commands target another rank, bank, or sub-channel).

[0039] For further explanation, FIG. 9 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing 602 a plurality of memory access requests in the staging buffer 112 (e.g., by the memory management unit 102 of the processor 100), selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 based on one or more arbitration rules, and moving 610 the memory access request 608 from the staging buffer 112 to the command queue 104.

[0040] Selecting 606, from the staging buffer 112, any one of a plurality of memory access requests 608 based on one or more mediation rules 606 is different from FIG. 6 in that it includes selecting 902 the memory access request 608 based on the page of the dynamic random access memory 106 targeted by another memory access request. When the memory access request to be executed targets a page that is not currently in the open state, an overhead occurs to close the currently open page and open the target page. By executing memory access requests targeting the same (e.g., open) page, this overhead is reduced. Thus, in some embodiments, the memory access request 608 is selected based on the page targeted by a memory access request already executed (e.g., a page already in the open state). In some embodiments, the memory access request 608 is selected based on the page targeted by a memory access request stored in the command queue 104 that is executed before the selected memory access request 608, such that when the selected memory access request 608 is executed, the target page is in the open state. In some embodiments, the memory access request 608 is selected based on the page targeted by another memory access request stored in the staging buffer 112 that is selected subsequent to moving to the command queue 104, such that when another memory access request is executed, the target page is in the open state.

[0041] For further explanation, FIG. 10 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing a plurality of memory access requests in a staging buffer 112 at 602 (e.g., by a memory management unit 102 of a processor 100), selecting at 606 any one of the plurality of memory access requests, i.e., a memory access request 608, from the staging buffer 112 based on one or more arbitration rules, and moving the memory access request 608 from the staging buffer 112 to a command queue 104 at 610.

[0042] Selecting at 606 any one of the plurality of memory access requests, i.e., a memory access request 608, from the staging buffer 112 based on one or more arbitration rules is different from FIG. 6 in that it includes selecting the memory access request 608 based on a priority value. In some embodiments, the priority value is an explicit priority value (e.g., a priority level) assigned to the memory access request 608. In another embodiment, the priority value is calculated based on an attribute of the memory access request, such as the elapsed time of the memory access request (e.g., the time when a given memory access request was generated or received by the memory management unit 102).

[0043] For further explanation, FIG. 11 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing a plurality of memory access requests in a staging buffer 112 at 602 (e.g., by a memory management unit 102 of a processor 100), selecting at 606 any one of the plurality of memory access requests, i.e., a memory access request 608, from the staging buffer 112 based on one or more arbitration rules, and moving the memory access request 608 from the staging buffer 112 to a command queue 104 at 610.

[0044] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is different from FIG. 6 in that it includes identifying 1102 another memory access request with a first page miss within the staging buffer 112. In other words, when other memory access requests are executed, page misses and corresponding operation overheads occur. For example, the occurrence of a page miss due to the execution of other memory access requests is identified by accessing the page table 110.

[0045] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is further different from FIG. 6 in that it also includes identifying 1104 a queued (queued) memory access request with a second page miss different from the first page miss within the command queue 104. For example, it is identified that the queued memory access request has the same request type as other memory access requests in the staging buffer, targets the same dynamic random access memory bank, but causes a page miss in a different row.

[0046] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is further different from FIG. 6 in that it also includes selecting 1106 the memory access request 608 in response to identifying the other memory access requests and the queued memory access requests. In other words, the memory access request 608 is preferentially selected over other memory access requests with a first page miss within the staging buffer 112.

[0047] For further explanation, FIG. 12 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing 602 a plurality of memory access requests in a staging buffer 112 (e.g., by a memory management unit 102 of a processor 100), selecting 606, based on one or more arbitration rules, any one of the plurality of memory access requests 608 from the staging buffer 112, and moving 610 the memory access request 608 from the staging buffer 112 to a command queue 104.

[0048] Selecting 606, based on one or more arbitration rules, any one of the plurality of memory access requests 608 from the staging buffer 112 is different from FIG. 6 in that it includes identifying 1202 another memory access request with a first page conflict within the staging buffer 112. In other words, when other memory access requests are executed, page conflicts and corresponding operation overheads occur. For example, the occurrence of a page conflict due to the execution of other memory access requests is identified by accessing a page table 110.

[0049] Selecting 606, based on one or more arbitration rules, any one of the plurality of memory access requests 608 from the staging buffer 112 is further different from FIG. 6 in that it also includes identifying 1204 a queued memory access request with a second page conflict different from the first page conflict within the command queue 104. For example, the queued memory access request has the same request type as other memory access requests within the staging buffer 112, targets the same dynamic random access memory bank, but is identified as causing a page conflict in a different row.

[0050] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is further different from FIG. 6 in that it also includes selecting 1206 the memory access request 608 in response to identifying other memory access requests and queued memory access requests. In other words, the memory access request 608 is preferentially selected over other memory access requests with a first page conflict within the staging buffer 112.

[0051] For further illustration, FIG. 13 shows a flowchart illustrating an exemplary method for arbitrating a staging buffer according to an embodiment of the present disclosure. The method includes storing 602 a plurality of memory access requests in the staging buffer 112 (e.g., by the memory management unit 102 of the processor 100), selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 based on one or more arbitration rules, and moving 610 the memory access request 608 from the staging buffer 112 to the command queue 104.

[0052] Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is different from FIG. 6 in that it includes identifying 1302 page hit requests within the command queue 104. Page hit requests include memory access requests targeting currently open pages of the dynamic random access memory 106. Based on one or more arbitration rules, selecting 606 any one of the plurality of memory access requests 608 from the staging buffer 112 is further different from FIG. 6 in that it includes selecting 1304 the memory access request 608 based on the memory access request 608 being another page hit request. In other words, the memory access request 608 is selected for transfer to the command queue 104 with priority over other memory access requests that may cause page misses. Accordingly, the staging buffer 112 holds page conflict requests. In some embodiments, the memory access request 608 is selected for transfer to the command queue 104, and the command queue 104 is configured to preferentially hold one or fewer memory access requests for each bank.

[0053] Considering the above description, readers will recognize the following as advantages of staging memory access requests according to embodiments of the present disclosure. · By using an additional staging buffer to reduce the load on the command queue, the performance of the computing system is improved. · By optimally selecting memory access requests to add to the command queue so as to reduce arithmetic overhead, the performance of the computing system is improved.

[0054] Exemplary embodiments of the present disclosure are mainly described with respect to a computer system that functions well to stage memory access requests. However, those skilled in the art, i.e., readers, will recognize that the present disclosure can also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium of machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in a hard drive or floppy disk, compact disks for an optical drive, magnetic tape, and others that those skilled in the art can come up with. Those skilled in the art will immediately recognize that any computer system with appropriate programming means can execute the steps of the method of the present disclosure embodied in a computer program product. Some of the exemplary embodiments described herein are software-oriented and installed and executed on computer hardware. However, those skilled in the art will also recognize that alternative embodiments implemented as firmware or hardware are also fully included within the scope of the present disclosure.

[0055] The present disclosure can be a system, method, and / or computer program product. The computer program product can include a computer-readable storage medium (s) having computer-readable program instructions for causing a processor to execute aspects of the present disclosure.

[0056] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile discs (DVD), memory sticks, floppy (registered trademark) disks, mechanically encoded devices such as punch cards or raised structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed to be a signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses passing through an optical fiber cable), or electrical signals transmitted through a wire.

[0057] The computer-readable program instructions described herein can be downloaded to each computing device / processing device from a computer-readable storage medium or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface of each computing device / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in the computer-readable storage medium within each computing device / processing device.

[0058] The computer-readable program instructions for performing the operations of this disclosure may be source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object-oriented programming languages such as Smalltalk or C++, or conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to customize the electronic circuit for performing aspects of this disclosure.

[0059] Aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0060] By providing these computer-readable program instructions to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, a machine is created, whereby the instructions, which are executed via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium storing the instructions contains a product comprising instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0061] Also, the computer-readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, whereby the instructions executed on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0062] The flowcharts and block diagrams in the figures illustrate the architecture, functions, and operations of possible embodiments of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function(s). In some alternative embodiments, the functions described in the blocks may occur in orders different than those shown in the drawings. For example, two blocks shown in succession may, in fact, be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the related functions. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0063] From the above description, it will be understood that various embodiments of the present disclosure may be subject to modifications and changes. The description in this specification is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the terms of the following claims.

Claims

1. A method for staging memory access requests, comprising: Receiving a memory access request for a dynamic random access memory; Storing the memory access request in a staging buffer; Moving the memory access request from the staging buffer to a command queue; Receiving another memory access request; Based on the staging buffer being full, storing the another memory access request in the command queue without storing the another memory access request in the staging buffer. A method.

2. Further comprising: selecting a memory access request from the command queue; Executing the memory access request. The method of Claim 1.

3. The method of Claim 1, further comprising identifying that the staging buffer is full. The method of Claim 1.

4. The method of Claim 1, further comprising selecting, based on one or more arbitration rules, a memory access request to move from a plurality of memory access requests in the staging buffer to the command queue. The method of Claim 1.

5. The method of Claim 4, wherein selecting the memory access request based on one or more arbitration rules includes selecting the memory access request based on an open page of the dynamic random access memory. The method of Claim 4.

6. The method of Claim 4, wherein selecting the memory access request based on one or more arbitration rules includes selecting the memory access request based on bank group rotation. The method of Claim 4.

7. The method of Claim 4, wherein selecting the memory access request based on one or more arbitration rules includes selecting the memory access request based on sub-channel balancing. The method of Claim 4.

8. The method of Claim 4, wherein selecting the memory access request based on one or more arbitration rules includes selecting the memory access request based on a request type of the memory access request. The method of Claim 4.

9. A system comprising a processor and a dynamic random access memory, wherein the processor is connected to the dynamic random access memory via a memory management unit, and the memory management unit Receiving a memory access request for the dynamic random access memory; Storing the memory access request in a staging buffer; Moving the memory access request from the staging buffer to a command queue; Receiving another memory access request; Based on the staging buffer being full, storing the another memory access request in the command queue without storing the another memory access request in the staging buffer; A system configured to perform; System.

10. The memory management unit is configured to: Select a memory access request from the command queue; Execute the memory access request; A system according to claim 9.

11. The memory management unit is configured to: Determine that the staging buffer is full; A system according to claim 9.

12. The memory management unit is configured to select, based on one or more arbitration rules, the memory access request to be moved to the command queue from a plurality of memory access requests in the staging buffer; A system according to claim 9.

13. The memory management unit is configured to select the memory access request based on one or more of an open page of the dynamic random access memory, bank group rotation, a request type of the memory access request, or sub-channel balancing, and thereby select the memory access request based on the one or more arbitration rules; A system according to claim 12. ​

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