Dynamic detection level in a non-volatile memory device

Abstract

A system, method and device dynamically determine a sensing level in a memory device. The device includes non-volatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a specified amount of memory sector activity. The device also includes a comparator configured to be coupled to at least one of the plurality of memory cells and at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based at least in part on a second reference value determined by a combination of the plurality of static reference cells and the at least two of the plurality of dynamic reference cells.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application is an international application of U.S. non - provisional application Ser. No. 17 / 649,326, filed on Jan. 28, 2022, which claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63 / 256,126, filed on Oct. 15, 2021, and the contents of these provisional applications are hereby incorporated by reference in their entirety into this specification.

[0002] This disclosure generally relates to memory devices, and more specifically, to dynamic sensing levels associated with such memory devices.

Background Art

[0003] Memory devices can store data values using memory cells within a memory array. Such a memory array can include word lines and bit lines for identifying and selecting such memory cells within the memory array. Further, a reference cell can be used to store a reference value for identifying what value can be stored in a particular memory cell. Such memory cells can undergo multiple program and erase operations, and thus their operating characteristics can change due to changes in their conductive characteristics. Therefore, conventional memory devices remain limited because bit errors occur due to such changes in operating characteristics as they age and the operating characteristics of the memory cells change.

Brief Description of the Drawings

[0004]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0005] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented concepts. The presented concepts may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the described concepts. Some concepts are described in conjunction with specific examples, which are not intended to be limiting as may be understood.

[0006] A memory device can include non-volatile memory cells that undergo multiple program and erase operations over the lifetime of such a memory device. Thus, the current distributions associated with such program and erase operations can drift and increase over time. Accordingly, a reference voltage that can be used to distinguish one memory state from another, or to distinguish a programmed state from an erased state, can initially provide accurate results, but as the drift begins, the reference voltage may no longer be accurate. For example, a static reference value can be initially selected such that the current distribution associated with the program operation is below the static reference value and the current distribution associated with the erase operation is above the static reference value. As the drift begins and the values of the distributions increase, the current distribution of the program operation can shift sufficiently such that a portion of the distribution is not larger than the static reference value. When this occurs, since at least a portion of both the distributions of the program operation and the erase operation are above the static reference value, the static reference value can no longer distinguish the two, and bit errors may occur.

[0007] Embodiments disclosed herein provide the ability to a dynamically determined reference level used in a sensing operation. As will be described in more detail below, a combination of a static reference cell and a dynamic reference cell can be used to represent a reference voltage level that tracks changes in the memory cell operation characteristics over time. Further, a plurality of groups of reference cells can be used in combination to reduce the variation of the reference voltage and improve the accuracy of representing the reference voltage. In this way, the accuracy of the reference voltage in its ability to model the drift or change in the operation characteristics of the memory cell is improved, and the accuracy of the sensing operation and the memory state determination is also improved. In this way, the bit error rate can be reduced and the lifetime of the memory device can be extended.

[0008] FIG. 1 shows an example of a device for dynamic detection level determination configured according to some embodiments. As will be described in more detail below, a memory device such as device 100 can include various memory cells that can be programmed into memory states. More specifically, the conductive characteristics of the memory cells may be configured to represent the memory states, and the sensing operation may be performed to identify or read such memory states. Also, as will be described in more detail below, the sensing level used in such a sensing operation can be dynamically determined to compensate for changes that may occur due to the aging and / or use of the memory cells.

[0009] In various embodiments, device 100 includes various bit lines and word lines such as bit line 102 and word line 104. As shown in FIG. 1, the bit lines and word lines may intersect at the memory cells and may thus be configured to select a particular memory cell based on the intersection of a selected bit line and a selected word line. Such a memory cell may be a metal oxide semiconductor field effect transistor (MOSFET) device and may have a threshold voltage that is changed or modified to represent the memory state. In various embodiments, the memory cell and / or the reference cell may be in a one-transistor (1T) configuration, a two-transistor (2T) configuration, or a split gate (1.5T) configuration, or a combination thereof. For example, a threshold voltage may be set for a particular MOSFET device, and the threshold voltage may be sensed and compared to a reference level to determine that a data value has been programmed and stored. More specifically, if the threshold voltage is greater than the reference level, it can represent a first memory state. Further, if the threshold voltage is less than the reference level, it can represent a second memory state. For example, a higher conductance (e.g., a higher cell current) and a lower threshold voltage can represent an erased state, and a lower conductance and a higher threshold voltage can represent a programmed state. Further details regarding such a comparison with the reference level will be discussed in more detail below.

[0010] In various embodiments, the memory cells included in device 100 are arranged in sub-units, also referred to herein as memory sectors. Thus, the memory cells within device 100 may be managed in a plurality of different sectors, and device 100 may include hundreds of memory sectors.

[0011] Device 100 further includes various reference cells, such as first reference cell 106 and second reference cell 108. As will be described in more detail below, the reference cells can be used to determine a reference voltage that is used for the determination of the memory states described above. Thus, the voltages stored by first reference cell 106 and second reference cell 108 can be used to determine a reference level, also referred to herein as a reference voltage, for a particular sense operation in a particular memory cell associated with those reference cells. Further details regarding such sense operations are described in more detail below.

[0012] In various embodiments, the first reference cell 106 is a static reference cell configured to have a current distribution that is between the current distribution of a program operation and the current distribution of an erase operation. Thus, the current distribution and corresponding reference voltage of the static reference cell are limited by the current distributions of the program and erase operations. Thus, the terms of the average and sigma, or variance, of the reference current distribution in the static reference cell remain substantially constant over the lifetime of device 100.

[0013] In various embodiments, the second reference cell 108 is a dynamic reference cell configured to have a current distribution that adjusts based on the aging of the memory cells over the lifetime of the device 100. Thus, in various embodiments, the dynamic reference cells may be programmed and erased along with their corresponding memory cells to accurately track the changes that occur due to such programming and erasing operations. Such changes may include an increase in the programming and erase currents used for the programming and erasing operations as the memory cells age. Thus, the current distribution of the dynamic reference cells can be dynamic and can change over time. Thus, the dynamic reference cells are tied to memory sector activity and have a reference voltage that changes over time, while the static reference cells are not tied to memory sector activity and do not change as much over time as the dynamic reference cells. As will be described in more detail below, the reference level can be determined using a combination of static and dynamic reference cells.

[0014] The device 100 further includes a sense amplifier 110 configured to perform the sensing operations described above. More specifically, the sense amplifier 110 may be an operational amplifier having one input terminal coupled to a memory cell such as the memory cell 111 and the other input terminal coupled to one or more reference cells. In this way, the sense amplifier 110 can compare the sensed voltage of the memory cell to a reference voltage determined by one or more reference cells, as will be described in more detail below. Further, the sense amplifier 110 may be included in or coupled to a comparator to perform a memory state determination.

[0015] Device 100 further includes various switches such as switch 112. In various embodiments, the switches are configured to selectively couple various bit lines together to average the voltages represented by the reference cells on those bit lines. More specifically, as shown in FIG. 1, switches 112, 114, and 116 are closed to couple bit line 102, bit line 118, bit line 120, and bit line 122. As also shown in FIG. 1, bit line 102 is coupled to first reference cell 106 and second reference cell 108, bit line 118 is coupled to third reference cell 124 and fourth reference cell 126, bit line 120 is coupled to fifth reference cell 128 and sixth reference cell 130, and bit line 122 is coupled to seventh reference cell 132 and eighth reference cell 134.

[0016] As shown in FIG. 1, switches 112, 114, and 116 are closed to average the reference voltages on bit lines 102, 118, 120, and 122. As will be explained in more detail below, each dynamic reference cell can have a relatively large variance in its reference voltage / current due to differences in the characteristics of the MOSFET devices and differences in the corresponding sector activities. Such averaging of the reference voltages can substantially reduce the variance of the reference voltage / current, and thus can extend the life and operation of device 100. As shown in FIG. 1, complementary switches such as switches 136, 138, and 140 are open.

[0017] FIG. 1 shows four sets of reference cells being used in combination, but it can be understood that any number of sets may be used. For example, eight sets of reference cells can be used to further reduce the variance of the reference voltage and current. For example, the variance of the reference current in a single pair of static and dynamic reference cells may be given by Equation 1 shown below.

Equation

[0018] When used in combination, the averaging of the reference currents can reduce the total variance. For example, the capacitance averaging of four pairs of static and dynamic reference cells can further reduce the variance as shown in Equation 2 below.

Number

[0019] Furthermore, the capacitance averaging of eight pairs of static and dynamic reference cells can further reduce the variance, as shown in Equation 3 below.

Number

[0020] In some embodiments, the number of sets of reference cells used can be dynamically updated and changed over the lifetime of device 100. For example, after a specified number of program operations and / or erase operations, eight sets of reference cells instead of four may be used. In this way, the number of sets of reference cells can be dynamically selected to further improve the efficiency and lifetime of device 100.

[0021] FIG. 2 shows an example of another device for dynamic detection level determination configured according to some embodiments. Similar to what was described above, a memory device such as device 200 may include various memory cells that can be programmed to store memory values. Also, as will be described in more detail below, the reference levels used in such detection operations can be dynamically determined to compensate for changes that may occur due to the aging and / or use of the memory cells. More specifically, a combination of reference cells can be used to determine a reference voltage for the detection operation while also compensating for the variance of such reference cells.

[0022] In various embodiments, device 200 includes a first reference cell 106, a second reference cell 108, and a sense amplifier 110, as described above with reference to FIG. 1. As shown in FIG. 2, the first reference cell 106 and the second reference cell 108 are coupled to bit line 102, and bit line 102 is coupled to the input terminals of sense amplifier 110. Further, as shown in FIG. 2, a plurality of sets of reference cells may be coupled to the input terminals of sense amplifier 110 via one or more switches, as described above with reference to FIG. 1. Further, an additional bit line 202 is coupled to memory cell 204 and also to additional input terminals of sense amplifier 110.

[0023] In some embodiments, four sets of reference cells are coupled to the input terminals of sense amplifier 110. Accordingly, the reference voltage can be determined based on Equation 4 shown below.

Equation

[0024] In Equation 4, V pre_charge may be a precharge voltage used to charge the memory cell to be read during the sensing operation. Accordingly, V pre_charge is a specified voltage known to device 200. Similarly, t sense as well as C bl and C sa may be known to device 200 or may be determined based on the measured behavior of the bit lines and / or the sense amplifier. In various embodiments, the capacitance and time values are determined during the design process. For example, known values such as C bl and C sa may be determined by the manufacturer using simulation tools such as SPICE. Further, timing values such as t sense may be determined by the manufacturer during the manufacturing process to meet timing specifications or performance parameters. In Equation 4, a further clarification of I ref_av is given by Equation 5 shown below.

Number

[0025] Therefore, I ref_av is determined by averaging the measured currents of each pair of reference cells, and the averaged current measurement can be used to determine the reference voltage based on Equation 4 above. In this way, the measurements of the set of reference cells may be used to determine the reference current and the reference voltage, which are then supplied to the input terminals of a sense amplifier, such as sense amplifier 110, for example. As shown in FIG. 2, this reference voltage may be compared with the measured currents and voltages obtained from memory cell 204 coupled to the other input terminal of sense amplifier 110 via bit line 202, and the output of sense amplifier 110 may provide an indication of the result of the sensing operation and the memory state stored in memory cell 204.

[0026] It can be understood that the embodiments disclosed in this specification can use different combinations of static reference cells and dynamic reference cells. As described above, a set or group of reference cells can include four static reference cells and four dynamic reference cells. In one example, all four static reference cells may be programmed to the same reference voltage and reference current / conductance. In various embodiments, the programming operations and erasing operations described in this specification can refer to full programming and full erasing. Further, all the dynamic reference cells may be programmed according to the programming operation of the device 200. In other examples, all four static reference cells can be programmed to the same reference voltage, but some of the dynamic reference cells are programmed and one or more of the dynamic reference cells remain in the erased state. In still other examples, all four static reference cells may be programmed to the same reference voltage, while one or more, or all, of the dynamic reference cells may be partially programmed or partially erased. Further, all four static reference cells may be programmed to the same reference voltage, and the dynamic reference cells may be disabled and not used during the average reference voltage determination. Therefore, different implementations of static and dynamic reference cells can be used to configure the reference current behavior to track the behavior of the memory cells with improved accuracy.

[0027] FIG. 3 shows an example of yet another device for dynamic detection level determination configured according to some embodiments. Similarly as described above, a memory device such as device 300 can include various memory cells that can be programmed to store memory values as well as associated reference cells. As will be described in more detail below, transistors can be used to implement the bit line selection logic as well as the switches described above.

[0028] Accordingly, device 300 can include various sense amplifiers such as sense amplifier 302, amplifier 304, amplifier 306, and amplifier 308. The sense amplifiers may be coupled to various bit lines of the mirrored memory sectors, as well as their associated memory cells and reference cells. As shown in FIG. 3, transistors such as first transistor 310 and second transistor 312 may be used to selectively couple bit lines such as bit line 314 and bit line 316 to a sense amplifier such as sense amplifier 302. Further, various transistors such as third transistor 318 may be used to couple bit lines such as bit line 316 and bit line 320 to each other. In this way, various selection transistors can be used to perform the averaging of the aforementioned currents and measurements. In various embodiments, the operation of the selection logic and other transistors may be controlled by a device or system component such as a memory controller.

[0029] FIG. 4 shows an example of a method for dynamic sense level determination configured according to some embodiments. Similar to what has been described above, various memory cells may be programmed to store memory values. Further, a method such as method 400 may be performed with respect to a dynamically determined reference level used for a read operation performed on such memory cells. In this way, the reference level used in such sensing operations can be dynamically determined to compensate for changes that may occur due to the aging and / or use of the memory cells.

[0030] Method 400 may perform operation 402 where a plurality of reference cells may be selected. As previously described, the plurality of reference cells may include one or more sets of reference cells. Further, the reference cells may include static reference cells and dynamic reference cells. Thus, during operation 402, a group or set of reference cells may be selected, and one or more switches may be configured to couple the bit lines of the identified reference cells. In various embodiments, the reference cells are identified based on a particular memory cell identified for a read or sense operation. Thus, the associated reference cells may be identified based on a specified mapping and / or complementary addressing scheme used in the mirror memory sector.

[0031] Method 400 may perform operation 404 where a reference value may be determined. Thus, a voltage may be applied to the reference cells as well as to the bit lines associated with the memory cells, as will be described in more detail below. The cells may be activated to discharge the voltage and thus provide one or more discharge currents. As will be described in more detail below, the switch connections may couple the bit lines of the reference cells together and thus average the discharge currents in the selected reference cells, providing a reference value seen by the input terminals of the sense amplifier coupled to the reference cells.

[0032] Method 400 can perform an operation 406 in which the memory cell state can be determined based at least in part on an averaged reference voltage. As described above, the transistors underlying the reference cell and the memory cell may be turned on, and the sense amplifier may determine whether the reference cell or the memory cell discharges faster and may perform a corresponding voltage comparison. The memory state of the memory cell can be determined based on the result of the discharge behavior such that it can be inferred from the conductance behavior described above in relation to the program state and the erase state. More specifically, a voltage of the memory cell that exceeds the averaged reference voltage can identify a first memory state, and a voltage of the memory cell that is below the averaged reference voltage can identify a second memory state. As described above, the discharge current of the reference cell is capacitively averaged, thus dramatically reducing the individual variance of the reference cell and enabling higher accuracy in memory state determination and reduction of error rates.

[0033] FIG. 5 shows an example of another method for dynamic sense level determination configured according to some embodiments. Similar to what was described above, the reference level can be dynamically determined for a read operation performed on such a memory cell. Thus, a method such as method 500 can be executed to identify and select a particular reference cell for a particular memory cell and utilize multiple reference cells for a single memory cell. In this way, the reference level used in such a sense operation can be dynamically determined to compensate for changes that may occur due to the aging and / or use of the memory cell.

[0034] Method 500 can perform an operation 502 that can identify a memory cell. In various embodiments, the identified memory cell may be the memory cell identified for a read operation or other memory operation. Thus, the memory cell can be identified as part of the operation of the memory device. In one example, the memory cell can be identified based on one or more identifiers or data values included in a memory access request.

[0035] Method 500 may perform an operation 504 in which a first plurality of reference cells can be identified. In various embodiments, the first plurality of reference cells includes static reference cells and dynamic reference cells. For example, the reference cells may include static reference cells and dynamic reference cells included on bit lines complementary to the identified memory cells. Thus, the memory cells may be included in a mirrored architecture as described above. The static reference cells and the dynamic reference cells can be identified based on the complementary relationship of the cells and / or a predetermined mapping stored in the memory.

[0036] Method 500 may perform an operation 506 in which a second plurality of reference cells can be identified. The second plurality of reference cells includes additional static reference cells and dynamic reference cells that are used in combination with the first plurality of static reference cells and dynamic reference cells as described above. More specifically, additional reference cells used for current averaging and variance reduction of reference values can be identified during operation 506. Although operations 504 and 506 are described separately, it can be understood that they may be performed simultaneously and / or as part of the same operation. Thus, operations 504 and 506 can be combined and performed as a single operation.

[0037] In some embodiments, the second plurality of static reference cells and dynamic reference cells can be identified based at least in part on a specified mapping or set of rules. For example, based on a specified number of bit lines that may have been determined during the configuration process of the memory device, static reference cells and dynamic reference cells can be identified for the next three bit lines. In this way, one or more predetermined rules can be used to identify additional reference cells. In various embodiments, the second plurality of reference cells may be identified based on logic implemented in firmware. In some embodiments, the second plurality of reference cells is identified based on programmable software. It can be understood that the second plurality of reference cells may be any suitable number of reference cells.

[0038] Method 500 may perform an operation 508 in which a first plurality of static memory cells and reference cells are coupled to a second plurality of static memory cells and reference cells. Thus, the switches may be closed to couple the bit lines together, and the terminals of the reference cells may be coupled together. As described above, the reference cells may also be coupled to the input terminals of a sense amplifier associated with the identified memory cells. In this way, the reference cells may be coupled to the first input terminal of the sense amplifier, and the identified memory cells may be coupled to the second input terminal of the same sense amplifier.

[0039] Method 500 can perform an operation 510 in which a precharge voltage is applied to a plurality of bit lines. Thus, a voltage can be applied to the bit lines to charge the bit lines to a predetermined voltage. As described above, the precharge voltage is a predetermined voltage that can be used for a scan operation as well as other memory operations.

[0040] Method 500 may perform an operation 512 that can generate one or more discharge currents. Thus, the gates of the reference cells and the memory cells can be opened or activated, and the charge voltage can discharge through the transistors underlying the reference cells and the memory cells. As described above, the discharge current may be averaged with respect to the selected reference cells because the selected reference cells are coupled to each other via switches, and one or more capacitances such as bit line capacitance and sense amplifier capacitance may further result in capacitance averaging. As described above with reference to Equations 1-3, the reference cells are coupled to each other and the currents of the reference cells are capacitively averaged, so the individual dispersions of the reference cells are reduced.

[0041] Method 500 can perform operation 514 that can determine a reference value. Thus, the reference value appears on the bit line coupled to the input terminal of the sense amplifier as a result of the averaged discharge current. Thus, a reference value corresponding to the capacitive averaging of the discharge current can be determined. In this way, the variance of the reference voltage represented by the reference cell is also reduced, the accuracy of the determination and application of the dynamic reference voltage is improved, and thus the bit error rate of the memory device disclosed herein is lower and the lifespan is longer.

[0042] Method 500 may perform operation 516 that can determine the memory state based at least in part on the reference value. Similar to what has been described above, the discharge rates of the voltage and current affect the output of the sense amplifier and provide an indication of whether the memory cell has a higher or lower conductance / threshold voltage than the reference cell, and thus whether the memory cell is in the program state or the erase state. More specifically, if the voltage of the memory cell is lower than the averaged reference voltage, it can be determined that the memory cell is in the erase state. If the voltage of the memory cell is higher than the averaged reference voltage, it can be determined that the memory cell is in the program state.

[0043] FIG. 6 shows an example of yet another method for dynamic sense level determination configured according to some embodiments. Similar to what has been described above, the reference level may be determined dynamically for the operations performed on the memory cells. Thus, a method such as method 600 can be performed to identify and select a particular memory sector and identify the reference cells within the particular memory sector. In this way, the reference level used in such sense operations can be determined dynamically in a manner compatible with memory sector architectures such as a mirrored memory array.

[0044] Method 600 can perform operation 602 that can identify memory cells and memory sectors. Similar to what has been described above, the identified memory cells may be the memory cells identified for a read operation or other memory operations, or may be identified as part of the operation of the memory device. In one example, the memory cells can be identified based on one or more identifiers or data values included in a memory access request. Further, the memory sectors associated with the cells may be identified. For example, the memory sector containing the memory cells may be identified based on a specified mapping.

[0045] Method 600 can perform operation 604 where a plurality of reference cells can be selected. In various embodiments, the reference cells may include static reference cells and dynamic reference cells coupled to complementary bitlines as the identified memory cells, and may be included in a mirrored architecture. More specifically, the memory sectors identified during operation 602 may be used to identify mirrored or complementary memory sectors, and appropriate reference cells may be identified within the complementary memory sectors. Thus, the static reference cells and dynamic reference cells may be identified based on the complementary relationship of the cells and sectors identified by a mapping stored in the memory. Similar to what has been described above, the reference cells can be used for current averaging and variance reduction of reference values.

[0046] Method 600 can perform operation 606 where a precharge voltage can be applied to a plurality of bitlines. Thus, a voltage can be applied to the bitlines to charge the bitlines to a predetermined voltage. As described above, the precharge voltage is a predetermined voltage that can be used for a scan operation as well as other memory operations.

[0047] Method 600 can perform an operation 608 in which a memory state can be determined based at least in part on the averaged discharge current and averaged reference voltage of a plurality of static memory cells and reference cells. Similar to what has been described above, the gates of the reference cells and the memory cells may be opened or activated, and the charging voltage may be discharged through transistors located below the reference cells and the memory cells. Also, as described above, the rate of voltage discharge affects the output of the sense amplifier and provides an indication of whether the memory cell has a higher or lower conductance than the reference cell, and thus whether the memory cell is in a programmed or erased state.

[0048] Method 600 can perform an operation 610 in which it can be determined whether other memory cells and memory sectors should be selected. Thus, if additional memory cells are to be read or scanned as part of a requested operation, those cells can be identified and method 600 can return to operation 602. If additional memory cells and memory sectors should not be selected, method 600 can end.

[0049] FIG. 7 shows an example of a system configured according to some embodiments. According to a particular exemplary embodiment, system 700 may be suitable for implementing the various components described above, such as device 100, device 200, and device 300. In various embodiments, system 700 can include a processor 701 configured to perform one or more processing operations. For example, processor 701 may be configured to perform selection and scanning operations and may further be configured to perform memory state determination operations. Also, system 700 may include a bus 715 configured to enable communication between the various components of system 700.

[0050] In various embodiments, system 700 can further include a memory array 702 and a control circuit 728 configured to implement the foregoing selection and scanning operation aspects. In various embodiments, control circuit 728 can include one or more processors and dedicated memory configured to implement the foregoing operations. In this way, system 700 can have a dedicated processing unit, such as control circuit 728, configured to implement the foregoing selection and scanning operations. In one example, control circuit 728 is a memory controller. Further, in some embodiments, control circuit 728 may be implemented in an application specific integrated circuit (ASIC) or in reprogrammable logic of a field programmable gate array. In some embodiments, control circuit 728 may be implemented in a programmable system or controller that further includes non-volatile memory, such as a programmable system on chip or PSoC (trademark) controller commercially available from Cypress Semiconductor of San Jose, California. In various embodiments, one or more components of system 700 may be implemented on the same circuit die and within the same package. For example, control circuit 728 and memory 702 may be implemented on the same circuit die. In some embodiments, they may be implemented on different dies and in different packages.

[0051] In various embodiments, communication interface 711 may be configured to transmit and receive data with other system components and may be configured to transmit and receive packets or data segments over a network. For example, communication interface 711 can be communicatively coupled to a user interface device via a bus such as bus 715 or over a communication network. As described above, communication interface 711 may be configured to receive data from such a user interface device that may be included in a data processing system or computer system. In various embodiments, such data can include data requests for applications executed by such a computer system.

[0052] FIG. 8 shows an example of a memory sector included in a device for dynamic detection level determination configured according to some embodiments. As will be described in more detail below, the memory sector may be configured to be mirrored. For example, a pair 804 of normal sectors 802 of a NOR flash memory 803 is accompanied by a sense amplifier 820 that generates an output signal according to the embodiments described above. In this example, each normal physical sector 802 includes four erase sectors, also called E sectors 808, and the pair 804 includes two normal sectors 802 sandwiching a dynamic reference word line (DREF WL), a static reference word line (static REF WL), and a sense amplifier (SA).

[0053] In one embodiment, by way of example, the physical sector pair 804 can include eight E sectors. As shown in FIG. 8, E sectors 0-3 are mirrored to E sectors 4-7. Detection of data located above or on one side of the SA is performed with respect to the other side of the SA (and vice versa). For example, memory cells within E sector 0 are detected using the static and dynamic reference cells at the bottom or opposite side of the SA. In various embodiments, the selection, combination, and algorithms for combining dynamic and static reference cells are disclosed in previous portions of this patent document.

[0054] The foregoing concepts have been described in some detail for clarity of understanding, but it is obvious that certain changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and devices. Accordingly, this embodiment should be considered illustrative and not restrictive.

Claims

1. A plurality of non-volatile memory cells included in a plurality of memory sectors and coupled to a plurality of bit lines and a plurality of word lines; A plurality of switches configured to couple at least some of the plurality of bit lines to each other during a sensing operation; A plurality of static reference cells configured to represent a first reference value for distinguishing between memory states; A plurality of dynamic reference cells configured to represent the first reference value after a specified amount of memory sector activity; A comparator configured to be coupled to at least one of the plurality of memory cells and at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based at least in part on a second reference value determined based on an averaging of the at least two combinations of the plurality of static reference cells and the plurality of dynamic reference cells; Comprising; The sensing operation is performed on the at least one memory cell, and each of the at least some of the plurality of bit lines is coupled to a static reference cell, and the at least some of the plurality of bit lines comprise the same number of bit lines as the number of static reference cells coupled to the comparator. Device.

2. The plurality of memory sectors are configured as mirrored erase sectors. The device according to claim 1.

3. Each of the at least some of the plurality of bit lines is further coupled to a dynamic reference cell in a mirrored memory sector corresponding to the memory sector of the at least one memory cell. The device according to claim 1 or 2.

4. At least one of the dynamic reference cells coupled to at least some of the plurality of bit lines is in a fully erased state or a partially erased state. The device according to claim 3.

5. The dynamic reference cells have a reference value that is partially programmed or fully programmed. The device according to claim 3.

6. The second reference value is determined based on a capacitive averaging of discharge currents through at least some of the combinations of the plurality of static reference cells and the plurality of dynamic reference cells. The device according to claim 1.

7. The combination comprises two or more pairs of a static reference cell and a dynamic reference cell. The device according to claim 6.

8. The capacitance averaging is configured to reduce the variance of the first reference value represented by at least some of the plurality of static reference cells and the plurality of dynamic reference cells. The device according to claim 6.

9. Identifying at least one memory cell among a plurality of memory cells included in a plurality of memory sectors and coupled to a plurality of bit lines and a plurality of word lines; Selecting a plurality of reference cells including at least two of a plurality of static reference cells and a plurality of dynamic reference cells and associated with the at least one memory cell, using a plurality of switches configured to couple at least some of the plurality of bit lines to each other during a sensing operation; Determining a reference value based on an averaging of the combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells; Determining the state of the at least one memory cell using a comparator based at least in part on the reference value; comprising The sensing operation is performed on the at least one memory cell, and each of the at least some of the plurality of bit lines is coupled to a static reference cell, and the at least some of the plurality of bit lines comprise the same number of bit lines as the number of static reference cells coupled to the comparator. Method.

10. The combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells is included in a mirrored erase sector corresponding to the memory sector of the at least one identified memory cell. The method according to claim 9.

11. The step of identifying at least one memory cell is included in a sensing operation at least partially performed by a sense amplifier. The method according to claim 9.

12. The reference value is determined based on a capacitance averaging of a discharge current through the combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells. The method according to claim 9.

13. The combination comprises two or more pairs of a static reference cell and a dynamic reference cell. The method according to claim 12.

14. The capacitance averaging reduces the variance of the reference voltages represented by at least some of the plurality of static reference cells and the plurality of dynamic reference cells. The method according to claim 12.

15. Identifying at least one memory cell among a plurality of memory cells included in a plurality of memory sectors and coupled to a plurality of bit lines and a plurality of word lines; Coupling the at least one memory cell to a comparator; Selecting a plurality of reference cells including at least two of a plurality of static reference cells and a plurality of dynamic reference cells using a plurality of switches configured to couple at least some of the plurality of bit lines to each other during a sensing operation; Coupling the plurality of reference cells to the comparator; Applying a precharge voltage to a plurality of bit lines coupled to the at least one memory cell and the plurality of reference cells; Discharging the precharge voltage through the at least one memory cell and the plurality of reference cells; Determining a state of the at least one memory cell using the comparator based at least in part on a result of the discharging and an averaging of the discharging through the plurality of reference cells; comprising The sensing operation is performed on the at least one memory cell, and each of the at least some of the plurality of bit lines is coupled to a static reference cell, and the at least some of the plurality of bit lines include the same number of bit lines as the number of static reference cells coupled to the comparator. Method.

16. At least two of the plurality of static reference cells and the plurality of dynamic reference cells are included in a mirrored erase sector corresponding to the memory sector of the at least one identified memory cell. The method according to claim 15.

17. The step of discharging further includes generating a discharge current through the plurality of reference cells, and the discharge current is capacitance averaged. The method according to claim 15.

18. The method further includes determining a reference value based on the discharge current. The method according to claim 17.

Images