Sequence pattern generator and sequence synchronization resumption method thereof

Abstract

To provide a sequence pattern generating device capable of restarting a sequence in a state where output arbitrarily selected by a user is synchronized.SOLUTION: A sequence pattern generating device includes a primary module 2 and a secondary module 3 having an output of respective two data signals, and a signal distribution circuit 5 that distributes signals output from a primary control unit 29 and a secondary control unit 39 to a primary data generation unit 26 and a secondary data generation unit 36 so that pieces of timing of the signals output from the control units are completely synchronized in a clock-like manner. The control units 29 and 39 of the modules 2 and 3 having the output, for which restart of a sequence is instructed, output a sequence restart signal to the signal distribution circuit 5, and the data generation units 26 and 36 restart the sequence in synchronization with the sequence restart signal distributed from the signal distribution circuit 5 for the output for which the synchronization of the restart of the sequence is set.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a sequence pattern generator that generates and outputs an arbitrary sequence pattern set by a user.

Background Art

[0002] In recent years, various digital communication devices have been required to have a larger transmission capacity with the increase in the number of users and the spread of multimedia communication. And, as an index for evaluating the quality of digital signals in these digital communication devices, the bit error rate defined as the comparison between the number of bit errors occurring in the received data and the total number of received data is known.

[0003] And, in the error rate measuring device for measuring the above-described bit error rate, a test signal including fixed data is transmitted to a device under test to be tested, and the measured signal input via the device under test and a reference signal serving as a reference are compared bit by bit to measure the error rate of the measured signal.

[0004] In this type of error rate measuring device, a pulse pattern generator that generates a data signal of a predetermined pulse pattern input as a test signal to a device under test corresponding to recent high-speed data communication is used.

[0005] Patent Document 1 describes a pulse pattern generator that sets a slave-side phase difference target value using correction data in a storage unit while setting a master-side phase difference target value according to the frequency of a reference clock signal in order to keep the phase states of a plurality of data signals constant.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the standards of high-speed serial buses such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express), there is a state machine called Link Training & Status State Machine (LTSSM), which manages the initialization of communication between devices and the adjustment of link speed.

[0008] Also, conventional error rate measurement devices have a function (sequence pattern function) to control the LTSSM of PCIe GEN1~5 and USB3.1 by quickly switching specific patterns defined by the standard from a pulse pattern generator (PPG: Pulse Pattern Generator) and transitioning to a specific state. The patterns for transitioning the device under test (DUT) are defined by the standard, and the output order of these patterns can be combined and output by the sequence pattern function.

[0009] In the PCIe standard, the number of lanes is defined in variations such as x1, x2, x4, x8, x16, etc. A pattern defined for each lane is transmitted to cause a state transition of the DUT.

[0010] In the normal usage range, a PCIe device only needs to have data synchronized among multiple lanes. However, as a requirement on the developer side of PCIe devices, there is a need to temporarily stop the sequences of multiple or all lanes and resume the sequences of arbitrarily specified multiple or all lanes at an arbitrary timing. However, the conventional sequence pattern function does not meet this requirement.

[0011] Accordingly, an object of the present invention is to provide a sequence pattern generator capable of resuming a sequence in a state where outputs arbitrarily selected by a user are synchronized.

Means for Solving the Problems

[0012] The sequence pattern generator of the present invention is a sequence pattern generator in which at least one module having an output of at least one data signal can be mounted, and the total number of outputs of the data signals is two or more, and a signal output from a control unit of any of the modules is distributed to each data generation unit of the modules so that the timings completely coincide clockwise. A signal distribution circuit is provided, and the control unit of the module having an output instructed to resume the sequence outputs a sequence resume signal to the signal distribution circuit, and the data generation unit resumes the sequence in synchronization with the sequence resume signal distributed from the signal distribution circuit for the output for which the synchronization of the resumption of the sequence is set.

[0013] With this configuration, a sequence resume signal is output to the signal distribution circuit by the control unit of the module having an output instructed to resume the sequence, and the data generation unit resumes the sequence in synchronization with the sequence resume signal distributed from the signal distribution circuit for the output for which the synchronization of the resumption of the sequence is set. Therefore, the sequence can be resumed in a state where the outputs arbitrarily selected by the user are synchronized.

[0014] In addition, the sequence synchronization restart method of the sequence pattern generator of the present invention can be equipped with at least one module having an output of at least one data signal, the total number of outputs of the data signal is two or more, and the signal output from the control unit of any of the modules is distributed to each data generation unit of the module so that the timings are exactly the same clockwise. It is a sequence synchronization restart method of a sequence pattern generator including a signal distribution circuit, and includes: a step in which the control unit of the module having an output instructed to restart the sequence outputs a sequence restart signal to the signal distribution circuit; a step in which the signal distribution circuit distributes the sequence restart signal to the data generation unit so that the timings are exactly the same clockwise; and a step in which the data generation unit restarts the sequence in synchronization with the sequence restart signal distributed from the signal distribution circuit for an output for which the synchronization of the restart of the sequence is set.

[0015] With this configuration, a sequence restart signal is output to the signal distribution circuit by the control unit of the module having an output instructed to restart the sequence, and by the signal distribution circuit, the sequence restart signal is distributed to the data generation unit so that the timings are exactly the same clockwise. The sequence is restarted in synchronization with the sequence restart signal distributed from the signal distribution circuit for an output for which the synchronization of the restart of the sequence is set. For this reason, the sequence can be restarted with the outputs arbitrarily selected by the user synchronized.

Advantages of the Invention

[0016] The present invention can provide a sequence pattern generator capable of restarting a sequence with the outputs arbitrarily selected by the user synchronized.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, with reference to the drawings, a sequence pattern generator according to an embodiment of the present invention will be described in detail.

[0019] In FIG. 1, a sequence pattern generator 1 according to an embodiment of the present invention includes a primary module 2 and a secondary module 3, each of which can output two data signals. The primary module 2 and the secondary module 3 are connected by wiring via a bridge route 4. Note that the primary module 2 and the secondary module 3 may output one data signal or two or more data signals.

[0020] The primary module 2 and the secondary module 3 are detachably provided in a slot (not shown) of the device body of the measuring device 11. As shown in FIG. 1, in the slot (not shown) of the measuring device 11, a plurality of modules such as a clock module 12 and a measurement module 13 are detachably provided in addition to the primary module 2 and the secondary module 3.

[0021] As shown in FIG. 1, the measuring device 11 includes an operation unit 14, a display unit 15, and a device control unit 16. A plurality of modules (primary module 2, secondary module 3, clock module 12, measurement module 13, etc.) selected according to the measurement content can be freely added, removed, and recombined with respect to slots (not shown), and various measurements of the object to be measured based on the standard can be performed in various forms.

[0022] The clock module 12 is composed of a clock generator and generates a reference clock signal (1 / 2 half-rate clock or full-rate clock) for input to the primary module 2 and the secondary module 3.

[0023] Note that the clock module 12 is not limited to a configuration that can be attached to and detached from a slot (not shown) of the measuring device 11, and an external clock generator separate from the measuring device 11 can also be used.

[0024] The measurement module 13 performs various measurements of the object to be measured based on the set values of the measurement parameters set by the operation of the operation unit 14.

[0025] The operation unit 14 includes, for example, a pointing device such as a mouse or a touch screen that operates a pointer or an icon on the display screen of the display unit 15, keys, switches, buttons, etc. provided on the device main body of the measuring device 11. In addition to the initial settings such as the initial value (minimum value or maximum value) of the bit rate that can be generated by the sequence pattern generator 1, the initial division ratio of the primary division unit 21 and the secondary division unit 31 of the primary module 2 and the secondary module 3 described later, the initial delay amounts of the respective delay circuit units 22, 23, 24 of the primary module 2 and the respective delay circuit units 32, 33, 34 of the secondary module 3, and the allowable range of the phase difference target value of the primary phase comparison unit 25 and the secondary phase comparison unit 35, the operation unit 14 performs operations related to various measurements such as instructions to start and stop measurement, designation of the measurement channel for setting the measurement parameters, and setting / change / reference of the measurement parameters on the setting screen.

[0026] Note that the initial value of the bit rate is preferably set to the minimum value of the bit rate range with a large phase margin, but the maximum value of the bit rate range may be set as the initial value of the bit rate.

[0027] The display unit 15 is composed of, for example, a liquid crystal display provided on the main body of the measuring device 11, and displays a setting screen for initial setting by the operation unit 14, a setting screen for a predetermined measurement channel, a measurement screen, etc. on the display screen.

[0028] The device control unit 16 is composed of a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), etc., and includes setting control of each module based on the operation of the operation unit 14, variable control of the bit rate, output control of the reference clock signal, various measurement controls of the object to be measured based on the measurement signal, display control of the setting screen and the measurement screen, etc., and comprehensively controls the primary module 2, the secondary module 3, the clock module 12, the measurement module 13, the operation unit 14, and the display unit 15.

[0029] Next, the configurations of the primary module 2 and the secondary module 3 that constitute the sequence pattern generator 1 will be described.

[0030] As shown in FIG. 1, the primary module 2 includes a primary frequency division unit 21, a primary first delay circuit unit 22, a primary second delay circuit unit 23, a primary third delay circuit unit 24, a primary phase comparison unit 25, a primary data generation unit 26, a primary first data multiplexing unit 27, a primary second data multiplexing unit 28, and a primary control unit 29.

[0031] The primary frequency division section 21 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides the reference clock signal generated by the clock module 12 or an external clock source by 1 / N, and inputs this 1 / N divided clock signal to the primary first delay circuit section 22 and the primary phase comparison section 25.

[0032] The reference clock signal is a half-rate clock or a full-rate clock having a frequency at which the sequence pattern generator 1 can operate (for example, 1.25 GHz to 16 GHz), and is generated by, for example, a clock source prepared by the user, an internal synthesizer incorporated in the measuring device 11 together with the sequence pattern generator 1, an external synthesizer separate from the measuring device 11, and the like. Then, reference clock signals having the same phase are input to the primary module 2 and the secondary module 3.

[0033] The primary first delay circuit section 22 is composed of, for example, an IQ modulator, and under the control of the primary control section 29, the phase angle of the divided clock signal from the primary frequency division section 21 is variably adjusted to adjust the delay amount so that the data signal (parallel data) input from the primary data generation section 26 to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 and the reference clock signal have an optimal phase relationship. The divided clock signal with the adjusted delay amount is input to the primary phase comparison section 25 via the primary second delay circuit section 23, and is also input to the secondary second delay circuit section 33 and the secondary third delay circuit section 34 of the secondary module 3 via the bridge route 4.

[0034] The primary second delay circuit section 23 is composed of, for example, an electronic delay in which delay elements (gate delays) that adjust the delay amount of the divided clock signal by performing switching in units of several picoseconds electrically are connected in multiple stages. The primary second delay circuit section 23 functions as a bypass circuit that allows the divided clock signal with the delay amount adjusted by the primary first delay circuit section 22 to pass through as it is and input it to the primary phase comparison section 25.

[0035] The primary third delay circuit section 24 is composed of electronic delays similar to those of the primary second delay circuit section 23, and has the same number of electronic delays as the number of transmission lanes of the parallel data generated by the primary data generation section 26. For example, if the number of transmission lanes of the parallel data is 8, the primary third delay circuit section 24 is composed of 8 electronic delays. This primary third delay circuit section 24 adjusts the delay amount appropriately for each data under the control of the primary control section 29 in order to perform skew adjustment of each data of the parallel data input from the primary data generation section 26 to the primary first data multiplexing section 27 and the primary second data multiplexing section 28.

[0036] The primary phase comparison section 25 compares the phase of the divided clock signal P1 input from the primary division section 21 with the phase of the divided clock signal P2 input from the primary division section 21, passing through the primary first delay circuit section 22 and input from the primary second delay circuit section 23 via the bridge route 4, regarding them as the clock and data input to the primary first data multiplexing section 27 and the primary second data multiplexing section 28, and outputs a phase difference signal (voltage signal) P2 - P1 corresponding to the phase difference to the primary control section 29.

[0037] The primary data generation section 26 is provided on one FPGA (Field Programmable Gate Array) capable of partial configuration, and generates parallel data of a predetermined number of transmission lanes (for example, 4 Gbps × 8 channels) at the timing of the divided clock signal from the primary third delay circuit section 24 as a data signal of an arbitrary pulse pattern set by the user, and outputs it to the primary first data multiplexing section 27 and the primary second data multiplexing section 28.

[0038] The primary first data multiplexing section 27 and the primary second data multiplexing section 28 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc., and multiplex the parallel data input from the primary data generation section 26 into serial data at the timing of the reference clock signal and output it.

[0039] The primary control unit 29 comprehensively controls the primary frequency division unit 21, each delay circuit unit 22, 23, 24 of the primary module 2, the primary phase comparison unit 25, the primary data generation unit 26, the primary first data multiplexing unit 27, and the primary second data multiplexing unit 28 so as to synchronize and output the phases of a plurality of data signals according to an arbitrary pulse pattern set by the user.

[0040] The primary control unit 29 stores, as correction data, the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 in association with each predetermined step of the frequency (bit rate) of the reference clock signal and tabulates it.

[0041] The primary control unit 29 sets the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 according to the frequency (bit rate) of the reference clock signal.

[0042] Note that the primary side phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±1 cycle (for example, ±31.25 psec in the case of 32 Gbit / s: corresponding to the cycle at which the turning of the primary frequency division unit 21 changes) from the center voltage value. Also, if the reference clock signal is a full-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±0.5 cycle from the center voltage value.

[0043] Also, when setting the primary side phase difference target value at a frequency (bit rate) of the reference clock signal not stored by the primary control unit 29, it is calculated by linear interpolation from the correction data at two points at the frequencies (bit rates) of the reference clock signals before and after that frequency (bit rate) of the reference clock signal.

[0044] The primary control unit 29 adjusts and controls the delay amounts of the respective delay circuit units 22, 23, and 24 of the primary module 2. Specifically, when the initial setting is performed by the operation unit 14, the primary control unit 29 adjusts and controls each of the delay circuit units 22, 23, and 24 of the primary module 2 to the initial delay amount.

[0045] Also, when outputting while keeping the pattern generation timing of the four data signals constant, the primary control unit 29 adjusts and controls the delay amount of the primary second delay circuit unit 23 so that the voltage reading value (voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 becomes approximately equal to the center voltage value.

[0046] Similar to the primary module 2, the secondary module 3 includes a secondary frequency division unit 31, a secondary first delay circuit unit 32, a secondary second delay circuit unit 33, a secondary third delay circuit unit 34, a secondary phase comparison unit 35, a secondary data generation unit 36, a secondary first data multiplexing unit 37, a secondary second data multiplexing unit 38, and a secondary control unit 39.

[0047] The secondary frequency division unit 31 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), similar to the primary frequency division unit 21 of the primary module 2. It frequency-divides the reference clock signal having the same phase as the reference clock signal input to the primary frequency division unit 21 of the primary module 2 by 1 / N, and inputs this 1 / N frequency-divided clock signal to the secondary first delay circuit unit 32 and the secondary phase comparison unit 35.

[0048] The secondary first delay circuit unit 32 is composed of an IQ modulator, similar to the primary first delay circuit unit 22 of the primary module 2. Although this secondary first delay circuit unit 32 is an originally unnecessary configuration, it is provided for the purpose of sharing the primary module 2 and the secondary module 3. Here, the output of the secondary first delay circuit unit 32 is open so that no output is provided even when the frequency-divided clock signal is input from the secondary frequency division unit 31.

[0049] The secondary second delay circuit section 33 is configured by an electronic delay in which delay elements (gate delays) that perform switching in units of, for example, several picoseconds electrically and adjust the delay amount of the divided clock signal are connected in multiple stages, similar to the primary second delay circuit section 23 of the primary module 2. The secondary second delay circuit section 33 adjusts the delay amount of the divided clock signal received from the primary module 2 under the control of the secondary control section 39 so that the phase relationship between the data signal (parallel data) input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38 and the reference clock signal is equivalent to the phase relationship between the data signal (parallel data) input to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 of the primary module 2 and the reference clock signal.

[0050] The secondary third delay circuit section 34 is configured by an electronic delay, similar to the primary third delay circuit section 24 of the primary module 2, and includes the same number of electronic delays as the number of transmission lanes of the parallel data generated by the secondary data generation section 36. The secondary third delay circuit section 34 appropriately adjusts the delay amount for each data under the control of the secondary control section 39 in order to perform skew adjustment of each data of the parallel data input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38.

[0051] The secondary phase comparison section 35 compares the phase of the divided clock signal S1 from the secondary division section 31 with the phase of the divided clock signal S2 input from the secondary second delay circuit section 33 via the bridge route 4 from the primary first delay circuit section 22 of the primary module 2, and outputs a phase difference signal (voltage signal) corresponding to the phase difference S2 - S1 to the secondary control section 39.

[0052] Similar to the primary data generation unit 26 of the primary module 2, the secondary data generation unit 36 is provided on one FPGA capable of partial configuration. As a data signal of an arbitrary pulse pattern set by the user, parallel data of a predetermined number of transmission lanes (for example, 4 Gbps × 8 channels) is generated at the timing of the divided clock signal from the secondary third delay circuit unit 34 and output to the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38.

[0053] Similar to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 of the primary module 2, the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc. They multiplex the parallel data input from the secondary data generation unit 36 into serial data at the timing of the reference clock signal and output it.

[0054] The secondary control unit 39 comprehensively controls the secondary division unit 31, each delay circuit unit 32, 33, 34 of the secondary module 3, the secondary phase comparison unit 35, the secondary data generation unit 36, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 in order to synchronize and output the phases of a plurality of data signals according to an arbitrary pulse pattern set by the user.

[0055] The secondary control unit 39 stores, as correction data tabulated by associating, for each predetermined step of the frequency (bit rate) of the reference clock signal, the secondary phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 and the error of the delay amount caused by the characteristics and wiring variations of each delay circuit unit 22, 23, 24 of the primary module 2 and each delay circuit unit 32, 33, 34 of the secondary module 3, and the phase shift associated with the deterioration of the duty ratio of the primary division unit 21 and the secondary division unit 31.

[0056] Note that the correction value is obtained by subtracting the primary phase difference target value (voltage reading value) from the secondary phase difference target value (voltage reading value).

[0057] The secondary control unit 39 sets the secondary phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 according to the frequency (bit rate) of the reference clock signal.

[0058] Note that the secondary phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, the allowable maximum value and the allowable minimum value are values shifted by ±1 cycle (for example, ±31.25 psec in the case of 32 Gbit / s: corresponding to the cycle at which the turn of the secondary frequency divider 31 changes) from the center voltage value, and it consists of a fixed allowable range. Also, if the reference clock signal is a full-rate clock, it consists of a fixed allowable range with values shifted by ±0.5 cycle from the center voltage value as the allowable maximum value and the allowable minimum value.

[0059] When setting the secondary phase difference target value at the frequency (bit rate) of the reference clock signal not stored in the secondary control unit 39, it is calculated by linear interpolation from the correction data at two points at the frequencies (bit rates) of the reference clock signals before and after that frequency (bit rate) of the reference clock signal.

[0060] Note that correction data can also be stored in advance, where the values obtained by adding the correction value to the center voltage value, the maximum value, and the minimum value of the primary phase difference target value at each predetermined step of the frequency (bit rate) of the reference clock signal are used as the center voltage value, the maximum value, and the minimum value of the secondary phase difference target value.

[0061] The secondary control unit 39 adjusts and controls the delay amounts of the respective delay circuit units 32, 33, and 34 of the secondary module 3. Specifically, when the initial setting is performed by the operation unit 14, the secondary control unit 39 adjusts and controls the respective delay circuit units 32, 33, and 34 of the secondary module 3 to their initial delay amounts.

[0062] Further, when the secondary control unit 39 outputs while keeping the pattern generation timings of the four data signals constant, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the voltage reading value (voltage value corresponding to the phase difference S2 - S1) of the secondary phase comparison unit 35 becomes approximately equal to the center voltage value.

[0063] Furthermore, when the secondary control unit 39 determines that the voltage reading value (voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 of the primary module 2 and the voltage reading value (voltage value corresponding to the phase difference signal S2 - S1) of the secondary phase comparison unit 35 of the secondary module 3 are not equal, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the phase advances or lags by an inverse multiple of the reference clock signal according to the change state of the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3.

[0064] For example, when the reference clock signal is a half-rate clock, if the change state of the voltage reading value of the secondary phase comparison unit 35 is rising with a right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase advances by 2UI. On the contrary, if the change state of the voltage reading value of the secondary phase comparison unit 35 is falling with a right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase lags by 2UI.

[0065] When the secondary control unit 39 outputs while keeping the pattern generation timings of the four data signals constant after the initial setting, when the bit rate is variably changed by a predetermined amount, it inhibits the secondary frequency division unit 31.

[0066] When the secondary control unit 39 variably changes the bit rate from the initial value (the minimum value or the maximum value of the bit rate range) by a predetermined amount and inhibits the secondary frequency division unit 31, it compares the voltage reading value (the voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 of the primary module 2 with the voltage reading value (the voltage value corresponding to the phase difference signal S2 - S1) of the secondary phase comparison unit 35 of the secondary module 3, and determines whether the voltage reading values of both are equal (whether P2 - P1 = S2 - S1).

[0067] By the way, in the configuration of FIG. 1 described above, in order to share the primary module 2 and the secondary module 3, the internal configurations of both modules 2 and 3 are made the same, but the secondary first delay circuit unit 32 of the secondary module 3 may be omitted.

[0068] In the sequence pattern generator 1 of the present embodiment, each of the primary module 2 and the secondary module 3 has two outputs (referred to as channel 1 and channel 2), and a maximum of four data signals can be output. Note that if modules are added, the number of outputs can be increased without being limited to this number.

[0069] As shown in FIG. 2, the sequence pattern generator 1 of the present embodiment can output four data signals synchronously, or can output a plurality of the four data signals synchronously.

[0070] In FIG. 2, at the start of the sequence at time 3, the sequence progresses in all Lanes, and at time 7, the output of the set sequence ends and pauses due to the pause setting. Then, at time 10, when the sequence is restarted by an operation on the user operation unit 14, only the sequences of the set Lane0 and Lane2 are restarted.

[0071] Note that the operations of starting and restarting the user's sequence can only be performed on one channel of one module.

[0072] Therefore, the sequence pattern generator 1 includes a signal distribution circuit 5. The signal distribution circuit 5 distributes the signal output from the primary control unit 29 or the secondary control unit 39 to the data generation units 26, 36 of each module 2, 3 so that the timings are exactly the same clockwise.

[0073] The data generation units 26, 36 start or resume the sequence according to the signal input from the signal distribution circuit 5. Note that the signal input from the signal distribution circuit 5 is divided and input into two outputs, one for channel 1 and the other for channel 2.

[0074] For example, when the sequence start signal input from the signal distribution circuit 5 is turned on, the data generation units 26, 36 start the sequence and continue the operation of the sequence while the sequence start signal is on.

[0075] Since the sequence start signal is output with synchronized timing by the signal distribution circuit 5, the start of the sequence can be synchronized.

[0076] For example, the data generation units 26, 36 resume the sequence by the sequence resume signal output from the synchronous sequence resume circuit 100 as shown in FIG. 3.

[0077] In FIG. 3, the synchronous sequence resume circuit 100 includes an OR circuit 101 and selectors 102, 103, 104, 105.

[0078] The OR circuit 101 takes the logical sum of the channel 1 sequence resume instruction signal and the channel 2 sequence resume instruction signal and outputs it.

[0079] The channel 1 sequence resume instruction signal and the channel 2 sequence resume instruction signal are input from the device control unit 16 to the data generation units 26, 36 via the control units 29, 39, and turn on when the resume of the sequence is selected by an operation on the user operation unit 14.

[0080] The signal output from the OR circuit 101 is input to the selectors 102 and 103. The selector 102 selects and outputs either the channel 1 sequence restart instruction signal or the output from the OR circuit 101 according to the in-module synchronization setting signal. If the in-module synchronization setting signal is "1" indicating that synchronization is set, the selector 102 selects the output from the OR circuit 101; if it is "0" indicating that synchronization is not set, the selector 102 selects the channel 1 sequence restart instruction signal.

[0081] The selector 103 selects and outputs either the channel 2 sequence restart instruction signal or the output from the OR circuit 101 according to the in-module synchronization setting signal. If the in-module synchronization setting signal is "1" indicating that synchronization is set, the selector 103 selects the output from the OR circuit 101; if it is "0" indicating that synchronization is not set, the selector 103 selects the channel 2 sequence restart instruction signal.

[0082] Note that the in-module synchronization setting signal is a signal indicating whether to synchronize the two outputs in modules 2 and 3 at the time of sequence restart.

[0083] The setting of whether to synchronize the two outputs in modules 2 and 3 at the time of sequence restart is set in the device control unit 16 by an operation on the user operation unit 14. When the in-module synchronization setting signal is such that sequence restart is selected for any output of modules 2 and 3 due to an operation on the user operation unit 14, it is input to the data generation units 26 and 36 via the control units 29 and 39 of modules 2 and 3 that have the output for which sequence restart is selected from the device control unit 16.

[0084] Selector 104 selects and outputs either the output of selector 102 or the channel 1 sequence restart signal input from signal distribution circuit 5 according to the channel 1 inter-module synchronization setting signal. If the channel 1 inter-module synchronization setting signal is "1", indicating that synchronization is set, selector 104 selects the channel 1 sequence restart signal input from signal distribution circuit 5; if it is "0", indicating that synchronization is not set, selector 104 selects the output of selector 102.

[0085] Selector 105 selects and outputs either the output of selector 103 or the channel 2 sequence restart signal input from signal distribution circuit 5 according to the channel 2 inter-module synchronization setting signal. If the channel 2 inter-module synchronization setting signal is "1", indicating that synchronization is set, selector 105 selects the channel 2 sequence restart signal input from signal distribution circuit 5; if it is "0", indicating that synchronization is not set, selector 105 selects the output of selector 103.

[0086] Note that the channel 1 inter-module synchronization setting signal and the channel 2 inter-module synchronization setting signal are signals indicating whether channel 1 or channel 2 is to be synchronized with the output across modules 2 and 3 at the time of sequence restart.

[0087] The setting of whether channel 1 or channel 2 is to be synchronized with the output across modules 2 and 3 at the time of sequence restart is such that when, through an operation on user operation unit 14, a channel across modules 2 and 3 is set as the channel for which the device control unit 16 synchronizes the restart of the sequence, and when the restart of the sequence is selected for any of the channels set by the operation on user operation unit 14, the channel 1 inter-module synchronization setting signal and the channel 2 inter-module synchronization setting signal are input from the device control unit 16 to data generation units 26 and 36 via control units 29 and 39 for the set channel.

[0088] In this way, the signal output from the selector 104 is regarded as the channel 1 sequence restart signal, and the signal output from the selector 105 is regarded as the channel 2 sequence restart signal.

[0089] Thus, depending on the synchronization setting at the time of the user's sequence restart, whether it is within-module synchronization or between-module synchronization, the sequence restart signal can synchronize the restart of the sequence.

[0090] In this embodiment, as shown in FIG. 4, the sequence restart signal is turned on at the start of the sequence at time 100, is once turned off at time 300 by the user's sequence restart operation, is turned on at time 350, and the sequence is restarted.

[0091] In this example, the sequence start signal is also used as the sequence restart signal. To use it as the sequence restart signal, it must be turned off once and then on at the time of sequence restart. However, if it is used directly as the sequence start signal, the operation will stop while it is off. For this reason, as shown in FIG. 4, a mask signal that becomes on before turning off at the time of sequence restart and remains on until turning on at the time of sequence restart is generated, and the off period of the sequence start signal is masked to be in the on state.

[0092] In this way, in the above-described embodiment, the control units 29 and 39 of the modules 2 and 3 having the output instructed to restart the sequence output the sequence restart signal to the signal distribution circuit 5, and the data generation units 26 and 36 restart the sequence in synchronization with the sequence restart signal distributed from the signal distribution circuit 5 for the output for which the synchronization of the sequence restart is set.

[0093] Thus, the sequence can be restarted in a state where the outputs arbitrarily selected by the user are synchronized.

[0094] In addition, in the present embodiment, the measurement device 11 is shown to include the operation unit 14, the display unit 15, and the device control unit 16. However, a personal computer connected to the measurement device 11 may replace the functions of the operation unit 14, the display unit 15, and the device control unit 16.

[0095] Although embodiments of the present invention have been disclosed, it is obvious that those skilled in the art can make changes without departing from the scope of the present invention. It is intended that all such modifications and equivalents be included in the following claims.

Explanation of Reference Numerals

[0096] 1 Sequence Pattern Generator 2 Primary Module 3 Secondary Module 5 Signal Distribution Circuit 14 Operation Unit 15 Display Unit 16 Device Control Unit 26 Primary Data Generation Unit 29 Primary Control Unit 36 Secondary Data Generation Unit 39 Secondary Control Unit

Claims

1. A sequence pattern generator (1) having at least one mountable module (2, 3) with an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, comprising a signal distribution circuit (5) for distributing a signal output from a control unit (29, 39) of any of the modules to respective data generation units (26, 36) of the modules so that the timings are exactly the same clockwise, a sequence pattern generator in which the control unit of the module having an output instructed to resume the sequence outputs a sequence resume signal to the signal distribution circuit, and the data generation unit resumes the sequence in synchronization with the sequence resume signal distributed from the signal distribution circuit for an output for which the synchronization of the resumption of the sequence is set.

2. A sequence synchronization resumption method for a sequence pattern generator (1) having at least one mountable module (2, 3) with an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, and comprising a signal distribution circuit (5) for distributing a signal output from a control unit (29, 39) of any of the modules to respective data generation units (26, 36) of the modules so that the timings are exactly the same clockwise, the method comprising: a step in which the control unit of the module having an output instructed to resume the sequence outputs a sequence resume signal to the signal distribution circuit; a step in which the signal distribution circuit distributes the sequence resume signal to the data generation unit so that the timings are exactly the same clockwise; and a step in which the data generation unit resumes the sequence in synchronization with the sequence resume signal distributed from the signal distribution circuit for an output for which the synchronization of the resumption of the sequence is set.

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