Data reception circuit, data reception system, and storage device

Abstract

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, the data receiving circuit comprising: a first amplification module configured to receive a data signal, a first reference signal, and a second reference signal, and to respond to a sampling clock signal while an enable signal has a first level value, and to select the data signal and the first reference signal according to a feedback signal, perform a first comparison, and output a first signal pair, or select the data signal and the second reference signal, perform a second comparison, and output a second signal pair, and a second amplification module configured to receive the output signal of the first amplification module as an input signal pair, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process. The embodiments of the present disclosure at least contribute to improving the receiving performance of the data receiving circuit and reducing its power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to data receiving circuits, data receiving systems, and storage devices.

[0002] This application claims the priority of a Chinese patent application with the invention title "Data Receiving Circuit, Data Receiving System, and Storage Device" and application number 202210787523.X filed on July 4, 2022, and all of its contents are incorporated herein by reference.

Background Art

[0003] In the application of memory, as the signal transmission speed becomes faster and faster, the influence of channel loss on signal quality becomes greater, which easily causes inter-symbol interference. Also, the difference in the level values between the data signal received by the data receiving circuit of the memory and the reference signal affects the judgment of the data signal by the data receiving circuit, thereby affecting the accuracy of the signal output by the data receiving circuit.

[0004] Currently, generally, an equalization circuit is used to compensate for the channel, and the equalization circuit may select a CTLE (Continuous Time Linear Equalizer) or a DFE (Decision Feedback Equalizer). However, there is room for improvement in the accuracy of the signal output by the currently used equalization circuit, there is room for improvement in the receiving performance of the equalization circuit, and there is room for reduction in the power consumption of the equalization circuit.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, which contribute to improving at least the receiving performance of the data receiving circuit and reducing the power consumption of the data receiving circuit.

Means for Solving the Problems

[0006] According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a data receiving circuit that receives an enable signal, a feedback signal, a data signal, a first reference signal, and a second reference signal, and in response to a sampling clock signal while the enable signal has a first level value, and based on the feedback signal, selects the data signal and the first reference signal to perform a first comparison to output a first signal pair as a result of the first comparison, or selects the data signal and the second reference signal to perform a second comparison to output a second signal pair as a result of the second comparison, and is configured to perform the first comparison in response to the sampling clock signal while the enable signal has a second level value to output the first signal pair, where the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal, a first amplification module, and a second amplification module that receives an output signal of the first amplification module as an input signal pair, performs an amplification process on a voltage difference of the input signal pair, and outputs a first output signal and a second output signal as a result of the amplification process.

[0007] In some embodiments, the first amplification module includes a first node, a second node, a third node, and a fourth node for outputting the first signal, the second signal, the third signal, and the fourth signal in response to the sampling clock signal respectively, an amplification unit configured to receive the data signal, the first reference signal, and the second reference signal, and a decision balance enable unit connected between the first node and the second node and between the third node and the fourth node, configured to receive the enable signal and the feedback signal, conduct a connection path between the first node and the second node based on the feedback signal while the enable signal has the first level value, or conduct a connection path between the third node and the fourth node, and block the connection path between the first node and the second node and block the connection path between the third node and the fourth node while the enable signal has the second level value.

[0008] In some embodiments, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal, the amplification unit has the first node and the second node, and is configured to receive the data signal and the first reference signal and perform the first comparison in response to the first sampling clock signal; a first comparison circuit, configured to receive the enable signal and the original sampling clock signal and output the second sampling clock signal, and when the enable signal has the first level value, the phase of the second sampling clock signal is opposite to the phase of the original sampling clock signal, and when the enable signal has the second level value, the second sampling clock signal is a logic high level signal; a clock generation circuit, having the third node and the fourth node, configured to receive the data signal and the second reference signal, perform the second comparison in response to the second sampling clock signal when the enable signal has the first level value, and conduct the connection path between the third node and the ground terminal and the connection path between the fourth node and the ground terminal when the enable signal has the second level value; and a second comparison circuit.

[0009] In some embodiments, the feedback signal includes a differential first feedback signal and a second feedback signal, and the determination balance enable unit includes a first enable unit configured to connect the first node and the second node by conducting in response to the enable signal and the first feedback signal, and a second enable unit configured to connect the third node and the fourth node by conducting in response to the enable signal and the second feedback signal. When the enable signal has the first level value, one of the first enable unit and the second enable unit is conducted, and when the enable signal has the second level value, both the first enable unit and the second enable unit are blocked.

[0010] In some embodiments, the first enable unit includes a ninth PMOS field effect transistor and a tenth PMOS field effect transistor. One end of the ninth PMOS field effect transistor is connected to the first node, the gate receives a complementary enable signal, the other end of the ninth PMOS field effect transistor is connected to one end of the tenth PMOS field effect transistor, the other end of the tenth PMOS field effect transistor is connected to the second node, the gate receives the first feedback signal, and the level of the complementary enable signal is opposite to the level of the enable signal.

[0011] In some embodiments, the first enable unit further includes a ninth NMOS field effect transistor and a tenth NMOS field effect transistor. One end of the ninth NMOS field effect transistor is connected to the first node, the gate receives the enable signal, the other end of the ninth NMOS field effect transistor is connected to one end of the tenth NMOS field effect transistor, the other end of the tenth NMOS field effect transistor is connected to the second node, the gate receives a first complementary feedback signal, and the first complementary feedback signal is opposite to the level of the first feedback signal.

[0012] In some embodiments, the second enable unit includes an eleventh PMOS field effect transistor and a twelfth PMOS field effect transistor. One end of the eleventh PMOS field effect transistor is connected to the third node, the gate receives a complementary enable signal, the other end of the eleventh PMOS field effect transistor is connected to one end of the twelfth PMOS field effect transistor, the other end of the twelfth PMOS field effect transistor is connected to the fourth node, the gate receives the second feedback signal, and the level of the complementary enable signal is opposite to the level of the enable signal.

[0013] In some embodiments, the second enabling unit further includes an 11th NMOS field effect transistor and a 12th NMOS field effect transistor. One end of the 11th NMOS field effect transistor is connected to the third node, the gate receives the enabling signal, the other end of the 11th NMOS field effect transistor is connected to one end of the 12th NMOS field effect transistor, the other end of the 12th NMOS field effect transistor is connected to the fourth node, the gate receives a second complementary feedback signal, and the second complementary feedback signal is opposite to the level of the second feedback signal.

[0014] In some embodiments, the first comparison circuit includes a first current source connected between a power supply node and a fifth node and configured to supply current to the fifth node in response to a first sampling clock signal, a first comparison unit connected to the first node, the second node, and the fifth node, receiving the data signal and the first reference signal, performing the first comparison when the first current source supplies current to the fifth node, and outputting the first signal and the second signal, and a first reset unit connected to the first node and the second node and configured to reset the first node and the second node in response to the first sampling clock signal. The second comparison circuit includes a second current source connected between a power supply node and a sixth node and configured to supply current to the sixth node in response to a second sampling clock signal, a second comparison unit connected to the third node, the fourth node, and the sixth node, receiving the data signal and the second reference signal, performing the second comparison when the second current source supplies current to the sixth node, and outputting the third signal and the fourth signal, and a second reset unit connected between the third node and the fourth node and configured to reset the third node and the fourth node in response to the second sampling clock signal.

[0015] In some embodiments, the first current source is connected between the power supply node and the fifth node, and includes a first PMOS field effect transistor whose gate receives the first sampling clock signal. The second current source is connected between the power supply node and the sixth node, and includes a second PMOS field effect transistor whose gate receives the second sampling clock signal.

[0016] In some embodiments, the first comparison unit includes a third PMOS field effect transistor connected between the first node and the fifth node and having a gate receiving the data signal, and a fourth PMOS field effect transistor connected between the second node and the fifth node and having a gate receiving the first reference signal. The second comparison unit includes a fifth PMOS field effect transistor connected between the third node and the sixth node and having a gate receiving the data signal, and a sixth PMOS field effect transistor connected between the fourth node and the sixth node and having a gate receiving the second reference signal.

[0017] In some embodiments, the first reset unit includes a first NMOS field effect transistor connected between the first node and the ground terminal and having a gate receiving the first sampling clock signal, and a second NMOS field effect transistor connected between the second node and the ground terminal and having a gate receiving the first sampling clock signal. The second reset unit includes a third NMOS field effect transistor connected between the third node and the ground terminal and having a gate receiving the second sampling clock signal, and a fourth NMOS field effect transistor connected between the fourth node and the ground terminal and having a gate receiving the second sampling clock signal.

[0018] In some embodiments, the clock generation circuit includes a first NAND gate circuit having one input terminal receiving the original sampling clock signal, the other input terminal connected to the power supply node, and an output terminal outputting the first sampling clock signal.

[0019] In some embodiments, the clock generation circuit includes a second NAND gate circuit in which one input terminal receives the original sampling clock signal, the other input terminal receives the enable signal, and the output terminal outputs a second sampling clock signal.

[0020] In some embodiments, the second amplification module includes a first input unit connected to a seventh node and an eighth node, configured to receive the first signal pair to perform a third comparison, and supply signals to the seventh node and the eighth node respectively as a result of the third comparison; a second input unit connected to the seventh node and the eighth node, configured to receive the second signal pair to perform a fourth comparison, and supply signals to the seventh node and the eighth node respectively as a result of the fourth comparison; and a latch unit connected to the seventh node and the eighth node, configured to amplify and latch the signal of the seventh node and the signal of the eighth node, and output the first output signal and the second output signal through a first output node and a second output node respectively.

[0021] In some embodiments, the first input unit includes a fifth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to the ground terminal, and a gate receiving the first signal, and a sixth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to the ground terminal, and a gate receiving the second signal. The second input unit includes a seventh NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to the ground terminal, and a gate receiving the third signal, and an eighth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to the ground terminal, and a gate receiving the fourth signal.

[0022] In some embodiments, the latch unit includes a 13th NMOS field-effect transistor and a 7th PMOS field-effect transistor, where the gates of both the 13th NMOS field-effect transistor and the 7th PMOS field-effect transistor are connected to the second output node, the source electrode of the 13th NMOS field-effect transistor is connected to the seventh node, the drain electrodes of both the 13th NMOS field-effect transistor and the 7th PMOS field-effect transistor are connected to the first output node, and the source electrode of the 7th PMOS field-effect transistor is connected to the power supply node; and a 14th NMOS field-effect transistor and an 8th PMOS field-effect transistor, where the gates of both the 14th NMOS field-effect transistor and the 8th PMOS field-effect transistor are connected to the first output node, the source electrode of the 14th NMOS field-effect transistor is connected to the eighth node, the drain electrodes of both the 14th NMOS field-effect transistor and the 8th PMOS field-effect transistor are connected to the second output node, and the source electrode of the 8th PMOS field-effect transistor is connected to the power supply node.

[0023] In some embodiments, the second amplification module further includes a third reset unit connected between the power supply node and the output terminal of the latch unit and configured to reset the output terminal of the latch unit.

[0024] In some embodiments, the third reset unit includes a 13th PMOS field-effect transistor connected between the first output node and the power supply node and having a gate receiving the original sampling clock signal, and a 14th PMOS field-effect transistor connected between the second output node and the power supply node and having a gate receiving the original sampling clock signal.

[0025] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a data receiving system, which includes a plurality of cascaded data transmission circuits. Each of the data transmission circuits includes the data receiving circuit according to any one of the above items, and a latch circuit connected to the data receiving circuit. The output signal of the data transmission circuit in the previous stage is used as the feedback signal of the data transmission circuit in the subsequent stage, and the output signal of the data transmission circuit in the last stage is used as the feedback signal of the data transmission circuit in the first stage.

[0026] In some embodiments, the data receiving circuit receives data in response to a sampling clock signal, and the data receiving system includes four cascaded data transmission circuits. The phase difference of the sampling clock signals of the data receiving circuits in adjacent stages is 90°.

[0027] In some embodiments, the first output signal and the second output signal output by the second amplification module of the data receiving circuit in the previous stage are used as the feedback signal of the data receiving circuit in the subsequent stage, or the signal output by the latch circuit in the previous stage is used as the feedback signal of the data receiving circuit in the subsequent stage.

[0028] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a storage device, which includes a plurality of data ports and a plurality of data receiving systems according to any one of the above items corresponding to each of the data ports.

Advantages of the Invention

[0029] The technical solutions according to the embodiments of the present disclosure have at least the following advantages.

[0030] The first amplification module can receive a data signal, a first reference signal, and a second reference signal, and can also receive an enable signal and a feedback signal. When the enable signal is in the first level value period, the first amplification module responds to the sampling clock signal and selects whether to perform a first comparison or a second comparison based on the feedback signal, enables one of the output first signal pair and second signal pair, and disables the other, thereby reducing the influence of inter-symbol interference of the received data signal on the data receiving circuit, and only one of the circuit for performing the first comparison and the circuit for performing the second comparison in the first amplification module may be in an operating state and the other may be in a non-operating state, contributing to reducing the power consumption of the data receiving circuit. When the enable signal is in the second level value period, the first amplification module only performs the first comparison in response to the sampling clock signal and fixedly outputs the valid first signal pair. At this time, the circuit for outputting the second signal pair in the first amplification module may be in a non-operating state, contributing to further reducing the power consumption of the data receiving circuit.

[0031] In this way, further control of the first amplification module can be realized by using the enable signal and the feedback signal, thereby selecting whether to consider the influence of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, the enable signal is in the first level value period, the first amplification module responds to the sampling clock signal, and selects the one with a relatively large difference in level values between the first signal pair or the second signal pair output based on the feedback signal, thereby ensuring that the second amplification module receives a pair of differential signals with a relatively large difference in signal level values. When there is no need to consider the influence of inter-symbol interference on the data receiving circuit, the enable signal is in the second level value period, the first amplification module only performs the first comparison in response to the sampling clock signal, and fixedly outputs the valid first signal pair, thereby improving the receiving performance of the data receiving circuit and realizing the effect of reducing the power consumption of the data receiving circuit.

[0032] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements having the same reference numerals in the drawings represent similar elements. Unless otherwise specified, the figures in the drawings do not limit the ratio. For the purpose of more clearly explaining the embodiments of the present disclosure or the technical solutions of the prior art, the drawings required to be used in the following embodiments are briefly described below. Of course, the drawings in the following description are merely some embodiments of the present disclosure. A person skilled in the art can obtain other drawings based on these drawings without the need for creative efforts.

Brief Description of the Drawings

[0033]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Modes for Carrying Out the Invention

[0034] Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device. In the data receiving circuit, further control of the first amplification module can be realized by using an enable signal and a feedback signal, thereby selecting whether to consider the influence of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, the enable signal is in the first level value period, the first amplification module responds to the sampling clock signal, and based on the feedback signal, selects whether to perform a first comparison or a second comparison, enables one of the output first signal pair and the second signal pair, disables the other, and further increases the difference in the signal level values of the valid signal pair, thereby ensuring that the second amplification module can receive a pair of differential signals with a larger difference in signal level values. When it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit, the enable signal is in the second level value period, the first amplification module only performs the first comparison in response to the sampling clock signal, fixes and outputs the valid first signal pair, thereby realizing the effect of improving the receiving performance of the data receiving circuit and reducing the power consumption of the data receiving circuit.

[0035] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. However, as will be understood by those skilled in the art, in each embodiment of the present disclosure, many technical details are provided to enable the reader to better understand the embodiments of the present disclosure. However, the claimed technical solutions of the embodiments of the present disclosure can be realized without these technical details and various changes and modifications based on the following embodiments.

[0036] One embodiment of the present disclosure provides a data receiving circuit, and a data receiving circuit according to an embodiment of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 3 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 4 is a functional block diagram of a first amplification module of a data receiving circuit according to an embodiment of the present disclosure, FIG. 5 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 6 is a schematic circuit structure diagram of a first amplification module of a data receiving circuit according to an embodiment of the present disclosure, FIG. 7 is another schematic circuit structure diagram of a first amplification module of a data receiving circuit according to an embodiment of the present disclosure, and FIG. 8 is a schematic circuit structure diagram of a second amplification module of a data receiving circuit according to an embodiment of the present disclosure.

[0037] Referring to FIGS. 1 and 3, the data receiving circuit 100 receives a data signal DQ, a first reference signal VR+, and a second reference signal VR−, and in response to a sampling clock signal clkN and based on a feedback signal fb, selects the data signal DQ and the first reference signal VR+ to perform a first comparison and output a first signal pair as a result of the first comparison, or selects the data signal DQ and the second reference signal VR− to perform a second comparison and output a second signal pair as a result of the second comparison, while the enable signal EnDfe has a second level value, it is configured to perform a first comparison in response to the sampling clock signal clkN and output a first signal pair. The first signal pair includes a first signal Sn+ and a second signal Sp+, and the second signal pair includes a third signal Sn− and a fourth signal Sp−. The first amplification module 101, and a second amplification module 102 configured to receive the output signal of the first amplification module 101 as an input signal pair, perform an amplification process on the voltage difference of the input signal pair, and output a first output signal Vout and a second output signal VoutN as a result of the amplification process.

[0038] As can be understood, when the enable signal EnDfe is in the first level value period, based on the difference of the previously received feedback signal fb, the first amplification module 101 can selectively perform the first comparison or the second comparison based on the enable signal EnDfe and different feedback signals fb at this time, output an effective first signal pair or an effective second signal pair to the first amplification module 101, and the other signal pair is invalid at this time. Note that the fact that the first signal pair is effective means that the level values of the first signal Sn+ and the second signal Sp+ in the first signal pair have a relatively large difference, and the fact that the second signal pair is effective means that the level values of the third signal Sn- and the fourth signal Sp- in the second signal pair have a relatively large difference. In this way, it is ensured that the second amplification module 102 receives a pair of differential signals with a relatively large difference in signal level values, and the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100 is reduced.

[0039] In some embodiments, when the level values of the first reference signal VR+ and the second reference signal VR− are different, for data signals DQ with different level values, it can satisfy that the difference in the level values between the data signal DQ and one of the first reference signal VR+ or the second reference signal VR− is relatively large. When the first amplification module 101 can perform the first comparison and the second comparison simultaneously, the first amplification module 101 can output a pair of signals with a larger difference in level values. In an embodiment of the present disclosure, when an inter-symbol interference phenomenon occurs in the data signal DQ received by the data receiving circuit 100, the first amplification module 101 can selectively perform the first comparison or the second comparison based on the difference in the feedback signal fb, and one of the output first signal pair and second signal pair is valid and the other is invalid. A valid pair of signals refers to a pair of signals with a larger difference in level values when the first comparison and the second comparison can be performed simultaneously, which can reduce the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100. As can be understood, when the enable signal EnDfe is in the first level value period, the first amplification module 101 can selectively perform a better comparison on the processing of the data signal DQ based on the received feedback signal fb, that is, selectively perform the first comparison or the second comparison, thereby obtaining a better pair of signals. In this way, when the enable signal EnDfe is in the first level value period, the first amplification module 101 will only perform one of the first comparison and the second comparison with better processing, and the other is in a non-operating state, contributing to reducing the power consumption of the data receiving circuit.

[0040] In addition, what the second amplification module 102 receives is a pair of differential signals with a relatively large difference in signal level values, thereby contributing to improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. Therefore, the cooperation between the first amplification module 101 and the second amplification module 102 contributes to improving the receiving performance of the data receiving circuit 100.

[0041] In another aspect, when the enable signal EnDfe is in the second level value period, regardless of how the level value of the feedback signal fb obtained based on the previously received data changes, the first amplification module 101 also performs a fixed first comparison based on the enable signal EnDfe at this time. That is, at this time, the first amplification module 101 fixes and outputs a valid first signal pair. At this time, the first amplification module 101 does not perform a second comparison. That is, the circuit for outputting the second signal pair in the first amplification module 101 may be in a non-operating state, which contributes to further reducing the power consumption of the data reception circuit.

[0042] As can be seen from the above analysis, further control of the first amplification module 101 can be realized by using the enable signal EnDfe and the feedback signal fb, so as to select whether to consider the influence of inter-symbol interference of the data received by the data reception circuit 100 on the data reception circuit 100. Thereby, the effect of improving the reception performance of the data reception circuit 100 and reducing the power consumption of the data reception circuit 100 is realized.

[0043] Regarding how to reduce the influence of inter-symbol interference of the data signal DQ received by the data reception circuit 100 on the data reception circuit 100, a specific example will be given below for a detailed explanation.

[0044] In some embodiments, when the level value of the first reference signal VR+ is higher than the level value of the second reference signal VR-, the data signal DQ is at a low level and the inter-symbol interference phenomenon occurs in the data signal DQ received by the data receiving circuit 100, the enable signal EnDfe is in the first level value period, and the first comparison is performed by the first amplification module 101 based on the enable signal EnDfe and the feedback signal fb at this time, that is, the output is a valid first signal pair. At this time, the difference in the level values between the data signal DQ and the first reference signal VR+ is larger than the difference in the level values between the data signal DQ and the second reference signal VR-. Then, performing the first comparison at this time will generate an output signal pair with a larger difference in level values compared to performing the second comparison. Therefore, the second amplification module 102 receiving the first signal pair obtained by performing the first comparison contributes to outputting the first output signal Vout and the second output signal VoutN that meet the requirements, that is, ensuring the accuracy of the first output signal Vout and the second output signal VoutN, thereby contributing to reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0045] Also, when the data signal DQ is at a high level and there is an inter-symbol interference phenomenon in the data signal DQ received by the data receiving circuit 100, the enable signal EnDfe is in the first level value period. At this time, the first amplification module 101 performs a second comparison based on the enable signal EnDfe and the feedback signal fb at this time, that is, the output is a valid second signal pair. At this time, the difference in the level values between the data signal DQ and the first reference signal VR+ is smaller than the difference in the level values between the data signal DQ and the second reference signal VR-. Then, performing the second comparison at this time will generate an output signal pair with a larger difference in level values compared to performing the first comparison. Therefore, the second amplification module 102 receiving the second signal pair obtained by performing the second comparison contributes to outputting the first output signal Vout and the second output signal VoutN that meet the requirements, that is, ensuring the accuracy of the first output signal Vout and the second output signal VoutN, thereby contributing to reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0046] As can be understood, in actual applications, the level value of the first reference signal VR+ may be lower than the level value of the second reference signal VR-.

[0047] As can be seen from the above, while the enable signal EnDfe has the first level value, the first amplification module 101 selectively performs the first comparison and the second comparison based on the feedback signal fb whose level value changes, so as to output a first signal pair or a second signal pair with a larger difference in level values, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the subsequent second amplification module 102, and thereby reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

[0048] In some embodiments, referring to FIG. 3, the first amplification module 101 has a first node net1, a second node net2, a third node net3, and a fourth node net4 for outputting a first signal Sn+, a second signal Sp+, a third signal Sn−, and a fourth signal Sp− in response to a sampling clock signal clkN, respectively, and an amplification unit 131 configured to receive a data signal DQ, a first reference signal VR+, and a second reference signal VR−; and a decision balance enable unit 141 connected between the first node net1 and the second node net2 and between the third node net3 and the fourth node net4, receiving an enable signal EnDfe and a feedback signal fb, and configured to conduct a connection path between the first node net1 and the second node net2 based on the feedback signal fb while the enable signal EnDfe has a first level value, or conduct a connection path between the third node net3 and the fourth node net4, and block the connection path between the first node net1 and the second node net2 and block the connection path between the third node net3 and the fourth node net4 while the enable signal EnDfe has a second level value.

[0049] In addition, when the decision balance enable unit 141 conducts the connection path between the first node net1 and the second node net2 based on the enable signal EnDfe and the feedback signal fb, the level value of the first signal Sn+ output by the first node net1 and the second node net2 is equal to the level value of the output second signal Sp+, that is, the amplification unit 131 does not perform the first comparison and cannot output a valid first signal pair. When the decision balance enable unit 141 conducts the connection path between the third node net3 and the fourth node net4 based on the enable signal EnDfe and the feedback signal fb, the level value of the third signal Sn− output by the third node net3 and the fourth node net4 is equal to the level value of the output fourth signal Sp−, that is, the amplification unit 131 does not perform the second comparison and cannot output a valid second signal pair.

[0050] As understood, when it is necessary to reduce the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is in the first level value period. At this time, based on the enable signal EnDfe and the feedback signal fb at this time, the decision balance enable unit 141 selectively conducts the connection path between the first node net1 and the second node net2, or the connection path between the third node net3 and the fourth node net4. The two nodes that conduct the path cannot output a valid signal pair, thereby causing the amplification unit 131 to selectively perform the first comparison or the second comparison. When it is not necessary to consider the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is in the second level value period. At this time, based on the enable signal EnDfe at this time, the decision balance enable unit 141 cuts off the connection path between the first node net1 and the second node net2 and the connection path between the third node net3 and the fourth node net4, and the amplification unit 131 only performs the first comparison under its own control. In addition, the decision balance enable unit 141 is integrated into the first amplification module 101, contributing to further reducing the layout area of the entire data receiving circuit 100.

[0051] It should be noted that the situation where it is necessary to consider inter-symbol interference is generally a situation where the received data signal DQ of the data receiving circuit 100 is high-speed data, that is, a situation where the data transmission speed is fast, and the situation where it is not necessary to consider inter-symbol interference is a situation where the received data signal DQ of the data receiving circuit 100 is generally low-speed data, that is, a situation where the data transmission speed is slow.

[0052] In some embodiments, referring to FIGS. 4 and 5, the sampling clock signal clkN includes a first sampling clock signal clkN1 and a second sampling clock signal clkN2. The amplification unit 131 has a first node net1 and a second node net2, and is configured to receive a data signal DQ and a first reference signal VR+ and perform a first comparison in response to the first sampling clock signal clkN1. A first comparison circuit 111, which is configured to receive an enable signal EnDfe and an original sampling clock signal clk and output a second sampling clock signal clkN2. During the period when the enable signal EnDfe has a first level value, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk. During the period when the enable signal EnDfe has a second level value, the second sampling clock signal clkN2 is a logic high level signal. A clock generation circuit 151, which has a third node net3 and a fourth node net4, receives a data signal DQ and a second reference signal VR−, and performs a second comparison in response to the second sampling clock signal clkN2 during the period when the enable signal EnDfe has a first level value. During the period when the enable signal EnDfe has a second level value, a connection path between the third node net3 and the ground terminal is conducted, and a connection path between the fourth node net4 and the ground terminal is conducted. A second comparison circuit 121 is provided.

[0053] As understood, regardless of whether it is necessary to consider the influence on the data reception circuit 100 of inter-symbol interference, when the enable signal EnDfe is in the first level value period and the decision balance enable unit 141 conducts the connection path between the third node net3 and the fourth node net4 based on the feedback signal fb, the first comparison circuit 111 can also perform the first comparison in response to the first sampling clock signal clkN1. When the enable signal EnDfe is in the second level value period and the decision balance enable unit 141 does not conduct the connection path between the first node net1 and the second node net2 based on the enable signal EnDfe at this time, the first comparison circuit 111 may perform the first comparison in response to the first sampling clock signal clkN1. As can be seen from the above, regardless of whether the enable signal EnDfe is in the first level value period or the second level value period, that is, regardless of whether it is necessary to consider the influence on the data reception circuit 100 of inter-symbol interference, the first comparison circuit 111 may also perform the first comparison in response to the first sampling clock signal clkN1. However, only when the enable signal EnDfe is in the first level value period and the decision balance enable unit 141 conducts the connection path between the first node net1 and the second node net2 based on the feedback signal fb, the second comparison circuit 121 can perform the second comparison in response to the second sampling clock signal clkN2 whose level value changes. When the enable signal EnDfe is in the second level value period, the second sampling clock signal clkN2 is a logic high level signal, and the second comparison circuit 121 conducts the connection paths between the third node net3 and the ground terminal and between the fourth node net4 and the ground terminal, pulling down the level values of both the third signal Sn- output from the third node net3 and the fourth signal Sp- output from the fourth node net4 to 0, that is, the second comparison circuit 121 does not perform the second comparison and cannot output a valid second signal pair.

[0054] In some embodiments, when the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk and the enable signal EnDfe is in the first level value period, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk. Then, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2 at this time. Thus, the first comparison circuit 111 at this time can perform the first comparison in response to the first sampling clock signal clkN1, or the second comparison circuit 121 can perform the second comparison in response to the second sampling clock signal clkN2. At the same time, based on the enable signal EnDfe and the feedback signal fb, the decision balance enable unit 141 further controls the potentials at the first node net1, the second node net2, the third node net3, and the fourth node net4. For example, the potential at the first node net1 is made the same as the potential at the second node net2, so that the amplification unit 131 cannot actually perform the first comparison and cannot output a valid first signal pair. Or, the potential at the third node net3 is made the same as the potential at the fourth node net4, so that the amplification unit 131 cannot actually perform the second comparison and cannot output a valid second signal pair. As can be seen from the above, through the cooperation of the amplification unit 131 and the decision balance enable unit 141, the amplification unit 131 can be selectively made to perform the first comparison or the second comparison.

[0055] In some embodiments, referring to FIGS. 4 and 5, the feedback signal fb may include a differential first feedback signal fbp and a second feedback signal fbn. The decision balance enable unit 141 is configured to connect the first node net1 and the second node net2 by conducting in response to the enable signal EnDfe and the first feedback signal fbp, and is configured to connect the third node net3 and the fourth node net4 by conducting in response to the enable signal EnDfe and the second feedback signal fbn. While the enable signal EnDfe has a first level value, one of the first enable unit 1411 and the second enable unit 1412 is conducted. While the enable signal EnDfe has a second level value, both the first enable unit 1411 and the second enable unit 1412 are configured to be blocked. The decision balance enable unit 141 may include a first enable unit 1411 and a second enable unit 1412.

[0056] As can be understood, when the first feedback signal fbp is at a high level, the second feedback signal fbn is at a low level. When the first feedback signal fbp is at a low level, the second feedback signal fbn is at a high level. Thus, when the enable signal EnDfe is in the first level value period, one of the first enable unit 1411 that receives the first feedback signal fbp and the second enable unit 1412 that receives the second feedback signal fbn is conducted, connecting one of the first node net1 and the second node net2 and the third node net3 and the fourth node net4, and selectively realizing the first comparison or the second comparison in the first amplification module 101. When the enable signal EnDfe is in the second level value period, regardless of how the level values of the first feedback signal fbp and the second feedback signal fbn change, the first enable unit 1411 and the second enable unit 1412 are also blocked based on the enable signal EnDfe at this time, and the amplification unit 131 only performs the first comparison under its own control.

[0057] In some embodiments, referring to FIGS. 6 and 7, the first enable unit 1411 may include a ninth PMOS field effect transistor MP9 and a tenth PMOS field effect transistor MP10. One end of the ninth PMOS field effect transistor MP9 is connected to the first node net1, the gate receives the complementary enable signal EnDfeN, the other end of the ninth PMOS field effect transistor MP9 is connected to one end of the tenth PMOS field effect transistor MP10, the other end of the tenth PMOS field effect transistor MP10 is connected to the second node net2, the gate receives the first feedback signal fbp, and the level of the complementary enable signal EnDfeN is opposite to the level of the enable signal EnDfe.

[0058] It should be noted that the fact that the level of the complementary enable signal EnDfeN is opposite to the level of the enable signal EnDfe means that when one of the complementary enable signal EnDfeN and the enable signal EnDfe is at a high level, the other is at a low level.

[0059] In one example, when it is necessary to reduce the impact on the data receiving circuit 100 of inter-symbol interference, the complementary enable signal EnDfeN is at a low level, and the ninth PMOS field effect transistor MP9 is turned on. At this time, the tenth PMOS field effect transistor MP10 is turned on or off based on the received first feedback signal fbp. Then, the first enable unit 1411 is turned on or off based on the first feedback signal fbp. When the first feedback signal fbp is at a high level, the tenth PMOS field effect transistor MP10 is turned off, and the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1, thereby outputting a valid first signal pair. When it is not necessary to consider the impact on the data receiving circuit 100 of inter-symbol interference, the complementary enable signal EnDfeN is at a high level, and the ninth PMOS field effect transistor MP9 is turned off. At this time, regardless of whether the first feedback signal fbp is at a high level or a low level, the first enable unit 1411 is also turned off, and the first comparison circuit 111 is not controlled by the first enable unit 1411 and can always perform a first comparison in response to the first sampling clock signal clkN1.

[0060] In some embodiments, referring to FIG. 7, the first enable unit 1411 includes the ninth PMOS field effect transistor MP9 and the tenth PMOS field effect transistor MP10. Further, the first enable unit 1411 may also include the ninth NMOS field effect transistor MN9 and the tenth NMOS field effect transistor MN10. One end of the ninth NMOS field effect transistor MN9 is connected to the first node net1, the gate receives the enable signal EnDfe, the other end of the ninth NMOS field effect transistor MN9 is connected to one end of the tenth NMOS field effect transistor MN10, the other end of the tenth NMOS field effect transistor MN10 is connected to the second node net2, the gate receives the first complementary feedback signal fbpN, and the level of the first complementary feedback signal fbpN is opposite to that of the first feedback signal fbp.

[0061] Note that the first-level value period of the enable signal EnDfe refers to the situation where the first enable unit 1411 determines that the enable signal EnDfe is within the level value range of logic level 1, i.e., high level. The second-level value period of the enable signal EnDfe refers to the situation where the first enable unit 1411 determines that the enable signal EnDfe is within the level value range of logic level 0, i.e., low level. That the first complementary feedback signal fbpN is opposite to the level of the first feedback signal fbp means that when one of the first complementary feedback signal fbpN and the first feedback signal fbp is at a high level, the other is at a low level.

[0062] In one example, when it is necessary to reduce the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a high level, the complementary enable signal EnDfeN is at a low level, and both the ninth PMOS field effect transistor MP9 and the ninth NMOS field effect transistor MN9 are turned on. At this time, the tenth PMOS field effect transistor MP10 is turned on or off based on the received first feedback signal fbp, and the tenth NMOS field effect transistor MN10 is turned on or off based on the received first complementary feedback signal fbpN. Then, the first enable unit 1411 is turned on or off based on the first feedback signal fbp and the first complementary feedback signal fbpN. When the first feedback signal fbp is at a high level and the first complementary feedback signal fbpN is at a low level, both the tenth PMOS field effect transistor MP10 and the tenth NMOS field effect transistor MN10 are turned off, and the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1, thereby outputting an effective first signal pair. When it is not necessary to consider the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a low level, the complementary enable signal EnDfeN is at a high level, and both the ninth PMOS field effect transistor MP9 and the ninth NMOS field effect transistor MN9 are turned off. At this time, regardless of whether the first feedback signal fbp and the first complementary feedback signal fbpN are at a high level or a low level, the first enable unit 1411 is also turned off, and the first comparison circuit 111 is not controlled by the first enable unit 1411 and can always perform a first comparison in response to the first sampling clock signal clkN1.

[0063] In some embodiments, referring to FIGS. 6 and 7, the second enable unit 1412 may include an 11th PMOS field effect transistor MP11 and a 12th PMOS field effect transistor MP12. One end of the 11th PMOS field effect transistor MP11 is connected to the third node net3, the gate receives the complementary enable signal EnDfeN, the other end of the 11th PMOS field effect transistor MP11 is connected to one end of the 12th PMOS field effect transistor MP12, the other end of the 12th PMOS field effect transistor MP12 is connected to the fourth node net4, the gate receives the second feedback signal fbn, and the level of the complementary enable signal EnDfeN is opposite to the level of the enable signal EnDfe.

[0064] In one example, when it is necessary to reduce the influence on the inter-symbol interference data receiving circuit 100, the complementary enable signal EnDfeN is at a low level, and the 11th PMOS field effect transistor MP11 is turned on. At this time, the 12th PMOS field effect transistor MP12 is turned on or off based on the received second feedback signal fbn. Then, the second enable unit 1412 is turned on or off based on the second feedback signal fbn. When the second feedback signal fbn is at a high level, the 12th PMOS field effect transistor MP12 is turned off, and the second comparison circuit 121 can perform a second comparison in response to the second sampling clock signal clkN2, thereby outputting a valid second signal pair. Since the first feedback signal fbp and the second feedback signal fbn are differential signals, when it is necessary to reduce the influence on the inter-symbol interference data receiving circuit 100, the first amplification module 101 can be realized to selectively perform the first comparison or the second comparison based on the feedback signal fb.

[0065] When there is no need to consider the influence on the inter-symbol interference data receiving circuit 100, the complementary enable signal EnDfeN is at a high level, and the 11th PMOS field effect transistor MP11 is cut off. At this time, regardless of whether the second feedback signal fbn is at a high level or a low level, the second enable unit 1412 is also cut off. The second comparison circuit 121 is not controlled by the second enable unit 1412. At this time, the second sampling clock signal clkN2 is a logic high level signal, and the second comparison circuit 121 does not perform the second comparison and cannot output a valid second signal pair. Thus, when there is no need to consider the influence on the inter-symbol interference data receiving circuit 100, it is realized that the first amplification module 101 has no choice but to perform the first comparison in response to the first sampling clock signal clkN1.

[0066] In some embodiments, referring to FIG. 7, the second enable unit 1412 includes the 11th PMOS field effect transistor MP11 and the 12th PMOS field effect transistor MP12. The second enable unit 1412 may further include the 11th NMOS field effect transistor MN11 and the 12th NMOS field effect transistor MN12. One end of the 11th NMOS field effect transistor MN11 is connected to the third node net3, the gate receives the enable signal EnDfe, the other end of the 11th NMOS field effect transistor MN11 is connected to one end of the 12th NMOS field effect transistor MN12, the other end of the 12th NMOS field effect transistor MN12 is connected to the fourth node net4, the gate receives the second complementary feedback signal fbnN, and the second complementary feedback signal fbnN is opposite to the level of the second feedback signal fbn.

[0067] Note that the fact that the second complementary feedback signal fbnN is opposite to the level of the second feedback signal fbn means that when one of the second complementary feedback signal fbnN and the second feedback signal fbn is at a high level, the other is at a low level.

[0068] In one example, when it is necessary to reduce the impact on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a high level, the complementary enable signal EnDfeN is at a low level, both the 11th PMOS field-effect transistor MP11 and the 11th NMOS field-effect transistor MN11 are conducting. At this time, the 12th PMOS field-effect transistor MP12 is turned on or off based on the received second feedback signal fbn, and the 12th NMOS field-effect transistor MN12 is turned on or off based on the received second complementary feedback signal fbnN. Then, the second enable unit 1412 is turned on or off based on the second feedback signal fbn and the second complementary feedback signal fbnN. When the second feedback signal fbn is at a high level and the second complementary feedback signal fbnN is at a low level, both the 12th PMOS field-effect transistor MP12 and the 12th NMOS field-effect transistor MN12 are turned off, and the second comparison circuit 121 can perform a second comparison in response to the second sampling clock signal clkN2, thereby outputting a valid second signal pair. Since the first feedback signal fbp and the second feedback signal fbn are differential signals, when it is necessary to reduce the impact on the inter-symbol interference data receiving circuit 100, the first amplification module 101 can be realized to selectively perform the first comparison or the second comparison based on the feedback signal fb.

[0069] When there is no need to consider the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a low level, the complementary enable signal EnDfeN is at a high level, both the 11th PMOS field effect transistor MP11 and the 11th NMOS field effect transistor MN11 are cut off. At this time, regardless of whether the second feedback signal fbn and the second complementary feedback signal fbnN are at a high level or a low level, the second enable unit 1412 is also cut off. The second comparison circuit 121 is not controlled by the second enable unit 1412. At this time, the second sampling clock signal clkN2 is a logic high level signal, and the second comparison circuit 121 does not perform the second comparison and cannot output a valid second signal pair. Thus, when there is no need to consider the influence on the inter-symbol interference data receiving circuit 100, it is realized that the first amplification module 101 has no choice but to perform the first comparison in response to the first sampling clock signal clkN1.

[0070] In some embodiments, referring to FIGS. 4 and 5, the first comparison circuit 111 may include a first current source 1111 connected between a power supply node Vcc (see FIG. 6) and a fifth node net5 and configured to supply current to the fifth node net5 in response to the first sampling clock signal clkN1; a first comparison unit 1112 connected to the first node net1, the second node net2, and the fifth node net5, configured to receive a data signal DQ and a first reference signal VR +, perform a first comparison when the first current source 1111 supplies current to the fifth node net5, and output a first signal Sn + and a second signal Sp +; and a first reset unit 1113 connected to the first node net1 and the second node net2 and configured to reset the first node net1 and the second node net2 in response to the first sampling clock signal clkN1.

[0071] The second comparison circuit 121 is connected between the power supply node Vcc and the sixth node net6, and includes a second current source 1211 configured to supply current to the sixth node net6 in response to the second sampling clock signal clkN2, a second comparison unit 1212 connected to the third node net3, the fourth node net4, and the sixth node net6, configured to receive the data signal DQ and the second reference signal VR-, perform a second comparison when the second current source 1211 supplies current to the sixth node net6, and output a third signal Sn- and a fourth signal Sp-, and a second reset unit 1213 connected between the third node net3 and the fourth node net4, configured to reset the third node net3 and the fourth node net4 in response to the second sampling clock signal clkN2.

[0072] As can be understood, the first comparison unit 1112 can output a first signal Sn+ and a second signal Sp+ by controlling the difference between the current supplied to the first node net1 and the current supplied to the second node net2 based on the voltage difference between the data signal DQ and the first reference signal VR+. The second comparison unit 1212 can output a third signal Sn- and a fourth signal Sp- by controlling the difference between the current supplied to the third node net3 and the current supplied to the fourth node net4 based on the voltage difference between the data signal DQ and the second reference signal VR-. Also, after the data receiving circuit 100 completes receiving the data signal DQ, the first reference signal VR+, and the second reference signal VR- and outputting the first output signal Vout and the second output signal VoutN once, the first reset unit 1113 can restore the level values at the first node net1 and the second node net2 to their initial values, and the second reset unit 1213 can restore the level values at the third node net3 and the fourth node net4 to their initial values, facilitating the subsequent data receiving circuit 100 to perform the next data reception and processing.

[0073] In some embodiments, the circuit structure of the first current source 1111 is the same as that of the second current source 1211, and the circuit structure of the first comparison unit 1112 is the same as that of the second comparison unit 1212. In this way, it contributes to making the first signal pair output by the first comparison circuit 111 mainly affected by the first reference signal VR+, or making the difference between the second signal pairs output by the second comparison circuit 121 mainly affected by the second reference signal VR-, and contributes to reducing the influence of the inter-symbol interference of the data signal DQ received by the data receiving circuit 100 on the data receiving circuit 100 based on the first reference signal VR+ and the second reference signal VR-, thereby further improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102.

[0074] In some embodiments, referring to FIGS. 6 and 7, the first current source 1111 may include a first PMOS field effect transistor MP1 connected between the power supply node Vcc and the fifth node net5 and having a gate receiving the first sampling clock signal clkN1, and the second current source 1112 may include a second PMOS field effect transistor MP2 connected between the power supply node Vcc and the sixth node net6 and having a gate receiving the second sampling clock signal clkN2.

[0075] Thus, when the first sampling clock signal clkN1 is at a low level, the gate of the first PMOS field-effect transistor MP1 receives the first sampling clock signal clkN1 and conducts, supplying current to the fifth node net5, putting the first comparison unit 1112 into an operating state, i.e., performing a first comparison on the received data signal DQ and the first reference signal VR+, and at the same time, the enable signal EnDfe is at a high level, the complementary enable signal EnDfeN is at a low level, the first feedback signal fbp is at a high level, and the first complementary feedback signal fbpN is at a low level. The first enable unit 1411 blocks the first node net1 and the second node net2. When the second sampling clock signal clkN2 is at a low level, the gate of the second PMOS field-effect transistor MP2 receives the second sampling clock signal clkN2 and conducts, supplying current to the sixth node net6, putting the second comparison unit 1212 into an operating state, performing a second comparison on the received data signal DQ and the second reference signal VR-, and at the same time, the enable signal EnDfe is at a high level, the complementary enable signal EnDfeN is at a low level, the second feedback signal fbn is at a high level, and the second complementary feedback signal fbnN is at a low level. The second enable unit 1412 blocks the third node net3 and the fourth node net4.

[0076] In one example, when the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk and it is necessary to reduce the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is in the first level value period, i.e., at a high level. The phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk. Then, at this time, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2. The first current source 1111 supplies current to the fifth node net5 so that the first comparison unit 1112 can be prepared to perform the first comparison, and the second current source 1211 supplies current to the sixth node net6 so that the second comparison unit 1212To enable the second comparison to be performed. At this time, the enable signal EnDfe is at a high level, the complementary enable signal EnDfeN is at a low level, and when the first feedback signal fbp is at a high level and the first complementary feedback signal fbpN is at a low level, the first enable unit 1411 cuts off the first node net1 and the second node net2, and the first comparison unit 1112 Performs the first comparison. At this time, the second feedback signal fbn is at a low level, and the second complementary feedback signal fbnN is at a high level. The second enable unit 1412 is connected to the third node net3 and the fourth node net4, and the second comparison unit 1212 Cannot perform the second comparison. When the first feedback signal fbp is at a low level and the first complementary feedback signal fbpN is at a high level, the first enable unit 1411 is connected to the first node net1 and the second node net2, and the first comparison unit 1112 Cannot perform the first comparison. At this time, the second feedback signal fbn is at a high level, and the second complementary feedback signal fbnN is at a low level. The second enable unit 1412 cuts off the third node net3 and the fourth node net4, and the second comparison unit 1212 Performs the second comparison.

[0077] Also, when there is no need to consider the influence on the symbol interference data receiving circuit 100, the enable signal EnDfe is in the second level value period, that is, at a low level. The second sampling clock signal clkN2 is a logic high level signal. The second PMOS field effect transistor MP2 is always cut off, making the current in the second comparison unit 1212 almost 0, thereby reducing the power consumption of the data receiving circuit 100. And at this time, the second comparison unit 1212 cannot perform the second comparison and cannot output a valid second signal pair. At this time, the first sampling clock signal clkN1 is a clock signal, and the first PMOS field effect transistor MP1 is turned on in response to the clock signal, thereby causing the first comparison unit 1112 to perform the first comparison, thereby outputting a valid first signal pair and enabling the entire data receiving circuit 100 to operate normally.

[0078] In some embodiments, referring continuously to FIGS. 6 and 7, the first comparison unit 1112 is connected between the first node net1 and the fifth node net5, and includes a third PMOS field effect transistor MP3 whose gate receives the data signal DQ, and is connected to MP4, and is connected between the second node net2 and the fifth node net5, and may include a fourth PMOS field effect transistor whose gate receives the first reference signal VR+. The second comparison unit 1212 may be connected between the third node net3 and the sixth node net6, and includes a fifth PMOS field effect transistor MP5 whose gate receives the data signal DQ, and is connected between the fourth node net4 and the sixth node net6, and may include a sixth PMOS field effect transistor whose gate receives the second reference signal VR-.

[0079] For the first comparison unit 1112, the changes in the level values of the data signal DQ and the first reference signal VR+ are not synchronized, the conduction time of the third PMOS field effect transistor MP3 that receives the data signal DQ is different from the conduction time of the fourth PMOS field effect transistor MP4 that receives the first reference signal VR+, and at the same time, the conduction degree of the third PMOS field effect transistor MP3 is different from the conduction degree of the fourth PMOS field effect transistor MP4. As can be understood, after the conduction degree of the third PMOS field effect transistor MP3 is different from the conduction degree of the fourth PMOS field effect transistor MP4, the current shunting capabilities at the fifth node net5 by the third PMOS field effect transistor MP3 and the fourth PMOS field effect transistor MP4 are also different, so that the voltage at the first node net1 is different from the voltage at the second node net2, contributing to outputting a first signal pair with a relatively large difference in the signal level values of the first signal Sn+ and the second signal Sp+.

[0080] For the second comparison unit 1212, the changes in the level values of the data signal DQ and the second reference signal VR- are not synchronized, the conduction time of the fifth PMOS field-effect transistor MP5 that receives the data signal DQ is different from the conduction time of the sixth PMOS field-effect transistor MP6 that receives the second reference signal VR-, and the conduction degree of the fifth PMOS field-effect transistor MP5 is different from the conduction degree of the sixth PMOS field-effect transistor MP6 at the same time. As can be understood, after the conduction degree of the fifth PMOS field-effect transistor MP5 is different from the conduction degree of the sixth PMOS field-effect transistor MP6, the current shunting capabilities at the sixth node net6 by the fifth PMOS field-effect transistor MP5 and the sixth PMOS field-effect transistor MP6 are also different, so that the voltage at the third node net3 is different from the voltage at the fourth node net4, contributing to outputting a second signal pair with a relatively large difference in the signal level values of the third signal Sn- and the fourth signal Sp-.

[0081] In one example, what the first amplification module 101 performs is the first comparison. When the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the conductivity of the third PMOS field effect transistor MP3 is greater than the conductivity of the fourth PMOS field effect transistor MP4. In this way, more current at the fifth node net5 flows through the path where the third PMOS field effect transistor MP3 is located, and the current at the first node net1 becomes greater than the current at the second node net2. As a result, the level value of the first signal Sn+ output by the first node net1 becomes higher, and the level value of the second signal Sp+ output by the second node net2 becomes lower. In another example, what the first amplification module 101 performs is the second comparison. When the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the conductivity of the fifth PMOS field effect transistor MP5 is greater than the conductivity of the sixth PMOS field effect transistor MP6. In this way, more current at the sixth node net6 flows through the path where the fifth PMOS field effect transistor MP5 is located, and the current at the third node net3 becomes greater than the current at the fourth node net4. As a result, the level value of the third signal Sn- output by the third node net3 becomes higher, and the level value of the fourth signal Sp- output by the fourth node net4 becomes lower.

[0082] Similarly, when the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the conductivity of the third PMOS field effect transistor MP3 is smaller than the conductivity of the fourth PMOS field effect transistor MP4. The level value of the first signal Sn+ output by the first node net1 is low, and the level value of the second signal Sp+ output by the second node net2 is high. When the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the conductivity of the fifth PMOS field effect transistor MP5 is smaller than the conductivity of the sixth PMOS field effect transistor MP6. The level value of the third signal Sn- output by the third node net3 is low, and the level value of the fourth signal Sp- output by the fourth node net4 is high.

[0083] In some embodiments, still referring to FIGS. 6 and 7, the first reset unit 1113 may include a first NMOS field effect transistor MN1 connected between the first node net1 and the ground terminal and having a gate receiving the first sampling clock signal clkN1, and a second NMOS field effect transistor MN2 connected between the second node net2 and the ground terminal and having a gate receiving the first sampling clock signal clkN1. The second reset unit 1213 may include a third NMOS field effect transistor MN3 connected between the third node net3 and the ground terminal and having a gate receiving the second sampling clock signal clkN2, and a fourth NMOS field effect transistor MN4 connected between the fourth node net4 and the ground terminal and having a gate receiving the second sampling clock signal clkN2.

[0084] In one example, when the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk and it is necessary to reduce the influence on the data reception circuit of inter-symbol interference, the enable signal EnDfe is in the first level value period, and the phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk. At this time, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2, both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are at a low level, and when both the first PMOS field effect transistor MP1 and the second PMOS field effect transistor MP2 are conducting, all of the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the third NMOS field effect transistor MN3, and the fourth NMOS field effect transistor MN4 are cut off. At this time, control is performed to conduct one of the first enable unit 1411 and the second enable unit 1412 based on the feedback signal fb, thereby realizing that the first amplification module 101 selectively performs the first comparison or the second comparison. At the same time, the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 may be used as the load of the first comparison unit 1112, thereby increasing the amplification gain of the first comparison unit 1112, and the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 may be used as the load of the second comparison unit 1212, thereby increasing the amplification gain of the second comparison unit 1212.

[0085] When both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are at a high level, both the first PMOS field-effect transistor MP1 and the second PMOS field-effect transistor MP2 are turned off, and there is no current flowing through the first comparison unit 1112 and the second comparison unit 1212. At this time, all of the first NMOS field-effect transistor MN1, the second NMOS field-effect transistor MN2, the third NMOS field-effect transistor MN3, and the fourth NMOS field-effect transistor MN4 are turned on, thereby pulling down the voltages at the first node net1, the second node net2, the third node net3, and the fourth node net4 to realize the reset of the first node net1, the second node net2, the third node net3, and the fourth node net4, facilitating the subsequent data receiving circuit 100 to perform the next data receiving and processing.

[0086] Also, when there is no need to consider the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is in the second level value period, the second sampling clock signal clkN2 is a logic high level signal, the second PMOS field effect transistor MP2 is always cut off. At this time, both the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 are turned on, thereby pulling down and conducting the connection path between the third node net3 and the ground terminal, and conducting the connection path between the fourth node net4 and the ground terminal to realize the reset of the third node net3 and the fourth node net4. At this time, the current in the second comparison unit 1212 is almost 0, contributing to reducing the power consumption of the data receiving circuit 100. At this time, when the first sampling clock signal clkN1 is at a low level, the first PMOS field effect transistor MP1 is turned on, and both the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 are cut off, thereby ensuring that the first comparison circuit 111 performs the first comparison and outputs a valid first signal pair, so that the subsequent second amplification module 102 can fixedly receive the first signal pair. Or, when the first sampling clock signal clkN1 is at a high level, the first PMOS field effect transistor MP1 is cut off, and both the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 are turned on, thereby pulling down the voltages at the first node net1 and the second node net2 to realize the reset of the first node net1 and the second node net2, facilitating the subsequent data receiving circuit 100 to perform the next data receiving and processing.

[0087] In some embodiments, still referring to FIGS. 6 and 7, the clock generation circuit 151 may include a first NAND gate circuit 1511 having one input terminal receiving the original sampling clock signal clk, the other input terminal connected to the power supply node Vcc, and the output terminal outputting the first sampling clock signal clkN1.

[0088] As can be understood, the input terminal connected to the power supply node Vcc of the first NAND gate circuit 1511 receives a high level. At this time, when the original sampling clock signal clk received by the other input terminal of the first NAND gate circuit 1511 is at a high level, the first sampling clock signal clkN1 is at a low level, and when the original sampling clock signal clk received by the other input terminal of the first NAND gate circuit 1511 is at a low level, the first sampling clock signal clkN1 is at a high level. In this way, the phase of the first sampling clock signal clkN1 is reversed from the phase of the original sampling clock signal clk. Therefore, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2, and the first amplification module 101 can selectively perform the first comparison or the second comparison.

[0089] In some embodiments, still referring to FIGS. 6 and 7, the clock generation circuit 151 may include a second NAND gate circuit 1512 having one input terminal receiving the original sampling clock signal clk, the other input terminal receiving the enable signal EnDfe, and the output terminal outputting the second sampling clock signal clkN2.

[0090] As understood, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the influence of the inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a high level. When the original sampling clock signal clk is at a high level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is at a low level. At this time, the first sampling clock signal clkN1 is also at a low level. The first amplification module 101 selectively performs one of the first comparison or the second comparison that is more excellent based on the feedback signal fb. The subsequent second amplification module 102 receives a valid first signal pair or a valid second signal pair, and the other set of signal pairs is invalid, reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100. When the original sampling clock signal clk is at a low level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is at a high level. At this time, the first sampling clock signal clkN1 is also at a high level. Then, at this time, both the first comparison unit 1112 and the second comparison unit 1212 are in an inactive state. The first reset unit 1113 restores the level values at the first node net1 and the second node net2 to the initial values, and the second reset unit 1213 can restore the level values at the third node net3 and the fourth node net4 to the initial values, facilitating the subsequent data receiving circuit 100 to perform the next data reception and processing.

[0091] When there is no need to consider the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is at a low level. At this time, regardless of whether the original sampling clock signal clk is at a high level or a low level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is also at a high level. Therefore, regardless of whether the first sampling clock signal clkN1 is at a high level or a low level, that is, regardless of whether the first comparison unit 1112 performs the first comparison, the connection paths between the third node net3 and the ground terminal and between the fourth node net4 and the ground terminal in the second comparison circuit 121 are also conducted. At this time, the current in the second comparison circuit 121 is almost 0, and neither performs the second comparison.

[0092] In some embodiments, referring to FIG. 5, the second amplification module 102 is connected to the seventh node net7 and the eighth node net8, receives the first signal pair to perform a third comparison, and supplies signals to the seventh node net7 and the eighth node net8 respectively as a result of the third comparison. The first input unit 112 configured to perform such operations, the second input unit 122 connected to the seventh node net7 and the eighth node net8, receives the second signal pair to perform a fourth comparison, and supplies signals to the seventh node net7 and the eighth node net8 respectively as a result of the fourth comparison. The latch unit 132 connected to the seventh node net7 and the eighth node net8, amplifies and latches the signals of the seventh node net7 and the eighth node net8, and outputs the first output signal Vout and the second output signal VoutN through the first output node net9 and the second output node net10 respectively, may be provided.

[0093] As can be understood, when it is necessary to reduce the influence on the data receiving circuit of inter-symbol interference, the enable signal EnDfe is in the first level value period, and the first amplification module 101 selectively performs the first comparison and the second comparison based on the feedback signal fb. One of the output first signal pair and second signal pair is valid and the other is invalid. And at this time, what the conductive input unit receives is the valid signal pair. And the valid signal pair refers to a pair of signal pairs with a greater difference in the level value that can be output when the first comparison and the second comparison can be performed simultaneously, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. When it is not necessary to consider the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is in the second level value period, the first amplification module 101 fixedly outputs a valid first signal pair, the first input unit 112 is conducted or cut off in response to the valid first signal pair, and the signal pair received by the second input unit 122 is invalid and in a cut-off state, thereby reducing the power consumption of the data receiving circuit.

[0094] The latch unit 132 is for outputting a high-level signal to the first output node net9 and a low-level signal to the second output node net10 based on the signals of the seventh node net7 and the eighth node net8, or outputting a low-level signal to the first output node net9 and a high-level signal to the second output node net10.

[0095] In some embodiments, referring to FIG. 8, the first input unit 112 may include a fifth NMOS field effect transistor MN5 having a drain electrode connected to the seventh node net7, a source electrode connected to the ground terminal, and a gate receiving the first signal Sn+; and a sixth NMOS field effect transistor MN6 having a drain electrode connected to the eighth node net8, a source electrode connected to the ground terminal, and a gate receiving the second signal Sp+. The second input unit 122 may include a seventh NMOS field effect transistor MN7 having a drain electrode connected to the seventh node net7, a source electrode connected to the ground terminal, and a gate receiving the third signal Sn-; and an eighth NMOS field effect transistor MN8 having a drain electrode connected to the eighth node net8, a source electrode connected to the ground terminal, and a gate receiving the fourth signal Sp-.

[0096] In one example, when the first amplification module 101 performs the first comparison, if the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the level value of the first signal Sn+ is low, and the level value of the second signal Sp+ is high. Then, the conductivity of the sixth NMOS field effect transistor MN6 is greater than the conductivity of the fifth NMOS field effect transistor MN5, making the voltage at the eighth node net8 lower than the voltage at the seventh node net7. Similarly, if the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the level value of the first signal Sn+ is high, and the level value of the second signal Sp+ is low. The conductivity of the fifth NMOS field effect transistor MN5 is greater than the conductivity of the sixth NMOS field effect transistor MN6, making the voltage at the seventh node net7 lower than the voltage at the eighth node net8.

[0097] In another example, when the first amplification module 101 performs a second comparison, if the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the level value of the third signal Sn- is low, and the level value of the fourth signal Sp- is high. Then, the conductivity of the eighth NMOS field effect transistor MN8 is greater than the conductivity of the seventh NMOS field effect transistor MN7, and the voltage at the eighth node net8 is made smaller than the voltage at the seventh node net7. Similarly, if the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the level value of the third signal Sn- is high, the level value of the fourth signal Sp- is low, the conductivity of the seventh NMOS field effect transistor MN7 is greater than the conductivity of the eighth NMOS field effect transistor MN8, and the voltage at the seventh node net7 is made smaller than the voltage at the eighth node net8.

[0098] In some embodiments, still referring to FIG. 8, the latch unit 132 may include an eighth NMOS field effect transistor MN13 and a seventh PMOS field effect transistor MP7, where the gates of both the eighth NMOS field effect transistor MN13 and the seventh PMOS field effect transistor MP7 are connected to the second output node net10, the source electrode of the eighth NMOS field effect transistor MN13 is connected to the seventh node net7, the drain electrodes of both the eighth NMOS field effect transistor MN13 and the seventh PMOS field effect transistor MP7 are connected to the first output node net9, and the source electrode of the seventh PMOS field effect transistor MP7 is connected to the power supply node Vcc; and a fourteenth NMOS field effect transistor MN14 and an eighth PMOS field effect transistor MP8, where the gates of both the fourteenth NMOS field effect transistor MN14 and the eighth PMOS field effect transistor MP8 are connected to the first output node net9, the source electrode of the fourteenth NMOS field effect transistor MN14 is connected to the eighth node net8, the drain electrodes of both the fourteenth NMOS field effect transistor MN14 and the eighth PMOS field effect transistor MP8 are connected to the second output node net10, and the source electrode of the eighth PMOS field effect transistor MP8 is connected to the power supply node Vcc.

[0099] In one example, when the first amplification module 101 performs the first comparison, if the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the level value of the first signal Sn+ is low, and the level value of the second signal Sp+ is high. Then, the voltage at the eighth node net8 is smaller than the voltage at the seventh node net7, thereby making the conductivity of the 14th NMOS field effect transistor MN14 larger than the conductivity of the 13th NMOS field effect transistor MN13, and making the voltage at the second output node net10 smaller than the voltage at the first output node net9. Then, the conductivity of the 8th PMOS field effect transistor MP8 is smaller than the conductivity of the 7th PMOS field effect transistor MP7, and the latch unit 132 forms positive feedback amplification. Further, the first output signal Vout output by the first output node net9 is set to a high level, and the second output signal VoutN output by the second output node net10 is set to a low level. Similarly, when the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the voltage at the seventh node net7 is smaller than the voltage at the eighth node net8, the first output signal Vout output by the first output node net9 is at a low level, and the second output signal VoutN output by the second output node net10 is at a high level.

[0100] In another example, when the first amplification module 101 performs the second comparison, if the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the level value of the third signal Sn- is low, and the level value of the fourth signal Sp- is high. Then, the conductivity of the eighth NMOS field-effect transistor MN8 is greater than the conductivity of the seventh NMOS field-effect transistor MN7, reducing the voltage at the eighth node net8 below the voltage at the seventh node net7, thereby raising the first output signal Vout output by the first output node net9 to a high level and lowering the second output signal VoutN output by the second output node net10 to a low level. Similarly, if the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the level value of the third signal Sn- is high, and the level value of the fourth signal Sp- is low. At this time, the first output signal Vout output by the first output node net9 is at a low level, and the second output signal VoutN output by the second output node net10 is at a high level.

[0101] In some embodiments, referring to FIG. 5, the second amplification module 102 may further include a third reset unit 142 connected between the power supply node Vcc and the output terminal of the latch unit 132 and configured to reset the output terminal of the latch unit 132. In this way, after the data receiving circuit 100 completes receiving the data signal DQ, the first reference signal VR+, and the second reference signal VR- and outputting the first output signal Vout and the second output signal VoutN once, the third reset unit 142 can restore the level values at the first output node net9 and the second output node net10 to their initial values, facilitating the subsequent data receiving circuit 100 to receive and process the next data.

[0102] In some embodiments, referring to FIG. 8, the third reset unit 142 includes a thirteenth PMOS field-effect transistor MP13 connected between the first output node net9 and the power supply node Vcc and having a gate that receives the original sampling clock signal clk, and a fourteenth PMOS field-effect transistor MP14 connected between the second output node net10 and the power supply node Vcc and having a gate that receives the original sampling clock signal clk.

[0103] In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. Referring to FIGS. 7 and 8 together, when it is necessary to reduce the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a logic level of 1, the complementary enable signal EnDfeN is at a logic level of 0, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk, and when the original sampling clock signal clk is at a high level, both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are at a low level. Then, both the first PMOS field effect transistor MP1 and the second PMOS field effect transistor MP2 are turned on. At this time, one of the first enable unit 1411 and the second enable unit 1412 is turned on based on the feedback signal fb, so that the first amplification module 101 can output only one of the valid first signal pair and the valid second signal pair. For example, when the first feedback signal fbp is at a high level and the second feedback signal fbn is at a low level, the first comparison unit 121 can perform the first comparison, and the second comparison unit 122 cannot perform the second comparison. At this time, the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the third NMOS field effect transistor MN3, the fourth NMOS field effect transistor MN4, the 13th PMOS field effect transistor MP13, and the 14th PMOS field effect transistor MP14 are all cut off.

[0104] When the original sampling clock signal clk is at a low level, both the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are at a high level. Then, both the first PMOS field-effect transistor MP1 and the second PMOS field-effect transistor MP2 are cut off. At this time, the first NMOS field-effect transistor MN1, the second NMOS field-effect transistor MN2, the third NMOS field-effect transistor MN3, and the fourth NMOS field-effect transistor MN4 are all turned on, thereby pulling down the voltages at the first node net1, the second node net2, the third node net3, and the fourth node net4 to realize the reset of the first node net1, the second node net2, the third node net3, and the fourth node net4. The 13th PMOS field-effect transistor MP13 and the 14th PMOS field-effect transistor MP14 are also turned on, thereby pulling up the voltages at the first output node net9 and the second output node net10 to realize the reset of the first output node net9 and the second output node net10.

[0105] When there is no need to consider the influence on the inter-symbol interference data receiving circuit 100, the enable signal EnDfe is at a logic level 0, and the complementary enable signal EnDfeN is at a logic level 1. At this time, regardless of whether the original sampling clock signal clk is at a high level or a low level, the second sampling clock signal clkN2 is always at a high level. Then, the second PMOS field-effect transistor MP2 is always cut off, thereby reducing the current in the second comparison circuit 121, and thereby reducing the power consumption of the data receiving circuit 100.

[0106] Hereinafter, with reference to FIGS. 6, 8, and Table 1, the specific operating principle of the data receiving circuit 100 according to an embodiment of the present disclosure will be described in detail.

[0107] In one example, when a plurality of data receiving circuits 100 are cascade-connected, the first output signal Vout output from the first output node net9 of the previous-stage data receiving circuit 100 is used as the first feedback signal fbp of the subsequent-stage data receiving circuit 100, and the second output signal VoutN output from the second output node net10 of the previous-stage data receiving circuit 100 is used as the second feedback signal fbn of the subsequent-stage data receiving circuit 100.

[0108] Hereinafter, a case where the level value of the received first reference signal VR+ is larger than the level value of the second reference signal VR- will be described as an example. When the data signal DQ is at the logic level 1, it indicates that the level value of the data signal DQ is larger than the level value of the first reference signal VR+. When the data signal DQ is at the logic level 0, it indicates that the level value of the data signal DQ is smaller than the level value of the second reference signal VR-. In Table 1, 1 indicates a high level and 0 indicates a low level.

[0109] When it is necessary to consider the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a high level, and the complementary enable signal EnDfeN is at a low level. At this time, the ninth PMOS field-effect transistor MP9 and the eleventh PMOS field-effect transistor MP11 are turned on, the tenth PMOS field-effect transistor MP10 is turned on or off in response to the first feedback signal fbp, and the twelfth PMOS field-effect transistor MP12 is turned on or off in response to the second feedback signal fbn.

[0110] Referring to Table 1, when the data signal DQ1 received by the front-stage data receiving circuit 100 is at logic level 1, the first output signal Vout output by the front-stage data receiving circuit 100, i.e., the first feedback signal fbp of the rear-stage data receiving circuit 100, is at a high level, and the second output signal VoutN output by the front-stage data receiving circuit 100, i.e., the second feedback signal fbn of the rear-stage data receiving circuit 100, is at a low level. At this time, the gate of the 10th PMOS field-effect transistor MP10 is blocked by receiving the first feedback signal fbp, the gate of the 12th PMOS field-effect transistor MP12 is conducted by receiving the second feedback signal fbn, the first amplification module 101 performs a first comparison, and outputs the first signal Sn+ and the second signal Sp+ via the first node net1 and the second node net2. The first input unit 112 is for supplying signals to the seventh node net7 and the eighth node net8 by performing a third comparison on the first signal Sn+ and the second signal Sp+, and there is no current flowing through the second input unit 122.

[0111] When the data signal DQ1 received by the front-stage data receiving circuit 100 is at logic level 1, the data signal DQ2 received by the rear-stage data receiving circuit 100 has the following two situations respectively.

[0112] Situation 1 Referring to Table 1, when the data signal DQ2 received by the subsequent data receiving circuit 100 is at logic level 0, if the difference from the level value of the data signal DQ1 received by the previous data receiving circuit 100 is relatively large, relatively large inter-symbol interference occurs. At this time, the first amplification module 101 in the subsequent data receiving circuit 100 performs a first comparison, outputs a first signal Sn+ and a second signal Sp+, and conducts the first input unit 112, that is, the second amplification module 102 in the subsequent data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+. At this time, in the subsequent data receiving circuit 100, the data signal DQ2 is at logic level 0, and the voltage difference between the data signal DQ2 and the first reference signal VR+ is larger than the voltage difference between the data signal DQ2 and the second reference signal VR-. If a second comparison can be performed at this time, the difference in the level values of the signals in the valid first signal pair obtained by performing the first comparison is larger than the difference in the level values of the signals in the valid second signal pair obtained by performing the second comparison. At this time, the second amplification module 102 receiving the valid first signal pair contributes to outputting a first output signal Vout and a second output signal VoutN with higher accuracy, thereby realizing the purpose of reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100, and not performing the second comparison at this time contributes to reducing the power consumption of the data receiving circuit 100.

[0113] Situation 2 Referring to Table 1, when the data signal DQ2 received by the subsequent data receiving circuit 100 is at logic level 1, the difference from the level value of the data signal DQ1 received by the previous data receiving circuit 100 is relatively small, relatively small inter-symbol interference occurs, or no inter-symbol interference occurs. At this time, the first amplification module 101 in the subsequent data receiving circuit 100 performs a first comparison, outputs a first signal Sn+ and a second signal Sp+, and conducts the first input unit 112, that is, the second amplification module 102 in the subsequent data receiving circuit 100 receives the first signal Sn+ and the second signal Sp+.

[0114] Referring to Table 1, when the data signal DQ1 received by the front-stage data receiving circuit 100 is at the logic level 0, the first output signal Vout output by the front-stage data receiving circuit 100, that is, the first feedback signal fbp of the rear-stage data receiving circuit 100, is at a low level, and the second output signal VoutN output by the front-stage data receiving circuit 100, that is, the second feedback signal fbn of the rear-stage data receiving circuit 100, is at a high level. At this time, the gate of the 10th PMOS field-effect transistor MP10 is turned on by receiving the first feedback signal fbp, the gate of the 12th PMOS field-effect transistor MP12 is cut off by receiving the second feedback signal fbn, the first amplification module 101 performs a second comparison, and outputs the third signal Sn- and the fourth signal Sp- via the third node net3 and the fourth node net4. The second input unit 122 is for supplying signals to the seventh node net7 and the eighth node net8 by performing a fourth comparison on the third signal Sn- and the fourth signal Sp-, and there is no current flowing through the first input unit 112.

[0115] When the data signal DQ1 received by the front-stage data receiving circuit 100 is at the logic level 0, the data signal DQ2 received by the rear-stage data receiving circuit 100 has the following two situations respectively.

[0116] Situation 3 Referring to Table 1, when the data signal DQ2 received by the rear-stage data receiving circuit 100 is at the logic level 0 when the rear-stage data receiving circuit 100 is at the logic level 0, the difference from the level value of the data signal DQ1 received by the front-stage data receiving circuit 100 is relatively small, relatively small inter-symbol interference occurs, or no inter-symbol interference occurs. At this time, the first amplification module 101 in the rear-stage data receiving circuit 100 performs a second comparison, outputs the third signal Sn- and the fourth signal Sp-, and conducts the second input unit 122, that is, the second amplification module 102 in the rear-stage data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-.

[0117] Situation 4 Referring to Table 1, when the data signal DQ2 received by the subsequent data receiving circuit 100 is at logic level 1, the difference from the level value of the data signal DQ1 received by the previous data receiving circuit 100 is relatively large, and relatively large inter-symbol interference occurs. At this time, the first amplification module 101 in the subsequent data receiving circuit 100 performs a second comparison, outputs the third signal Sn- and the fourth signal Sp-, and conducts the second input unit 122, that is, the second amplification module 102 in the subsequent data receiving circuit 100 receives the third signal Sn- and the fourth signal Sp-. At this time, in the subsequent data receiving circuit 100, the data signal DQ2 is at logic level 1, and the voltage difference between the data signal DQ2 and the second reference signal VR- is larger than the voltage difference between the data signal DQ2 and the first reference signal VR+. When the first comparison can be performed at this time, the difference in the level values of the signals in the effective second signal pair obtained by performing the second comparison is larger than the difference in the level values of the signals in the effective first signal pair obtained by performing the first comparison. At this time, the fact that the second amplification module 102 receives the effective second signal pair contributes to outputting a first output signal Vout and a second output signal VoutN with higher accuracy, thereby realizing the purpose of reducing the influence of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100, and not performing the first comparison at this time contributes to reducing the power consumption of the data receiving circuit 100.

[0118]

Table 1

[0119] When there is no need to consider the influence on the data receiving circuit 100 of inter-symbol interference, the enable signal EnDfe is at a low level, and the complementary enable signal EnDfeN is at a high level. At this time, both the ninth PMOS field-effect transistor MP9 and the eleventh PMOS field-effect transistor MP11 are cut off, the first amplification module 101 performs a fixed first comparison, outputs the first signal Sn+ and the second signal Sp+, and the first input unit 112 is conducted or cut off in response to the first signal pair. At this time, both the third signal Sn- and the fourth signal Sp- output by the second comparison circuit 121 are logic low-level signals, and the second input unit 122 responsive to the third signal Sn- and the fourth signal Sp- is cut off.

[0120] In addition, in the above description of the high level and the low level, the high level may be a level value equal to or higher than the power supply voltage, and the low level may be a level value equal to or lower than the ground voltage. Moreover, the high level and the low level are relative terms, and the specific level value ranges included in the high level and the low level may be determined based on a specific device. For example, in the case of an NMOS field-effect transistor, the high level refers to the level value range of the gate voltage that can conduct the NMOS field-effect transistor, and the low level refers to the level value range of the gate voltage that can cut off the NMOS field-effect transistor. In the case of a PMOS field-effect transistor, the low level refers to the level value range of the gate voltage that can conduct the PMOS field-effect transistor, and the high level refers to the level value range of the gate voltage that can cut off the PMOS field-effect transistor. Also, the high level may be the logic level 1 in the above description, and the low level may be the logic level 0 in the above description.

[0121] In short, further control of the first amplification module 101 is realized by using the enable signal EnDfe and the feedback signal fb, thereby selecting whether to consider the influence of inter-symbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the first level value period, and the first amplification module 101 selects whether to perform the first comparison or the second comparison based on the feedback signal fb in response to the sampling clock signal clkN, enables one of the output first signal pair and second signal pair, disables the other, and further increases the difference in the signal level values of the effective signal pair, thereby ensuring that the second amplification module 102 receives a pair of differential signals with a relatively large difference in signal level values. When it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, and the first amplification module 101 only performs the first comparison in response to the sampling clock signal clkN, fixes and outputs the effective first signal pair, thereby realizing the effect of improving the receiving performance of the data receiving circuit 100 and reducing the power consumption of the data receiving circuit 100.

[0122] Another embodiment of the present disclosure further provides a data receiving system, and the data receiving system according to another embodiment of the present disclosure will be described in detail below with reference to the drawings. FIG. 2 is a functional block diagram of a data receiving system according to another embodiment of the present disclosure.

[0123] Referring to FIG. 2, the data receiving system includes a plurality of data transmission circuits 120 connected in cascade. Each data transmission circuit 120 includes the data receiving circuit 100 described in an embodiment of the present disclosure and a latch circuit 110 connected to the data receiving circuit 100. The output signal of the previous-stage data transmission circuit 120 is used as the feedback signal fb of the subsequent-stage data transmission circuit 120, and the output signal of the last-stage data transmission circuit 120 is used as the feedback signal fb of the first-stage data transmission circuit 120.

[0124] The latch circuit 110 is provided in a one-to-one correspondence with the data reception circuit 100, and the latch circuit 110 is for latching and outputting a signal output by the data reception circuit 100 corresponding to the latch circuit 110.

[0125] In some embodiments, the data reception circuit 100 receives data in response to a sampling clock signal, and the data reception system includes four cascaded data reception circuits 100, and the phase difference of the sampling clock signals clkN of adjacent-stage data reception circuits 100 is 90°. Thus, the period of the sampling clock signal clkN is twice the period of the data signal DQ received by the data port, contributing to saving clock wiring and power consumption.

[0126] Note that, taking as an example the case where the data reception system includes four cascaded data reception circuits 100 in FIG. 2 and the phase difference of the sampling clock signals of adjacent-stage data reception circuits 100 is 90°, in actual applications, the number of cascaded data reception circuits 100 included in the data reception system is not limited, and the phase difference of the sampling clock signals of adjacent-stage data reception circuits 100 may be reasonably set based on the number of cascaded data reception circuits 100.

[0127] In some embodiments, the first output signal Vout and the second output signal VoutN output by the second amplification module 102 of the previous-stage data reception circuit 100 are used as the feedback signal fb of the subsequent-stage data reception circuit 100. Thus, the output of the data reception circuit 100 is directly transmitted to the subsequent-stage data transmission circuit 120 without having to pass through the latch circuit 110, contributing to reducing the data transmission delay, or the signal output by the previous-stage latch circuit 110 is used as the feedback signal fb of the subsequent-stage data reception circuit 100.

[0128] In short, the data receiving system according to another embodiment of the present disclosure can utilize the enable signal EnDfe and the feedback signal fb to achieve further control over the first amplification module 101, thereby selecting whether to consider the influence of inter-symbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the first level value period, and the first amplification module 101 selects whether to perform a first comparison or a second comparison based on the feedback signal fb in response to the sampling clock signal clkN, enables one of the output first signal pair and the second signal pair, disables the other, and further increases the difference in the signal level values of the enabled signal pair, thereby ensuring that the second amplification module 102 receives a pair of differential signals with a relatively large difference in signal level values, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102, and thus contributing to improving the receiving performance of the data receiving system. When it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, and the first amplification module 101 performs only the first comparison in response to the sampling clock signal clkN, fixes and outputs the valid first signal pair, thereby reducing the power consumption of the data receiving system.

[0129] Another embodiment of the present disclosure further provides a memory device, comprising a plurality of data ports and a plurality of data receiving systems according to any one of the above items, each corresponding to one of the data ports. Thus, when it is necessary to reduce the influence of inter-symbol interference on the memory device, each data port in the memory device can flexibly adjust the data signal DQ received by the data receiving system, and improve the adjustment ability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the memory device. When it is not necessary to consider the influence of inter-symbol interference on the memory device, the enable signal EnDfe is in the second level value period, and the first amplification module 101 only performs the first comparison in response to the sampling clock signal clkN, fixes and outputs a valid first signal pair, thereby reducing the power consumption of the memory device.

[0130] As will be understood by those skilled in the art, each of the above embodiments is a specific example for implementing the present disclosure. However, in actual applications, various changes can be made in form and details without departing from the gist and scope of the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the gist and scope of the embodiments of the present disclosure. Therefore, the patent scope of the embodiments of the present disclosure should be subject to the scope limited by the claims.

Claims

1. A data reception circuit, which receives an enable signal, a feedback signal, a data signal, a first reference signal, and a second reference signal, and in response to a sampling clock signal and based on the feedback signal, selects the data signal and the first reference signal to perform a first comparison to output a first signal pair as a result of the first comparison, or selects the data signal and the second reference signal to perform a second comparison to output a second signal pair as a result of the second comparison while the enable signal has a first level value, and is configured to perform the first comparison in response to the sampling clock signal to output the first signal pair while the enable signal has a second level value, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal, and a first amplification module; a second amplification module configured to receive an output signal of the first amplification module as an input signal pair, perform an amplification process on a voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process; The first amplification module includes a first node, a second node, a third node, and a fourth node for outputting the first signal, the second signal, the third signal, and the fourth signal respectively in response to the sampling clock signal, and an amplification unit configured to receive the data signal, the first reference signal, and the second reference signal; a decision balance enable unit connected between the first node and the second node and between the third node and the fourth node, receiving the enable signal and the feedback signal, configured to conduct a connection path between the first node and the second node based on the feedback signal while the enable signal has the first level value, or conduct a connection path between the third node and the fourth node, and configured to block the connection path between the first node and the second node and block the connection path between the third node and the fourth node while the enable signal has the second level value; the feedback signal includes a differential first feedback signal and a second feedback signal, and the decision balance enable unit includes a first enable unit configured to connect the first node and the second node by conducting in response to the enable signal and the first feedback signal; A second enable unit configured to connect the third node and the fourth node by conducting in response to the enable signal and the second feedback signal; One of the first enable unit and the second enable unit is conducted while the enable signal has a first level value, and both the first enable unit and the second enable unit are cut off while the enable signal has a second level value; The sampling clock signal includes a first sampling clock signal and a second sampling clock signal, and the amplification unit; A first comparison circuit having the first node and the second node, configured to receive the data signal and the first reference signal, and perform the first comparison in response to the first sampling clock signal; A clock generation circuit configured to receive the enable signal and the original sampling clock signal and output the second sampling clock signal, wherein the phase of the second sampling clock signal is opposite to the phase of the original sampling clock signal while the enable signal has the first level value, and the second sampling clock signal is a logic high level signal while the enable signal has the second level value; A data receiving circuit comprising: a second comparison circuit having the third node and the fourth node, configured to receive the data signal and the second reference signal, perform the second comparison in response to the second sampling clock signal while the enable signal has the first level value, conduct a connection path between the third node and the ground terminal, and conduct a connection path between the fourth node and the ground terminal while the enable signal has the second level value. **Claim 2** The first enable unit; Comprising a ninth PMOS field effect transistor and a tenth PMOS field effect transistor, one end of the ninth PMOS field effect transistor is connected to the first node, the gate receives a complementary enable signal, the other end of the ninth PMOS field effect transistor is connected to one end of the tenth PMOS field effect transistor, the other end of the tenth PMOS field effect transistor is connected to the second node, the gate receives the first feedback signal, and the level of the complementary enable signal is opposite to the level of the enable signal; A ninth NMOS field effect transistor and a tenth NMOS field effect transistor are provided. One end of the ninth NMOS field effect transistor is connected to the first node, the gate receives the enable signal, the other end of the ninth NMOS field effect transistor is connected to one end of the tenth NMOS field effect transistor, the other end of the tenth NMOS field effect transistor is connected to the second node, the gate receives a first complementary feedback signal, and the first complementary feedback signal is opposite to the level of the first feedback signal. The second enable unit A tenth PMOS field effect transistor and an eleventh PMOS field effect transistor are provided. One end of the tenth PMOS field effect transistor is connected to the third node, the gate receives a complementary enable signal, the other end of the tenth PMOS field effect transistor is connected to one end of the eleventh PMOS field effect transistor, the other end of the eleventh PMOS field effect transistor is connected to the fourth node, the gate receives the second feedback signal, and the level of the complementary enable signal is opposite to the level of the enable signal. A tenth NMOS field effect transistor and an eleventh NMOS field effect transistor are provided. One end of the tenth NMOS field effect transistor is connected to the third node, the gate receives the enable signal, the other end of the tenth NMOS field effect transistor is connected to one end of the eleventh NMOS field effect transistor, the other end of the eleventh NMOS field effect transistor is connected to the fourth node, the gate receives a second complementary feedback signal, and the second complementary feedback signal is opposite to the level of the second feedback signal. The data receiving circuit according to claim 1.

3. The first comparison circuit A first current source connected between the power supply node and the fifth node and configured to supply current to the fifth node in response to a first sampling clock signal. A first comparison unit connected to the first node, the second node and the fifth node, receiving the data signal and the first reference signal, performing the first comparison when the first current source supplies current to the fifth node, and outputting the first signal and the second signal. A first reset unit connected to the first node and the second node and configured to reset the first node and the second node in response to the first sampling clock signal; and the second comparison circuit, A second current source connected between the power supply node and the sixth node and configured to supply current to the sixth node in response to the second sampling clock signal; A second comparison unit connected to the third node, the fourth node, and the sixth node, receiving the data signal and the second reference signal, performing the second comparison when the second current source supplies current to the sixth node, and outputting the third signal and the fourth signal; The data receiving circuit according to claim 1, further comprising a second reset unit connected between the third node and the fourth node and configured to reset the third node and the fourth node in response to the second sampling clock signal.

4. The first current source Is connected between the power supply node and the fifth node and includes a first PMOS field effect transistor whose gate receives the first sampling clock signal; The second current source Is connected between the power supply node and the sixth node and includes a second PMOS field effect transistor whose gate receives the second sampling clock signal; The first comparison unit Includes a third PMOS field effect transistor connected between the first node and the fifth node and having a gate receiving the data signal; And a fourth PMOS field effect transistor connected between the second node and the fifth node and having a gate receiving the first reference signal. The second comparison unit Includes a fifth PMOS field effect transistor connected between the third node and the sixth node and having a gate receiving the data signal; And a sixth PMOS field effect transistor connected between the fourth node and the sixth node and having a gate receiving the second reference signal. The first reset unit Includes a first NMOS field effect transistor connected between the first node and the ground terminal and having a gate receiving the first sampling clock signal; And a second NMOS field effect transistor connected between the second node and the ground terminal and having a gate receiving the first sampling clock signal. The second reset unit A third NMOS field effect transistor connected between the third node and the ground terminal and having a gate receiving the second sampling clock signal; A fourth NMOS field effect transistor connected between the fourth node and the ground terminal and having a gate receiving the second sampling clock signal, the data receiving circuit according to claim 3. **Claim 5** The clock generation circuit Comprises a first NAND gate circuit having one input terminal receiving the original sampling clock signal, the other input terminal connected to a power supply node, and an output terminal outputting the first sampling clock signal; The data receiving circuit according to claim 1, comprising a second NAND gate circuit having one input terminal receiving the original sampling clock signal, the other input terminal receiving the enable signal, and an output terminal outputting the second sampling clock signal. **Claim 6** The second amplification module A first input unit connected to a seventh node and an eighth node, receiving the first signal pair to perform a third comparison, and configured to supply signals to the seventh node and the eighth node respectively as a result of the third comparison; A second input unit connected to the seventh node and the eighth node, receiving the second signal pair to perform a fourth comparison, and configured to supply signals to the seventh node and the eighth node respectively as a result of the fourth comparison; A latch unit connected to the seventh node and the eighth node, amplifying and latching the signals of the seventh node and the eighth node, and configured to output the first output signal and the second output signal through a first output node and a second output node respectively; A third reset unit connected between a power supply node and an output terminal of the latch unit and configured to reset the output terminal of the latch unit, the data receiving circuit according to claim 1. **Claim 7** The first input unit A fifth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to the ground terminal, and a gate receiving the first signal; A sixth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to the ground terminal, and a gate receiving the second signal, and The second input unit A seventh NMOS field-effect transistor in which a drain electrode is connected to the seventh node, a source electrode is connected to a ground terminal, and a gate receives the third signal, An eighth NMOS field-effect transistor in which a drain electrode is connected to the eighth node, a source electrode is connected to a ground terminal, and a gate receives the fourth signal, and the latch unit includes a thirteenth NMOS field-effect transistor and a seventh PMOS field-effect transistor in which the gates of both the thirteenth NMOS field-effect transistor and the seventh PMOS field-effect transistor are connected to the second output node, the source electrode of the thirteenth NMOS field-effect transistor is connected to the seventh node, the drain electrodes of both the thirteenth NMOS field-effect transistor and the seventh PMOS field-effect transistor are connected to the first output node, and the source electrode of the seventh PMOS field-effect transistor is connected to a power supply node, a fourteenth NMOS field-effect transistor and an eighth PMOS field-effect transistor in which the gates of both the fourteenth NMOS field-effect transistor and the eighth PMOS field-effect transistor are connected to the first output node, the source electrode of the fourteenth NMOS field-effect transistor is connected to the eighth node, the drain electrodes of both the fourteenth NMOS field-effect transistor and the eighth PMOS field-effect transistor are connected to the second output node, and the source electrode of the eighth PMOS field-effect transistor is connected to the power supply node, the third reset unit includes a thirteenth PMOS field-effect transistor connected between the first output node and the power supply node and having a gate that receives an original sampling clock signal, a fourteenth PMOS field-effect transistor connected between the second output node and the power supply node and having a gate that receives the original sampling clock signal, the data reception circuit according to claim 6. **Claim 8** A data reception system comprising a plurality of data transmission circuits connected in cascade, each of the data transmission circuits including the data reception circuit according to claim 1 and a latch circuit connected to the data reception circuit, wherein an output signal of the previous-stage data transmission circuit is used as the feedback signal of the subsequent-stage data transmission circuit. A data receiving system in which an output signal of the data transmission circuit at the final stage is a feedback signal of the data transmission circuit at the first stage. **Claim 9** The data receiving system according to claim 8, wherein the data receiving circuit receives data in response to a sampling clock signal, and the data receiving system includes four data transmission circuits connected in cascade, and a phase difference of the sampling clock signals of the data receiving circuits in adjacent stages is 90°. **Claim 10** The data receiving system according to claim 8, wherein the first output signal and the second output signal output by the second amplification module of the data receiving circuit in the previous stage are feedback signals of the data receiving circuit in the subsequent stage, or a signal output by the latch circuit in the previous stage is a feedback signal of the data receiving circuit in the subsequent stage. **Claim 11** A storage device, comprising: a plurality of data ports; a plurality of data receiving systems according to claim 8, each corresponding to one of the data ports.

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