Starting the codes simultaneously

Abstract

Apparatus, systems, and techniques for causing one or more software modules to be executed by a processor simultaneously. In at least one embodiment, the one or more processors execute one or more software drivers to cause two or more graphics kernels to be executed simultaneously. In at least one embodiment, causing the two or more graphics kernels to be executed simultaneously includes performing operations to prepare the two or more graphics kernels to be launched on one or more graphics processing cores. In at least one embodiment, the one or more software drivers are to receive instructions from an application programming interface (API) to prepare the two or more graphics kernels to be executed simultaneously.

Description

Technical Field

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 175,211, filed Apr. 15, 2021, titled "ASYNCHRONOUS WORK SUBMISSION TRACKING WITH FINE-GRAINED SERIALIZATION", the entire content of which is incorporated herein by reference (Attorney Docket No. 0112912-277PR0).

[0002] At least one embodiment relates to processing resources used to implement one or more software drivers to simultaneously cause two or more software modules to be executed by a processor. For example, it includes performing operations simultaneously to prepare two or more graphics kernels such that a software driver for causing two or more graphics kernels to be executed simultaneously is launched on one or more graphics processing cores.

Background Art

[0003] Various improvements in the field of computing have generally enabled applications to be executed faster and more efficiently, but inefficiencies can still negatively impact performance. As one example, the ability to parallelize various computational tasks is affected by various system limitations, such as operations that are generally performed serially, and can cause delays while one operation is being performed before another operation begins.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one of ordinary skill in the art that the inventive concept may be practiced without one or more of these specific details.

[0006] In at least one embodiment, a software driver for a GPU can receive a plurality of requests to cause a workload to be executed on one or more GPUs. In at least one embodiment, a plurality of CPUs or a plurality of CPU cores submit a plurality of requests to launch a kernel on the GPU. In at least one embodiment, a CPU core also executes one or more software drivers. For example, a multi-core CPU calls or invokes an application programming interface (API) to launch (e.g., prepare) several kernels on a single GPU. In at least one embodiment, the driver receives these requests and performs operations to launch the kernel, such as copying data from CPU memory to GPU memory for executing the kernel. In at least one embodiment, these operations are continuously performed in the order in which the kernel is instructed to be launched, and this sequential approach is a bottleneck because launching a kernel does not necessarily require all CPU resources, but the operations to launch one kernel are blocked until the operations to launch another kernel are completed.

[0007] In at least one embodiment, preparing the graphics kernel to be launched involves performing operations that need to be carried out so that one or more GPUs can execute the kernel at runtime (e.g., provide data, verify that the kernel is correctly configured). In at least one embodiment, the graphics kernel is a kernel to be implemented by a graphics processor and may not necessarily involve operations with computer graphics, but can be a kernel for artificial intelligence operations (e.g., deep learning, neural networks), fifth generation (5G) new radio network operations, and other applications.

[0008] In at least one embodiment, to reduce and improve bottlenecks, reduce latency, and increase throughput, one or more circuits, processors, or systems are for performing operations to start two or more kernels in parallel (e.g., simultaneously). In at least one embodiment, when two or more kernels are to be started on a GPU, a software driver for the GPU monitors the performance of operations to start the kernels and identifies operations that can be performed in parallel. In at least one embodiment, when the operations to start a first kernel can be run in parallel with the operations to start a second kernel, the driver performs those operations to be performed in parallel. In at least one embodiment, when the operations to start a second kernel cannot be performed in parallel with the operations to start a first kernel, the driver causes the performance of the operations to start the second kernel to be blocked, interrupted, or synchronized such that the operations are performed in the order necessary to perform the operations. Some examples of operations that can be performed simultaneously when preparing a kernel to start include determining the block dimension and grid dimension for the kernel, storing the arguments that will be used by the kernel, verifying that the kernel is correctly configured, and encoding the kernel in code for runtime execution of the kernel. In at least one embodiment, a processor includes one or more circuits for causing such operations to start two or more computer programs to be performed in parallel (e.g., simultaneously). In at least one embodiment, one or more circuits cause one or more software modules to be performed simultaneously by a processor. In at least one embodiment, a software module includes a component or part of a program that includes one or more routines. In at least one embodiment, a software module includes operations for performing routines for an application, such as virtual machine operations or virtual system operations (e.g., for setting up or preparing a virtual machine to start).In at least one embodiment, the software module includes operations for a neural network, a fast Fourier transform, or a software graphics module.

[0009] In at least one embodiment, a software driver for a GPU or multiple GPUs has a tracking structure for monitoring the progress of operations that can be performed in parallel, and the tracking structure includes semaphores and value thresholds for monitoring the progress of different operations. In at least one embodiment, the tracking structure is updated sequentially and can function as a thread that blocks other threads while it is being updated. In at least one embodiment, by including tracking within isolated objects, APIs called by multiple CPU threads can proceed without interference (e.g., blocking or waiting only for a small section of code to be processed and to update the tracked object).

[0010] In at least one embodiment, a graphics kernel includes a kernel (e.g., a function) that is to be executed on one or more GPUs. In at least one embodiment, an operation that can be performed in parallel with or executed concurrently with another operation for launching a kernel is called an "independent" operation because it does not depend on another kernel launch operation to be performed independently, and an operation that depends on another kernel launch operation needs to be performed sequentially or in order (e.g., one kernel operation blocks another) and is called a "dependent operation".

[0011] FIG. 1 is a block diagram showing a computing environment 100 for causing or preparing for one or more software modules (e.g., a graphics kernel) to be launched on a GPU simultaneously according to at least one embodiment. In at least one embodiment, FIG. 1 includes a CPU 102 having one or more central processing (CPU) cores 103 and 104, an application 105, an application programming interface 110, a driver 115, a graphics processing unit 120, one or more graphics processing unit (GPU) cores 125, 130, 135, and one or more graphics kernels 140 and 145. In at least one embodiment, FIG. 1 also includes a first launch operation 150 and a second launch operation 155, which may overlap (e.g., be performed in parallel or simultaneously) at time 160 as disclosed herein and in FIGS. 2-4.

[0012] In at least one embodiment, multiple CPU cores 103 and 104 running application 105 submit requests to API 110 to initiate operations on GPU 120 (e.g., operations to be processed or computed on the GPU) to accelerate the workload. In at least one embodiment, application 105 is a software program or source code that calls API 110 to perform operations. In at least one embodiment, application 105 includes one or more software modules. In at least one embodiment, API 110 can be the CUDA API from NVIDIA (see, e.g., FIG. 2). For example, a graphics processing program or a math library application running on CPU 102 submits several requests to API 110 to perform operations using GPU 120 to accelerate the processing of several operations (e.g., general matrix math operations such as convolution, fast Fourier transform, matrix multiplication including sparse matrices), and API 110 communicates with driver 115 to prepare a graphics kernel to perform such operations. In at least one embodiment, driver 115 can be a CUDA driver (see, e.g., FIG. 2). In at least one embodiment, driver 115 is a software driver. In at least one embodiment, driver 115 can be hard-coded or hard-wired into one or more circuits. In at least one embodiment, computing environment 100 includes two or more drivers 115, such as several CUDA drivers. In at least one embodiment, driver 115 is a library, a library of APIs, or a single API that controls GPU 120 and prepares GPU 120 to perform operations. In at least one embodiment, driver 112 can determine which operations can be performed in parallel and which operations need to be performed sequentially when starting graphics kernels 140 and 150.Some examples of operations that can be performed concurrently when preparing the kernel to start include determining the block and grid dimensions for the kernel, storing the arguments that will be used by the kernel, verifying that the kernel is correctly configured, and encoding the kernel in code for execution at runtime. In at least one embodiment, the processor includes one or more circuits for causing such operations to initiate two or more computer programs to be executed in parallel (e.g., concurrently).

[0013] In at least one embodiment, GPU 120 can be a parallel processing unit or can include a number of parallel processing units. In at least one embodiment, GPU 120 is part of a system-on-chip (SoC) having a host processor (e.g., a CPU) and a device processor (e.g., GPU 120) including an interconnect (e.g., Peripheral Component Interconnect Express (PCI-e)).

[0014] In at least one embodiment, CPU cores 103 and 104 can execute threads that submit workload requests to API 110, referred to as "CPU threads," and driver 115 can receive requests from these different CPU threads and monitor the progress of workload requests from these different CPU threads in the stream (see, e.g., FIG. 2).

[0015] FIG. 2 is a block diagram illustrating application CUDA requests processed within computer system 200 according to at least one embodiment. In at least one embodiment, computing environment 100 in FIG. 1 includes computer system 200 disclosed in FIG. 2. For example, application 105 from FIG. 1 can submit workload requests to the CUDA software stack as shown in FIG. 2.

[0016] In at least one embodiment, FIG. 2 includes a software application 105 (e.g., as disclosed in FIG. 1) and a CUDA software stack 206 including a CUDA API 208 and a CUDA driver 210 (e.g., as disclosed in FIG. 1, where API 110 corresponds to the CUDA API driver). In at least one embodiment, CUDA is used for illustrative purposes, but the techniques described herein are applicable to other parallel computing platforms and API models such as HIP and OneAPI.

[0017] In at least one embodiment, to efficiently achieve a set of results using computer system 200, software application 105 provides application CUDA requirements 204 to CUDA software stack 106. In at least one embodiment, CUDA software stack 106 includes CUDA API 108 and CUDA driver 110. In at least one embodiment, CUDA API 108 includes calls and libraries that expose the functionality of GPU 120 to application developers. In at least one embodiment, CUDA driver 110 is configured to translate application CUDA requirements 204 received by CUDA API 108 into lower-level commands that are executed against components within GPU 120. In at least one embodiment, CUDA driver 210 is a library, a library of APIs, or a single API that controls GPU 120 and prepares GPU 120 to perform operations. In at least one embodiment, CUDA driver 210 determines which operations can be performed in parallel and which operations need to be performed sequentially when launching a graphics kernel. Some examples of operations that can be performed simultaneously when preparing the kernel to launch include determining the block dimension and grid dimension for the kernel, storing the arguments that will be used by the kernel, verifying that the kernel is correctly configured, and encoding the kernel in code for runtime execution of the kernel. In at least one embodiment, the processor comprises one or more circuits for causing such operations to launch two or more computer programs that are to be performed in parallel (e.g., simultaneously).

[0018] In at least one embodiment, the CUDA driver 210 monitors one or more CUDA streams 212, and the one or more CUDA streams submit operations to be performed for execution within the GPU 120 to the GPU 120. In at least one embodiment, each CUDA stream 212 includes any number of kernels (e.g., functions), including zero, interleaved with any number of other work components, including zero, such as memory operations. In at least one embodiment, each kernel has defined inputs and generally performs calculations for each element of an input list. In at least one embodiment, within each CUDA stream 212, the kernels execute in the issue order on the GPU 120. In at least one embodiment, kernels included in different CUDA streams 212 can operate concurrently and can be interleaved. In at least one embodiment, while CUDA streams can be used, Intel queues and / or AMD queues or AMD streams of operations can be implemented or prepared for launching in the systems disclosed herein.

[0019] FIG. 3 is a stream flow diagram showing a stream (e.g., a CUDA stream) in a computing environment 300 according to at least one embodiment. In at least one embodiment, the stream flow diagram represents a stream of work to be performed in the computing environment 100 of FIG. 1 or the work performed by the computer system 200 of FIG. 2, e.g., a stream of work to be performed by the driver 115 from FIG. 1 or the CUDA driver 210 from FIG. 2. In at least one embodiment, FIG. 3 includes a tracking structure 305, a CPU thread 310, another CPU thread 315, signaling arrows 320 and 325, and a reference time 330 (e.g., in microseconds, milliseconds, or another unit of time for measuring the processing of a workload). In at least one embodiment, the tracking structure 305 is a stream managed by a driver such as the driver 115 from FIG. 1 or the CUDA driver 210 from FIG. 2. In at least one embodiment, the tracking structure 305 is a stream that includes a work submission received by a driver from an API, and the stream functions as a blocking stream in that it is processed in parallel and prevents other streams from proceeding until it signals that another stream can start. In at least one embodiment, the tracking structure 305 includes semaphores and values for each semaphore, and the driver processing of the stream can determine whether a particular value of a semaphore has been reached so that the driver processing of the stream can reach a certain value. In at least one embodiment, the tracking structure 305 may be referred to as a pending work marker because the operations in the stream need to be processed sequentially (e.g., in a certain order) so that other operations can be performed. For example, as shown, in the stream to the right of the tracking structure 305, the stream can include a waiting operation that waits for one or more software drivers to perform a sequential operation (also called "serialization") to update the tracking structure before causing another stream to be performed. In at least one embodiment, each CPU thread corresponds to a stream in the driver as shown in FIG. 3.

[0020] In at least one embodiment, CPU threads 310 and CPU threads 315 can be related to requests from application 105 (FIG. 1) to perform operations on the GPU, and the driver monitors and controls such requests in the stream and uses the stream to prepare the graphics kernel to perform the operations, and the operations are independent of the results from other operations to be performed. For example, these are independent operations and can be performed simultaneously or in parallel. For example, CPU thread 310 can include operations for verifying that the graphics kernel is correctly set or that a data memory transfer from host memory to device memory is complete, and the verification operation or the memory transfer operation is independent of the results of another operation (e.g., an operation in CPU thread 315), so it can be performed independently.

[0021] FIG. 4 is a process flow diagram showing a process of a software driver for preparing a software module or kernel to start on one or more graphics processing cores according to at least one embodiment. In at least one embodiment, a processor comprising one or more circuits, or a system comprising one or more processors, performs a process 400 for preparing a kernel to start on one or more graphics processing cores. For example, a system comprising a plurality of CPU cores performs process 400, and a host processor (e.g., a CPU) provides instructions for performing some or all of the steps of process 400. In at least one embodiment, the system disclosed in FIGS. 1-3 can perform some or all of the operations of process 400.

[0022] In at least one embodiment, some or all of process 400 (or any other process described herein, or variations and / or combinations thereof) is implemented under the control of one or more computer systems configured with computer-executable instructions, and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, by software, or by a combination thereof. In at least one embodiment, the code is stored in a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions usable to implement process 400 are not stored using only a transient signal (e.g., a propagating transient electrical or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuit elements (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 400 is implemented at least partially on a computer system, such as those described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) implements process 400. In at least one embodiment, process 400 can begin at request operation 405 and proceed to generation operation 410.

[0023] In request operation 405, one or more CPUs or one or more CPU cores that run an application submit a request to an API or software stack in order to perform operations such as operations for software modules on a GPU. For example, a graphics processing program or a weather program requests that calculation operations (such as general matrix mathematical operations including convolution, fast Fourier transform, matrix multiplication including sparse matrices) be accelerated on a GPU or one or more GPUs. In at least one embodiment, the application is a software program or source code that calls an API for performing an operation, and the API prepares the request to be handled by a driver for the GPU. In at least one embodiment, the API can be the CUDA API from NVIDIA (see, e.g., FIG. 2). In at least one embodiment, the API communicates with the driver to prepare a graphics kernel to perform such an operation based on the received request.

[0024] In generation operation 410, in at least one embodiment, the driver generates a tracking structure for tracking startup operations for a graphics kernel. In at least one embodiment, the tracking structure is a data structure in the driver that tracks all pending operations for starting a kernel corresponding to a request from request operation 405. In at least one embodiment, the tracking structure includes semaphores and values that can be reached or exceeded. In at least one embodiment, the driver can sequentially update the tracking structure so that the operations are performed in an appropriate order to avoid creating errors. In at least one embodiment, the tracking structure includes tracking the progress of different streams or threads performing operations for starting a kernel.

[0025] In preparation operation 415, in at least one embodiment, a software driver (implemented by one or more processors) prepares one or more graphics kernels to be launched on one or more GPUs by performing operations. In at least one embodiment, the driver can determine which operations can be performed in parallel and which operations need to be performed sequentially when launching the graphics kernel. Some examples of operations that can be performed simultaneously when preparing the kernel to be launched include determining the block dimension and grid dimension for the kernel, storing the arguments that will be used by the kernel, verifying that the kernel is correctly configured, and encoding the kernel in code for runtime execution of the kernel. In at least one embodiment, the processor includes one or more circuits for causing such operations to launch two or more computer programs to be performed in parallel (e.g., simultaneously). In at least one embodiment, when the operations for launching the first kernel can be run in parallel with the operations for launching the second kernel, the driver performs those operations to be performed in parallel. In at least one embodiment, when the operations for launching the second kernel cannot be performed in parallel with the operations for launching the first kernel, the driver causes the execution of the operations for launching the second kernel to be blocked, interrupted, or synchronized such that the operations are performed in the order necessary to perform the operations. Some examples of operations that can be performed simultaneously when preparing the kernel to be launched include determining the block dimension and grid dimension for the kernel, storing the arguments that will be used by the kernel, verifying that the kernel is correctly configured, and encoding the kernel in code for runtime execution of the kernel.In at least one embodiment, the processor comprises one or more circuits for causing such operations to initiate two or more computer programs to be executed in parallel (e.g., simultaneously).

[0026] In the end determination operation 420, in at least one embodiment, one or more CPUs or CPU cores that perform an application request determine whether all operations for initiating one or more graphics kernels have been performed. If other operations still need to be performed, or if the driver receives a new request corresponding to setting more graphics kernels, one or more circuits repeat performing the preparation operation in the preparation operation 420. Based on a request from the application, when all operations for setting, initiating, or starting one or more graphics kernels are completed, one or more circuits can terminate the processor 400.

[0027] After the end determination operation 420, in at least one embodiment, one or more circuits can repeat the process 400 or a part of the process 400 for one or more other applications (e.g., GPUs) that require performing operations in parallel processing, for example. In at least one embodiment, after the end determination operation 420, the GPU can execute or run the kernel set by one or more circuits that performed the process 400.

[0028] Data center FIG. 5 shows an exemplary data center 500 according to at least one embodiment. In at least one embodiment, the data center 500 includes, without limitation, a data center infrastructure layer 510, a framework layer 520, a software layer 530, and an application layer 540. In at least one embodiment, the data center 500 includes the system disclosed in FIGS. 1-3 and performs all or part of the process 400 disclosed in FIG. 4.

[0029] In at least one embodiment, as shown in FIG. 5, the data center infrastructure layer 510 may include a resource orchestrator 512, grouped computing resources 514, and node computing resources (referred to as "node C.R.") 516(1) to 516(N), where "N" represents any positive integer. In at least one embodiment, the node C.R.s 516(1) to 516(N) may include, but are not limited to, any number of central processing units (referred to as "CPU"), or other processors (including accelerators, field programmable gate arrays (referred to as "FPGA"), data processing units (referred to as "DPU") in network devices, graphics processors, etc.), memory devices (such as dynamic read-only memory), storage devices (such as solid state or disk drives), network input / output (referred to as "NW I / O") devices, network switches, virtual machines (referred to as "VM"), power modules, and cooling modules. In at least one embodiment, one or more of the node C.R.s among 516(1) to 516(N) may be servers having one or more of the computing resources described above.

[0030] In at least one embodiment, the grouped computing resources 514 can include a separate grouping of node C.R.s stored within one or more racks (not shown), or many racks stored in a data center at various geographic locations (also not shown). A separate grouping of node C.R.s within the grouped computing resources 514 can include grouped computing resources, network resources, memory resources, or storage resources that are configured or allocated to support one or more workloads. In at least one embodiment, some node C.R.s that include a CPU or processor can be grouped within one or more racks to provide computing resources for supporting one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches in any combination.

[0031] In at least one embodiment, the resource orchestrator 512 can configure or otherwise control one or more node C.R.s 516(1)-516(N) and / or the grouped computing resources 514. In at least one embodiment, the resource orchestrator 512 can include a software design infrastructure ("SDI") management entity for the data center 500. In at least one embodiment, the resource orchestrator 512 can include hardware, software, or some combination thereof.

[0032] In at least one embodiment, as shown in FIG. 5, the framework layer 520 includes, without limitation, a job scheduler 532, a configuration manager 534, a resource manager 536, and a distributed file system 538. In at least one embodiment, the framework layer 520 may include a framework for supporting the software 552 of the software layer 530 and / or one or more applications 542 of the application layer 540. In at least one embodiment, the software 552 or the application(s) 542 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 520 may be of a type of free and open-source software web application framework, such as Apache Spark (trademark) (hereinafter "Spark") that may utilize the distributed file system 538 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 532 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 500. In at least one embodiment, the configuration manager 534 may be able to configure different layers, such as the software layer 530 and the framework layer 520 including Spark and the distributed file system 538 for supporting large-scale data processing. In at least one embodiment, the resource manager 536 may be able to manage clustered or grouped computing resources that are mapped or allocated to support the distributed file system 538 and the job scheduler 532. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 514 in the data center infrastructure layer 510.In at least one embodiment, the resource manager 536 can manage these mapped or allocated computing resources in cooperation with the resource orchestrator 512.

[0033] In at least one embodiment, the software 552 included in the software layer 530 can include software used by at least a portion of the node C.R.s 516(1) - 516(N), the grouped computing resources 514, and / or the distributed file system 538 of the framework layer 520. One or more types of software can include, but are not limited to, Internet web page search software, email virus scan software, database software, and streaming video content software.

[0034] In at least one embodiment, the application(s) 542 included in the application layer 540 can include one or more types of applications used by at least a portion of the node C.R.s 516(1) - 516(N), the grouped computing resources 514, and / or the distributed file system 538 of the framework layer 520. In at least one or more types of applications, it can include, but is not limited to, CUDA applications.

[0035] In at least one embodiment, any one of the configuration manager 534, the resource manager 536, and the resource orchestrator 512 can implement any number and type of self - correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self - correcting actions can free the data center operator of the data center 500 from determining configurations at risk of failure and, in some cases, avoiding under - utilized and / or low - performing portions of the data center.

[0036] Computer-based system The following figures describe an exemplary computer-based system that may be used to implement at least one embodiment, without limitation.

[0037] FIG. 6 shows a processing system 600 according to at least one embodiment. In at least one embodiment, the processing system 600 is included in the systems disclosed in FIGS. 1-3 and can implement all or part of the process 400 disclosed in FIG. 4. In at least one embodiment, the processing system 600 includes one or more processors 602 and one or more graphics processors 608 and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a number of processors 602 or processor cores 607. In at least one embodiment, the processing system 600 is a processing platform incorporated within a system-on-a-chip ("SoC") integrated circuit for use in a mobile device, a handheld device, or an embedded device.

[0038] In at least one embodiment, the processing system 600 can include, or be incorporated within, a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, the processing system 600 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 600 can also include, be coupled with, or be incorporated within wearable devices such as a smartwatch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 600 is a television or set-top box device having one or more processors 602 and a graphical interface generated by one or more graphics processors 608.

[0039] In at least one embodiment, one or more processors 602 each include one or more processor cores 607 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 607 is configured to process a particular instruction set 609. In at least one embodiment, the instruction set 609 can facilitate computing via a complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, the processor cores 607 can each process different instruction sets 609, and the instruction sets 609 can include instructions for facilitating the emulation of other instruction sets. In at least one embodiment, the processor cores 607 can also include other processing devices such as a digital signal processor (DSP).

[0040] In at least one embodiment, the processor 602 includes a cache memory ("cache") 604. In at least one embodiment, the processor 602 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of the processor 602. In at least one embodiment, the processor 602 also uses an external cache (e.g., a level 3 ("L3") cache or a last level cache ("LLC")), not shown, which can be shared among the processor cores 607 using known cache coherence techniques. In at least one embodiment, additionally, a register file 606 is included in the processor 602, and the register file 606 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 606 can include general-purpose registers or other registers.

[0041] In at least one embodiment, one or more processors 602 are coupled to one or more interface buses 610 to transmit communication signals, such as address, data, or control signals, between the processor 602 and other components in the processing system 600. In at least one embodiment, the interface bus 610 in one embodiment can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 610 is not limited to the DMI bus and can include one or more peripheral component interconnect buses (e.g., "PCI": Peripheral Component Interconnect, PCI Express ("PCIe")), memory buses, or other types of interface buses. In at least one embodiment, the (one or more) processors 602 include an integrated memory controller 616 and a platform controller hub 630. In at least one embodiment, the memory controller 616 facilitates communication between the memory device and other components of the processing system 600, and the platform controller hub ("PCH": platform controller hub) 630 provides connections to I / O devices via a local input / output ("I / O": Input / Output) bus.

[0042] In at least one embodiment, the memory device 620 can be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, a phase change memory device, or any other memory device having suitable performance to act as a processor memory. In at least one embodiment, the memory device 620 can operate as a system memory for the processing system 600 to store data 622 and instructions 621 for use when one or more processors 602 execute an application or process. In at least one embodiment, the memory controller 616 can also be coupled to an optional external graphics processor 612, and the external graphics processor 612 can communicate with one or more graphics processors 608 in the processor 602 to perform graphics operations and media operations. In at least one embodiment, the display device 611 can be connected to the (one or more) processors 602. In at least one embodiment, the display device 611 can include one or more of an internal display device, such as in the case of a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 611 can include a head mounted display (“HMD”), such as a stereoscopic display device for use in a virtual reality (“VR”) application or an augmented reality (“AR”) application.

[0043] In at least one embodiment, the platform controller hub 630 enables peripheral devices to be connected to the memory device 620 and the processor 602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 646, a network controller 634, a firmware interface 628, a wireless transceiver 626, a touch sensor 625, and a data storage device 624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, the touch sensor 625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (「LTE」) transceiver. In at least one embodiment, the firmware interface 628 enables communication with system firmware and can be, for example, a unified extensible firmware interface (「UEFI」). In at least one embodiment, the network controller 634 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 610. In at least one embodiment, the audio controller 646 is a multi-channel high-definition audio controller.In at least one embodiment, the processing system 600 includes an optional legacy I / O controller 640 for coupling a legacy (e.g., Personal System 2 (“PS / 2”)) device to the processing system 600. In at least one embodiment, the platform controller hub 630 can also be connected to one or more Universal Serial Bus (“USB”) controller 642 connected input devices, such as a combination of a keyboard and a mouse 643, a camera 644, or other USB input devices.

[0044] In at least one embodiment, instances of the memory controller 616 and the platform controller hub 630 can be incorporated into a discrete external graphics processor, such as the external graphics processor 612. In at least one embodiment, the platform controller hub 630 and / or the memory controller 616 can be external to one or more processors 602. For example, in at least one embodiment, the processing system 600 can include an external memory controller 616 and a platform controller hub 630, which can be configured as a memory controller hub and a peripheral controller hub within a system chipset communicating with the (one or more) processors 602.

[0045] FIG. 7 shows a computer system 700 according to at least one embodiment. In at least one embodiment, the computer system 700 is included in the systems disclosed in FIGS. 1 - 3 and can implement all or part of the process 400 disclosed in FIG. 4. For example, the computer system 700 can be the CPU 102 from FIG. 1. In at least one embodiment, the computer system 700 can be a system, SOC, or some combination with interconnected devices and components. In at least one embodiment, the computer system 700 is formed with a processor 702 that can include an execution unit for executing instructions. In at least one embodiment, the computer system 700 can include components such as the processor 702 for employing an execution unit that includes logic for implementing algorithms for processing data, without limitation. In at least one embodiment, the computer system 700 can include a processor such as a PENTIUM® processor family, Xeon™, Itanium® from Intel Corporation in Santa Clara, California, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessor, but other systems (including PCs with other microprocessors, engineering workstations, set - top boxes, etc.) can also be used. In at least one embodiment, the computer system 700 can execute a version of the WINDOWS® operating system available from Microsoft Corporation in Redmond, Washington, but other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces can also be used.

[0046] In at least one embodiment, the computer system 700 can be used in other devices such as a handheld device and an embedded application. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor (DSP), a system on a chip (SoC), a network computer (NetPC), a set-top box, a network hub, a wide area network (WAN) switch, or any other system that can execute one or more instructions.

[0047] In at least one embodiment, computer system 700 may include, without limitation, a processor 702, which may include, without limitation, one or more execution units 708 configured to execute a Compute Unified Device Architecture (「CUDA」) program (CUDA (registered trademark) is developed by NVIDIA Corporation of Santa Clara, California). In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 700 is a single-processor desktop or server system. In at least one embodiment, computer system 700 may be a multi-processor system. In at least one embodiment, processor 702 may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 702 may be coupled to a processor bus 710, which may transmit data signals between processor 702 and other components in computer system 700.

[0048] In at least one embodiment, processor 702 may include, without limitation, a level 1 (“L1”) internal cache memory (“cache”) 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may exist external to processor 702. In at least one embodiment, processor 702 may also include a combination of both internal and external caches. In at least one embodiment, register file 706 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer registers.

[0049] In at least one embodiment, execution unit 708, which includes logic for performing, without limitation, integer and floating point operations, also exists within processor 702. Processor 702 may also include a microcode (“u-code”) read only memory (“ROM”) that stores microcode for several macro instructions. In at least one embodiment, execution unit 708 may include logic for handling a packed instruction set 709. In at least one embodiment, by including the packed instruction set 709 in the instruction set of general purpose processor 702 along with the associated circuitry for executing the instructions, operations used by many multimedia applications may be performed using packed data in general purpose processor 702. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0050] In at least one embodiment, execution unit 708 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 700 may include, without limitation, memory 720. In at least one embodiment, memory 720 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. Memory 720 may store (one or more) instructions 719 and / or data 721 represented by data signals executable by processor 702.

[0051] In at least one embodiment, a system logic chip may be coupled to processor bus 710 and memory 720. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 716, and processor 702 may communicate with MCH 716 via processor bus 710. In at least one embodiment, MCH 716 may provide a high-bandwidth memory path 718 to memory 720 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 716 may direct data signals between processor 702, memory 720, and other components in computer system 700, and may bridge data signals between processor bus 710, memory 720, and system I / O 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 716 may be coupled to memory 720 through high-bandwidth memory path 718, and graphics / video card 712 may be coupled to MCH 716 via an Accelerated Graphics Port (“AGP”) interconnect 714.

[0052] In at least one embodiment, computer system 700 may use system I / O 722, which is a proprietary hub interface bus for coupling MCH 716 to an I / O controller hub (“ICH”) 730. In at least one embodiment, ICH 730 may provide direct connections to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripheral devices to memory 720, the chipset, and processor 702. Examples may include, without limitation, an audio controller 729, a firmware hub (“flash BIOS”) 728, a wireless transceiver 726, data storage 724, a legacy I / O controller 723 that includes a user input interface 725 and a keyboard interface, a serial expansion port such as a USB 727, and a network controller 734. Data storage 724 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0053] In at least one embodiment, FIG. 7 shows a system that includes interconnected hardware devices or “chips”. In at least one embodiment, FIG. 7 may show an exemplary SoC. In at least one embodiment, the devices shown in FIG. 7 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 700 are interconnected using a Compute Express Link (“CXL”) interconnect.

[0054] FIG. 8 shows a system 800 according to at least one embodiment. In at least one embodiment, the system 800 is included in the systems disclosed in FIGS. 1-3 and can implement all or part of the process 400 disclosed in FIG. 4. For example, the system 800 can be the CPU 102 from FIG. 1. In at least one embodiment, the system 800 is an electronic device that utilizes a processor 810. In at least one embodiment, the system 800 can be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more in-premises service providers or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0055] In at least one embodiment, the system 800 can include a processor 810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 810 is I 2They are coupled using a bus or interface such as a C bus, a System Management Bus (SMBus), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI), a High Definition Audio (HDA) bus, a Serial Advance Technology Attachment (SATA) bus, USB (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (UART) bus. In at least one embodiment, FIG. 8 shows a system including interconnected hardware devices or “chips”. In at least one embodiment, FIG. 8 may show an exemplary System-on-Chip (SoC). In at least one embodiment, the devices shown in FIG. 8 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 8 are interconnected using a CXL interconnect.

[0056] In at least one embodiment, FIG. 8 shows a display 824, a touch screen 825, a touch pad 830, a near field communication unit (“NFC”) 845, a sensor hub 840, a thermal sensor 846, an express chipset (“EC”) 835, a trusted platform module (“TPM”) 838, BIOS / firmware / flash memory (“BIOS, FW flash”) 822, a DSP 860, a solid state disk (“SSD”) or a hard disk drive (“HDD”) 820, a wireless local area network unit (“WLAN”) 850, a Bluetooth unit 852, a wireless wide area network unit (“WWAN”) 856, a global positioning system (“GPS”) 855, a camera such as a USB3.0 camera (“USB3.0 camera”) 854, or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 815 implemented, for example, in the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0057] In at least one embodiment, through the components described above, other components may be communicatively coupled to the processor 810. In at least one embodiment, an accelerometer 841, an ambient light sensor (“ALS”), 842, a compass 843, and a gyroscope 844 may be communicatively coupled to the sensor hub 840. In at least one embodiment, a thermal sensor 839, a fan 837, a keyboard 836, and a touch pad 830 may be communicatively coupled to the EC 835. In at least one embodiment, a speaker 863, headphones 864, and a microphone (“mic”) 865 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 862, and the audio unit 862 may be communicatively coupled to the DSP 860. In at least one embodiment, the audio unit 862 may include, for example, but not limited to, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 857 may be communicatively coupled to the WWAN unit 856. In at least one embodiment, components such as the WLAN unit 850 and the Bluetooth unit 852, as well as the WWAN unit 856, may be implemented in a next generation form factor (“NGFF”).

[0058] FIG. 9 shows an exemplary integrated circuit 900 according to at least one embodiment. In at least one embodiment, the integrated circuit 900 is included in the system disclosed in FIGS. 1-3 and can implement all or part of the process 400 disclosed in FIG. 4. For example, the integrated circuit 900 can be included in the CPU 102 from FIG. 1. In at least one embodiment, the exemplary integrated circuit 900 is a SoC that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 900 includes one or more application processors 905 (e.g., CPU, DPU), at least one graphics processor 910, and additionally may include an image processor 915 and / or a video processor 920, any of which can be modular IP cores. In at least one embodiment, the integrated circuit 900 includes peripheral devices or bus logic including a USB controller 925, a UART controller 930, an SPI / SDIO controller 935, and an I 2 S / I 2 2C controller 940. In at least one embodiment, the integrated circuit 900 can include a display device 945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 950 and a mobile industry processor interface (MIPI) display interface 955. In at least one embodiment, storage can be provided by a flash memory subsystem 960 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 965 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 970.

[0059] FIG. 10 shows a computing system 1000 according to at least one embodiment. In at least one embodiment, the computing system 1000 is included in the systems disclosed in FIGS. 1-3 and can implement all or part of the process 400 disclosed in FIG. 4. For example, the computer system 1000 can be included in the CPU 102 from FIG. 1. In at least one embodiment, the computing system 1000 includes a processing subsystem 1001 having one or more processors 1002 and a system memory 1004 that communicate via an interconnect path that can include a memory hub 1005. In at least one embodiment, the memory hub 1005 can be a separate component within a chipset component or can be incorporated within one or more processors 1002. In at least one embodiment, the memory hub 1005 is coupled to an I / O subsystem 1011 via a communication link 1006. In at least one embodiment, the I / O subsystem 1011 includes an I / O hub 1007 that can enable the computing system 1000 to receive input from one or more input devices 1008. In at least one embodiment, the I / O hub 1007 can enable a display controller that can be included in one or more processors 1002 to provide output to one or more display devices 1010A. In at least one embodiment, one or more display devices 1010A coupled to the I / O hub 1007 can include local, internal, or embedded display devices.

[0060] In at least one embodiment, processing subsystem 1001 includes one or more parallel processors 1012 coupled to memory hub 1005 via a bus or other communication link 1013. In at least one embodiment, communication link 1013 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCIe, or can be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1012 include a number of processing cores and / or processing clusters, such as many integrated core processors, to form a parallel or vector processing system focused on calculations. In at least one embodiment, one or more parallel processors 1012 form a graphics processing subsystem, and the graphics processing subsystem can output pixels to one of one or more display devices 1010A coupled via I / O hub 1007. In at least one embodiment, one or more parallel processors 1012 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1010B.

[0061] In at least one embodiment, the system storage unit 1014 can be connected to the I / O hub 1007 to provide a storage mechanism for the computing system 1000. In at least one embodiment, an I / O switch 1016 can be used to provide an interface mechanism to enable connections between the I / O hub 1007 and other components such as a network adapter 1018 and / or a wireless network adapter 1019 that can be incorporated into the platform, as well as various other devices that can be added via one or more add-in devices 1020. In at least one embodiment, the network adapter 1018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0062] In at least one embodiment, the computing system 1000 can include other components not explicitly shown that can also be connected to the I / O hub 1007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 10 can be implemented using any suitable protocol such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or (one or more) protocols such as an NVLink high-speed interconnect, or an interconnect protocol.

[0063] In at least one embodiment, one or more parallel processors 1012 incorporate circuit elements optimized for graphics and video processing, such as a video output circuit element, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1012 incorporate circuit elements optimized for general-purpose processing. In at least one embodiment, the components of computing system 1000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1012, memory hub 1005, processor(s) 1002, and I / O hub 1007 can be incorporated into a System-on-a-Chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1000 can be incorporated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1000 can be incorporated into a multi-chip module (MCM), and the multi-chip module can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1011 and display device 1010B are omitted from computing system 1000.

[0064] Processing system The following figures depict an exemplary processing system that can be used to implement at least one embodiment, without limitation.

[0065] FIG. 11 shows an accelerated processing unit (APU) 1100 according to at least one embodiment. In at least one embodiment, the APU 1100 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the APU 1100 can be included in the GPU 120 from FIG. 1. In at least one embodiment, the APU 1100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1100 can be configured to execute application programs such as CUDA programs. In at least one embodiment, the APU 1100 includes, but is not limited to, a core complex 1110, a graphics complex 1140, a fabric 1160, an I / O interface 1170, a memory controller 1180, a display controller 1192, and a multimedia engine 1194. In at least one embodiment, the APU 1100 can include any number of core complexes 1110, any number of graphics complexes 1150, any number of display controllers 1192, and any number of multimedia engines 1194 in any combination. For illustrative purposes, multiple instances of the same object are shown herein with a reference number that identifies the object and, if necessary, a numbered parenthesis that identifies the instance.

[0066] In at least one embodiment, core complex 1110 is a CPU, graphics complex 1140 is a GPU, and APU 1100 is a processing unit that incorporates 1110 and 1140, among other things, on a single chip. In at least one embodiment, some tasks may be assigned to core complex 1110 and other tasks may be assigned to graphics complex 1140. In at least one embodiment, core complex 1110 is configured to execute main control software related to APU 1100, such as an operating system. In at least one embodiment, core complex 1110 is the master processor of APU 1100 and controls and coordinates the operation of other processors. In at least one embodiment, core complex 1110 issues commands to control the operation of graphics complex 1140. In at least one embodiment, core complex 1110 may be configured to execute host-executable code derived from CUDA source code, and graphics complex 1140 may be configured to execute device-executable code derived from CUDA source code.

[0067] In at least one embodiment, core complex 1110 includes, among other things, cores 1120(1) to 1120(4) and L3 cache 1130. In at least one embodiment, core complex 1110 may include any number of cores 1120 and any number and type of caches in any combination. In at least one embodiment, core 1120 is configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1120 is a CPU core.

[0068] In at least one embodiment, each core 1120 includes, without limitation, a fetch / decode unit 1122, an integer execution engine 1124, a floating point execution engine 1126, and an L2 cache 1128. In at least one embodiment, the fetch / decode unit 1122 fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate micro-instructions to the integer execution engine 1124 and the floating point execution engine 1126. In at least one embodiment, the fetch / decode unit 1122 can simultaneously dispatch a micro-instruction to the integer execution engine 1124 and another micro-instruction to the floating point execution engine 1126. In at least one embodiment, the integer execution engine 1124 performs, without limitation, integer and memory operations. In at least one embodiment, the floating point engine 1126 performs, without limitation, floating point and vector operations. In at least one embodiment, the fetch decode unit 1122 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1124 and the floating point execution engine 1126.

[0069] In at least one embodiment, each core 1120(i), where i is an integer representing a particular instance of core 1120, can access the L2 cache 1128(i) included in core 1120(i). In at least one embodiment, each core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, is connected to other cores 1120 included in core complex 1110(j) via an L3 cache 1130(j) included in core complex 1110(j). In at least one embodiment, a core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, can access all of the L3 cache 1130(j) included in core complex 1110(j). In at least one embodiment, the L3 cache 1130 can include, without limitation, any number of slices.

[0070] In at least one embodiment, the graphics complex 1140 may be configured to perform compute operations in a highly parallel fashion. In at least one embodiment, the graphics complex 1140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations related to rendering images to a display. In at least one embodiment, the graphics complex 1140 is configured to perform operations not related to graphics. In at least one embodiment, the graphics complex 1140 is configured to perform both operations related to graphics and operations not related to graphics.

[0071] In at least one embodiment, the graphics complex 1140 includes, without limitation, any number of compute units 1150 and an L2 cache 1142. In at least one embodiment, the compute units 1150 share the L2 cache 1142. In at least one embodiment, the L2 cache 1142 is partitioned. In at least one embodiment, the graphics complex 1140 includes, without limitation, any number of compute units 1150 and any number and type of cache (including 0). In at least one embodiment, the graphics complex 1140 includes, without limitation, any amount of dedicated graphics hardware.

[0072] In at least one embodiment, each compute unit 1150 includes, without limitation, any number of SIMD units 1152 and shared memory 1154. In at least one embodiment, each SIMD unit 1152 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1150 may execute any number of thread blocks, where each thread block executes on a single compute unit 1150. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1152 executes different warps. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via the shared memory 1154.

[0073] In at least one embodiment, fabric 1160 is a system interconnect that facilitates data and control transmissions across core complex 1110, graphics complex 1140, I / O interface 1170, memory controller 1180, display controller 1192, and multimedia engine 1194. In at least one embodiment, APU 1100 may include any amount and type of system interconnects, in addition to or instead of fabric 1160, that facilitate data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to APU 1100. In at least one embodiment, I / O interface 1170 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1170. In at least one embodiment, peripheral devices coupled to I / O interface 1170 may include, but are not limited to, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0074] In at least one embodiment, display controller AMD92 displays an image on one or more display devices, such as a liquid crystal display (「LCD」) device. In at least one embodiment, multimedia engine 1194 includes any amount and type of circuit elements related to multimedia, including but not limited to a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controller 1180 facilitates data transfer between APU1100 and unified system memory 1190. In at least one embodiment, core complex 1110 and graphics complex 1140 share unified system memory 1190.

[0075] In at least one embodiment, APU1100 implements a memory subsystem that includes any amount and type of memory controller 1180 and memory devices (e.g., shared memory 1154) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU1100 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 1228, L3 cache 1130, and L2 cache 1142), and one or more cache memories may be private to any number of components (e.g., core 1120, core complex 1110, SIMD unit 1152, compute unit 1150, and graphics complex 1140) or shared among any number of components.

[0076] FIG. 12 shows a CPU 1200 according to at least one embodiment. In at least one embodiment, the CPU 1200 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1200 may be configured to execute application programs. In at least one embodiment, the CPU 1200 is configured to execute main control software such as an operating system. In at least one embodiment, the CPU 1200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1200 may be configured to execute host-executable code derived from CUDA source code, and the external GPU may be configured to execute device-executable code derived from such CUDA source code. In at least one embodiment, the CPU 1200 includes, without limitation, any number of core complexes 1210, a fabric 1260, an I / O interface 1270, and a memory controller 1280.

[0077] In at least one embodiment, the core complex 1210 includes, without limitation, cores 1220(1) to 1220(4) and an L3 cache 1230. In at least one embodiment, the core complex 1210 may include any number of cores 1220 and any number and type of caches in any combination. In at least one embodiment, the core 1220 is configured to execute instructions of a specific ISA. In at least one embodiment, each core 1220 is a CPU core.

[0078] In at least one embodiment, each core 1220 includes, without limitation, a fetch / decode unit 1222, an integer execution engine 1224, a floating point execution engine 1226, and an L2 cache 1228. In at least one embodiment, the fetch / decode unit 1222 fetches instructions, decodes such instructions, generates micro-operations, and dispatches distinct micro-instructions to the integer execution engine 1224 and the floating point execution engine 1226. In at least one embodiment, the fetch / decode unit 1222 can simultaneously dispatch one micro-instruction to the integer execution engine 1224 and another micro-instruction to the floating point execution engine 1226. In at least one embodiment, the integer execution engine 1224 performs, without limitation, integer and memory operations. In at least one embodiment, the floating point engine 1226 performs, without limitation, floating point and vector operations. In at least one embodiment, the fetch decode unit 1222 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 1224 and the floating point execution engine 1226.

[0079] In at least one embodiment, each core 1220(i), where i is an integer representing a particular instance of core 1220, can access the L2 cache 1228(i) included in core 1220(i). In at least one embodiment, each core 1220 included in a core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, is connected to other cores 1220 in the core complex 1210(j) via an L3 cache 1230(j) included in the core complex 1210(j). In at least one embodiment, a core 1220 included in a core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, can access all of the L3 cache 1230(j) included in the core complex 1210(j). In at least one embodiment, the L3 cache 1230 can include, without limitation, any number of slices.

[0080] In at least one embodiment, fabric 1260 is a system interconnect that facilitates data and control transmissions across core complexes 1210(1) - 1210(N), where N is an integer greater than 0, I / O interface 1270, and memory controller 1280. In at least one embodiment, CPU 1200 may include any amount and type of system interconnect, in addition to or instead of fabric 1260, which facilitates data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1200. In at least one embodiment, I / O interface 1270 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1270. In at least one embodiment, peripheral devices coupled to I / O interface 1270 may include, but are not limited to, a display, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0081] In at least one embodiment, the memory controller 1280 facilitates data transfer between the CPU 1200 and the system memory 1290. In at least one embodiment, the core complex 1210 and the graphics complex 1240 share the system memory 1290. In at least one embodiment, the CPU 1200 implements a memory subsystem that includes any amount and type of memory controller 1280 and memory devices, which may be dedicated to one component or shared among multiple components. In at least one embodiment, the CPU 1200 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 1228 and L3 cache 1230), and the one or more cache memories may each be private to any number of components (e.g., core 1220 and core complex 1210) or shared among any number of components.

[0082] FIG. 13 shows an exemplary accelerator integration slice 1390 according to at least one embodiment. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services instead of a plurality of graphics processing engines included in a graphics acceleration module. Each of the graphics processing engines may comprise a separate GPU. Alternatively, the graphics processing engines may comprise different types of graphics processing engines, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines, within a GPU. In at least one embodiment, the graphics acceleration module may be a GPU having a plurality of graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs incorporated on a common package, line card, or chip.

[0083] The application effective address space 1382 within the system memory 1314 stores the process element 1383. In one embodiment, the process element 1383 is stored in response to a GPU call 1381 from an application 1380 running on the processor 1307. The process element 1383 includes the process state of the corresponding application 1380. The work descriptor ("WD") 1384 included in the process element 1383 can be a single job requested by the application or may include a pointer to a queue of jobs. In at least one embodiment, the WD 1384 is a pointer to a job request queue in the application effective address space 1382.

[0084] The graphics acceleration module 1346 and / or individual graphics processing engines can be shared by all or a subset of the processes in the system. In at least one embodiment, the infrastructure for setting the process state and sending the WD 1384 to the graphics acceleration module 1346 to initiate a job in a virtualized environment can be included.

[0085] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine. Since the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integration circuit for the owning partition, and when the graphics acceleration module 1346 is assigned, the operating system initializes the accelerator integration circuit for the owning process.

[0086] During operation, the WD fetch unit 1391 in the accelerator integration slice 1390 fetches the next WD 1384, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1346. As shown, the data from the WD 1384 is stored in the register 1345 and can be used by the memory management unit ("MMU": memory management unit) 1339, the interrupt management circuit 1347, and / or the context management circuit 1348. For example, one embodiment of the MMU 1339 includes segment / page walk circuitry for accessing the segment / page table 1386 within the OS virtual address space 1385. The interrupt management circuit 1347 can process interrupt events ("INT": interrupt) 1392 received from the graphics acceleration module 1346. When performing a graphics operation, the effective address 1393 generated by the graphics processing engine is translated to a physical address by the MMU 1339.

[0087] In one embodiment, the same set of registers 1345 is replicated for each graphics processing engine and / or for the graphics acceleration module 1346 and can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included within the accelerator integration slice 1390. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

Table 1

[0088] Exemplary registers that can be initialized by the operating system are shown in Table 2.

Table 2

[0089] In one embodiment, each WD1384 is specific to a particular graphics acceleration module 1346 and / or a particular graphics processing engine. The WD1384 may contain all the information required by the graphics processing engine to perform the work, or the WD1384 may be a pointer to a memory location set by the application for the command queue of the work to be completed.

[0090] Figures 14A - 14B illustrate an exemplary graphics processor according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general - purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within a SoC.

[0091] FIG. 14A shows an exemplary graphics processor 1410 of a SoC integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1410 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the graphics processor 1410 can be included in the GPU 120 from FIG. 1. FIG. 14B shows an additional exemplary graphics processor 1440 of a SoC integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1410 of FIG. 14A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1440 of FIG. 14B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1410, 1440 can be a variation of the graphics processor 910 of FIG. 9.

[0092] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A - 1415N (e.g., 1415A, 1415B, 1415C, 1415D - 1415N - 1, and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs via separate logic, whereby the vertex processor 1405 is optimized to execute operations for vertex shader programs, and the one or more fragment processors 1415A - 1415N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the (one or more) fragment processors 1415A - 1415N use the primitives and vertex data generated by the vertex processor 1405 to create a frame buffer to be displayed on a display device. In at least one embodiment, the (one or more) fragment processors 1415A - 1415N are optimized to execute fragment shader programs as provided in the OpenGL API, and the OpenGL API can be used to perform operations similar to pixel shader programs as provided in the Direct 3D API.

[0093] In at least one embodiment, the graphics processor 1410 additionally includes one or more MMUs 1420A - 1420B, one or more caches 1425A - 1425B, and one or more circuit interconnects 1430A - 1430B. In at least one embodiment, one or more MMUs 1420A - 1420B provide a virtual - physical address mapping for the graphics processor 1410, which includes the vertex processor 1405 and / or one or more fragment processors 1415A - 1415N, and they can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1425A - 1425B. In at least one embodiment, one or more MMUs 1420A - 1420B can be synchronized with one or more other MMUs in the system, which include one or more MMUs associated with one or more of the application processors 905, image processors 915, and / or video processors 920 of FIG. 9, such that each processor 905 - 920 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A - 1430B enable the graphics processor 1410 to interface with other IP cores within the SoC either via the internal bus of the SoC or via a direct connection.

[0094] In at least one embodiment, the graphics processor 1440 includes one or more MMUs 1420A - 1420B, caches 1425A - 1425B, and circuit interconnects 1430A - 1430B of the graphics processor 1410 of FIG. 14A. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A - 1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F - 1455N - 1, and 1455N), and the one or more shader cores 1455A - 1455N provide a unified shader core architecture that can execute all types of programmable shader code, where a single core, or type, or core includes shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher for dispatching execution threads to the one or more shader cores 1455A - 1455N, and a tiling unit 1458 for accelerating tiling operations for tile - based rendering, where rendering operations for a scene are sub - divided in the image space, for example, to utilize local - space coherence within the scene or to optimize the use of internal caches.

[0095] FIG. 15A shows a graphics core 1500 according to at least one embodiment. In at least one embodiment, the graphics core 1500 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the graphics core 1500 can be the GPU cores 125, 130, and 135 from FIG. 1. In at least one embodiment, the graphics core 1500 can be included within the graphics processor 910 of FIG. 9. In at least one embodiment, the graphics core 1500 can be the unified shader cores 1455A-1455N as in the case of FIG. 14B. In at least one embodiment, the graphics core 1500 includes a shared instruction cache 1502, a texture unit 1518, and a cache / shared memory 1520, which are common to the execution resources within the graphics core 1500. In at least one embodiment, the graphics core 1500 can include a plurality of slices 1501A-1501N, or partitions for each core, and the graphics processor can include a plurality of instances of the graphics core 1500. The slices 1501A-1501N can include support logic that includes local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and sets of registers 1510A-1510N.In at least one embodiment, slices 1501A to 1501N can include a set of additional function units (AFUs) 1512A to 1512N, floating-point units (FPUs) 1514A to 1514N, integer arithmetic logic units (ALUs) 1516 to 1516N, address computational units (ACUs) 1513A to 1513N, double-precision floating-point units (DPFPUs) 1515A to 1515N, and matrix processing units (MPUs) 1517A to 1517N.

[0096] In at least one embodiment, FPUs 1514A to 1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and DPFPUs 1515A to 1515N perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 1516A to 1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, MPUs 1517A to 1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, MPUs 1517 to 1517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1512A to 1512N can perform additional logical operations not supported by floating-point units or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0097] Figure 15B shows a general-purpose graphics processing unit (GPGPU) 1530 according to at least one embodiment. In at least one embodiment, the GPGPU 1530 is highly parallel and suitable for introduction on a multi-chip module. In at least one embodiment, the GPGPU 1530 can be configured to enable highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1530 can be directly linked to other instances of the GPGPU 1530 to create a multi-GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, the GPGPU 1530 includes a host interface 1532 to enable connection to a host processor. In at least one embodiment, the host interface 1532 is a PCIe interface. In at least one embodiment, the host interface 1532 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to distribute the execution threads associated with those commands across a set of compute clusters 1536A - 1536H. In at least one embodiment, the compute clusters 1536A - 1536H share a cache memory 1538. In at least one embodiment, the cache memory 1538 can act as a higher-level cache for the cache memories within the compute clusters 1536A - 1536H.

[0098] In at least one embodiment, the GPGPU 1530 includes memories 1544A - 1544B coupled to compute clusters 1536A - 1536H via a set of memory controllers 1542A - 1542B. In at least one embodiment, the memories 1544A - 1544B can include various types of memory devices including DRAM, or graphics random access memory such as synchronous graphics random access memory (SGRAM) including graphics double data rate (GDDR) memory.

[0099] In at least one embodiment, each of the compute clusters 1536A - 1536H includes a set of graphics cores such as the graphics core 1500 of FIG. 15A, and the set of graphics cores can include multiple types of integer and floating - point logic units capable of performing arithmetic operations at various precisions, including those suitable for calculations related to CUDA programs. For example, in at least one embodiment, at least a subset of the floating - point units in each of the compute clusters 1536A - 1536H can be configured to perform 16 - bit or 32 - bit floating - point arithmetic, and different subsets of the floating - point units can be configured to perform 64 - bit floating - point arithmetic.

[0100] In at least one embodiment, multiple instances of GPGPU 1530 can be configured to operate as a compute cluster. Compute clusters 1536A-1536H can implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes I / O hub 1539, and I / O hub 1539 couples GPGPU 1530 to GPU link 1540 that enables direct connection to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect to transmit and receive data to / from other GPGPU 1530s or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 are located in separate data processing systems and communicate via a network device accessible via host interface 1532. In at least one embodiment, GPU link 1540 can be configured to enable connection to a host processor in addition to, or as an alternative to, host interface 1532. In at least one embodiment, GPGPU 1530 can be configured to execute CUDA programs.

[0101] FIG. 16A shows a parallel processor 1600 according to at least one embodiment. In at least one embodiment, the parallel processor 1600 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the parallel processor 1600 can be the GPU 120 from FIG. 1. In at least one embodiment, various components of the parallel processor 1600 can be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits ("ASICs"), or FPGAs.

[0102] In at least one embodiment, the parallel processor 1600 includes a parallel processing unit 1602. In at least one embodiment, the parallel processing unit 1602 includes an I / O unit 1604 that enables communication with other devices, including other instances of the parallel processing unit 1602. In at least one embodiment, the I / O unit 1604 can be directly connected to other devices. In at least one embodiment, the I / O unit 1604 connects to other devices via the use of a hub or switch interface, such as a memory hub 1605. In at least one embodiment, the connection between the memory hub 1605 and the I / O unit 1604 forms a communication link. In at least one embodiment, the I / O unit 1604 is connected to a host interface 1606 and a memory crossbar 1616, the host interface 1606 receives commands targeted at performing processing operations, and the memory crossbar 1616 receives commands targeted at performing memory operations.

[0103] In at least one embodiment, when host interface 1606 receives a command buffer via I / O unit 1604, host interface 1606 can direct a work operation for performing those commands to front end 1608. In at least one embodiment, front end 1608 is coupled to scheduler 1610, and scheduler 1610 is configured to distribute commands or other work items to processing array 1612. In at least one embodiment, scheduler 1610 ensures that processing array 1612 is properly configured and in an active state before tasks are distributed to processing array 1612. In at least one embodiment, scheduler 1610 is implemented via firmware logic running on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 1610 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularities, enabling rapid preemption and context switching of threads running on processing array 1612. In at least one embodiment, host software can attest a workload for scheduling on processing array 1612 via one of a plurality of graphics processing portals. In at least one embodiment, the workload can then be automatically distributed across processing array 1612 by scheduler 1610 logic within a microcontroller that includes scheduler 1610.

[0104] In at least one embodiment, the processing array 1612 can include up to "N" clusters (e.g., cluster 1614A, cluster 1614B ~ cluster 1614N). In at least one embodiment, each cluster 1614A - 1614N of the processing array 1612 can execute a number of simultaneous threads. In at least one embodiment, the scheduler 1610 can use various scheduling and / or work distribution algorithms to allocate work to the clusters 1614A - 1614N of the processing array 1612, and those algorithms can vary according to the workload generated for each type of program or calculation. In at least one embodiment, the scheduling can be dynamically addressed by the scheduler 1610 or can be partially assisted by compiler logic during the compilation of the program logic configured for execution by the processing array 1612. In at least one embodiment, different clusters 1614A - 1614N of the processing array 1612 can be allocated to process different types of programs or to perform different types of calculations.

[0105] In at least one embodiment, the processing array 1612 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 1612 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 1612 can include logic for executing processing tasks including filtering video and / or audio data, performing modeling operations including physical operations, and performing data conversion.

[0106] In at least one embodiment, processing array 1612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1612 can include additional logic, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic, to support the execution of such graphics processing operations. In at least one embodiment, processing array 1612 can be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1602 can transfer data from system memory via I / O unit 1604 for processing. In at least one embodiment, during processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 1622) during processing and then written back to system memory.

[0107] In at least one embodiment, when the parallel processing unit 1602 is used to perform graphics processing, the scheduler 1610 may be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the plurality of clusters 1614A-1614N of the processing array 1612. In at least one embodiment, portions of the processing array 1612 may be configured to perform different types of processing. For example, in at least one embodiment, for display, to create a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data created by one or more of the clusters 1614A-1614N may be stored in a buffer to enable the intermediate data to be transmitted between the clusters 1614A-1614N for further processing.

[0108] In at least one embodiment, processing array 1612 can receive processing tasks to be executed via scheduler 1610, and scheduler 1610 receives commands defining the processing tasks from front end 1608. In at least one embodiment, the processing task can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, scheduler 1610 can be configured to fetch the index corresponding to the task or receive the index from front end 1608. In at least one embodiment, front end 1608 can be configured to ensure that processing array 1612 is configured in an active state before the workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is started.

[0109] In at least one embodiment, each of one or more instances of the parallel processing unit 1602 can be coupled to a parallel processor - memory 1622. In at least one embodiment, the parallel processor - memory 1622 can be accessed via a memory crossbar 1616, and the memory crossbar 1616 can receive memory requests from the processing array 1612 as well as the I / O unit 1604. In at least one embodiment, the memory crossbar 1616 can access the parallel processor - memory 1622 via a memory interface 1618. In at least one embodiment, the memory interface 1618 can include a plurality of partition units (e.g., partition unit 1620A, partition units 1620B - 1620N), and the plurality of partition units can each be coupled to a portion (e.g., a memory unit) of the parallel processor - memory 1622. In at least one embodiment, the number of partition units 1620A - 1620N is configured to be equal to the number of memory units, such that the first partition unit 1620A has a corresponding first memory unit 1624A, the second partition unit 1620B has a corresponding memory unit 1624B, and the Nth partition unit 1620N has a corresponding Nth memory unit 1624N. In at least one embodiment, the number of partition units 1620A - 1620N may not be equal to the number of memory devices.

[0110] In at least one embodiment, the memory units 1624A-1624N can include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM including GDDR memory. In at least one embodiment, the memory units 1624A-1624N can also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 1622, a render target, such as a frame buffer or texture map, can be stored across the memory units 1624A-1624N, enabling the partition units 1620A-1620N to write portions of each render target in parallel. In at least one embodiment, a local instance of the parallel processor memory 1622 can be excluded to be advantageous for a unified memory design that utilizes system memory in conjunction with local cache memory.

[0111] In at least one embodiment, any one of clusters 1614A - 1614N of processing array 1612 can process data to be written to any one of memory units 1624A - 1624N within parallel processor - memory 1622. In at least one embodiment, memory cross - bar 1616 can be configured to transfer the output of each of clusters 1614A - 1614N to any partition unit 1620A - 1620N that can perform additional processing operations on the output, or to another cluster 1614A - 1614N. In at least one embodiment, each of clusters 1614A - 1614N can communicate with memory interface 1618 through memory cross - bar 1616 to read from or write to various external memory devices. In at least one embodiment, memory cross - bar 1616 has a connection to memory interface 1618 for communicating with I / O unit 1604, as well as a connection to a local instance of parallel processor - memory 1622, which enables processing units within different clusters 1614A - 1614N to communicate with system memory or other memory that is not local to parallel processing unit 1602. In at least one embodiment, memory cross - bar 1616 can use virtual channels to separate traffic streams between clusters 1614A - 1614N and partition units 1620A - 1620N.

[0112] In at least one embodiment, multiple instances of the parallel processing unit 1602 can be provided on a single add-in card or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the parallel processing unit 1602 can be configured to interoperate even if the different instances have differences in the number of processing cores, the amount of local parallel processor memory, and / or other configurations. For example, in at least one embodiment, some instances of the parallel processing unit 1602 can include a higher precision floating point unit than other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 1602 or the parallel processor 1600 can be implemented in various configurations and form factors including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0113] FIG. 16B shows a processing cluster 1694 according to at least one embodiment. In at least one embodiment, the processing cluster 1694 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. In at least one embodiment, the processing cluster 1694 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1694 is one of the processing clusters 1614A-1614N of FIG. 16. In at least one embodiment, the processing cluster 1694 can be configured to execute multiple threads in parallel, and the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction multiple data ("SIMD") instruction-issuing technique is used to support parallel execution of multiple threads without providing a plurality of independent instruction units. In at least one embodiment, a single instruction multiple thread ("SIMT") technique is used to support parallel execution of a number of threads that are overall synchronized, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 1694.

[0114] In at least one embodiment, the operation of processing cluster 1694 can be controlled via a pipeline manager 1632 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1632 receives instructions from the scheduler 1610 of FIG. 16 and manages the execution of those instructions via the graphics multiprocessor 1634 and / or the texture unit 1636. In at least one embodiment, the graphics multiprocessor 1634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures can be included within the processing cluster 1694. In at least one embodiment, one or more instances of the graphics multiprocessor 1634 can be included within the processing cluster 1694. In at least one embodiment, the graphics multiprocessor 1634 can process data, and a data crossbar 1640 can be used to distribute the processed data to one of a plurality of possible destinations including other shader units. In at least one embodiment, the pipeline manager 1632 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 1640.

[0115] In at least one embodiment, each graphics multiprocessor 1634 within the processing cluster 1694 can include the same set of function execution logic (e.g., arithmetic logic units, load / store units (「LSU」), etc.). In at least one embodiment, the function execution logic can be configured in a pipeline fashion where new instructions can be issued before the previous instruction has completed. In at least one embodiment, the function execution logic supports various operations including integer and floating point arithmetic, comparison operations, boolean operations, bit shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware can be utilized to perform different operations, and any combination of functional units can exist.

[0116] In at least one embodiment, the instructions sent to processing cluster 1694 configure a thread. In at least one embodiment, a set of threads running across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1634. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during cycles in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1634. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1634, processing can be performed over successive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1634.

[0117] In at least one embodiment, the graphics multi-processor 1634 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multi-processor 1634 can forego an internal cache and use the cache memory (e.g., L1 cache 1648) within the processing cluster 1694. In at least one embodiment, each graphics multi-processor 1634 also has access to a level 2 ("L2") cache within a partition unit (e.g., partition units 1620A - 1620N of FIG. 16A), and those L2 caches are shared among all processing clusters 1694 and can be used to transfer data between threads. In at least one embodiment, the graphics multi-processor 1634 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to the parallel processing unit 1602 can be used as global memory. In at least one embodiment, the processing cluster 1694 includes multiple instances of the graphics multi-processor 1634, and the graphics multi-processor 1634 can share common instructions and data, and the common instructions and data can be stored in the L1 cache 1648.

[0118] In at least one embodiment, each processing cluster 1694 may include an MMU 1645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1645 may be present within the memory interface 1618 of FIG. 16. In at least one embodiment, the MMU 1645 includes a set of page table entries (“PTEs”) used to map virtual addresses to the physical addresses of tiles and optionally cache line indices. In at least one embodiment, the MMU 1645 may include a translation lookaside buffer (“TLB”) or cache, which may be present within the graphics multiprocessor 1634, the L1 cache 1648, or the processing cluster 1694. In at least one embodiment, the physical addresses are processed to spread surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0119] In at least one embodiment, the processing cluster 1694 can be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, the texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1634 and, if necessary, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1634 outputs the processed task to the data crossbar 1640 to provide the processed task to another processing cluster 1694 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1616. In at least one embodiment, the pre-raster operation unit ("pre-ROP") 1642 is configured to receive data from the graphics multiprocessor 1634 and direct the data to the ROP unit, and the ROP unit can be located with a partitioning unit (e.g., partitioning units 1620A - 1620N of FIG. 16) as described herein. In at least one embodiment, the pre-ROP 1642 can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0120] FIG. 16C shows a graphics multi-processor 1696 according to at least one embodiment. In at least one embodiment, the graphics multi-processor 1696 is the graphics multi-processor 1634 of FIG. 16B. In at least one embodiment, the graphics multi-processor 1696 is coupled to the pipeline manager 1632 of the processing cluster 1694. In at least one embodiment, the graphics multi-processor 1696 has an execution pipeline that includes, without limitation, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more GPGPU cores 1662, and one or more LSUs 1666. The GPGPU cores 1662 and the LSUs 1666 are coupled to the cache memory 1672 and the shared memory 1670 via a memory and cache interconnect 1668.

[0121] In at least one embodiment, the instruction cache 1652 receives a stream of instructions to be executed from the pipeline manager 1632. In at least one embodiment, the instructions are cached in the instruction cache 1652 and dispatched for execution by the instruction unit 1654. In at least one embodiment, the instruction unit 1654 can dispatch instructions as a thread group (e.g., a warp), and each thread of the thread group is assigned to a different execution unit within the GPGPU core 1662. In at least one embodiment, instructions can access any of the local, shared, or global address spaces by specifying an address in the unified address space. In at least one embodiment, the address mapping unit 1656 can be used to translate an address in the unified address space to an individual memory address that can be accessed by the LSU 1666.

[0122] In at least one embodiment, the register file 1658 provides a set of registers to the functional units of the graphics multiprocessor 1696. In at least one embodiment, the register file 1658 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 1662, LSU 1666) of the graphics multiprocessor 1696. In at least one embodiment, the register file 1658 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 1658. In at least one embodiment, the register file 1658 is divided among different thread groups being executed by the graphics multiprocessor 1696.

[0123] In at least one embodiment, each GPGPU core 1662 can include an FPU and / or an integer ALU used to execute the instructions of the graphics multiprocessor 1696. The GPGPU cores 1662 can have the same architecture or different architectures. In at least one embodiment, the first portion of the GPGPU core 1662 includes a single-precision FPU and an integer ALU, and the second portion of the GPGPU core 1662 includes a double-precision FPU. In at least one embodiment, the FPU can implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1696 can additionally include one or more fixed-function units or special-function units for performing specific functions such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1662 can also include fixed or special-function logic.

[0124] In at least one embodiment, the GPGPU core 1662 includes SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core 1662 are generated at compile time by a shader compiler or can be automatically generated when executing a compiled program written for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0125] In at least one embodiment, the memory and cache interconnect 1668 is an interconnect network that connects each functional unit of the graphics multiprocessor 1696 to the register file 1658 and the shared memory 1670. In at least one embodiment, the memory and cache interconnect 1668 is a crossbar interconnect that enables the LSU 1666 to implement load and store operations between the shared memory 1670 and the register file 1658. In at least one embodiment, the register file 1658 can operate at the same frequency as the GPGPU core 1662, and thus, the data transfer between the GPGPU core 1662 and the register file 1658 has a very low latency. In at least one embodiment, the shared memory 1670 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1696. In at least one embodiment, the cache memory 1672 can be used as a data cache, for example, to cache texture data communicated between a functional unit and the texture unit 1636. In at least one embodiment, the shared memory 1670 can also be used as a cached and managed program. In at least one embodiment, threads executing on the GPGPU core 1662 can programmatically store data in the shared memory in addition to automatically cached data stored in the cache memory 1672.

[0126] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU is integrated as a core on the same package or chip and can be communicatively coupled to the core via a processor bus / interconnect within the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuit elements / logic to efficiently process these commands / instructions.

[0127] FIG. 17 shows a graphics processor 1700 according to at least one embodiment. In at least one embodiment, the graphics processor 1700 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the graphics processor 1700 can be the GPU 120 from FIG. 1. In at least one embodiment, the graphics processor 1700 includes a ring interconnect 1702, a pipeline front end 1704, a media engine 1737, and graphics cores 1780A-1780N. In at least one embodiment, the ring interconnect 1702 couples the graphics processor 1700 to other graphics processors or other processing units including one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1700 is one of many processors incorporated within a multi-core processing system.

[0128] In at least one embodiment, the graphics processor 1700 receives a batch of commands via the ring interconnect 1702. In at least one embodiment, incoming commands are interpreted by the command streamer 1703 in the pipeline front end 1704. In at least one embodiment, the graphics processor 1700 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1780A - 1780N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1703 supplies the commands to the geometry pipeline 1736. In at least one embodiment, for at least some media processing commands, the command streamer 1703 supplies the commands to the video front end 1734, and the video front end 1734 couples to the media engine 1737. In at least one embodiment, the media engine 1737 includes a video quality engine ("VQE") 1730 for video and image post - processing and a multi - format encode / decode ("MFX") engine 1733 for providing hardware - accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1736 and the media engine 1737 each generate an execution thread for the thread execution resources provided by at least one graphics core 1780A.

[0129] In at least one embodiment, the graphics processor 1700 includes a scalable thread execution resource characterized by modular graphics cores 1780A - 1780N (which may also be referred to as core slices), each having a plurality of sub - cores 1750A - 1750N, 1760A - 1760N (which may also be referred to as core sub - slices). In at least one embodiment, the graphics processor 1700 can have any number of graphics cores 1780A - 1780N. In at least one embodiment, the graphics processor 1700 includes a graphics core 1780A having at least a first sub - core 1750A and a second sub - core 1760A. In at least one embodiment, the graphics processor 1700 is a low - power processor having a single sub - core (e.g., sub - core 1750A). In at least one embodiment, the graphics processor 1700 includes a plurality of graphics cores 1780A - 1780N, each including a first set of sub - cores 1750A - 1750N and a second set of sub - cores 1760A - 1760N. In at least one embodiment, each sub - core among the first sub - cores 1750A - 1750N includes at least an execution unit ("EU": execution unit) 1752A - 1752N and a first set of media / texture samplers 1754A - 1754N. In at least one embodiment, each sub - core among the second sub - cores 1760A - 1760N includes at least an execution unit 1762A - 1762N and a second set of samplers 1764A - 1764N. In at least one embodiment, each sub - core 1750A - 1750N, 1760A - 1760N shares a set of shared resources 1770A - 1770N. In at least one embodiment, the shared resource 1770 includes a shared cache memory and pixel operation logic.

[0130] FIG. 18 shows a processor 1800 according to at least one embodiment. In at least one embodiment, the processor 1800 may include, without limitation, logic circuitry for executing instructions. In at least one embodiment, the processor 1800 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the processor 1800 may be the CPU 102 from FIG. 1. In at least one embodiment, the processor 1800 may execute instructions including, but not limited to, x86 instructions, AMR instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 1810 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled by MMX (trademark) technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point formats may operate on packed data elements with SIMD and Streaming SIMD Extension (SSE) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or more (collectively referred to as "SSEx" technology) may hold such packed data operands. In at least one embodiment, the processor 1810 may execute instructions for accelerating CUDA programs.

[0131] In at least one embodiment, the processor 1800 includes an in-order front end (“front end”) 1801 that fetches instructions to be executed and prepares instructions for later use in the processor pipeline. In at least one embodiment, the front end 1801 may include several units. In at least one embodiment, an instruction prefetcher 1826 fetches instructions from memory and feeds the instructions to an instruction decoder 1828, and the instruction decoder 1828 decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 1828 decodes the received instruction into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) for execution. In at least one embodiment, the instruction decoder 1828 parses the instruction into an opcode and corresponding data and control fields that can be used by the microarchitecture to perform an operation. In at least one embodiment, a trace cache 1830 may assemble the decoded uops into a program-order sequence or trace in a uop queue 1834 for execution. In at least one embodiment, when the trace cache 1830 encounters a complex instruction, a microcode ROM 1832 provides the uops necessary to complete the operation.

[0132] In at least one embodiment, there are instructions that can be converted into a single micro-op, and there are also instructions that require several micro-ops to complete the entire operation. In at least one embodiment, if five or more micro-ops are required to complete an instruction, the instruction decoder 1828 may access the microcode ROM 1832 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing in the instruction decoder 1828. In at least one embodiment, an instruction may be stored in the microcode ROM 1832 if several micro-ops are required to achieve the operation. In at least one embodiment, the trace cache 1830 determines the correct micro-instruction pointer for reading the microcode sequence by referring to an entry point programmable logic array ( "PLA") to complete one or more instructions from the microcode ROM 1832. In at least one embodiment, after the microcode ROM 1832 finishes sequencing the micro-ops for an instruction, the front end 1801 of the machine may resume fetching micro-ops from the trace cache 1830.

[0133] In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 1803 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers for smoothing the flow of instructions and rearranging them in order to optimize performance when instructions flow down the pipeline and are scheduled for execution. The out-of-order execution engine 1803 includes, without limitation, an allocator / register renamer 1840, a memory uop queue 1842, an integer / floating point uop queue 1844, a memory scheduler 1846, a fast scheduler 1802, a slow / general purpose floating point scheduler ("slow / general purpose FP (floating point) scheduler") 1804, and a simple floating point scheduler ("simple FP scheduler") 1806. In at least one embodiment, the fast scheduler 1802, the slow / general purpose floating point scheduler 1804, and the simple floating point scheduler 1806 are collectively also referred to herein as "uop schedulers 1802, 1804, 1806". The allocator / register renamer 1840 allocates the machine buffers and resources required by each uop for execution. In at least one embodiment, the allocator / register renamer 1840 renames logical registers upon entry into the register file. In at least one embodiment, the allocator / register renamer 1840 also allocates an entry for each uop in one of two uop queues, namely the memory uop queue 1842 for memory operations and the integer / floating point uop queue 1844 for non-memory operations, prior to the memory scheduler 1846 and the uop schedulers 1802, 1804, 1806. In at least one embodiment, the uop schedulers 1802, 1804, 1806 determine when a uop is ready to execute based on its dependent input register operand sources being ready and the availability of the execution resources required by the uop to complete its operations.In at least one embodiment, the fast scheduler 1802 of the at least one embodiment may schedule every half of the main clock cycle, and the low-speed / general-purpose floating-point scheduler 1804 and the simple floating-point scheduler 1806 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 1802, 1804, 1806 arbitrate dispatch ports to schedule uops for execution.

[0134] In at least one embodiment, the execution block 1811 includes, but is not limited to, the integer register file / bypass network 1808, the floating-point register file / bypass network (the "FP register file / bypass network") 1810, the address generation units ("AGU": address generation unit) 1812 and 1814, the fast ALUs 1816 and 1818, the low-speed ALU 1820, the floating-point ALU ("FP") 1822, and the floating-point move unit ("FP move") 1824. In at least one embodiment, the integer register file / bypass network 1808 and the floating-point register file / bypass network 1810 are also referred to herein as the "register files 1808, 1810". In at least one embodiment, the AGUs 1812 and 1814, the fast ALUs 1816 and 1818, the low-speed ALU 1820, the floating-point ALU 1822, and the floating-point move unit 1824 are also referred to herein as the "execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824". In at least one embodiment, the execution block may include any number and type of register files, bypass networks, address generation units, and execution units, including (including 0) in any combination.

[0135] In at least one embodiment, register files 1808, 1810 may be disposed between uop schedulers 1802, 1804, 1806 and execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824. In at least one embodiment, integer register file / bypass network 1808 performs integer operations. In at least one embodiment, floating point register file / bypass network 1810 performs floating point operations. In at least one embodiment, each of register files 1808, 1810 may include, without limitation, a bypass network, which may bypass or forward a just-completed result that has not yet been written to the register file to a new dependent uop. In at least one embodiment, register files 1808, 1810 may communicate data with each other. In at least one embodiment, integer register file / bypass network 1808 may include, without limitation, two separate register files, namely one register file for lower 32-bit data and a second register file for upper 32-bit data. In at least one embodiment, since floating point instructions typically have operands with a width of 64 to 128 bits, floating point register file / bypass network 1810 may include, without limitation, entries with a width of 128 bits.

[0136] In at least one embodiment, execution units 1812, 1814, 1816, 1818, 1820, 1822, 1824 may execute instructions. In at least one embodiment, register files 1808, 1810 store integer and floating point data operand values that microinstructions need to execute. In at least one embodiment, processor 1800 may include any number and combination of execution units 1812, 1814, 1816, 1818, 1820, 1822, 1824, without limitation. In at least one embodiment, floating point ALU 1822 and floating point move unit 1824 may execute floating point, MMX, SIMD, AVX and SSE, or other operations. In at least one embodiment, floating point ALU 1822 may include a 64-bit floating point divider for executing division, square root, and remainder micro-ops, without limitation. In at least one embodiment, instructions with floating point values may be handled by floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 1816, 1818. In at least one embodiment, fast ALUs 1816, 1818 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, slow ALU 1820 may include integer execution hardware for long latency type operations such as multipliers, shifts, flag logic, and branch processing, without limitation, so most complex integer operations proceed to slow ALU 1820. In at least one embodiment, memory load / store operations may be performed by AGUs 1812, 1814. In at least one embodiment, fast ALU 1816, fast ALU 1818, and slow ALU 1820 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 1816, fast ALU 1818, and slow ALU 1820 may be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, floating point ALU 1822 and floating point move unit 1824 may be implemented to support various operands with various bit widths.In at least one embodiment, the floating point ALU 1822 and the floating point shift unit 1824 can operate on 128-bit wide packed data operands combined with SIMD and multimedia instructions.

[0137] In at least one embodiment, the uop schedulers 1802, 1804, 1806 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, since uops can be speculatively scheduled and executed in the processor 1800, the processor 1800 may also include logic for handling memory misses. In at least one embodiment, when a data load misses in the data cache, there may be ongoing dependent operations in the pipeline that has passed through a scheduler with temporarily inaccurate data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use inaccurate data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0138] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be one that is accessible from outside the processor (from the perspective of the programmer). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within a processor using any number of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, combinations of dedicated physical registers and physically registers dynamically allocated, and the like. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0139] FIG. 19 shows a processor 1900 according to at least one embodiment. In at least one embodiment, the processor 1900 is included in the systems disclosed in FIGS. 1 - 3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the processor 1900 can be the CPU 102 from FIG. 1. In at least one embodiment, the processor 1900 includes, without limitation, one or more processor cores (“cores”) 1902A - 1902N, an integrated memory controller 1914, and an integrated graphics processor 1908. In at least one embodiment, the processor 1900 can include additional cores up to an additional processor core 1902N represented by the dashed box. In at least one embodiment, each of the processor cores 1902A - 1902N includes one or more internal cache units 1904A - 1904N. In at least one embodiment, each processor core also has access to one or more shared cache units 1906.

[0140] In at least one embodiment, the internal cache units 1904A - 1904N and the shared cache unit 1906 represent a cache memory hierarchy within the processor 1900. In at least one embodiment, the cache memory units 1904A - 1904N can include at least one level of instruction and data caches within each processor core, and one or more levels of shared intermediate-level caches such as L2, L3, level 4 (“L4”), or other levels of caches, where the highest level of cache before external memory is classified as the LLC. In at least one embodiment, cache coherence logic maintains coherence among the various cache units 1906 and 1904A - 1904N.

[0141] In at least one embodiment, the processor 1900 may also include a set of one or more bus controller units 1916 and a system agent core 1910. In at least one embodiment, the one or more bus controller units 1916 manage a set of peripheral buses such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 1910 provides management functionality for various processor components. In at least one embodiment, the system agent core 1910 includes one or more integrated memory controllers 1914 for managing access to various external memory devices (not shown).

[0142] In at least one embodiment, one or more of the processor cores 1902A - 1902N include support for simultaneous multithreading. In at least one embodiment, the system agent core 1910 includes components for coordinating and operating the processor cores 1902A - 1902N during multithreaded processing. In at least one embodiment, the system agent core 1910 may additionally include a power control unit ( "PCU"), and the PCU includes logic and components for adjusting the power state of one or more of the processor cores 1902A - 1902N and the graphics processor 1908.

[0143] In at least one embodiment, the processor 1900 additionally includes a graphics processor 1908 for performing graphics processing operations. In at least one embodiment, the graphics processor 1908 is coupled to a system agent core 1910 that includes a shared cache unit 1906 and one or more integrated memory controllers 1914. In at least one embodiment, the system agent core 1910 also includes a display controller 1911 for driving the graphics processor output to one or more attached displays. In at least one embodiment, the display controller 1911 can also be a separate module coupled to the graphics processor 1908 via at least one interconnect, or can be integrated within the graphics processor 1908.

[0144] In at least one embodiment, a ring-based interconnect unit 1912 is used to couple the internal components of the processor 1900. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switched interconnects, or other techniques can be used. In at least one embodiment, the graphics processor 1908 is coupled to the ring interconnect 1912 via an I / O link 1913.

[0145] In at least one embodiment, the I / O link 1913 represents at least one of a plurality of types of I / O interconnects that includes an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1918 such as an eDRAM module. In at least one embodiment, each of the processor cores 1902A - 1902N and the graphics processor 1908 uses the embedded memory module 1918 as a shared LLC.

[0146] In at least one embodiment, processor cores 1902A - 1902N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 1902A - 1902N are heterogeneous from the perspective of the ISA, where one or more of processor cores 1902A - 1902N execute a common instruction set and one or more other cores of processor cores 1902A - 19 - 02N execute a subset of the common instruction set, or a different instruction set. In at least one embodiment, processor cores 1902A - 1902N are heterogeneous from the perspective of the microarchitecture, where one or more cores with a relatively high power consumption are coupled with one or more cores with a lower power consumption. In at least one embodiment, processor 1900 may be implemented on one or more chips or as a SoC integrated circuit.

[0147] FIG. 20 shows a graphics processor core 2000 according to at least one of the embodiments described. In at least one embodiment, the graphics processor core 2000 is included in the systems disclosed in FIGS. 1 - 3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the graphics processor core 2000 can be the GPU cores 125, 130, and 135 from FIG. 1. In at least one embodiment, the graphics processor core 2000 is included within a graphics core array. In at least one embodiment, the graphics processor core 2000, sometimes referred to as a core slice, can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2000 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 2000 can include a fixed - function block 2030 coupled to a plurality of sub - cores 2001A - 2001F, also referred to as sub - slices, which include modular blocks of general - purpose and fixed - function logic.

[0148] In at least one embodiment, the fixed - function block 2030 can include a geometry / fixed - function pipeline 2036 that is shared by all sub - cores in the graphics processor 2000, for example, in a lower - performance and / or lower - power graphics processor implementation. In at least one embodiment, the geometry / fixed - function pipeline 2036 includes a 3D fixed - function pipeline, a video front - end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages the unified return buffer.

[0149] In at least one embodiment, the fixed function block 2030 also includes a graphics SoC interface 2037, a graphics microcontroller 2038, and a media pipeline 2039. The graphics SoC interface 2037 provides an interface between the graphics core 2000 and other processor cores within the SoC integrated circuit. In at least one embodiment, the graphics microcontroller 2038 is a programmable sub-processor configurable to manage various functions of the graphics processor 2000, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2039 includes logic for facilitating the decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2039 implements media operations via requests to the compute logic or sampling logic within sub-cores 2001-2001F.

[0150] In at least one embodiment, the SoC interface 2037 enables the graphics core 2000 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, where the other components within the SoC include memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, the SoC interface 2037 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, enable the use of global memory atomics that can be shared between the graphics core 2000 and the CPU within the SoC, and / or implement it. In at least one embodiment, the SoC interface 2037 also implements power management control for the graphics core 2000 and can enable an interface between the clock domain of the graphics core 2000 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2037 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, the commands and instructions can be dispatched to the media pipeline 2039 when media operations are to be performed, or to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipelines 2036, geometry and fixed-function pipelines 2014) when graphics processing operations are to be performed.

[0151] In at least one embodiment, the graphics microcontroller 2038 may be configured to perform various scheduling and management tasks for the graphics core 2000. In at least one embodiment, the graphics microcontroller 2038 may perform graphics and / or calculate workload scheduling for the execution unit (EU) arrays 2002A - 2002F, 2004A - 2004F within the sub - cores 2001A - 2001F and various graphics parallel engines. In at least one embodiment, the host software running on the CPU core of the SoC including the graphics core 2000 may submit a workload to one of a plurality of graphics processor doorbells, and this doorbell calls a scheduling operation for the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should run next, submitting the workload to the command streamer, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2038 may also promote a low - power or idle state for the graphics core 2000 and provide the graphics core 2000 with the ability to save and restore registers within the graphics core 2000 across low - power state transitions, independent of the operating system and / or the graphics driver software on the system.

[0152] In at least one embodiment, the graphics core 2000 can have up to N modular sub-cores, more or fewer than the six sub-cores 2001A - 2001F shown. For each set of N sub-cores, in at least one embodiment, the graphics core 2000 can also include shared function logic 2010, shared and / or cache memory 2012, geometry / fixed function pipeline 2014, and additional fixed function logic 2016 for accelerating various graphics and calculating processing operations. In at least one embodiment, the shared function logic 2010 can include logic units (e.g., samplers, math, and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2000. The shared and / or cache memory 2012 can be an LLC for the N sub-cores 2001A - 2001F within the graphics core 2000 and can also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, the geometry / fixed function pipeline 2014 can be included instead of the geometry / fixed function pipeline 2036 within the fixed function block 2030 and can include the same or similar logic units.

[0153] In at least one embodiment, the graphics core 2000 includes additional fixed function logic 2016 which can include various fixed function acceleration logic for use by the graphics core 2000. In at least one embodiment, the additional fixed function logic 2016 includes an additional geometry pipeline for use in position only shading. In position only shading, there are at least two geometry pipelines, namely the full geometry pipeline within the geometry / fixed function pipelines 2016, 2036, and a cull pipeline, which can be an additional geometry pipeline included within the additional fixed function logic 2016. In at least one embodiment, the cull pipeline is a reduced version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can execute different instances of an application, and each instance has a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, which enables shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades the vertex position attributes without performing rasterization and rendering of pixels to the frame buffer, so the cull pipeline logic within the additional fixed function logic 2016 can execute the position shader in parallel with the main application and generate critical results faster than the full pipeline overall. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles have been culled. In at least one embodiment, the full pipeline (which may be referred to as a replay pipeline in this instance) can consume the visibility information, skip the culled triangles, and shade only the visible triangles, which are ultimately passed to the rasterization phase.

[0154] In at least one embodiment, the additional fixed function logic 2016 can also include general-purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0155] In at least one embodiment, each of the graphics sub-cores 2001A - 2001F includes a set of execution resources, and the set of execution resources can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 2001A - 2001F include a plurality of EU arrays 2002A - 2002F, 2004A - 2004F, thread dispatch and inter-thread communication (TD / IC) logic 2003A - 2003F, 3D (e.g., texture) samplers 2005A - 2005F, media samplers 2006A - 2006F, shader processors 2007A - 2007F, and shared local memory (SLM) 2008A - 2008F. The EU arrays 2002A - 2002F, 2004A - 2004F each include a plurality of execution units, and the plurality of execution units are GPGPUs capable of performing floating-point and integer / fixed-point logical operations in the service of graphics operations, media operations, or compute operations including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2003A - 2003F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between the threads executing on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2005A - 2005F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D sampler can read texture data in different ways based on the configured sample state and texture format associated with a given texture. In at least one embodiment, the media samplers 2006A - 2006F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each of the graphics sub-cores 2001A - 2001F can alternatively include unified 3D and media samplers. In at least one embodiment, threads executing on execution units within each of the sub-cores 2001A - 2001F can utilize shared local memories 2008A - 2008F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0156] FIG. 21 shows a parallel processing unit (PPU) 2100 according to at least one embodiment. In at least one embodiment, the PPU 2100 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the PPU 2100 can be the GPU 120 from FIG. 1. In at least one embodiment, the PPU 2100 is composed of machine-readable code that, when executed by the PPU 2100, causes the PPU 2100 to implement some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2100 is a multi-threaded processor, and the multi-threaded processor is implemented on one or more integrated circuit devices and utilizes multi-threading as a latency hiding technique designed to process computer-readable instructions (also simply called instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by the PPU 2100. In at least one embodiment, the PPU 2100 is a GPU configured to implement a graphics rendering pipeline for processing 3D graphics data to generate 2D image data for display on a display device such as an LCD device. In at least one embodiment, the PPU 2100 is utilized to perform calculations such as linear algebra operations and machine learning operations. FIG. 21 shows an exemplary parallel processor for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture that can be implemented in at least one embodiment.

[0157] In at least one embodiment, one or more PPU2100s are configured to accelerate high performance computing (HPC), data centers, and machine learning applications. In at least one embodiment, one or more PPU2100s are configured to accelerate CUDA programs. In at least one embodiment, the PPU2100 includes, without limitation, an I / O unit 2106, a front-end unit 2110, a scheduler unit 2112, a work distribution unit 2114, a hub 2116, a crossbar (X bar) 2120, one or more general processing clusters (GPCs) 2118, and one or more partition units (memory partition units) 2122. In at least one embodiment, the PPU2100 is connected to a host processor or another PPU2100 via one or more high-speed GPU interconnects (GPU interconnects) 2108. In at least one embodiment, the PPU2100 is connected to a host processor or other peripheral devices via a system bus or interconnect 2102. In at least one embodiment, the PPU2100 is connected to a local memory with one or more memory devices (memory). In at least one embodiment, the memory device 2104 includes, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured as and / or configurable as a high-bandwidth memory (HBM) subsystem in which multiple DRAM dies are stacked within each device.

[0158] In at least one embodiment, the high-speed GPU interconnect 2108 may refer to a wire-based multi-lane communication link, which is used by the system to scale and include one or more PPUs 2100 in combination with one or more CPUs, and supports cache coherence and CPU mastering between the PPU 2100 and the CPU. In at least one embodiment, data and / or commands are transmitted to / from other units of the PPU 2100, such as one or more copy engines, video encoders, video decoders, power management units, and other components that may not be explicitly shown in FIG. 21, through the hub 2116 by the high-speed GPU interconnect 2108.

[0159] In at least one embodiment, the I / O unit 2106 is configured to communicate (e.g., commands, data) with a host processor (not shown in FIG. 21) via the system bus 2102. In at least one embodiment, the I / O unit 2106 communicates with the host processor directly via the system bus 2102 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, the I / O unit 2106 may communicate with one or more other processors such as one or more of the PPUs 2100 via the system bus 2102. In at least one embodiment, the I / O unit 2106 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, the I / O unit 2106 implements an interface for communicating with external devices.

[0160] In at least one embodiment, the I / O unit 2106 decodes packets received via the system bus 2102. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2100 to perform various operations. In at least one embodiment, the I / O unit 2106 sends the decoded commands to various other units of the PPU 2100 specified by the commands. In at least one embodiment, the commands are sent to the front-end unit 2110 and / or to other units of the PPU 2100 such as the hub 2116 or one or more copy engines, video encoders, video decoders, power management units (not explicitly shown in FIG. 21). In at least one embodiment, the I / O unit 2106 is configured to route communications between and among various logical units of the PPU 2100.

[0161] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2100 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory that is accessible (e.g., readable / writable) by both the host processor and the PPU 2100, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2102 via memory requests sent via the system bus 2102 by the I / O unit 2106. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2100, whereby the front-end unit 2110 receives a pointer to one or more command streams, manages the one or more command streams, reads commands from the command streams, and forwards the commands to various units of the PPU 2100.

[0162] In at least one embodiment, the front-end unit 2110 is coupled to a scheduler unit 2112 that configures the various GPCs 2118 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2112 is configured to track state information related to the various tasks managed by the scheduler unit 2112, where the state information can indicate which of the GPCs 2118 a task is assigned to, whether the task is active or inactive, the priority level associated with the task, and the like. In at least one embodiment, the scheduler unit 2112 manages the execution of multiple tasks on one or more of the GPCs 2118.

[0163] In at least one embodiment, the scheduler unit 2112 is coupled to a work distribution unit 2114 configured to dispatch tasks for execution on the GPC 2118. In at least one embodiment, the work distribution unit 2114 tracks the number of scheduled tasks received from the scheduler unit 2112, and the work distribution unit 2114 manages a pending task pool and an active task pool for each of the GPCs 2118. In at least one embodiment, the pending task pool comprises a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2118, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2118, such that when one of the GPCs 2118 completes execution of a task, that task is removed from the active task pool for the GPC 2118 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2118. In at least one embodiment, when an active task is idle on the GPC 2118, such as while waiting for data dependencies to be resolved, the active task is removed from the GPC 2118 and returned to the pending task pool, during which time another task in the pending task pool is selected and scheduled for execution on the GPC 2118.

[0164] In at least one embodiment, the work distribution unit 2114 communicates with one or more GPCs 2118 via an X-bar 2120. In at least one embodiment, the X-bar 2120 is an interconnect network that couples many of the units of the PPU 2100 to other units of the PPU 2100 and may be configured to couple the work distribution unit 2114 to a particular GPC 2118. In at least one embodiment, one or more other units of the PPU 2100 may also be connected to the X-bar 2120 via a hub 2116.

[0165] In at least one embodiment, the task is managed by the scheduler unit 2112 and dispatched to one of the GPCs 2118 by the work distribution unit 2114. The GPC 2118 is configured to process the task and generate a result. In at least one embodiment, the result can be consumed by other tasks within the GPC 2118, routed to a different GPC 2118 via the X-bar 2120, or stored in the memory 2104. In at least one embodiment, the result can be written to the memory 2104 via the partition unit 2122, and the partition unit 2122 implements a memory interface for reading and writing data to / from the memory 2104. In at least one embodiment, the result can be sent to another PPU 2104 or CPU via the high-speed GPU interconnect 2108. In at least one embodiment, the PPU 2100 includes U partition units 2122 equal to the number of separate individual memory devices 2104 coupled to the PPU 2100, without limitation.

[0166] In at least one embodiment, the host processor executes a driver kernel, and the driver kernel implements an application programming interface ("API") that enables one or more applications running on the host processor to schedule operations for execution on the PPU 2100. In at least one embodiment, multiple compute applications are executed simultaneously by the PPU 2100, and the PPU 2100 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2100, and the driver kernel outputs the tasks to one or more streams being processed by the PPU 2100. In at least one embodiment, each task comprises one or more groups of related threads, sometimes referred to as warps. In at least one embodiment, a warp comprises multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that include instructions to perform a task and exchange data through shared memory.

[0167] FIG. 22 shows a GPC2200 according to at least one embodiment. In at least one embodiment, the GPC2200 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. In at least one embodiment, the GPC2200 is the GPC2118 of FIG. 21. In at least one embodiment, each GPC2200 includes, without limitation, several hardware units for processing tasks, and each GPC2200 includes, without limitation, a pipeline manager 2202, a pre-raster operation unit ("PROP") 2204, a raster engine 2208, a work distribution crossbar ("WDX"), an MMU 2218, one or more data processing clusters ("DPC"), and any suitable combination of parts.

[0168] In at least one embodiment, the operation of GPC2200 is controlled by pipeline manager 2202. In at least one embodiment, pipeline manager 2202 manages the configuration of one or more DPCs 2206 for processing tasks assigned to GPC2200. In at least one embodiment, pipeline manager 2202 configures at least one of the one or more DPCs 2206 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 2206 is configured to execute a vertex shader program on programmable streaming multiprocessor ("SM") 2214. In at least one embodiment, pipeline manager 2202 is configured to route packets received from a work distribution unit to appropriate logical units within GPC2200. In at least one embodiment, some packets may be routed to fixed function hardware units in PROP2204 and / or raster engine 2208, and other packets may be routed to DPC2206 for processing by primitive engine 2212 or SM2214. In at least one embodiment, pipeline manager 2202 configures at least one of DPCs 2206 to implement a computing pipeline. In at least one embodiment, pipeline manager 2202 configures at least one of DPCs 2206 to execute at least a portion of a CUDA program.

[0169] In at least one embodiment, the PROP unit 2204 is configured to route data generated by the raster engine 2208 and the DPC 2206 to a raster operation (「ROP」) unit in a partition unit, such as the memory partition unit 2122 described in more detail above in conjunction with FIG. 21. In at least one embodiment, the PROP unit 2204 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2208 includes some fixed function hardware units configured to perform various raster operations, including but not limited to. In at least one embodiment, the raster engine 2208 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile combination engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates a plane equation for the geometric primitive defined by the vertices, and the plane equation is transmitted to the coarse raster engine to generate coverage information for the primitive (e.g., x, y coverage masks for tiles), and the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z-test are culled and transmitted to the clipping engine, where fragments outside the frustum are clipped. In at least one embodiment, fragments that pass clipping and culling are passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2208 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2206.

[0170] In at least one embodiment, each DPC2206 included in GPC2200 includes, without limitation, an M Pipe Controller (“MPC”) 2210, a primitive engine 2212, one or more SMs 2214, and any suitable combination thereof. In at least one embodiment, MPC2210 controls the operation of DPC2206 to route packets received from pipeline manager 2202 to appropriate units in DPC2206. In at least one embodiment, packets related to vertices are routed to a primitive engine 2212 configured to fetch vertex attributes related to the vertices from memory, whereas, in contrast, packets related to shader programs can be sent to SM2214.

[0171] In at least one embodiment, SM2214 includes a programmable streaming processor configured to process tasks represented by, but not limited to, a number of threads. In at least one embodiment, SM2214 is multi-threaded and configured to execute multiple threads (e.g., 32 threads) from a particular group of threads simultaneously, implements a SIMD architecture, and each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instruction. In at least one embodiment, SM2214 implements a SIMT architecture, and each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable simultaneous processing between warps and serial execution within a warp when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to enable equal simultaneous processing between all threads, within and between warps. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instruction are converged and executed in parallel for better efficiency. At least one embodiment of SM2214 is described in further detail in conjunction with FIG. 23.

[0172] In at least one embodiment, the MMU 2218 provides an interface between the GPC 2200 and a memory partition unit (e.g., partition unit 2122 of FIG. 21), and the MMU 2218 provides virtual address to physical address translation, memory protection, and mediation of memory requests. In at least one embodiment, the MMU 2218 provides one or more translation lookaside buffers (TLBs) for performing virtual address to physical address translation in memory.

[0173] FIG. 23 shows a streaming multiprocessor ( "SM") 2300 according to at least one embodiment. In at least one embodiment, SM 2300 is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, SM 2300 can be part of the GPU 120 from FIG. 1. In at least one embodiment, SM 2300 is the SM 2214 of FIG. 22. In at least one embodiment, SM 2300 includes, without limitation, an instruction cache 2302, one or more scheduler units 2304, a register file 2308, one or more processing cores ( "cores") 2310, one or more special function units ( "SFUs") 2312, one or more LSUs 2314, an interconnect network 2316, a shared memory / L1 cache 2318, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPC of the parallel processing unit (PPU), and each task is assigned to a specific data processing cluster (DPC) within the GPC. When the task is related to a shader program, the task is assigned to one of the SMs 2300. In at least one embodiment, the scheduler unit 2304 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SM 2300. In at least one embodiment, the scheduler unit 2304 schedules thread blocks for execution as warps of parallel threads, and each thread block is assigned at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, the scheduler unit 2304 manages multiple different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from multiple different cooperating groups to various functional units (e.g., processing cores 2310, SFUs 2312, and LSUs 2314) during each clock cycle.

[0174] In at least one embodiment, a "coordination group" may refer to a programming model for organizing a group of communicating threads, where the programming model enables a developer to express the granularity at which threads communicate, enabling a richer and more efficient expression of parallel decomposition. In at least one embodiment, a coordination startup API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, APIs of conventional programming models provide a single simple construct for synchronizing coordinated threads, namely a barrier (e.g., the syncthreads() function) across all threads of a thread block. However, in at least one embodiment, a programmer can define a group of threads at a granularity smaller than a thread block, synchronize within the defined group, and enable higher performance, design flexibility, and software reuse in the form of a collective functional interface across the entire set of groups. In at least one embodiment, a coordination group enables a programmer to explicitly define a group of threads at sub-block granularity and multi-block granularity and perform collective operations such as synchronization on the threads within the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, thereby enabling libraries and utility functions to synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, coordination group primitives enable new patterns of coordinated parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the grid of thread blocks.

[0175] In at least one embodiment, the dispatch unit 2306 is configured to send instructions to one or more of the functional units, and the scheduler unit 2304 includes two dispatch units 2306 that, without limitation, enable two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2304 includes a single dispatch unit 2306 or an additional dispatch unit 2306.

[0176] In at least one embodiment, each SM2300 includes, in at least one embodiment, a register file 2308 that provides a set of registers to the functional units of the SM2300, without limitation. In at least one embodiment, the register file 2308 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2308. In at least one embodiment, the register file 2308 is divided among different warps being executed by the SM2300, and the register file 2308 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2300 includes, without limitation, a plurality of L processing cores 2310. In at least one embodiment, the SM2300 includes, without limitation, a large number (e.g., 128 or more) of individual processing cores 2310. In at least one embodiment, each processing core 2310 includes, without limitation, fully pipelined, single-precision, double-precision, and / or mixed-precision processing units, which include, without limitation, floating-point arithmetic logic units and integer arithmetic logic units. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2310 includes, without limitation, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0177] In at least one embodiment, a tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included within processing core 2310. In at least one embodiment, a tensor core is configured to perform deep learning matrix arithmetic, such as convolutional operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0178] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the sum matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, a tensor core operates on 16-bit floating point input data with a 32-bit floating point sum. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating point addition with other intermediate products for a 4×4×4 matrix multiplication. In at least one embodiment, tensor cores are used to perform much larger two-dimensional or even higher-dimensional matrix operations built from these smaller elements. In at least one embodiment, an API, such as the CUDA-C++ API, exposes special matrix load operations, matrix multiply and accumulate operations, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, a warp-level interface assumes a 16×16 size matrix spanning all 32 threads of a warp.

[0179] In at least one embodiment, each SM2300 includes M SFU2312s that perform special functions (such as, but not limited to, attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFU2312 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFU2312 includes, but is not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (such as a 2D array of texels) from memory and a sample texture map and create sampled texture values for use in a shader program executed by the SM2300. In at least one embodiment, the texture map is stored in the shared memory / L1 cache 2318. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (such as texture maps with different levels of detail). In at least one embodiment, each SM2300 includes, but is not limited to, two texture units.

[0180] In at least one embodiment, each SM2300 includes N LSU2314s that implement load and store operations between the shared memory / L1 cache 2318 and the register file 2308. In at least one embodiment, each SM2300 includes, but is not limited to, an interconnect network 2316 that connects each of the functional units to the register file 2308 and connects the LSU2314 to the register file 2308 and the shared memory / L1 cache 2318. In at least one embodiment, the interconnect network 2316 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 2308 and connect the LSU2314 to the register file 2308 and a memory location in the shared memory / L1 cache 2318.

[0181] In at least one embodiment, the shared memory / L1 cache 2318 is an array of on-chip memory that enables data storage and communication between the SM 2300 and the primitive engine and between threads within the SM 2300. In at least one embodiment, the shared memory / L1 cache 2318 has a storage capacity of, but not limited to, 128 KB and is in the path from the SM 2300 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2318 is used to cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2318, the L2 cache, and the memory are auxiliary stores.

[0182] In at least one embodiment, combining a data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity can be used as a cache by a program that does not use shared memory, such as when the shared memory is configured to use half of the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2318 enables the shared memory / L1 cache 2318 to provide high-bandwidth and low-latency access to frequently reused data while functioning as a high-throughput pipe for streaming data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed to create a much simpler programming model. In at least one embodiment and in a general-purpose parallel computing configuration, the work distribution unit directly assigns and distributes blocks of threads to DPCs. In at least one embodiment, the threads within a block execute the same program, perform calculations, communicate between threads using the shared memory / L1 cache 2318, read and write to global memory through the shared memory / L1 cache 2318 and the memory partition unit using the LSU 2314, using unique thread IDs in the calculations to ensure that each thread generates a unique result. In at least one embodiment, when configured for general-purpose parallel computing, the SM2300 writes commands that can be used by the scheduler unit 2304 to launch new work on a DPC.

[0183] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in a SoC together with one or more other devices such as an additional PPU, memory, a RISC CPU, an MMU, a digital-to-analog converter (DAC).

[0184] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on the motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU (iGPU) included in the chipset of the motherboard.

[0185] Software constructs for general-purpose computing The following figures describe exemplary software constructs for implementing at least one embodiment, without limitation.

[0186] FIG. 24 shows a software stack of a programming platform according to at least one embodiment. In at least one embodiment, the software stack of the programming platform is included in the systems disclosed in FIGS. 1-3 and can communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. For example, the software stack of the programming platform can be the CUDA software stack 206 from FIG. 2. In at least one embodiment, the programming platform is a platform for leveraging the hardware on a computing system to accelerate compute tasks. In at least one embodiment, the programming platform can be accessible to software developers through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (``ROCm''), OpenCL (OpenCL (trademark) is developed by the Khronos group), SYCL, or Intel One API.

[0187] In at least one embodiment, the software stack 2400 of the programming platform provides an execution environment for the application 2401. In at least one embodiment, the application 2401 can include any computer software that can be launched on the software stack 2400. In at least one embodiment, the application 2401 can include, without limitation, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0188] In at least one embodiment, the application 2401 and the software stack 2400 operate on the hardware 2407. In at least one embodiment, the hardware 2407 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices that support the programming platform. In at least one embodiment, such as in the case of CUDA, the software stack 2400 is vendor-specific and may be compatible only with devices from a particular vendor or vendors. In at least one embodiment, such as in the case of OpenCL, the software stack 2400 can be used with devices from different vendors. In at least one embodiment, the hardware 2407 includes a host connected to another device that can be accessed to perform compute tasks via application programming interface (“API”) calls. In at least one embodiment, in contrast to the host within the hardware 2407, which can include, without limitation, a CPU (although it can also include a compute device) and its memory, the devices within the hardware 2407 can include, without limitation, GPUs, FPGAs, AI engines, or other compute devices (although it can also include a CPU) and their memory.

[0189] In at least one embodiment, the software stack 2400 of the programming platform includes, without limitation, some libraries 2403, a runtime 2405, and a device kernel driver 2406. In at least one embodiment, each of the libraries 2403 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2403 may include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2403 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2403 may include functions for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2403 are related to corresponding APIs 2402 that may include one or more APIs that expose the functions implemented in the libraries 2403.

[0190] In at least one embodiment, the application 2401 is written as source code that is compiled into executable code, as will be described in more detail below in conjunction with FIGS. 29-31. In at least one embodiment, the executable code of the application 2401 can operate, at least in part, on an execution environment provided by the software stack 2400. In at least one embodiment, during execution of the application 2401, code that needs to operate on the device, as opposed to the host, may be reached. In at least one embodiment, in such a case, the runtime 2405 may be called to load and start the essential code on the device. In at least one embodiment, the runtime 2405 may include any technically feasible runtime system capable of supporting the execution of the application S01.

[0191] In at least one embodiment, the runtime 2405 is implemented as one or more runtime libraries associated with the corresponding API(s) shown as (one or more) APIs 2404. In at least one embodiment, one or more of such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization. In at least one embodiment, the memory management function may include, but is not limited to, functions for allocating, deallocating, copying device memory, and transferring data between host memory and device memory. In at least one embodiment, the execution control function may include, but is not limited to, functions for launching a function (which may be called a "kernel" when the function is a global function callable from the host) on the device and setting attribute values in a buffer maintained by a runtime library for a given function to be executed on the device.

[0192] In at least one embodiment, the runtime library and the corresponding API(s) 2404 may be implemented in any technically feasible manner. In at least one embodiment, a (or any number of) API(s) may expose a low-level set of functions for fine-grained control of the device, while another (or any number of) API(s) may expose a higher-level set of such functions. In at least one embodiment, a high-level runtime API may be built on top of a low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0193] In at least one embodiment, the device kernel driver 2406 is configured to facilitate communication with underlying devices. In at least one embodiment, the device kernel driver 2406 may provide low-level functionality that APIs, such as the (one or more) APIs 2404, and / or other software rely on. In at least one embodiment, the device kernel driver 2406 may be configured to compile intermediate representation (“IR”) code to binary code at runtime. In at least one embodiment, in the case of CUDA, the device kernel driver 2406 may compile Parallel Thread Execution (“PTX”) IR code, which is not hardware-specific, to binary code for a particular target device at runtime (with caching of the compiled binary code), which may also be referred to as “finalizing” the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not exist when the source code is first compiled to PTX code. Alternatively, in at least one embodiment, the device source code may be compiled to binary code offline without the device kernel driver 2406 needing to compile the IR code at runtime.

[0194] FIG. 25 shows a CUDA implementation of the software stack 2400 of FIG. 24 according to at least one embodiment. In at least one embodiment, a CUDA software stack 2500 on which an application 2501 can be launched includes a CUDA library 2503, a CUDA runtime 2505, a CUDA driver 2507, and a device kernel driver 2508. In at least one embodiment, the CUDA software stack 2500 executes on hardware 2509, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California.

[0195] In at least one embodiment, application 2501, CUDA runtime 2505, and device kernel driver 2508 may each implement functionality similar to application 2401, runtime 2405, and device kernel driver 2406, respectively, as described above in conjunction with FIG. 24. In at least one embodiment, CUDA driver 2507 includes a library (libcuda.so) that implements CUDA driver API 2506. In at least one embodiment, similar to CUDA runtime API 2504 implemented by CUDA runtime library (cudart), CUDA driver API 2506 may expose functions for, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, CUDA driver API 2506 differs from CUDA runtime API 2504 in that CUDA runtime API 2504 simplifies device code management by providing implicit initialization, context management (similar to a process), and module management (similar to a dynamically loaded library). In at least one embodiment, in contrast to high-level CUDA runtime API 2504, CUDA driver API 2506 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, CUDA driver API 2506 may expose functions for context management that are not exposed by CUDA runtime API 2504. In at least one embodiment, CUDA driver API 2506 also supports OpenCL, for example, in addition to CUDA runtime API 2504, without language dependence. Further, in at least one embodiment, the development library including CUDA runtime 2505 may be considered separate from the driver components including user-mode CUDA driver 2507 and kernel-mode device driver 2508 (sometimes referred to as the "display" driver).

[0196] In at least one embodiment, the CUDA library 2503 may include, but is not limited to, a math library, a deep learning library, a parallel algorithm library, and / or a signal / image / video processing library, which can be utilized by parallel computing applications such as the application 2501. In at least one embodiment, the CUDA library 2503 may include, among other things, the cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (BLAS) for performing linear algebra operations, the cuFFT library for calculating the fast Fourier transform (FFT), and the cuRAND library for generating random numbers, etc., which may include math libraries. In at least one embodiment, the CUDA library 2503 may include, among other things, deep learning libraries such as the primitive cuDNN library for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0197] FIG. 26 shows a ROCm implementation of the software stack 2400 of FIG. 24 according to at least one embodiment. In at least one embodiment, the ROCm software stack 2600 on which the application 2601 can be launched includes a language runtime 2603, a system runtime 2605, a thunk 2607, and a ROCm kernel driver 2608. In at least one embodiment, the ROCm software stack 2600 runs on the hardware 2609, which may include a GPU, and the GPU supports ROCm and is developed by AMD Corporation of Santa Clara, California.

[0198] In at least one embodiment, application 2601 may implement functionality similar to application 2401 described above in conjunction with FIG. 24. In at least one embodiment, further, language runtime 2603 and system runtime 2605 may implement functionality similar to runtime 2405 described above in conjunction with FIG. 24. In at least one embodiment, language runtime 2603 and system runtime 2605 are different in that system runtime 2605 implements the ROCr system runtime API 2604 and utilizes a heterogeneous system architecture (HSA) runtime API, which is a language-independent runtime. In at least one embodiment, the HSA runtime API exposes an interface for accessing and interacting with an AMD GPU, which includes functions for, among other things, memory management, execution control via designed dispatch of kernels, error handling, system and agent information, and runtime initialization and shutdown, and is a thin user-mode API. In contrast to system runtime 2605 in at least one embodiment, language runtime 2603 is an implementation of a language-specific runtime API 2602 layered on top of the ROCr system runtime API 2604. In at least one embodiment, the language runtime API may include, but is not limited to, among other things, a heterogeneous compute interface for portability (HIP) language runtime API, a heterogeneous compute compiler (HCC) language runtime API, or an OpenCL API. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes functions similar to those of the CUDA runtime API 2504 described above in conjunction with FIG. 25, such as functions for memory management, execution control, device management, error handling, and synchronization.

[0199] In at least one embodiment, the ROCt (ROCt) 2607 is an interface 2606 that can be used to interact with the underlying ROCm driver 2608. In at least one embodiment, the ROCm driver 2608 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for a GPU developed by AMD that implements functionality similar to the device kernel driver 2406 described above in conjunction with FIG. 24. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources via hardware features.

[0200] In at least one embodiment, various libraries (not shown) are included in the ROCm software stack 2600 above the language runtime 2603 and can provide functional similarities to the CUDA libraries 2503 described above in conjunction with FIG. 25. In at least one embodiment, the various libraries can include, but are not limited to, mathematical, deep learning, and / or other libraries, such as the hipBLAS library that implements a function similar to that of CUDA cuBLAS, and the rocFFT library for calculating an FFT similar to CUDA cuFFT.

[0201] Figure 27 shows an OpenCL implementation of the software stack 2400 of FIG. 24 according to at least one embodiment. In at least one embodiment, an OpenCL software stack 2700 on which an application 2701 can be launched includes an OpenCL framework 2710, an OpenCL runtime 2706, and a driver 2707. In at least one embodiment, the OpenCL software stack 2700 runs on non-vendor-specific hardware 2509. In at least one embodiment, since OpenCL is supported by devices developed by different vendors, a specific OpenCL driver may be required to interoperate with hardware from such vendors.

[0202] In at least one embodiment, the application 2701, the OpenCL runtime 2706, the device kernel driver 2707, and the hardware 2708 may each implement functionality similar to the application 2401, the runtime 2405, the device kernel driver 2406, and the hardware 2407, respectively, described above in conjunction with FIG. 24. In at least one embodiment, the application 2701 further includes an OpenCL kernel 2702 having code to be executed on the device.

[0203] In at least one embodiment, OpenCL defines a "platform" that enables a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides platform layer APIs and runtime APIs, shown as platform API 2703 and runtime API 2705. In at least one embodiment, the runtime API 2705 uses a context to manage the execution of kernels on a device. In at least one embodiment, each identified device may be associated with a respective context, and the runtime API 2705 uses each context to manage, inter alia, command queues, program objects, and kernel objects for that device and may share memory objects. In at least one embodiment, the platform API 2703 exposes functionality that allows, inter alia, a device context to be used to select and initialize a device, submit work to the device via a command queue, and enable data transfer between the device and the host. In at least one embodiment, further, the OpenCL framework provides various built-in functions (not shown), including, inter alia, mathematical functions, relational functions, and image processing functions.

[0204] In at least one embodiment, compiler 2704 is also included within OpenCL framework 2710. In at least one embodiment, the source code can be compiled offline before the application is executed or can be compiled online during the execution of the application. In contrast to CUDA and ROCm, in at least one embodiment, an OpenCL application can be compiled online by compiler 2704, which is included to represent any number of compilers that can be used to compile source code and / or IR code into binary code, such as standard portable intermediate representation (“SPIR-V”) code. Alternatively, in at least one embodiment, an OpenCL application can be compiled offline before the execution of such an application.

[0205] FIG. 28 shows software supported by a programming platform according to at least one embodiment. In at least one embodiment, programming platform 2804 is configured to support various programming models 2803, middleware and / or libraries 2802, and framework 2801 that an application 2800 may rely on. In at least one embodiment, application 2800 can be an AI / ML application implemented using a deep learning framework, such as MXNet, PyTorch, or TensorFlow, for example, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and / or CUDA libraries such as NVIDA Developer Data Loading Library (“DALI®”) to provide accelerated computing on the underlying hardware.

[0206] In at least one embodiment, the programming platform 2804 can be one of the CUDA, ROCm, or OpenCL platforms, respectively, described above in conjunction with FIGS. 25, 26, and 27. In at least one embodiment, the programming platform 2804 supports a plurality of programming models 2803 that are abstractions of computing systems that provide a basis for allowing the representation of algorithms and data structures. In at least one embodiment, the programming model 2803 can expose the characteristics of the underlying hardware in order to improve performance. In at least one embodiment, the programming model 2803 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (C++AMP), Open Multi-Processing (OpenMP), Open Accelerators (OpenACC), and / or Vulcan Compute.

[0207] In at least one embodiment, library and / or middleware 2802 provides an implementation of the abstractions of programming model 2804. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, such middleware includes software that provides services to an application in addition to the software available from programming platform 2804. In at least one embodiment, library and / or middleware 2802 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Further, in at least one embodiment, library and / or middleware 2802 may include the NCCL and ROCm Communication Collectives Library ("RCCL") libraries that provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0208] In at least one embodiment, application framework 2801 depends on library and / or middleware 2802. In at least one embodiment, each of application frameworks 2801 is a software framework used to implement a standard structure of application software. In at least one embodiment, returning to the AI / ML examples described above, AI / ML applications may be implemented using frameworks such as the Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks.

[0209] FIG. 29 shows compiling code for execution on one of the programming platforms of FIGS. 24-27 according to at least one embodiment. In at least one embodiment, compiler 2901 receives source code 2900 that includes both host code and device code. In at least one embodiment, compiler 2901 is configured to convert source code 2900 into host-executable code 2902 for execution on the host and device-executable code 2903 for execution on the device. In at least one embodiment, source code 2900 can be compiled either offline before execution of the application or online during execution of the application.

[0210] In at least one embodiment, source code 2900 can include code in any programming language supported by compiler 2901, such as C++, C, Fortran, etc. In at least one embodiment, source code 2900 can be included in a single source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single source file can be a.cu file that includes CUDA code or a.hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 2900 can include multiple source code files rather than a single source file in which the host code and device code are separated.

[0211] In at least one embodiment, compiler 2901 is configured to compile source code 2900 into host-executable code 2902 for execution on a host and device-executable code 2903 for execution on a device. In at least one embodiment, compiler 2901 performs operations including parsing source code 2900 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 2900 includes a single source file, compiler 2901 separates device code from host code in such a single source file, compiles the device code and the host code into device-executable code 2903 and host-executable code 2902 respectively, and may link device-executable code 2903 and host-executable code 2902 to each other in a single file, as will be described in more detail below with respect to FIG. 30.

[0212] In at least one embodiment, host-executable code 2902 and device-executable code 2903 can be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host-executable code 2902 can include native object code and device-executable code 2903 can include code in PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host-executable code 2902 and device-executable code 2903 can include target binary code.

[0213] FIG. 30 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 24-27 according to at least one embodiment. In at least one embodiment, compiler 3001 is configured to receive source code 3000, compile source code 3000, and output an executable file 3010. In at least one embodiment, source code 3000 is a single source file, such as a.cu file,.hip.cpp file, or a file in another format, that includes both host code and device code. In at least one embodiment, compiler 3001 can be, but is not limited to, an NVIDIA CUDA compiler ( "NVCC": NVIDIA CUDA compiler) for compiling CUDA code in a.cu file, or an HCC compiler for compiling HIP code in a.hip.cpp file.

[0214] In at least one embodiment, compiler 3001 includes a compiler front end 3002, a host compiler 3005, a device compiler 3006, and a linker 3009. In at least one embodiment, compiler front end 3002 is configured to separate device code 3004 from host code 3003 in source code 3000. In at least one embodiment, device code 3004 is compiled by device compiler 3006 into device-executable code 3008, which, as described, may include binary code or IR code. In at least one embodiment, separately, host code 3003 is compiled by host compiler 3005 into host-executable code 3007. In at least one embodiment, in the case of NVCC, host compiler 3005 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3006 may be, but is not limited to, a low-level virtual machine (LLVM)-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, in the case of HCC, both host compiler 3005 and device compiler 3006 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0215] In at least one embodiment, after compiling source code 3000 into host-executable code 3007 and device-executable code 3008, linker 3009 links host-executable code 3007 and device-executable code 3008 to each other in executable file 3010. In at least one embodiment, native object code for the host and PTX or binary code for the device can be linked to each other in an Executable and Linkable Format (ELF) file, which is a container format used to store object code.

[0216] FIG. 31 shows translating source code prior to compiling the source code according to at least one embodiment. In at least one embodiment, source code 3100 is passed through translation tool 3101, and translation tool 3101 translates source code 3100 into translated source code 3102. In at least one embodiment, compiler 3103 is used to compile translated source code 3102 into host-executable code 3104 and device-executable code 3105 in a process similar to the compilation of source code 2900 by compiler 2901 into host-executable code 2902 and device-executable 2903 as described above in conjunction with FIG. 29.

[0217] In at least one embodiment, the translation performed by the translation tool 3101 is used to port the source 3100 for execution in an environment different from the environment in which it was originally intended to operate. In at least one embodiment, the translation tool 3101 may include a HIP translator that is used to “hipify” CUDA code, which targets the CUDA platform, into HIP code that can be compiled and executed on the ROCm platform, among other things. In at least one embodiment, the translation of the source code 3100 may include parsing the source code 3100 and converting calls to the (one or more) APIs provided by a certain programming model (e.g., CUDA) into corresponding calls to the (one or more) APIs provided by another programming model (e.g., HIP), as will be described in more detail below in conjunction with FIGS. 32A-33. In at least one embodiment, returning to the example of hipifying CUDA code, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library may be converted into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 3101 is sometimes incomplete and may require additional manual effort to fully port the source code 3100.

[0218] Configuring a GPU for general-purpose computing The following figures depict exemplary architectures for compiling and executing compute source code, according to at least one embodiment, among other things.

[0219] FIG. 32A shows a system 32A00 configured to compile and execute CUDA source code 3210 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 32A00 includes, without limitation, CUDA source code 3210, a CUDA compiler 3250, host-executable code 3270(1), host-executable code 3270(2), CUDA device-executable code 3284, a CPU 3290, a CUDA-capable GPU 3294, a GPU 3292, a CUDA-to-HIP translation tool 3220, HIP source code 3230, a HIP compiler driver 3240, an HCC 3260, and HCC device-executable code 3282.

[0220] In at least one embodiment, CUDA source code 3210 is a set of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, without limitation, a mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-capable GPU 3290, GPU 32192, or another GPGPU. In at least one embodiment, host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3290.

[0221] In at least one embodiment, the CUDA source code 3210 includes, without limitation, any number (including 0) of global functions 3212, any number (including 0) of device functions 3214, any number (including 0) of host functions 3216, and any number (including 0) of host / device functions 3218. In at least one embodiment, the global functions 3212, the device functions 3214, the host functions 3216, and the host / device functions 3218 can be mixed within the CUDA source code 3210. In at least one embodiment, each of the global functions 3212 is executable on the device and callable from the host. In at least one embodiment, one or more of the global functions 3212 can thus serve as an entry point to the device. In at least one embodiment, each of the global functions 3212 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3212 define a kernel, the kernel is executable on the device, and is callable from such a device. In at least one embodiment, the kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0222] In at least one embodiment, each of the device functions 3214 is executed on the device and callable only from such a device. In at least one embodiment, each of the host functions 3216 is executed on the host and callable only from such a host. In at least one embodiment, each of the host / device functions 3216 defines both a host version of the function that is executable on the host and callable only from such a host, and a device version of the function that is executable on the device and callable only from such a device.

[0223] In at least one embodiment, the CUDA source code 3210 may also include any number of calls to any number of functions defined via the CUDA runtime API 3202, among other things. In at least one embodiment, the CUDA runtime API 3202 may include any number of functions that execute on the host, among other things, for allocating and deallocating device memory, transferring data between host memory and device memory, managing a system with multiple devices, etc. In at least one embodiment, the CUDA source code 3210 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, the CUDA API can be any API designed for use by CUDA code. In at least one embodiment, the CUDA API includes, among other things, the CUDA runtime API 3202, the CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment, and with respect to the CUDA runtime API 3202, the CUDA driver API is a lower-level API but provides more fine-grained control of the device. In at least one embodiment, examples of CUDA libraries include, among other things, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0224] In at least one embodiment, the CUDA compiler 3250 compiles input CUDA code (e.g., the CUDA source code 3210) to produce host-executable code 3270(1) and CUDA device-executable code 3284. In at least one embodiment, the CUDA compiler 3250 is NVCC. In at least one embodiment, the host-executable code 3270(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3290. In at least one embodiment, the CPU 3290 can be any processor optimized for sequential instruction processing.

[0225] In at least one embodiment, the CUDA device executable code 3284 is a compiled version of the device code included in the input source code that is executable on a CUDA-enabled GPU 3294. In at least one embodiment, the CUDA device executable code 3284 includes, without limitation, binary code. In at least one embodiment, the CUDA device executable code 3284 includes, without limitation, IR code such as PTX code, which is further compiled at runtime by the device driver into binary code for a particular target device (e.g., CUDA-enabled GPU 3294). In at least one embodiment, the CUDA-enabled GPU 3294 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3294 is developed by NVIDIA Corporation of Santa Clara, California.

[0226] In at least one example, the CUDA-to-HIP translation tool 3220 is configured to translate CUDA source code 3210 into functionally similar HIP source code 3230. In at least one example, HIP source code 3230 is a set of human-readable code in the HIP programming language. In at least one example, HIP code is human-readable code in the HIP programming language. In at least one example, the HIP programming language is an extension of the C++ programming language that includes, without limitation, a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one example, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one example, for instance, the HIP programming language includes, without limitation, one or more mechanisms for defining a global function 3212, but such a HIP programming language may not support dynamic parallel processing, and thus the global function 3212 defined in the HIP code may be callable only from the host.

[0227] In at least one embodiment, the HIP source code 3230 includes, without limitation, any number of global functions 3212 (including 0), any number of device functions 3214 (including 0), any number of host functions 3216 (including 0), and any number of host / device functions 3218 (including 0). In at least one embodiment, the HIP source code 3230 may also include any number of calls to any number of functions specified in the HIP runtime API 3232. In at least one embodiment, the HIP runtime API 3232 includes, without limitation, a functionally similar version of a subset of the functions included in the CUDA runtime API 3202. In at least one embodiment, the HIP source code 3230 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API can be any API designed for use with HIP code and / or ROCm. In at least one embodiment, the HIP API includes, without limitation, the HIP runtime API 3232, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0228] In at least one embodiment, the CUDA-to-HIP translation tool 3220 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP translation tool 3220 converts any number of calls to functions specified in the CUDA runtime API 3202 to any number of calls to functions specified in the HIP runtime API 3232.

[0229] In at least one embodiment, the CUDA-to-HIP translation tool 3220 is a tool known as hipify-perl that performs a text-based translation process. In at least one embodiment, the CUDA-to-HIP translation tool 3220 is a tool known as hipify-clang, which performs a more complex and robust translation process involving parsing CUDA code using clang (a compiler front-end) and then translating the resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual editing) in addition to the modifications performed by the CUDA-to-HIP translation tool 3220.

[0230] In at least one embodiment, the HIP compiler driver 3240 is a front-end that determines the target device 3246 and then configures a compiler compatible with the target device 3246 to compile the HIP source code 3230. In at least one embodiment, the target device 3246 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3240 may determine the target device 3246 in any technically feasible manner.

[0231] In at least one embodiment, when the target device 3246 is compatible with CUDA (e.g., a CUDA - compatible GPU 3294), the HIP compiler driver 3240 generates a HIP / NVCC compile command 3242. In at least one embodiment, and as described in more detail in conjunction with FIG. 32B, the HIP / NVCC compile command 3242 configures the CUDA compiler 3250 to compile the HIP source code 3230 using, without limitation, a HIP - to - CUDA translation header and the CUDA runtime library. In at least one embodiment, and in response to the HIP / NVCC compile command 3242, the CUDA compiler 3250 generates host - executable code 3270(1) and CUDA device - executable code 3284.

[0232] In at least one embodiment, if the target device 3246 is not compatible with CUDA, the HIP compiler driver 3240 generates HIP / HCC compile commands 3244. In at least one embodiment, and as described in more detail in conjunction with FIG. 32C, the HIP / HCC compile commands 3244 configure HCC 3260 to compile HIP source code 3230 using, without limitation, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to the HIP / HCC compile commands 3244, HCC 3260 generates host-executable code 3270(2) and HCC device-executable code 3282. In at least one embodiment, the HCC device-executable code 3282 is a compiled version of the device code included in the HIP source code 3230 that is executable on the GPU 3292. In at least one embodiment, the GPU 3292 can be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, the GPU 3292 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the GPU 3292 is a CUDA-incompatible GPU 3292.

[0233] For illustrative purposes only, three different flows that can be implemented in at least one embodiment for compiling the CUDA source code 3210 for execution on the CPU 3290 and different devices are illustrated in FIG. 32A. In at least one embodiment, the direct CUDA flow compiles the CUDA source code 3210 for execution on the CPU 3290 and the CUDA-capable GPU 3294 without translating the CUDA source code 3210 to HIP source code 3230. In at least one embodiment, the indirect CUDA flow translates the CUDA source code 3210 to HIP source code 3230 and then compiles the HIP source code 3230 for execution on the CPU 3290 and the CUDA-capable GPU 3294. In at least one embodiment, the CUDA / HCC flow translates the CUDA source code 3210 to HIP source code 3230 and then compiles the HIP source code 3230 for execution on the CPU 3290 and the GPU 3292.

[0234] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via a series of bubbles annotated with dashed lines and A1 - A3. In at least one embodiment, as illustrated by the bubble annotated with A1, the CUDA compiler 3250 receives the CUDA source code 3210 and the CUDA compile command 3248 that configures the CUDA compiler 3250 to compile the CUDA source code 3210. In at least one embodiment, the CUDA source code 3210 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, in response to the CUDA compile command 3248, the CUDA compiler 3250 generates host - executable code 3270(1) and CUDA device - executable code 3284 (illustrated by the bubble annotated with A2). In at least one embodiment, as illustrated by the bubble annotated with A3, the host - executable code 3270(1) and the CUDA device - executable code 3284 may be executed on the CPU 3290 and the CUDA - enabled GPU 3294, respectively. In at least one embodiment, the CUDA device - executable code 3284 includes, without limitation, binary code. In at least one embodiment, the CUDA device - executable code 3284 includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

[0235] An indirect CUDA flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with dashed lines and B1 - B6. In at least one embodiment, as illustrated by the bubble annotated with B1, the CUDA - to - HIP translation tool 3220 receives the CUDA source code 3210. In at least one embodiment, as illustrated by the bubble annotated with B2, the CUDA - to - HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one embodiment, as illustrated by the bubble annotated with B3, the HIP compiler driver 3240 receives the HIP source code 3230 and determines that the target device 3246 is CUDA - compatible.

[0236] In at least one embodiment, and as illustrated by the bubble annotated with B4, the HIP compiler driver 3240 generates a HIP / NVCC compile command 3242 and sends both the HIP / NVCC compile command 3242 and the HIP source code 3230 to the CUDA compiler 3250. In at least one embodiment, and as will be described in more detail in conjunction with FIG. 32B, the HIP / NVCC compile command 3242 configures the CUDA compiler 3250 to compile the HIP source code 3230 using, without limitation, a HIP-to-CUDA translation header and the CUDA runtime library. In at least one embodiment, and in response to the HIP / NVCC compile command 3242, the CUDA compiler 3250 generates host-executable code 3270(1) and CUDA device-executable code 3284 (illustrated by the bubble annotated with B5). In at least one embodiment, and as illustrated by the bubble annotated with B6, the host-executable code 3270(1) and the CUDA device-executable code 3284 can be executed on the CPU 3290 and the CUDA-capable GPU 3294, respectively. In at least one embodiment, the CUDA device-executable code 3284 includes, without limitation, binary code. In at least one embodiment, the CUDA device-executable code 3284 includes, without limitation, PTX code and is further compiled into binary code for a specific target device at runtime.

[0237] The CUDA / HCC flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with solid lines and C1 - C6. In at least one embodiment, as illustrated by the bubble annotated with C1, the CUDA - to - HIP translation tool 3220 receives the CUDA source code 3210. In at least one embodiment, as illustrated by the bubble annotated with C2, the CUDA - to - HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one embodiment, as illustrated by the bubble annotated with C3, the HIP compiler driver 3240 receives the HIP source code 3230 and determines that the target device 3246 is not CUDA - compatible.

[0238] In at least one embodiment, the HIP compiler driver 3240 generates a HIP / HCC compile command 3244 and sends both the HIP / HCC compile command 3244 and the HIP source code 3230 to HCC3260 (illustrated by the bubble annotated with C4). In at least one embodiment, as will be described in more detail in conjunction with FIG. 32C, the HIP / HCC compile command 3244 configures HCC3260 to compile the HIP source code 3230 using, without limitation, the HCC header and the HIP / HCC runtime library. In at least one embodiment, in response to the HIP / HCC compile command 3244, HCC3260 generates host - executable code 3270(2) and HCC device - executable code 3282 (illustrated by the bubble annotated with C5). In at least one embodiment, as illustrated by the bubble annotated with C6, the host - executable code 3270(2) and the HCC device - executable code 3282 can be executed on the CPU3290 and the GPU3292, respectively.

[0239] In at least one embodiment, after the CUDA source code 3210 is translated into HIP source code 3230, the HIP compiler driver 3240 can then be used to generate executable code for either the CUDA - compatible GPU 3294 or GPU 3292 without re - executing the CUDA - to - HIP translation tool 3220. In at least one embodiment, the CUDA - to - HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230, and the HIP source code 3230 is then stored in memory. In at least one embodiment, the HIP compiler driver 3240 then configures the HCC 3260 to generate host - executable code 3270(2) and HCC device - executable code 3282 based on the HIP source code 3230. In at least one embodiment, the HIP compiler driver 3240 then configures the CUDA compiler 3250 to generate host - executable code 3270(1) and CUDA device - executable code 3284 based on the stored HIP source code 3230.

[0240] FIG. 32B shows a system 3204 configured to compile and execute the CUDA source code 3210 of FIG. 32A using a CPU 3290 and a CUDA - compatible GPU 3294, according to at least one embodiment. In at least one embodiment, the system 3204 includes, without limitation, the CUDA source code 3210, the CUDA - to - HIP translation tool 3220, the HIP source code 3230, the HIP compiler driver 3240, the CUDA compiler 3250, the host - executable code 3270(1), the CUDA device - executable code 3284, the CPU 3290, and the CUDA - compatible GPU 3294.

[0241] In at least one example, and as previously described herein in conjunction with FIG. 32A, the CUDA source code 3210 includes, without limitation, any number of global functions 3212 (including 0), any number of device functions 3214 (including 0), any number of host functions 3216 (including 0), and any number of host / device functions 3218 (including 0). In at least one example, the CUDA source code 3210 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0242] In at least one example, the CUDA-to-HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one example, the CUDA-to-HIP translation tool 3220 converts each kernel call in the CUDA source code 3210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3210 to any number of other functionally similar HIP calls.

[0243] In at least one embodiment, the HIP compiler driver 3240 determines that the target device 3246 is CUDA - capable and generates a HIP / NVCC compile command 3242. In at least one embodiment, the HIP compiler driver 3240 then configures the CUDA compiler 3250 via the HIP / NVCC compile command 3242 to compile the HIP source code 3230. In at least one embodiment, as part of configuring the CUDA compiler 3250, the HIP compiler driver 3240 provides access to a HIP - to - CUDA translation header 3252. In at least one embodiment, the HIP - to - CUDA translation header 3252 translates any number of constructs (e.g., functions) specified in any number of HIP APIs to any number of constructs specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3250 uses the HIP - to - CUDA translation header 3252 in conjunction with a CUDA runtime library 3254 corresponding to the CUDA runtime API 3202 to generate host - executable code 3270(1) and CUDA device - executable code 3284. In at least one embodiment, the host - executable code 3270(1) and the CUDA device - executable code 3284 can then be executed on the CPU 3290 and the CUDA - capable GPU 3294, respectively. In at least one embodiment, the CUDA device - executable code 3284 includes, without limitation, binary code. In at least one embodiment, the CUDA device - executable code 3284 includes, without limitation, PTX code and is further compiled at runtime to binary code for a particular target device.

[0244] FIG. 32C shows a system 3206 configured to compile and execute the CUDA source code 3210 of FIG. 32A using a CPU 3290 and a CUDA-incompatible GPU 3292, according to at least one embodiment. In at least one embodiment, the system 3206 includes, without limitation, the CUDA source code 3210, a CUDA-to-HIP translation tool 3220, HIP source code 3230, a HIP compiler driver 3240, HCC 3260, host-executable code 3270(2), HCC device-executable code 3282, the CPU 3290, and the GPU 3292.

[0245] In at least one embodiment, and as previously described herein in conjunction with FIG. 32A, the CUDA source code 3210 includes, without limitation, any number of global functions 3212 (including 0), any number of device functions 3214 (including 0), any number of host functions 3216 (including 0), and any number of host / device functions 3218 (including 0). In at least one embodiment, the CUDA source code 3210 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0246] In at least one embodiment, the CUDA-to-HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one embodiment, the CUDA-to-HIP translation tool 3220 converts each kernel call in the CUDA source code 3210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3210 to any number of other functionally similar HIP calls.

[0247] In at least one embodiment, the HIP compiler driver 3240 then determines that the target device 3246 is not CUDA - compliant and generates a HIP / HCC compile command 3244. In at least one embodiment, the HIP compiler driver 3240 then configures the HCC 3260 to execute the HIP / HCC compile command 3244 to compile the HIP source code 3230. In at least one embodiment, the HIP / HCC compile command 3244 configures the HCC 3260 to use the HIP / HCC runtime library 3258 and the HCC header 3256 to generate, without limitation, host - executable code 3270(2) and HCC device - executable code 3282. In at least one embodiment, the HIP / HCC runtime library 3258 corresponds to the HIP runtime API 3232. In at least one embodiment, the HCC header 3256 includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, the host - executable code 3270(2) and the HCC device - executable code 3282 can be executed on the CPU 3290 and the GPU 3292, respectively.

[0248] FIG. 33 shows an exemplary kernel translated by the CUDA - to - HIP translation tool 3220 of FIG. 32C, according to at least one embodiment. In at least one embodiment, the CUDA source code 3210 divides the overall problem that a given kernel is designed to solve into relatively coarse sub - problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub - problem is further divided into relatively fine - grained pieces that can be solved in parallel and in concert by the threads within the thread block. In at least one embodiment, the threads within the thread block can work in concert by sharing data through shared memory and by synchronizing their execution to coordinate memory accesses.

[0249] In at least one embodiment, the CUDA source code 3210 organizes the thread blocks associated with a given kernel into a one-dimensional grid, two-dimensional grid, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes any number of threads, although not limited thereto, and the grid includes any number of thread blocks, although not limited thereto.

[0250] In at least one embodiment, the kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid that executes the kernel for a given kernel call and associated stream are specified using the CUDA kernel launch syntax 3310. In at least one embodiment, the CUDA kernel launch syntax 3310 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream>>>(KernelArguments);". In at least one embodiment, the execution configuration syntax is the "<<<...>>>" construct inserted between the kernel name ("KernelName") and the list of kernel arguments enclosed in parentheses ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3310 includes, although not limited thereto, the CUDA launch function syntax instead of the execution configuration syntax.

[0251] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, the type dim3 is a CUDA-defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z is default set to 1. In at least one embodiment, if y is not specified, y is default set to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread that executes the kernel is given a unique thread ID that is accessible within the kernel through an intrinsic variable (e.g., "threadIdx").

[0252] In at least one embodiment, and with respect to CUDA kernel launch syntax 3310, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that is dynamically allocated per thread block for a given kernel call in addition to the statically allocated memory. In at least one embodiment, and with respect to CUDA kernel launch syntax 3310, SharedMemorySize is default set to 0. In at least one embodiment, and with respect to CUDA kernel launch syntax 3310, "Stream" is an optional argument that specifies the associated stream and is default set to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands that execute in order (optionally issued by different host threads). In at least one embodiment, different streams can execute commands out of order with respect to each other or simultaneously.

[0253] In at least one embodiment, the CUDA source code 3210 includes, without limitation, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code that runs on the host and includes, without limitation, a kernel call to cause the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16×16 and the numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock>>>(A,B,C);". In at least one embodiment, and as per the CUDA kernel launch syntax 3310, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16×N / 16, where each thread block has dimensions 16×16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes the kernel MatAdd to perform one pairwise addition.

[0254] In at least one embodiment, while translating CUDA source code 3210 to HIP source code 3230, the CUDA-to-HIP translation tool 3220 translates each kernel call in the CUDA source code 3210 from CUDA kernel launch syntax 3310 to HIP kernel launch syntax 3320 and converts any number of other CUDA calls in the source code 3210 to any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel launch syntax 3320 is specified as “hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel launch syntax 3320 as in the case of the CUDA kernel launch syntax 3310 (previously described herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in the HIP kernel launch syntax 3320 and are optional in the CUDA kernel launch syntax 3310.

[0255] In at least one embodiment, a portion of the HIP source code 3230 illustrated in FIG. 33 is identical to a portion of the CUDA source code 3210 illustrated in FIG. 33, except for the kernel call to execute on the device in the kernel MatAdd. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 3230 using the same "__global__" declaration specifier as the kernel MatAdd is defined in the CUDA source code 3210. In at least one embodiment, the kernel call in the HIP source code 3230 is "hipLaunchKernelGGL(MatAdd,numBlocks,threadsPerBlock,0,0,A,B,C);", while the corresponding kernel call in the CUDA source code 3210 is "MatAdd<<<numBlocks,threadsPerBlock>>>(A,B,C);".

[0256] FIG. 34 shows the CUDA-incompatible GPU 3292 of FIG. 32C in more detail according to at least one embodiment. In at least one embodiment, the GPU 3292 is developed by Santa Clara's AMD corporation. In at least one embodiment, the GPU 3292 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3292 is configured to execute graphics pipeline operations such as rendering commands, pixel operations, geometric calculations, and other operations related to rendering images to a display. In at least one embodiment, the GPU 3292 is configured to execute operations not related to graphics. In at least one embodiment, the GPU 3292 is configured to execute both operations related to graphics and operations not related to graphics. In at least one embodiment, the GPU 3292 can be configured to execute the device code included in the HIP source code 3230.

[0257] In at least one embodiment, GPU 3292 includes, without limitation, any number of programmable processing units 3420, a command processor 3410, an L2 cache 3422, a memory controller 3470, a DMA engine 3480(1), a system memory controller 3482, a DMA engine 3480(2), and a GPU controller 3484. In at least one embodiment, each programmable processing unit 3420 includes, without limitation, a workload manager 3430 and any number of compute units 3440. In at least one embodiment, the command processor 3410 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3430. In at least one embodiment, for each programmable processing unit 3420, the associated workload manager 3430 distributes work to the compute units 3440 included in the programmable processing unit 3420. In at least one embodiment, each compute unit 3440 may execute any number of thread blocks, but each thread block executes on a single compute unit 3440. In at least one embodiment, a workgroup is a thread block.

[0258] In at least one embodiment, each compute unit 3440 includes, without limitation, any number of SIMD units 3450 and a shared memory 3460. In at least one embodiment, each SIMD unit 3450 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3450 includes, without limitation, a vector ALU 3452 and a vector register file 3454. In at least one embodiment, each SIMD unit 3450 executes different warps. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different sets of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via the shared memory 3460.

[0259] In at least one embodiment, the programmable processing unit 3420 is referred to as a "shader engine". In at least one embodiment, each programmable processing unit 3420 includes, without limitation, in addition to the compute unit 3440, any amount of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 3420 includes, without limitation, any number (including 0) of geometry processors, any number (including 0) of rasterizers, any number (including 0) of render back ends, a workload manager 3430, and any number of compute units 3440.

[0260] In at least one embodiment, compute unit 3440 shares L2 cache 3422. In at least one embodiment, L2 cache 3422 is partitioned. In at least one embodiment, GPU memory 3490 is accessible by all compute units 3440 in GPU 3292. In at least one embodiment, memory controller 3470 and system memory controller 3482 facilitate data transfer between GPU 3292 and a host, and DMA engine 3480(1) enables asynchronous memory transfer between GPU 3292 and such a host. In at least one embodiment, memory controller 3470 and GPU controller 3484 facilitate data transfer between GPU 3292 and other GPUs 3292, and DMA engine 3480(2) enables asynchronous memory transfer between GPU 3292 and other GPUs 3292.

[0261] In at least one embodiment, the GPU 3292 includes any amount and type of system interconnect that facilitates data and control transmissions across any number and type of directly or indirectly linked components, which may be internal or external to the GPU 3292. In at least one embodiment, the GPU 3292 includes any number and type of I / O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices. In at least one embodiment, the GPU 3292 may include any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, the GPU 3292 implements a memory subsystem that includes any amount and type of memory controllers (e.g., memory controller 3470 and system memory controller 3482) and memory devices (e.g., shared memory 3460) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the GPU 3292 implements a cache subsystem that includes one or more cache memories (e.g., L2 cache 3422), and the one or more cache memories may each be private to any number of components (e.g., SIMD unit 3450, compute unit 3440, and programmable processing unit 3420) or shared among any number of components.

[0262] Figure 35 shows how the threads of an exemplary CUDA grid 3520, according to at least one embodiment, are mapped to different compute units 3440 of FIG. 34. In at least one embodiment, and for illustrative purposes only, the grid 3520 has a GridSize of BX×BY×1 and a BlockSize of TX×TY×1. In at least one embodiment, the grid 3520 thus includes, without limitation, (BX*BY) thread blocks 3530, and each thread block 3530 includes, without limitation, (TX*TY) threads 3540. The threads 3540 are illustrated in FIG. 35 as squiggly arrows.

[0263] In at least one embodiment, the grid 3520 is mapped to a programmable processing unit 3420(1) that includes, without limitation, compute units 3440(1) to 3440(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3530 are mapped to compute unit 3440(1), and the remaining thread blocks 3530 are mapped to compute unit 3440(2). In at least one embodiment, each thread block 3530 may include, without limitation, any number of warps, and each warp is mapped to a different SIMD unit 3450 of FIG. 34.

[0264] In at least one embodiment, the warps within a given thread block 3530 may synchronize with each other and communicate through a shared memory 3460 included within the associated compute unit 3440. For example, and in at least one embodiment, the warps in thread block 3530(BJ,1) may synchronize with each other and communicate through shared memory 3460(1). For example, and in at least one embodiment, the warps in thread block 3530(BJ + 1,1) may synchronize with each other and communicate through shared memory 3460(2).

[0265] Figure 36 shows how to migrate existing CUDA code to Data Parallel C++ code according to at least one embodiment. In at least one embodiment, migrating existing CUDA code to Data Parallel C++ code can be included in the systems disclosed in FIGS. 1-3 and communicate with these systems to implement all or part of the process 400 disclosed in FIG. 4. Data Parallel C++ (DPC++) can refer to an open standard-based alternative to a single architecture proprietary language, which allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs), and also perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that follow ISO C++ with which developers may be familiar. DPC++ incorporates the standard SYCL from the Khronos Group to support data parallel processing and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the concepts, portability, and efficiency underlying OpenCL, which enables code for heterogeneous processors to be written in a "single source" style using standard C++. SYCL can enable single-source development where C++ template functions can contain both host code and device code, build complex algorithms using OpenCL acceleration, and then reuse them across their entire source code for different types of data.

[0266] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be introduced across various hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be introduced across various hardware targets, and a DPC++ compatibility tool can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++-based tool kit includes a DPC++ compiler for introducing applications across various hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, and any suitable combination thereof.

[0267] In at least one embodiment, a DPC++ programming model is utilized simply for one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallel processing using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs), uses a single source language, and can clearly communicate execution and memory dependencies. The mapping within DPC++ code can be used to migrate an application to operate on a set of hardware or hardware devices that best accelerates the workload. Even on platforms without available accelerators, the host can be available to simplify the development and debugging of device code.

[0268] In at least one embodiment, CUDA source code 3600 is provided as input to a DPC++ compatibility tool 3602 to generate human-readable DPC++ 3604. In at least one embodiment, the human-readable DPC++ 3604 includes inline comments generated by the DPC++ compatibility tool 3602, which guide the developer as to how and / or where to modify the DPC++ code to complete 3606 the coding and tuning to the desired performance, thereby generating DPC++ source code 3608.

[0269] In at least one embodiment, the CUDA source code 3600 is a set of human-readable source code of the CUDA programming language or includes such a set. In at least one embodiment, the CUDA source code 3600 is human-readable source code of the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, a mechanism for defining device code and distinguishing between device code and host code. In at least one embodiment, the device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA), can be executed on one or more processor cores of the device, or can include a more parallelizable workflow. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-compatible GPU, a GPU, or another GPGPU. In at least one embodiment, the host code is source code that is executable on the host after compilation. In at least one embodiment, some or all of the host code and device code can be executed in parallel across a CPU and a GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 3600 described with respect to FIG. 36 can conform to the CUDA source code described elsewhere in this specification.

[0270] In at least one embodiment, the DPC++ compatibility tool 3602 refers to an executable tool, program, application, or any other suitable type of tool that is used to facilitate the migration of CUDA source code 3600 to DPC++ source code 3608. In at least one embodiment, the DPC++ compatibility tool 3602 is a command-line based code migration tool that is available as part of a DPC++ tool kit used to port existing CUDA sources to DPC++. In at least one embodiment, the DPC++ compatibility tool 3602 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file that is at least partially written in DPC++ and is called human-readable DPC++ 3604. In at least one embodiment, the human-readable DPC++ 3604 includes comments generated by the DPC++ compatibility tool 3602 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when the CUDA source code 3600 calls a CUDA API that does not have a similar DPC++ API, and other examples where user intervention is required will be described in more detail later.

[0271] In at least one embodiment, a workflow for migrating CUDA source code 3600 (e.g., an application or a portion thereof) includes creating one or more compile database files, migrating CUDA to DPC++ using DPC++ compatibility tool 3602, completing the migration and validating it, thereby generating DPC++ source code 3608, and compiling the DPC++ source code 3608 using a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts the commands executed when a Makefile is run and stores them in a compile database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the intercept-built command converts Makefile commands to DPC compatible commands.

[0272] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture compile options, macro defs, and include paths and writes this data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, DPC++ compatibility tool 3602 parses the compile database and applies options when migrating the input source. In at least one embodiment, the use of intercept-build is optional but highly recommended for Make or CMake based environments. In at least one embodiment, the migration database includes commands, directories, and files, the commands may include the necessary compile flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0273] In at least one embodiment, the DPC++ compatibility tool 3602 migrates CUDA code (e.g., an application) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ compatibility tool 3602 is available as part of a tool kit. In at least one embodiment, the DPC++ tool kit includes an intercept-build tool. In at least one embodiment, the intercept-built tool creates a compile database that captures compile commands to migrate CUDA files. In at least one embodiment, the compile database generated by the intercept-built tool is used by the DPC++ compatibility tool 3602 to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 3602 generates human-readable DPC++ 3604, which may be DPC++ code that, when generated by the DPC++ compatibility tool 3602, may not be compiled by a DPC++ compiler and may require additional plumbing to identify portions of the code that were not migrated correctly and may involve manual intervention, such as by a developer. In at least one embodiment, the DPC++ compatibility tool 3602 provides hints or tools embedded in the code to assist a developer in manually migrating additional code that may not be automatically migrated. In at least one embodiment, the migration is a one-time activity for a source file, project, or application.

[0274] In at least one embodiment, the DPC++ compatibility tool 36002 is capable of migrating all portions of the CUDA code to DPC++ successfully, and there may simply be an optional step to manually verify and tune the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3602 directly generates DPC++ source code 3608 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3602. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code, which can optionally be adjusted by the developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0275] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using at least in part the DPC++ compatibility tool 3602. In at least one embodiment, the CUDA source code can include one or more header files that can include CUDA header files. In at least one embodiment, the CUDA source file includes the <cuda.h> header file and the <stdio.h> header file that can be used to print text. In at least one embodiment, a portion of the vector addition kernel CUDA source file can be written as or related to the following.

Number

Number

[0276] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 3602 parses the CUDA source code and replaces header files with appropriate DPC++ header files and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is a concept of thread IDs, and correspondingly, in DPC++ or SYCL, for each element, there is a local identifier.

[0277] In at least one embodiment, and with respect to the CUDA source files presented above, there are two vectors A and B that are initialized, and the vector addition result is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating the CUDA code to DPC++ code, the DPC++ compatibility tool 3602 converts the CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3602 can be optimized, for example, by reducing the dimensions of the nd_item, thereby increasing memory and / or processor utilization.

[0278] In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to the unified shared memory SYCL call malloc_device(), which relies on SYCL concepts such as platform, device, context, and queue, where the device and context are passed. In at least one embodiment, the SYCL platform can have multiple devices (e.g., a host and a GPU device), the device can have multiple queues to which jobs can be submitted, each device can have a context, the context can have multiple devices, and can manage shared memory objects.

[0279] In at least one embodiment, and with respect to the CUDA source files presented above, the main() function calls or invokes VectorAddKernel() to add two vectors A and B to each other and store the result in vector C. In at least one embodiment, the CUDA code for calling VectorAddKernel() is replaced by DPC++ code for submitting the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group where VectorAddKernel() is called.

[0280] In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls for copying device memory and then freeing the memory for vectors A, B, and C are migrated to the corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is without being modified by the DPC++ compatibility tool 3602. In at least one embodiment, the DPC++ compatibility tool 3602 modifies the CUDA API for memory setup and / or host calls to execute kernels on the acceleration device. In at least one embodiment, and with respect to the CUDA source files presented above, the corresponding human-readable DPC++ 3604 (e.g., which can be compiled) is written as follows or relates to the following. [Number] [Number] [Number]

[0281] In at least one embodiment, the human-readable DPC++ 3604 refers to the output generated by the DPC++ compatibility tool 3602 and can be optimized in one way or another. In at least one embodiment, the human-readable DPC++ 3604 generated by the DPC++ compatibility tool 3602 can be manually edited by the developer after migration for the sake of making it more sustainable, performance, or other considerations. In at least one embodiment, the DPC++ code generated by a DPC++ compatibility tool 36002 such as the disclosed DPC++ can be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which uses only a single dimension and can thus be refactored to reduce memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by the DPC++ compatibility tool 3602 and replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 3602 has options for changing how it migrates CUDA code to DPC++ code. In at least one embodiment, the DPC++ compatibility tool 3602 is redundant because it uses a general template for migrating CUDA code to DPC++ code that works in many cases.

[0282] In at least one embodiment, the CUDA-to-DPC++ migration workflow includes steps to prepare for migration using an intercept-build script, steps to perform the migration of a CUDA project to DPC++ using the DPC++ Compatibility Tool 3602, steps to manually review and edit the migrated source files for completion and sanity, and steps to compile the final DPC++ code to generate a DPC++ application. In at least one embodiment, the manual review of DPC++ source code may be required in one or more scenarios including, but not limited to, that the migrated API does not return an error code (CUDA code can return an error code which can then be consumed by the application, while SYCL uses exceptions to report errors and thus does not use an error code to surface errors), that CUDA compute-capability dependent logic is not supported by DPC++, and that statements may not be removed. In at least one embodiment, scenarios where DPC++ code requires manual intervention may include, but are not limited to, that error code logic is replaced with or commented out with a (*,0) code, that an equivalent DPC++ API is not available, CUDA compute-capability dependent logic, hardware-dependent APIs (clock()), missing features, unsupported APIs, runtime measurement logic, handling built-in vector type conflicts, migration of the cuBLAS API, etc.

[0283] In at least one embodiment, one or more of the techniques described herein utilize the oneAPI programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data parallel programming productivity. In at least one embodiment, the DPC++ programming language is at least partially based on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model developed by Intel Corporation of Santa Clara, California, etc.

[0284] In at least one embodiment, oneAPI and / or the oneAPI programming model are utilized to interact with various accelerator architectures, GPU architectures, processor architectures, and / or variants thereof. In at least one embodiment, oneAPI includes a set of libraries that implement various functionality. In at least one embodiment, oneAPI includes at least the oneAPI DPC++ library, the oneAPI math kernel library, the oneAPI data analytics library, the oneAPI deep neural network library, the oneAPI collective communication library, the oneAPI threading building block library, the oneAPI video processing library, and / or variants thereof.

[0285] In at least one embodiment, the oneAPI DPC++ Library, also known as oneDPL, is a library that implements algorithms and functions for accelerating DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions such as parallel algorithms, iterators, function object classes, range-based APIs, and / or variants thereof. In at least one embodiment, oneDPL implements one or more classes and / or functions of the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0286] In at least one embodiment, the oneAPI Math Kernel Library, also known as oneMKL, is a library that implements various optimizations and parallelized routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and / or linear algebra package (LAPACK) high-density linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more fast Fourier transform (FFT) functions.

[0287] In at least one embodiment, the oneAPI Data Analytics Library, also known as oneDAL, is a library that implements various data analytics applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for preprocessing, transformation, analysis, modeling, validation, and decision-making for data analytics in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to legacy C++ interfaces, enabling GPU usage for various algorithms.

[0288] In at least one embodiment, the oneAPI Deep Neural Network Library, also known as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and / or their variants.

[0289] In at least one embodiment, the oneAPI Collective Communications Library, also known as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built on lower-level communication middleware such as the Message Passing Interface (MPI) and libfabric. In at least one embodiment, oneCCL enables a set of deep learning-specific optimizations such as priority, persistent operations, out-of-order execution, and / or their variants. In at least one embodiment, oneCCL implements various CPU and GPU functions.

[0290] In at least one embodiment, the oneAPI threading building block library, also known as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based shared parallel programming on the host. In at least one embodiment, oneTBB implements general parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and can be used on various processors such as GPUs, PPUs, CPUs, and / or their variants.

[0291] In at least one embodiment, the oneAPI video processing library, also known as oneVPL, is a library that is utilized to accelerate video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media-centric and video analysis workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

[0292] In at least one example, the oneAPI programming model utilizes the DPC++ programming language. In at least one example, the DPC++ programming language is a programming language that includes, without limitation, functionally similar versions of CUDA constructs for defining device code and differentiating device code from host code. In at least one example, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one example, one or more CUDA programming model operations are implemented using the oneAPI programming model that uses the DPC++ programming language.

[0293] The exemplary embodiments described herein may relate to the CUDA programming model, but it should be noted that the techniques described herein may be utilized with any suitable programming model, such as HIP, oneAPI (e.g., using oneAPI-based programming to implement or implement the methods disclosed herein), and / or variations thereof.

[0294] In at least one embodiment, one or more components of the systems and / or processors disclosed above can communicate with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuit elements, or integrated circuit components including, for example, an upscaler or upsampler for upscaling an image, an image blender or image blending component for blending, mixing, or adding images together, a sampler for sampling an image (e.g., as part of a DSP), a neural network circuit configured to implement an upscaler for upscaling an image (e.g., from a low-resolution image to a high-resolution image), or other hardware for modifying or generating an image, frame, or video to adjust its resolution, size, or pixels. One or more components of the systems and / or processors disclosed above can use the components described in this disclosure to implement methods, operations, or instructions for generating or modifying an image.

[0295] At least one embodiment of the present disclosure can be described in view of the following clauses.

[0296] Clause 1. A processor comprising one or more circuits for causing two or more software modules to be executed simultaneously by the processor.

[0297] Clause 2. The processor according to Clause 1, wherein one or more circuits are for implementing one or more software drivers, and the one or more software drivers are for causing two or more software modules to be executed simultaneously by the processor.

[0298] Clause 3. The processor according to clause 1 or 2, wherein one or more circuits simultaneously cause one or more operations for starting a first one of two or more software modules to be performed simultaneously with one or more operations for starting a second one of the two or more software modules.

[0299] Clause 4. The processor according to any one of clauses 1 to 3, wherein two or more software modules include two or more graphics kernels to be implemented by a single graphics processing unit.

[0300] Clause 5. The processor according to any one of clauses 1 to 4, wherein two or more software modules include two or more graphics kernels to be implemented by a plurality of graphics processing units.

[0301] Clause 6. The processor according to any one of clauses 1 to 5, wherein an application programming interface (API) causes one or more software drivers to simultaneously perform operations for preparing two or more software modules to be started simultaneously.

[0302] Clause 7. The processor according to any one of clauses 1 to 6, wherein simultaneously causing two or more software modules to be implemented by a processor includes simultaneously performing operations for preparing two or more software modules to be implemented by one or more graphics processing cores.

[0303] Clause 8. A processor according to any one of Clauses 1 to 7, including causing two or more software modules to be simultaneously implemented, which includes simultaneously performing operations for verifying that two or more software modules are configured to be implemented by one or more graphics processing units.

[0304] Clause 9. A processor according to any one of Clauses 1 to 8, wherein one or more circuits are for implementing one or more software drivers, and one or more software drivers include a data tracking structure for synchronizing one or more operations that should be performed in parallel and sequentially to prepare two or more graphics kernels to be launched.

[0305] Clause 10. A processor according to any one of Clauses 1 to 9, wherein one or more circuits are for implementing one or more software drivers, and one or more software drivers perform operations for encoding a work submission from one or more central processing cores to be implemented by one or more graphics processing cores.

[0306] Clause 11. A system comprising a memory for storing instructions, which, when executed by one or more processors, cause the system to cause two or more software modules to be simultaneously implemented by the processor to occur.

[0307] Clause 12. A system according to Clause 11, wherein the system is for implementing one or more software drivers, and one or more software drivers are for causing two or more software modules to be simultaneously implemented by the processor.

[0308] Clause 13. The system is for implementing one or more software drivers, and the one or more software drivers are for causing two or more graphics kernels to be implemented simultaneously by causing at least a first graphics kernel and a second graphics kernel to be implemented, the system according to Clause 11 or 12.

[0309] Clause 14. The system according to any one of Clauses 11 to 13, wherein two or more software modules include two or more graphics kernels to be implemented by a single graphics processing unit.

[0310] Clause 15. The system according to any one of Clauses 11 to 14, wherein two or more software modules include two or more graphics kernels to be implemented by a plurality of graphics processing units.

[0311] Clause 16. Causing two or more software modules to be implemented simultaneously includes simultaneously performing operations for verifying that the two or more software modules are configured to be implemented by one or more graphics processing units, the system according to any one of Clauses 11 to 15.

[0312] Clause 17. The system is for implementing one or more software drivers, and the one or more software drivers include a data tracking structure for synchronizing one or more operations to be performed in parallel and sequentially for preparing two or more graphics kernels to be launched, the system according to any one of Clauses 11 to 16.

[0313] Clause 18. The system for implementing one or more software drivers, wherein the one or more software drivers perform operations for encoding work submissions from one or more central processing cores to be performed by one or more graphics processing cores, the system according to any one of Clauses 11 to 17.

[0314] Clause 19. The system for implementing one or more software drivers, wherein the one or more software drivers include a data tracking structure for tracking the progress of operations to be performed in parallel and sequentially to prepare one or more graphics kernels to start up, the system according to any one of Clauses 11 to 18.

[0315] Clause 20. The system according to any one of Clauses 11 to 19, wherein causing two or more software modules to be executed simultaneously includes performing operations for encoding work submissions from different central processing cores to be performed by one or more graphics processing cores.

[0316] Clause 21. A machine-readable medium storing one or more instructions, which, when executed by one or more processors, cause the one or more processors to, at least, cause two or more software modules to be executed simultaneously by the processor to occur.

[0317] Clause 22. One or more circuits for implementing one or more software drivers, wherein the one or more software drivers are for causing two or more software modules to be executed simultaneously by a processor, the machine-readable medium according to Clause 21.

[0318] Clause 23. The machine-readable medium according to clause 21 or 22, wherein one or more circuits are configured to simultaneously cause one or more operations for starting a first one of two or more software modules to be performed simultaneously with one or more operations for starting a second one of the two or more software modules.

[0319] Clause 24. The machine-readable medium according to any one of clauses 21 to 23, wherein two or more software modules include two or more graphics kernels to be executed by a single graphics processing unit.

[0320] Clause 25. The machine-readable medium according to any one of clauses 21 to 24, wherein two or more software modules include two or more graphics kernels to be executed by a plurality of graphics processing units.

[0321] Clause 26. The machine-readable medium according to any one of clauses 21 to 25, wherein an application programming interface (API) is configured to cause one or more software drivers to simultaneously perform operations for preparing two or more software modules to be started simultaneously.

[0322] Clause 27. A method comprising the step of simultaneously causing two or more software modules to be executed by a processor. Including.

[0323] Clause 28. The method according to clause 27, wherein the step of simultaneously causing two or more software modules to be executed further comprises Performing operations for preparing two or more graphics kernels to be started on one or more graphics processing cores. Including.

[0324] Clause 29. The method further comprises obtaining one or more operations to operate in parallel and one or more operations to operate sequentially for starting two or more graphics kernels on one or more graphics processing cores The method according to clause 27 or 28.

[0325] Clause 30. The method further comprises receiving, from one or more central processing cores, a request for preparing two or more graphics kernels to be started on one or more graphics processing cores The method according to any one of clauses 27 to 29.

[0326] Clause 31. The method further comprises receiving, in one or more software drivers, an instruction from an application programming interface (API) for preparing two or more graphics kernels to be executed simultaneously, the method according to any one of clauses 27 to 30.

[0327] Clause 32. The method further comprises obtaining the status of preparing one or more graphics kernels to be started, at least partially based on a data tracking structure of one or more software drivers that track the progress of operations operating in parallel and operations operating sequentially for preparing one or more graphics kernels, the method according to any one of clauses 27 to 31.

[0328] Clause 33. The method further comprises performing one or more software drivers, and performing, in one or more software drivers, one or more operations for encoding a work submission from one or more central processing cores to be performed by one or more graphics processing cores The method according to any one of clauses 27 to 32, further comprising

[0329] Other variations are within the scope of the present disclosure. Accordingly, while the disclosed techniques are capable of various modifications and alternative constructions, some of their exemplary embodiments are shown in the drawings and described in detail above. However, it is not intended to limit the present disclosure to the specific one or more disclosed forms, and on the contrary, it is to be understood that it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the disclosure, as defined in the appended claims.

[0330] In the context of describing the disclosed embodiments (in particular, in the context of the following claims), the use of the terms "a", "an", and "the", as well as similar indicators, should be construed to cover both the singular and the plural, unless otherwise stated in this specification or clearly contradicted by the context, and should not be construed as a definition of the terms. The terms "comprising", "having", "including", and "containing" should be construed as open-ended terms (meaning "including, but not limited to") unless otherwise stated. The term "connected" should be construed, when unmodified and referring to a physical connection, as being joined to, either partially or wholly contained within, attached to, or engaged with one another, even if there is something intervening. The recitation of a range of values herein is merely intended to serve as a concise method of referring individually to each separate value that falls within the range, unless otherwise stated in this specification and unless each separate value is incorporated herein as if it were individually recited herein. The use of the term "set" (e.g., "a set of items") or "subset" should be construed as a non-empty set comprising one or more members, unless otherwise stated or contradicted by the context. Further, unless otherwise stated or contradicted by the context, the term "subset" of a corresponding set does not necessarily refer to a strict subset of the corresponding set, and the subset and the corresponding set may be equal.

[0331] Conjunctive words such as the phrase "at least one of A, B, and C" or "at least one of A, B and C" are understood in the context generally used to indicate that, unless otherwise specifically stated or clearly negated by the context, items, terms, etc. can be either any one of A or B or C, or any non-empty subset of the set of A, B, and C. For example, in an illustrative example of a set having three members, the conjunctive phrases "at least one of A, B, and C" and "at least one of A, B and C" refer to any one of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive words do not generally imply that some embodiments require the presence of at least one of each of at least one of A, at least one of B, and at least one of C. Further, unless otherwise stated or not apparent from the context, the term "plurality" indicates a plural state (e.g., "a plurality of items" indicates multiple items). The number of items that are plural is at least two, but may be more when so indicated either explicitly or by the context. Further, unless otherwise stated or not apparent from the context, the phrase "based on" means "at least partially based on" and does not mean "based only on".

[0332] The operations of the processes described herein may be performed in any suitable order, unless otherwise stated herein or clearly precluded by context. In at least one embodiment, a process such as a process described herein (or a variation and / or combination thereof) is performed under the control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or by a combination thereof. In at least one embodiment, the code is stored in a computer-readable storage medium in the form of, for example, a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium excludes a transient signal (e.g., a propagating transient electrical or electromagnetic transmission), but includes non-transitory data storage circuit elements (e.g., buffers, caches, and queues) within a transceiver of the transient signal, and is a non-transitory computer-readable storage medium. In at least one embodiment, the code (e.g., executable code or source code) is stored in a set of one or more non-transitory computer-readable storage media, the storage media storing executable instructions that, when executed by one or more processors of a computer system (e.g., as a result of being executed), cause the computer system to perform the operations described herein (or have other memory for storing the executable instructions). The set of non-transitory computer-readable storage media comprises, in at least one embodiment, a plurality of non-transitory computer-readable storage media, one or more of the individual non-transitory storage media of the plurality of non-transitory computer-readable storage media having none of the code, but the plurality of non-transitory computer-readable storage media collectively storing all of the code.In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors. For example, a non-transitory computer-readable storage medium stores the instructions, a main central processing unit (“CPU”) executes some of the instructions, and a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors, and different processors execute different subsets of instructions.

[0333] Accordingly, in at least one embodiment, a computer system is configured to implement one or more services that perform the operations of the processes described herein, either alone or in combination, and such a computer system is composed of applicable hardware and / or software that enables the performance of the operations. Further, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment, a distributed computer system that operates in different ways such that a distributed computer system comprising a plurality of devices performs the operations described herein and a single device does not perform all the operations.

[0334] Any examples provided herein, or the use of exemplary language (e.g., “such as”), are intended merely to clarify embodiments of the present disclosure and do not limit the scope of the present disclosure unless otherwise claimed. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the present disclosure.

[0335] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference had been individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0336] In the specification and claims, the terms "coupled" and "connected" may be used along with their derivatives. It should be understood that these terms are not necessarily intended to be synonyms of each other. Rather, in certain instances, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other but still interact or cooperate with each other.

[0337] Unless otherwise specifically stated, throughout the specification, terms such as "processing," "computing," "calculating," or "determining" refer to actions and / or processes of a computer or computing system, or similar electronic computing device that manipulate and / or transform data represented as physical quantities, such as electronic quantities, within registers and / or memories of the computing system into other data similarly represented as physical quantities within memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0338] Similarly, the term "processor" can refer to any device, or portion of a device, that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. By way of non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can comprise one or more processors. A "software" process as used herein can include software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process can refer to a plurality of processes for performing instructions serially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein only when one or more methods can be embodied by a system and the method can be considered a system.

[0339] In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuit elements that take one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operations such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND / OR or XOR. In at least one embodiment, an arithmetic logic unit is stateless and made of physical switching components such as semiconductor transistors configured to form logic gates. In at least one embodiment, an arithmetic logic unit can operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit can be constructed as an asynchronous logic circuit with an internal state that is not maintained in an associated register set. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor and produce an output that can be stored by the processor in another register or memory location.

[0340] In at least one embodiment, as a result of processing instructions fetched by a processor, the processor presents one or more inputs or operands to an arithmetic logic unit and causes the arithmetic logic unit to produce a result based at least in part on instruction codes provided to the arithmetic logic unit's inputs. In at least one embodiment, the instruction codes provided to the ALU by the processor are based at least in part on instructions executed by the processor. In at least one embodiment, combinational logic in the ALU processes the inputs and produces an output placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on an output bus so that the result produced by the ALU is sent to a desired location by clocking the processor.

[0341] This specification may refer to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be implemented in various ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be implemented by transferring data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be implemented by transferring data via a computer network from an entity providing the data to an entity acquiring the data. This specification may also refer to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transferring data as input or output parameters of a function call, parameters of an application programming interface, or an inter-process communication mechanism.

[0342] The above description has been presented for exemplary implementations of the described techniques, but other architectures may be used to implement the described functionality and are intended to be within the scope of this disclosure. Further, for purposes of explanation, a specific distribution of responsibilities has been defined above, but various functions and responsibilities may be distributed and divided in different ways depending on the situation.

[0343] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

Claim 1 A processor comprising one or more circuits, wherein the one or more circuits cause the processor to concurrently execute two or more software modules, the one or more circuits execute one or more software drivers, and the one or more software drivers include a data tracking structure for synchronizing one or more operations that are executed in parallel and sequentially to prepare two or more graphics kernels to be launched, a processor. Claim 2 The processor according to claim 1, wherein the one or more circuits execute the one or more software drivers, and the one or more software drivers cause the processor to concurrently execute the two or more software modules. Claim 3 The processor according to claim 1, wherein one or more operations for launching a first software module among the two or more software modules are concurrently executed at the same time as one or more operations for launching a second software module among the two or more software modules by the one or more circuits. Claim 4 The processor according to claim 1, wherein the two or more software modules include the two or more graphics kernels implemented by a single graphics processing unit. Claim 5 The processor according to claim 1, wherein the two or more software modules include the two or more graphics kernels implemented by a plurality of graphics processing units. Claim 6 The processor according to claim 1, wherein an application programming interface (API) causes the one or more software drivers to concurrently execute operations for preparing the two or more software modules to be launched simultaneously. Claim 7 The processor according to claim 1, wherein the processor concurrently executing the two or more software modules includes concurrently executing operations for preparing the two or more software modules to be implemented by one or more graphics processing cores. Claim 8 Simultaneously implementing the two or more software modules includes simultaneously implementing an operation for verifying that the two or more software modules are set to be implemented by one or more graphics processing units, the processor according to claim 1.

9. The one or more circuits implement the one or more software drivers, and the one or more software drivers implement operations for encoding work submissions from one or more central processing cores that are implemented by one or more graphics processing cores, the processor according to claim 1.

10. A system comprising a memory for storing instructions, wherein when the instructions are implemented by one or more processors, the system causes the processor to simultaneously implement two or more software modules. The system implements one or more software drivers, and the one or more software drivers include a data tracking structure for synchronizing one or more operations that are performed in parallel and sequentially to prepare two or more graphics kernels to be launched, a system.

11. A system comprising a memory for storing instructions, wherein when the instructions are implemented by one or more processors, the system causes the processor to simultaneously implement two or more software modules. The system implements one or more software drivers, and the one or more software drivers include a data tracking structure for tracking the progress of operations that are performed in parallel and sequentially to prepare one or more graphics kernels to be launched, a system.

12. The system implements the one or more software drivers, and the one or more software drivers cause the processor to simultaneously implement the two or more software modules, the system according to claim 10 or 11.

13. The system according to claim 10 or 11, wherein the system implements the one or more software drivers, and the one or more software drivers cause two or more graphics kernels to be implemented simultaneously, at least a first graphics kernel and a second graphics kernel being implemented.

14. The system according to claim 10 or 11, wherein the two or more software modules include two or more graphics kernels implemented by a single graphics processing unit.

15. The system according to claim 10 or 11, wherein the two or more software modules include two or more graphics kernels implemented by a plurality of graphics processing units.

16. The system according to claim 10 or 11, wherein simultaneously implementing the two or more software modules includes simultaneously performing operations for verifying that the two or more software modules are configured to be implemented by one or more graphics processing units.

17. The system according to claim 10 or 11, wherein the system implements the one or more software drivers, and the one or more software drivers perform operations for encoding work submissions from one or more central processing cores implemented by one or more graphics processing cores.

18. The system according to claim 10 or 11, wherein simultaneously implementing the two or more software modules includes performing operations for encoding work submissions from different central processing cores implemented by one or more graphics processing cores.

19. A machine-readable medium storing one or more instructions, which, when executed by one or more processors, cause the one or more processors to cause at least the processor to simultaneously implement two or more software modules. A machine-readable medium in which the processor implements one or more software drivers, the one or more software drivers including a data tracking structure for synchronizing one or more operations that are executed in parallel and sequentially to prepare two or more graphics kernels to be launched.

20. The machine-readable medium according to claim 19, wherein the one or more processors implement the one or more software drivers, and the one or more software drivers cause the one or more processors to simultaneously execute the two or more software modules.

21. The machine-readable medium according to claim 19, wherein, by the one or more processors, one or more operations for launching a first software module among the two or more software modules are simultaneously executed at the same time as one or more operations for launching a second software module among the two or more software modules.

22. The machine-readable medium according to claim 19, wherein the two or more software modules include two or more graphics kernels implemented by a single graphics processing unit.

23. The machine-readable medium according to claim 19, wherein the two or more software modules include two or more graphics kernels implemented by a plurality of graphics processing units.

24. The machine-readable medium according to claim 19, wherein, by an application programming interface (API), the one or more software drivers simultaneously execute operations for preparing the two or more software modules so as to be launched simultaneously.

25. A step of causing a processor to simultaneously execute two or more software modules comprising a method, wherein the method acquires a status of preparing one or more graphics kernels to be launched, at least partially based on a data tracking structure of one or more software drivers that track the progress of operations that operate in parallel and sequentially to prepare the one or more graphics kernels. The method further comprising.

26. The step of simultaneously executing the two or more software modules further comprises performing an operation for preparing two or more graphics kernels to be launched on one or more graphics processing cores The method according to claim 25, comprising: **Claim 27** The method comprises: obtaining one or more concurrently operating operations and one or more sequentially operating operations for launching two or more graphics kernels on one or more graphics processing cores The method according to claim 25, further comprising: **Claim 28** The method comprises: receiving, from one or more central processing cores, a request for preparing two or more graphics kernels to be launched on one or more graphics processing cores The method according to claim 25, further comprising: **Claim 29** The method comprises: receiving, in the one or more software drivers, an instruction from an application programming interface (API) for preparing two or more graphics kernels to be simultaneously executed The method according to claim 25, further comprising: **Claim 30** The method comprises: performing, in the one or more software drivers, one or more operations for encoding a work submission from one or more central processing cores to be performed by one or more graphics processing cores The method according to claim 25, further comprising:

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