Determination and Use of Byte Error Position Signals

Abstract

To provide a byte error position signal determination and use method and circuit configuration.SOLUTION: A method identifies at least one byte error in a binary string containing a plurality of bytes. If the binary string is not erroneous, it is a code word in error code. A circuit configuration is capable of determining each of the at least two byte error position signals using an error syndrome component of the error code. It is designed so that at least two byte error position signals indicate whether or not the byte in the binary string associated with the byte error position signal is incorrect. At least two byte error position signals are determined in parallel.SELECTED DRAWING: None

Description

Background Art

[0001] It is known to recognize an error in data existing in the form of bytes for each byte and correct it for each byte. Here, a byte can include at least 2 bits. At least one error in at least one bit of one byte is called a byte error. When at least one bit of one byte is incorrect, a byte error exists. When only at least one bit of only one byte is incorrect, this is a single-byte error.

[0002] Correction of a single-byte error is described, for example, in (Non-Patent Document 1).

[0003] When bits of two different bytes are incorrect, this is a double-byte error. Therefore, when bits in k bytes are incorrect (that is, at least one bit in each of the k bytes has an error), it can be said that there is a k-byte error.

[0004] The general motivation is to quickly perform error correction of bytes that may be incorrect. This applies, for example, when data in byte form is read out of memory in parallel and provided in parallel. In such a scenario, it may also be advantageous to perform error correction in parallel.

[0005] Here, "parallel" particularly means that error correction for at least two bytes or a part of error correction is performed at least partly simultaneously (for example, also at least partly overlapping in time).

[0006] Byte error correction can be performed, for example, by Reed-Solomon codes.

[0007] OKANO (Patent Document 2) describes a circuit configuration for correcting a double-byte error using Reed-Solomon codes. Here, the drawback is that the correction of the double-byte error described in OKANO is relatively slow.

Prior Art Documents

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0009] The problem of the present invention is to eliminate the drawbacks of known solutions for correcting byte errors, and in particular, to enable error correction of errors in a plurality of bytes as quickly as possible.

[0010] In particular, one problem is to provide error correction for m-byte errors (m ≧ 2) related to memory cells, such as MRAM memory cells and RRAM memory cells, thereby enhancing the reliability of data read from the memory cells.

Means for Solving the Problem

[0011] This problem is solved according to the features of the independent claims. Preferred embodiments are apparent particularly from the dependent claims.

[0012] To solve the above problem, a circuit configuration for determining at least two byte error position signals, - identifying at least one byte error in a binary sequence including a plurality of bytes, - the binary sequence being the codeword of an error code when there is no error, - the circuit configuration being designed such that each of at least two byte error position signals can be determined using components of the error syndrome of the error code, and each of the at least two byte error position signals indicates whether the byte of the binary sequence associated with that byte error position signal is in error, - at least two byte error position signals are determined in parallel, is proposed.

[0013] It should be noted that one byte error position signal can be determined for each byte of the binary sequence. Thus, each byte of the binary sequence is combined or associated with a byte error position signal. The value of the byte error position signal indicates whether the byte associated with the byte error position signal has an error.

[0014] The error code is, for example, an error correction and / or error detection code. For example, a Reed-Solomon code can be used as the error code.

[0015] In this context, "parallel" means, in particular, that at least a part of them are parallel to each other, that is, for example, the values are determined simultaneously in time or at least partially simultaneously in time.

[0016] In one variant form, the circuit configuration can determine a byte error position signal using the components of the error syndrome of the error code, and the byte error position signal is designed to indicate that there are correctable errors for at least two bytes among the bytes of the binary sequence.

[0017] In one variant form, the error code is a t-byte error correction code, and at least (t + 1) byte error position signals are determined in parallel.

[0018] In one variant form, the binary sequence has a 2-byte error.

[0019] In one variant form, each byte of the binary sequence has m bits, where m ≥ 2 holds.

[0020] In one variant form, the error code is - a t-byte error correction code, or - a t-byte error correction and (t + 1)-byte error detection code where t ≥ 2 holds.

[0021] In one variant form, the binary sequence has at least (t + 1) correctable bytes.

[0022] In one variant form, the error syndrome has at least 2·t components s1, s2,..., s 2t where each component contains m bits respectively and m ≥ 2.

[0023] A correctable byte is a byte for which error correction is performed when a byte error can be corrected by a byte error correction code if there is a byte error within that byte.

[0024] In one variant, the byte error position signal has a first value if the byte associated with the byte error position signal is incorrect, and a second value if the byte associated with the byte error position signal is not incorrect.

[0025] In one variant, at least one of the byte error position signals is determined for at least one corrected byte.

[0026] In one variant, the binary sequence includes data bytes and check bytes, and the data bytes and / or the check bytes constitute correctable bytes.

[0027] In particular, only the data bytes can be corrected. It is also possible to correct only the check bytes or a combination of the data bytes and the check bytes. Here, the data bytes may be the used data, and the check bytes may be additional check information that can be used for correcting the used data.

[0028] Also, in order to solve the above problems, a circuit configuration for correcting at least one byte error in a binary sequence including a plurality of bytes, where the binary sequence is, when correct, the codeword of an error code, and the circuit configuration is - determining at least one byte error position signal using components of the error syndrome of the error code, and it being possible to determine whether a byte of the binary sequence is incorrect by means of the byte error position signal, - determining at least one byte error correction value, and being able to correct the incorrect byte position identified by the byte error position signal based on the byte error correction value, - designed such that at least one of the byte error correction values is determined for at least one correct byte, a circuit configuration is proposed.

[0029] In one variant, at least one byte error position signal and / or at least one byte error correction value are determined in parallel.

[0030] In particular, at least two byte error correction values can be determined in parallel.

[0031] In one variant, the error code is a t-byte error correction code, and at least (t + 1) byte error position signals are determined in parallel.

[0032] In one variant, the error code is a t-byte error correction code, and at least (t + 1) byte error correction values are determined in parallel.

[0033] In one variant, at least (t + 1) byte error correction values are determined using at most three Galois field multipliers, where t ≥ 2.

[0034] In one variant, the circuit configuration is designed to correct one of the byte errors by operating the byte error position signal with the byte error correction value for the incorrect byte.

[0035] In one variant, the circuit configuration is designed to correct t-byte errors, where t ≥ 2 holds.

[0036] In one variant, the circuit configuration is further designed to correct one-byte errors.

[0037] In one variant, the circuit configuration is further designed to correct τ-byte errors, where t ≥ τ > 2 holds.

[0038] In one variant, in the case of a two-byte error, if the i-th byte is a correctable byte, - the byte error position signal for the i-th byte is

Equation

Equation

[0039] In a variant form, in the case of a 2-byte error, the byte error correction value of the i-th byte is

Number

[0040] The circuit configuration can be divided into individual sub-circuit configurations. In particular, the circuit configuration described here can be realized with one or multiple components.

[0041] Furthermore, the circuit configuration can be realized using synthesis tools.

[0042] In a variant form, in the case of a 2-byte error, the correction of correctable bytes is determined according to three components of the error syndrome and the byte error position signal.

[0043] Also, a method for determining at least two byte error position signals, - identifying at least one byte error in a binary sequence including a plurality of bytes, - when the binary sequence is correct, it is the codeword of the error code, - each of at least two byte error position signals is determined using components of the error syndrome of the error code to indicate whether the byte of the binary sequence related to the byte error position signal is incorrect, - at least two byte error position signals are determined in parallel, a method is presented.

[0044] Furthermore, a method for correcting at least one byte error in a binary sequence including a plurality of bytes, where the binary sequence is the codeword of the error code when it is correct, and the above method is -Determining at least one byte error position signal using components of the error syndrome of the error code, and determining whether a byte of the binary sequence is incorrect by the at least one byte error position signal; Determining at least one byte error correction value, based on which the incorrect byte position identified by the byte error position signal is corrected; Determining at least one of the byte error correction values for at least one correct byte; A method is presented.

[0045] Hereinafter, the above-described characteristics, features, and advantages of the present invention, and the manner of achieving them, will be described in connection with a schematic description of exemplary embodiments. The exemplary embodiments will be described in more detail in connection with the drawings. Here, for clarity, the same reference numerals can be assigned to the same elements or elements having the same function. BRIEF DESCRIPTION OF THE DRAWINGS

[0046]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

DETAILED DESCRIPTION OF THE INVENTION

[0047] As an example, byte error correction using Reed-Solomon codes will be described below. Here, a byte can include a plurality of bits.

[0048] For each correctable byte position, a signal (also called a byte error position signal) is specified that enables determination of whether that byte is in error. For example, the byte error position signal has a value of 1 when the byte is in error and a value of 0 when the byte is not in error.

[0049] The byte error position signal is preferably determined by the value of a locator polynomial. In the case of byte error correction codes, one locator polynomial can be used for each number of errors.

[0050] Therefore, it is particularly proposed to determine the byte error position signal for the correctable byte positions of a byte error correction code, where the byte error correction code can particularly correct at least two byte errors.

[0051] Here, the correctable byte position is the byte position at which correction is performed when an error correctable by a byte error correction code occurs.

[0052] A byte is, for example, a data byte, a combination of a data byte and a check byte, or a subset thereof. The data byte preferably includes the data in use.

[0053] Regarding the byte position, a byte error correction value can be determined, and based on the byte error correction value, the byte position is corrected when an error occurs there. The byte error position signal indicates whether an error has occurred for a certain byte, and this error can be corrected by the byte error correction value. Also, the individual byte positions can be masked by the byte error position signal, in which case no correction is performed.

[0054] In particular, one option is to multiply by 0 the byte error correction value that is not used for correction at the byte position (for example, because the byte position is correct). To that extent, multiplying by 0 the byte error correction value also corresponds to not using the byte error correction value at the byte position.

[0055] General description of Reed - Solomon codes Hereinafter, some concepts and characteristics of Reed - Solomon codes will be described.

[0056] For example, - a t - byte error correction code, and - a t - byte error correction and (t + 1) - byte detection code are considered. In particular, the cases of t = 2 and t = 1 are considered.

[0057] For example, a Reed - Solomon code known as a byte error correction code can be used. Regarding the Reed - Solomon code, see, for example, (Patent Document 3) or (Patent Document 4).

[0058] The 1-byte error correction and 2-byte error detection Reed-Solomon code has the following H matrix

Number

Number

[0059] Here, α i is an element of the Galois field GF(2 m ). This is, for example, an exponential function representation. α may be a primitive element of the Galois field GF(2 m ). The exponent j of α j can be interpreted as mod2 m -1.

[0060] From the H matrix according to Equation (1), the following H matrix can be derived.

Number

[0061] For the 2-byte error correction and 3-byte error detection code, the following H matrix is used.

Number

[0062] Each column of the H matrix represented by Equation (3) corresponds to 1 byte.

[0063] When the symbol length is N bytes or m·N bits (where each byte has m bits), only N columns of the H matrix according to Equation (1) or Equation (3) are used. For example, the remaining (last) 2 m -2-N columns can be deleted.

[0064] In general, for a t-byte error correction and t + 1-byte error detection code, the H matrix can be expressed as follows.

Number

[0065] Hereinafter, as an example, a code that can correct 2-byte errors and detect 3-byte errors will be considered.

[0066] When an error occurs, the correct vector v = v 0 ,…,v N-1 is scrambled into the incorrect vector v ’ = v ’0 ,…,v ’N-1 .

[0067] The components v 0 ,…,v N-1 of the vector v are bytes each containing m bits. Thus, for i = 0,…, N - 1,

Number

Number

[0068] The m-bit byte can also be called an element of the Galois field GF(2 m ).

[0069] In the case of a 1-byte error, only one byte is incorrect, that is, for a specific i ∈ {0,…, N - 1}, the associated i-th byte is incorrect.

[0070] The correct i-th byte is

Number

Number

[0071] The byte error in the i-th byte is - the incorrect byte position i, and - the byte error value, can be represented as follows.

Number

Number

[0072] The position of the i-th byte can also be represented as α i and.

[0073] When the byte error is corrected by the byte error value e at the byte position i i a byte error correction value equal to the byte error value can be determined for the byte position i.

[0074] In this example, for the byte error to be corrected, the byte error value is equal to the byte error correction value; to that extent, the concepts "byte error value" and "byte error correction value" can be used synonymously.

[0075] To avoid the subscript numbers from becoming difficult to read, hereinafter, the byte error value is represented by the alphabetic characters a, b, c.

[0076] The byte error correction value for the i-th byte can also be represented as a(i).

[0077] The byte positions are i, j, k, …, or α i , α j , α k , … and can be represented by this, where α is a generating element of the Galois field GF(2 m ).

[0078] The error syndrome s has syndrome components (also called components, error syndrome components, partial error syndromes, partial syndromes) s1, s2, s3, s4, s5, and these are determined as follows with respect to the H matrix by Equation (3). s1 = (α 0 , α 0 , …, α 0 ) · (v ’0 , v ’1 , …, v ’N-1 ) T , s2 = (α 0 , α 1 , …, α N-1 ) · (v ’0 , v ’1 , …, v ’N-1 ) T , s3 = (α 0 , α 2 , …, α 2(N-1) ) · (v ’0 , v ’1 , …, v ’N-1 ) T , s4 = (α 0 , α 3 , …, α 3(N-1) ) · (v ’0 , v ’1 , …, v ’N-1 ) T , s5 = (α 0 , α 4 , …, α 4(N-1) ) · (v ’0 , v ’1 , …, v ’N-1 ) T

[0079] Here, (v ’0 , …, v ’N-1 ) T is a column vector having components v ’0 , …, v ’N-1 , and this column vector can also be called the transposed vector of the row vector (v ’0 , …, v ’N-1 ).

[0080] The syndrome components s1, s2, s3, s4, s5 each constitute a byte having m bits.

[0081] When there is no error, s1 = s2 = s3 = s4 = s5 = 0 holds.

[0082] When there is a one-byte error having a byte error value α at the i-th byte error position, the following equation holds. s1 = α 0 ·a = a s2 = a i ·a s3 = a 2i ·a s4 = a 3i ·a s5 = a 4i ·a (4)

[0083] When there is a two-byte error having byte error values a and b at byte error positions i and j, the following equation holds. s1 = α 0 a + α 0 b = a + b s2 = a i ·a + α j ·b s3 = a 2i ·a + α 2j ·b s4 = a 3i ·a + α 3j ·b s5 = a 4i ·a + α 4j ·b (5)

[0084] If there is a 3-byte error with byte error positions i, j, and k and byte error values a, b, and c, the following equations hold. s1 = α 0 a + α 0 b + α 0 c = a + b + c s2 = a i ·a + α j ·b + α k ·c s3 = a 2i ·a + α 2j ·b + α 2k ·c s4 = a 3i ·a + α 3j ·b + α 3k ·c s5 = a 4i ·a + α 4j ·b + α 4k ·c (6)

[0085] Regarding the errors under consideration, the following relationships are satisfied. 1. For 1-byte errors, s1 = a ≠ 0 (7) And

Number

Number

Number

Number

[0086] Byte error position α i And α j In the case of a 2-byte error in the i-th and j-th bytes, the equation

Number

Number

[0087] Correspondingly, the byte error position for a single-byte error is determined by the zero position of the first-order locator polynomial. Generally, 1 ≦ τ ≦ t For, the incorrect byte positions in the τ-byte error for a t-byte error correction code are determined by the zero positions of the τ-order locator polynomial.

[0088] When the codeword consists of N·m bits and thus N bytes, there are N different byte positions regarded as byte error positions. In contrast, in the corresponding bit correction code, there are m·N bit positions that may be incorrect.

[0089] The first-order locator polynomial is used for a single-byte error, and the second-order locator polynomial is used for a two-byte error.

[0090] Supplementary Explanation of Reed-Solomon Code In the case of a two-byte error, the byte error correction value a(i) for the i-th byte can be determined according to only the syndrome components s1, s2, s3 and the byte position i.

[0091] Here, for example, it is an advantage that multiple byte error correction values can be determined in parallel for at least three correctable bytes.

[0092] For example, assume there is a 2-byte error. The byte error correction values for each byte position can be determined in parallel based on the provided syndrome components s1, s2, s3, and the known positions of the correctable bytes. The byte error correction values are determined for both of the incorrect bytes and at least for the non-incorrect bytes.

[0093] The byte error correction value determined for the i-th byte position matches the byte error value at this i-th position.

[0094] Similarly (and in some cases in parallel), the determined byte error position signals determine whether there is a byte error in the target byte and whether to perform correction using the byte error correction value. If the byte error position signal indicates that there is no byte error at the corresponding position, no correction is performed using the byte error correction value determined for this position.

[0095] In other words, the byte error position signal determines at which byte positions to perform correction using the provided byte error correction value. If the byte error position signal for a certain byte position indicates a byte error, correction is performed using the byte error correction value. If the byte error position signal for this byte position does not indicate a byte error, no correction is performed.

[0096] Considering a t-byte error correction code, the corresponding byte error correction values for more than t correctable byte positions can be determined, and then the byte error position signals for all or some of the byte positions are determined. The byte error correction values can also be determined in parallel with the byte error position signals.

[0097] If there is no byte error in the i-th byte, the byte error correction value determined for this i-th byte is not used for correction based on the value of the byte error position signal. In this case, since no correction is performed based on the byte error position signal, the byte error correction value determined for this non-incorrect byte

Number

[0098] In the case of a 2-byte error, for the byte error position i, the byte error correction value a(i) of the i-th byte is given by the formula [Number] can be determined to hold.

[0099] For a 2-byte error, if the byte position i where the byte error has occurred is known, based on formula (13), the byte error correction value a(i) for the incorrect byte position i is determined from the syndrome components s1, s2, s3, and the value α i determined by

[0100] For the byte position k, the byte error correction value a(k) is [Number] determined in parallel as, for example,

[0101] and is independent of whether the byte position k is actually incorrect.

[0102] If the byte error position signal indicates that there is a byte error at the byte position k, the error correction of the k-th byte is performed by the byte error correction value a(k) determined for this byte position k.

[0103] Thus, the byte error correction value for a byte position exists already before it is determined whether an error actually occurs at this byte position.

[0104] For various byte positions, the corresponding byte error correction values can be determined in parallel. In particular, for all correctable byte positions, or for a subset of the correctable byte positions, the byte error correction values can be determined in parallel.

[0105] If a byte error correction code can correct up to t erroneous bytes, for example, for all correctable byte positions, or for a subset of at least t + 1 correctable byte positions, more than t byte error correction values can be determined in parallel regardless of whether there is a byte error at the byte position.

[0106] The value of the byte error position signal determines whether the byte error correction value is used for correcting the corresponding byte.

[0107] The correctable byte positions can be, for example, all data bytes, a subset of the data bytes, check bytes, all bytes of the codeword of a t - byte error correction code, or a subset of the bytes of the codeword of a t - byte error correction code.

[0108] Here, the byte error position signal can be determined, for example, with respect to a byte position to take a first value if the byte at the byte position is in error and to take a second value different from the first value if the byte at the byte position is not in error.

[0109] The byte error position signal can be determined using the corresponding locator polynomial.

[0110] Byte error position signal for a single - byte error For a single - byte error, the first - order locator polynomial is x·s1 = s2(15), and the solution or zero position

Number

[0111] The byte error correction value a(i) for the incorrect byte position i is a(i)=s1(17) is.

[0112] For each k-th byte, the byte error correction value a(k)=s1=a (18) is determined.

[0113] If the error at the i-th byte has the byte error correction value a and thus s1 = a, for each byte k, the byte error correction value a(k)=a is determined according to equation (18). The byte error correction value a(k)=a is used for the i-th byte to be actually corrected and masked (e.g., set to zero) for the bytes not to be corrected. The decision on whether a byte is corrected or not is made based on the value of the corresponding byte error position signal.

[0114] For each byte, in the case of a single-byte error, the byte error position signal is determined using equation (15). The byte error position signal for the byte position i is -α i is 1 if it is the zero position of the locator polynomial according to equation (15), -α i is 0 if it is not the zero position of the locator polynomial according to equation (15).

[0115] The correction of the i-th byte is performed only if α i is the zero position of the locator polynomial according to equation (15).

[0116] Byte error position signal for double-byte error The action of the byte error position signal in the correction of double-byte errors will be described based on an example.

[0117] When a t-byte error correction code is used with t ≧ 2, in the case of a 2-byte error, the positions of the incorrect bytes are determined by the two zero positions of the quadratic locator polynomial according to Equation (12).

[0118] If the positions of the incorrect bytes are positions i and j, the byte error position signal is, for example, α i and α j is 1 when they are the zero positions of the quadratic locator polynomial according to Equation (12), and 0 in all other cases

[0119] For each byte position k, the byte error correction value

Number

[0120] The value of the byte error position signal for byte position k determines whether correction is performed at this byte position k. If the byte error position signal is 1, correction is performed; if the byte error position signal is 0, no correction is performed.

[0121] For byte position k = i, the byte error correction value a(i) is determined such that the incorrect i-th byte is corrected by the byte error correction value a(i). Similarly, for byte position k = j, the byte error correction value a(j) is determined such that the incorrect j-th byte is corrected by the byte error correction value a(j).

[0122] For all other byte positions k where k ≠ i, j, there is no byte error, and thus no correction is performed for these byte positions. Since the byte error position signal takes the value 0 at this byte position and thus no correction is required for this byte position, the byte error correction value a(k) is not used for correction even when it is determined to be non-zero.

[0123] Processing of 1-byte error, 2-byte error, and 3-byte error The following describes how to recognize byte errors and distinguish them from each other. For example, consider a 2-byte error correction code. As a supplement, 3-byte error recognition will also be described.

[0124] 1. First, start with the case where only 1-byte errors or 2-byte errors exist. In such an example, for 2-byte errors, according to Equation (9),

Number

Number

[0125] Furthermore, it is possible to distinguish the case where neither 1-byte errors nor 2-byte errors have occurred. Since s1 = 0 already, it can be concluded that neither 1-byte errors nor 2-byte errors have occurred.

[0126] When the probability of 3-byte errors is extremely small, in this case, it can be concluded that no errors have occurred.

[0127] 2. Here, consider the case where only 1-byte errors, only 2-byte errors, or only 3-byte errors exist. For 3-byte errors, according to Equation (11),

Number

[0128] Correspondingly, for 2-byte errors or 1-byte errors,

Number

[0129] When there are 2-byte errors, furthermore, Equation (9)

Number

[0130] Regarding 1-byte errors, equations (7) and (8)

Number

[0131] Since the condition by equation (9) also holds for 3-byte errors, from this condition alone, it cannot be concluded that there are 2-byte errors.

[0132] Correction of 2-byte errors can be performed as follows. For each byte position i where i ∈ {0, 1, …, N - 1}, the value L(α i ) of the quadratic locator polynomial is determined according to the following equation.

Number

[0133] L(α i ) = 0, the i-th byte is corrected. If L(α i ) ≠ 0, the i-th byte is not corrected. The byte error position signal BPs i can indicate whether the correction of each byte is performed. The byte error position signal BPs i is determined, for example, by

Number

[0134] Galois field GF(2 m) In a circuit configuration that realizes operations, for example, a multiplier, a constant multiplier, a squarer, a cube (third power) generator, etc. are adopted. The circuit technology adoption of each such operation is known. Hereinafter, as an example, in a Galois field determined by a remainder polynomial, for example, how a multiplier, a squarer, a cube generator, and a constant multiplier can be realized will be described. For example, assuming m = 5, a byte consists of m = 5 bits, and the corresponding Galois field is GF(2 5 )

[0135] In the Galois field GF(2 m ) for m = 5 For example, m = 5 is selected, and the underlying Galois field GF(2 m ) = GF(2 5 ) = GF(32) contains a total of 32 elements

[0136] The elements of the Galois field GF(32) are represented in various forms in Figure 13. The remainder polynomial of the Galois field GF(32) is the polynomial p(x) = 1 + x 2 + x 5 )

[0137] The first column of the table shown in Figure 13 is in exponential representation (also called exponential function representation), and contains the elements α 5 ) of GF(2 i ≠ 0 for i = 0, 1,..., 30. The zero element of the field does not have an exponential representation. In the second column of the table, all elements are listed in polynomial representation with respect to the associated remainder polynomial p(x). The third column of the table shows the tuple or vector representation of the elements of GF(2 5 ). The vector representation of the elements can be directly read from the polynomial representation. Here, the five components of the vector representation, from left to right, are the coefficients of the associated powers of x x 0 , x 1 , x 2 , x 3 , x 4 )

[0138] The corresponding polynomial expression is obtained from the power expression α i mod (1 + x 2 + x 5 ). For example, the polynomial expression of α5 is i x x 5 mod (1 + x 2 + x 5 ) = 1 + x 2 Since this holds, it is 1 + x 2 .

[0139] The multiplication of two elements of the Galois field can be performed in the exponent expression or the polynomial expression. When two elements of the Galois field GF(2 m ) = GF(2 5 ) are given in the exponent expression α i and α j , their product is as follows. α i ·α j = α k Here, k = (i + j) mod (2 m - 1) = (i + j) mod 31

[0140] When the elements to be multiplied in the Galois field are in the vector expression or the polynomial expression, their multiplication can be performed by a Galois field multiplier. Hereinafter, as an example, the multiplication of two elements in the polynomial expression will be described. To multiply two elements given in the polynomial expression as elements of the Galois field GF(2 m ) = GF(2 5 ), the polynomials can be directly multiplied by each other in the normal manner, and the result can be determined as the remainder of the remainder polynomial.

[0141] For example, given the polynomials 1 + x 2 + x 3 and x + x 3 , their direct multiplication (1 + x 2 + x 3 )(x + x3 ) = x + x 4 + x 5 + x 6 is obtained.

[0142] x 5 = 1 + x 2 mod (1 + x 2 + x 5 ) and x 6 = x + x 3 mod (1 + x 2 + x 5 ) by x + x 4 + x 5 + x 6 = x + x 4 + 1 + x 2 + x + x 3 = 1 + x 2 + x 3 + x 4 becomes.

[0143] Therefore, as a result, (1 + x 2 + x 3 )·(x + x 3 ) = 1 + x 2 + x 3 + x 4 holds.

[0144] Hereinafter, in the Galois field GF(2 m(x) = x 5 + x 2 + 1 ) having 5 the first element a(x) a(x) = a4x 4 + a3x 3 + a2x 2 + a1x + a0 and the second element b(x) b(x) = b4x 4 + b3x 3 + b2x 2 + b1x + b0 Describe the case where they are multiplied. By directly multiplying the polynomials a(x) and b(x), first, an 8th-degree polynomial is obtained. x 5 mod (1 + x 2 + x 5 ) = 1 + x 2 , x 6 mod (1 + x 2 + x 5 ) = x + x 3 , x 7 mod (1 + x 2 + x 5 ) = x 2 + x 4 , x 8 mod (1 + x 2 + x 5 ) = 1 + x 2 + x 3 By this, a 4th-degree polynomial is obtained as follows. c4x 4 + c3x 3 + c2x 2 + c1x 1 + c0 = a(x)·b(x) mod m(x) = = (a0b4 + a1b3 + a2b2 + a3b1 + a3b4 + a4b0 + a4b3)·x 4 + + (a0b3 + a1b2 + a2b1 + a2b4 + a3b0 + a3b3 + a4b2 + a4b4)·x 3 + + (a0b2 + a1b1 + a1b4 + a2b0 + a2b3 + a3b2 + a3b4 + a4b1 + a4b3 + a4b4)·x 2 + + (a0b1 + a1b0 + a2b4 + a3b3 + a4b2)·x 1 + + (a0b0 + a1b4 + a2b3 + a3b2 + a4b1 + a4b4)

[0145] This relationship is realized by a Galois field multiplier having five first binary inputs, five second binary inputs, and five binary outputs. This will be described in detail below.

[0146] For the first five inputs of the Galois field multiplier, binary values a0, a1, a2, a3, a4 are input, for the second five inputs, binary values b0, b1, b2, b3, b4 are input, and for the five binary outputs, values c0, c1, c2, c3, c4 are output, where (a0b0 + a1b4 + a2b3 + a3b2 + a4b1 + a4b4) = c0, (22) (a0b1 + a1b0 + a2b4 + a3b3 + a4b2) = c1(23) (a0b2 + a1b1 + a1b4 + a2b0 + a2b3 + a3b2 + a3b4 + a4b1 + a4b3 + a4b4) = c2(24) (a0b3 + a1b2 + a2b1 + a2b4 + a3b0 + a3b3 + a4b2 + a4b4) = c3(25) (a0b4 + a1b3 + a2b2 + a3b1 + a3b4 + a4b0 + a4b3) = c4(26) Here, the symbol “+” represents mod2 addition (XOR operation).

[0147] The implementation of equations (22) to (26) can be performed by a Galois field multiplier, for example, using AND gates and XOR gates (exclusive OR gates). For example, within the scope of implementation, synthesis tools can also be used.

[0148] a(x) = a0 + a1x 1 + a2x 2 + a3x 3 + a4x 4 when given as (a(x)) 2 mod m(x) = = [a0 + a1x 2 + a2x 4 + a3x 6 + a4x 8 mod (1 + x 2 + x 5 ) = = (a2)x4 +(a3 + a4)x 3 +(a1 + a4)x 2 +a3x 1 +(a0 + a4) holds true.

[0149] Correspondingly, the square of an element in the Galois field GF(2 5 ) can be realized by a squarer with five binary inputs and five binary outputs. The five binary inputs are supplied with binary values a0, a1, a2, a3, a4, and the five binary outputs provide binary values d0, d1, d2, d3, d4. a0 + a4 = d0, (27) a3 = d1, (28) a1 + a4 = d2, (29) a3 + a4 = d3, (30) a2 = d4, (31) holds true, where the symbol ‘+’ also indicates mod2 addition (XOR operation) here.

[0150] The remainder polynomial m(x) = 1 + x 2 + x 5 For realizing the squarer in the Galois field GF(2 5 ), equations (27) to (31) can be implemented by, for example, XOR gates.

[0151] In the example of the Galois field GF(2 5 ), describe how to determine the cube of an element given in polynomial representation.

[0152] Polynomial a(x) = a0 + a1x 1 + a2x 2 + a3x 3 + a4x 4 The cube (a(x)) 3 is determined as the remainder of the polynomial m(x) = 1 + x 2 + x 5 When determined as the remainder, the following equation holds true. (a(x)) 3mod m(x)= =(a0a2 + a0a4 + a1a2 + a1a3 + a1a4 + a2a3 + a2a4 + a3 + a3a4)·x 4 + +(a0a4 + a1 + a2 + a2a3 + a2a4 + a3 + a4)·x 3 + +(a0a1 + a0a2 + a0a4 + a1a2 + a2a4 + a3a4 + a4)·x 2 + +(a0a1 + a0a3 + a2 + a3 + a3a4 + a4)·x 1 + +(a0 + a0a4 + a1a2 + a1a3 + a2a3)

[0153] Correspondingly, the generation of the cubes of the elements in the Galois field GF(2 5 ) can be realized by a cube generator having five binary inputs and five binary outputs. The five binary inputs are supplied with the binary values a0, a1, a2, a3, a4, and the five binary outputs provide the binary values f0, f1, f2, f3, f4. f0 = a0 + a0a4 + a1a2 + a1a3 + a2a3 (32) f1 = a0a1 + a0a3 + a2 + a3 + a3a4 + a4 (33) f2 = a0a1 + a0a2 + a0a4 + a1a2 + a2a4 + a3a4 + a4 (34) f3 = a0a4 + a1 + a2 + a2a3 + a2a4 + a3 + a4 (35) f4 = a0a2 + a0a4 + a1a2 + a1a3 + a1a4 + a2a3 + a2a4 + a3 + a3a4 (36) hold.

[0154] For example, the cube generator can be realized in this example in the Galois field GF(2 2 +x 5 ) having the remainder polynomial m(x) = 1 + x 5 ) simply by implementing equations (32) - (36).

[0155] Alternatively, the cube generator can be realized from a squarer and a Galois field multiplier connected downstream. Also, higher powers of the element a(x) can be realized in a corresponding manner using appropriate components.

[0156] The implementation of a constant multiplier in the Galois field GF(2 m ) is described below as an example for m = 5. The remainder polynomial is m(x)=1+x 2 +x 5 .

[0157] If a ∈ GF(2 5 ), any element of the Galois field can be represented in the following polynomial form. a(x)=a0+a1x+a2x 2 +a3x 3 +a4x 4 (37)

[0158] As the constant to be multiplied, for example, α 9 is selected, and its polynomial representation is, according to the table shown in Figure 13, α 9 (x)=x+x 3 +x 4 (38) . As the multiplication, a(x)·α 9 (x) mod (1+x 2 +x 5 )=b0+b1x+b2x 2 +b3x 3 +b4x 4 (39) is obtained, b0=a1+a2, (40) b1=a0+a2+a3, (41) b2=a2+a3+a4, (42) b3=a0+a3+a4, (43) b4=a0+a1+a4(44) .

[0159] The output values b0, …, b4 can be derived from the input values a0, …, a4 corresponding to the relationships represented by formulas (40) to (44), and the output values are determined by the XOR operation from the input values. Here, the symbol “+” indicates modulo 2 addition (XOR operation). Correspondingly, the constant multiplier can be realized by an XOR gate.

[0160] Explanation of the byte error position signal generator for generating the byte error position signal FIG. 1 shows an exemplary circuit configuration for determining the byte error position signal. For example, consider a two-byte error correction error code having a codeword consisting of n bytes each having m bits.

[0161] The circuit configuration has N byte error position signal generators 10, 11, …, 1i, …, 1N−1, and the byte error position signal generators 10, 11, …, 1i, …, 1N−1 provide byte error position signals BPs0, BPs1, …, BPs i , …, BPs N-1 via their respective 1-bit wide outputs.

[0162] To the respective 4·m-bit wide inputs of the N byte error position signal generators 10, 11, …, 1i, …, 1N−1, an error syndrome s = s1, s2, s3, s4 of 4·m-bit width provided by a syndrome generator (not shown in FIG. 1) is provided, and this error syndrome consists of syndrome components s1, s2, s3, s4 each of m-bit width.

[0163] When all bytes are corrected in the case of one error, N = n holds. When less than n bytes are corrected in the case of one error, N < n holds. For example, in the case of an error, only data bytes can be corrected. In such an example, parity bytes cannot be corrected.

[0164] The byte error position signal generator 10 is configured as follows, for example. - The byte error position signal generator 10

Number

Number

[0165] The byte error position signal generator 11 is configured as follows, for example. - The byte error position signal generator 11 is,

Number

Number

[0166] The byte error position signal generator 1i is configured as follows, for example. - The byte error position signal generator 1i is,

Number

Number

[0167] The byte error position signal generator 1N-1 is configured as follows, for example. -Byte error position signal generator 1N-1, [Number] when the following equations hold, byte error position signal BPs N-1 = 1 is output, -Byte error position signal generator 1N-1, [Number] when the following equations hold, byte error position signal BPs N-1 = 0 is output.

[0168] Here, the exponents of α mod 2 m -1 can each be interpreted.

[0169] If there are two-byte errors and the j-th byte and the k-th byte are in error, for i = j and for i = k, byte error position signal BPs i is 1, and for all remaining byte error position signals BPs l where l ≠ j, k, is 0, where 0 ≦ i, j, k, l ≦ N - 1, α 0 = 1 holds, and 1 is the identity element of the Galois field GF(2 m ).

[0170] Byte error position signal generator according to Figure 2 Figure 2 shows a circuit configuration showing a possible form of the circuit configuration shown in Figure 1.

[0171] The byte error position signal generator 10 shown in Figure 1 includes the following. -Sub-circuit 210 having one 4·m-bit width input for inputting components s1, s2, s3, and s4 of error syndrome s = s1, s2, s3, s4, and three m-bit width outputs, -Constant multiplier 220 having a first m-bit width input, a second m-bit width input, and one m-bit width output, - A constant multiplier 230 having a first m-bit width input, a second m-bit width input, and one m-bit width output, - An XOR circuit 240 having three m-bit width inputs each, and one m-bit width output, and - A NOR circuit 250 having one m-bit width input and one 1-bit width binary output

[0172] Sub-circuit 210, upon receiving an input of error syndrome s, - Outputs s1·s4 + s2·s3 at a first output, - At a second output, [Number] Outputs it, - At a third output, [Number] Outputs it and is designed to be like this.

[0173] The first output of sub-circuit 210 is connected to the first input of constant multiplier 220. A constant α 0 = 1 is input to the second input of constant multiplier 220, whereby at the output of constant multiplier 220, α 0 (s1·s4 + s2·s3)= s1·s4 + s2·s3 is provided.

[0174] The output of constant multiplier 220 is connected to the first input of XOR circuit 240.

[0175] The second output of sub-circuit 210 is connected to the first input of constant multiplier 230. A constant α 2·0 = α 0 is input to the second input of constant multiplier 230, whereby at the output of constant multiplier 230, [Number] is provided.

[0176] The output of the constant multiplier 230 is connected to the second input of the XOR circuit 240.

[0177] The third output of the partial circuit 210 is connected to the third input of the XOR circuit 240.

[0178] The XOR circuit 240 generates, for example, an XOR operation for each component of the m-bit-wide values input to its three inputs, and with its m-bit-wide output, the value

Number

[0179] The byte error position signal generator 11 shown in FIG. 1 includes the following. - A partial circuit 211 having one 4·m-bit-wide input for inputting the components s1, s2, s3, and s4 of the error syndrome s = s1, s2, s3, s4, and three m-bit-wide outputs, - A constant multiplier 221 having a first m-bit-wide input, a second m-bit-wide input, and one m-bit-wide output, - A constant multiplier 231 having a first m-bit-wide input, a second m-bit-wide input, and one m-bit-wide output, - An XOR circuit 241 having three m-bit-wide inputs each and one m-bit-wide output, and - A NOR circuit 251 having one m-bit-wide input and one 1-bit-wide binary output

[0180] When the partial circuit 211 receives the input of the error syndrome s, - With its first output, outputs s1·s4 + s2·s3, - With the second output,

Number

Number

[0181] The first output of the partial circuit 211 is connected to the first input of the constant multiplier 221. The constant α 1 is input to the second input of the constant multiplier 221, whereby at the output of the constant multiplier 221, α 1 (s1·s4 + s2·s3) is provided.

[0182] The output of the constant multiplier 221 is connected to the first input of the XOR circuit 241.

[0183] The second output of the partial circuit 211 is connected to the first input of the constant multiplier 231. The constant α 2 is input to the second input of the constant multiplier 231, whereby at the output of the constant multiplier 231,

Number

[0184] The output of the constant multiplier 231 is connected to the second input of the XOR circuit 241.

[0185] The third output of the partial circuit 211 is connected to the third input of the XOR circuit 241.

[0186] The XOR circuit 241 generates, for example, the XOR operation for each component of the values of m-bit width input to its three inputs, and with its output of m-bit width, the value

Number

[0187] The byte error position signal generator 1i shown in FIG. 1 includes the following. - a subcircuit 21i having one 4·m-bit wide input for inputting the components s1, s2, s3, and s4 of the error syndrome s = s1, s2, s3, s4, and three m-bit wide outputs, - a constant multiplier 22i having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output, - a constant multiplier 23i having a first m-bit wide input, a second m-bit wide input, and one m-bit wide output, - an XOR circuit 24i having three m-bit wide inputs each and one m-bit wide output, and - a NOR circuit 25i having one m-bit wide input and one 1-bit wide binary output

[0188] The subcircuit 21i, upon input of the error syndrome s, - outputs s1·s4 + s2·s3 at the first output, - at the second output,

Number

Number

[0189] The first output of the subcircuit 21i is connected to the first input of the constant multiplier 22i. A constant α is applied to the second input of the constant multiplier 22i iis input, whereby, at the output of the constant multiplier 22i, α i (s1·s4 + s2·s3) is provided.

[0190] The output of the constant multiplier 22i is connected to the first input of the XOR circuit 24i.

[0191] The second output of the partial circuit 21i is connected to the first input of the constant multiplier 23i. To the second input of the constant multiplier 23i, the constant α 2·i is input, whereby, at the output of the constant multiplier 23i,

Number

[0192] The output of the constant multiplier 23i is connected to the second input of the XOR circuit 24i.

[0193] The third output of the partial circuit 21i is connected to the third input of the XOR circuit 24i.

[0194] The XOR circuit 24i generates, for example, an XOR operation for each component of the m-bit-wide values input to its three inputs, and with its m-bit-wide output, the value

Number

[0195] The byte error position signal generator 1N-1 shown in FIG. 1 includes the following. - A sub - circuit 21N - 1 having one 4·m - bit - wide input for inputting components s1, s2, s3, and s4 of an error syndrome s = s1, s2, s3, s4, and three m - bit - wide outputs each, - A constant multiplier 22N - 1 having a first m - bit - wide input, a second m - bit - wide input, and one m - bit - wide output, - A constant multiplier 23N - 1 having a first m - bit - wide input, a second m - bit - wide input, and one m - bit - wide output, - An XOR circuit 24N - 1 having three m - bit - wide inputs each and one m - bit - wide output, and - A NOR circuit 25N - 1 having one m - bit - wide input and one 1 - bit - wide binary output

[0196] When the sub - circuit 21N - 1 receives the input of the error syndrome s, - At the first output, it outputs s1·s4 + s2·s3, - At the second output,

Number

Number

[0197] The first output of the sub - circuit 21N - 1 is connected to the first input of the constant multiplier 22N - 1. A constant α N-1 is input to the second input of the constant multiplier 22N - 1, whereby at the output of the constant multiplier 22N - 1, α N-1 (s1·s4 + s2·s3) is provided.

[0198] The output of the constant multiplier 22N - 1 is connected to the first input of the XOR circuit 24N - 1.

[0199] The second output of the partial circuit 21N-1 is connected to the first input of the constant multiplier 23N-1. A constant α 2·(N-1) is input to the second input of the constant multiplier 23N-1, whereby the output of the constant multiplier 23N-1 is

Number

[0200] The output of the constant multiplier 23N-1 is connected to the second input of the XOR circuit 24N-1.

[0201] The third output of the partial circuit 21N-1 is connected to the third input of the XOR circuit 24N-1.

[0202] The XOR circuit 24N-1 generates, for example, an XOR operation for each component of the m-bit wide values input to its three inputs, and with its m-bit wide output, the value

Number

[0203] Exemplary integration of partial circuits The partial circuits 210, 211, …, 21i, …, 21N-1 in FIG. 2 are functionally the same. Therefore, it is possible to integrate these partial circuits into a partial circuit 31.

[0204] FIG. 3 shows a partial circuit 31 that integrates the partial circuits 210, 211, …, 21i, …, 21N-1. The rest of the circuit portion shown in FIG. 3 is the same as in FIG. 2.

[0205] For example, byte error position signal generators 10, 11, …, 1i, …, 1N-1 according to FIG. 1 can use a common sub-circuit 31.

[0206] Exemplary implementation of sub-circuit 31 FIG. 4 shows a possible implementation of the sub-circuit 31 shown in FIG. 3.

[0207] The sub-circuit 31 has four inputs each with a width of m bits for inputting components s1, s2, s3, s4 that make up the syndrome s. Further, four multipliers 41, 42, 44, and 47 each having two inputs with a width of m bits and one output with a width of m bits, two squarers 45 and 48 each having one input with a width of m bits and one output with a width of m bits, and three XOR circuits 43, 46, and 49 each having two inputs with a width of m bits and one output with a width of m bits are provided.

[0208] The XOR circuits 43, 46, 49 each perform an XOR operation for each component of the m-component values input to their respective inputs. The multipliers perform multiplication in the Galois field GF(2 m ), and the squarers square the operand input to their input in the Galois field GF(2 m ) as well.

[0209] The input for sending component s1 is connected to the first input of multiplier 41 and the first input of multiplier 44.

[0210] The input for sending component s2 is connected to the first input of multiplier 42, the first input of multiplier 47, and the input of squarer 45.

[0211] The input for sending component s3 is connected to the second input of multiplier 42, the second input of multiplier 44, and the input of squarer 48.

[0212] The input for sending component s4 is connected to the second input of multiplier 41 and the second input of multiplier 47.

[0213] The output of multiplier 41 is connected to the first input of XOR circuit 43. The output of multiplier 42 is connected to the second input of XOR circuit 43. The output of XOR circuit 43 provides the signal s1s4 + s2s3.

[0214] The output of multiplier 44 is connected to the first input of XOR circuit 46. The output of squarer 45 is connected to the second input of XOR circuit 46. The output of XOR circuit 46 provides the signal [Number] is provided.

[0215] The output of multiplier 47 is connected to the first input of XOR circuit 49. The output of squarer 48 is connected to the second input of XOR circuit 49. The output of XOR circuit 49 provides the signal [Number] is provided.

[0216] Byte error correction value for 2-byte error FIG. 5 shows an exemplary circuit for generating a byte error correction value for a total of N bytes in the case of a 2-byte error. The N bytes to be considered are numbered from 0 to N - 1.

[0217] The byte error correction value a(i) for the i-th (0 ≦ i ≦ N - 1) byte cor is determined according to the actual error syndrome s, the byte position i, and the byte error position signal BPs i as a(i) cor = BPs i · a(i) is determined according to.

[0218] For example, the byte error correction value is determined for all N byte positions. For byte positions that are not in error, the byte error correction value is masked. For example, the masking is performed by multiplying the byte error correction value by a byte error position signal having a value of 0.

[0219] If there are 2-byte errors at byte positions i and j, the i-th and j-th bytes can be corrected. This is done by XORing the i-th and j-th bytes with the corresponding byte error correction value a(i) cor =a(i)≠0 or a(j) cor =a(j)≠0 for each component.

[0220] Bytes that are not incorrect are not corrected. For this purpose, for those byte positions, the byte error correction value is set to 0 (e.g., multiplication of the previously described byte error correction value by 0), and then the byte to be corrected is XORed with this value 0 for each component. The XOR operation with the value 0 does not change the original value.

[0221] For the i-th incorrect byte, the byte error position signal is BPs i =1, and a(i) cor =BPs i ·a(i)=a(i) holds.

[0222] For the j-th incorrect byte, the byte error position signal is BPsj = 1, and a(j) cor =BPsj·a(j)=a(j) holds.

[0223] For the k-th (k≠i,j) non-incorrect byte, the byte error position signal is BPsk = 0, and a(k) cor =BPsk·a(k)=0 holds.

[0224] If the k-th (k≠i,j) byte is not incorrect, that byte is not corrected. This can be achieved by XORing the k-th byte with the value 0 for each component so as not to change the value of the k-th byte according to the example shown in FIG. 5. Thereby, the byte error position signal masks the byte error correction value to 0, and thus no correction is performed.

[0225] In the case of a 2-byte error, when the first byte error is at byte position j and the second byte error is at byte position k, the byte error correction value a(j) cor and a(k) cor are non-zero, and the byte error correction values a(i) cor for i ≠ j, k are each 0. At this time, BPsj = BPsk = 1 and BPs i = 0 (for i ≠ j, k) also holds.

[0226] Figure 5 shows one 4·m-bit width (or 4·m dimensions) input for inputting the error syndrome s, and the byte error position signals BPs0, BPs1,..., BPs i ,..., BPs N-1 and one 1-bit width (or 1 dimension) output for outputting the byte error position signals BPs0, BPs1,..., BPs i ,..., BPs N-1 including N byte error position signal generators 10, 11,..., 1i,..., 1N-1 for generating.

[0227] Figure 5 further shows N byte error correction value generators 510, 511,..., 51i,..., 5N-1, which - have a first 1-bit width input for inputting the byte error position signal, - have a second 3·m-bit width input for inputting the components s1, s2, s3 of the error syndrome s, - and have an m-bit width output for outputting the byte error correction values a(0) cor , a(1) cor ,..., a(i) cor ,..., a(N-1) cor corresponding to the respective byte positions. respectively.

[0228] Furthermore, Figure 5 includes N XOR circuits 520, 521,..., 52i,..., 52N-1, each of which - A first input of m-bit width for entering the corresponding byte error correction value, - A second input of m-bit width for entering the corresponding byte to be corrected, - And an output of m-bit width for outputting the corrected byte of m-bit width respectively.

[0229] The actual error syndrome s is input to the 4·m-bit width input of the byte error position signal generator 10. The byte error position signal BPs0 is output by the 1-bit width output of the byte error position signal generator 10 that is connected to the first input of the byte error correction value generator 510.

[0230] The components s1, s2, s3 of the error syndrome s are input to the second 3·m-bit width input of the byte error correction value generator 510. The byte error correction value generator 510 provides the byte error correction value a(0) cor at its output. The output of the byte error correction value generator 510 is connected to the first input of the XOR circuit 520. The byte value of the 0th byte that may be incorrect is input to the second input of the XOR circuit 520.

Number

Number

Number

[0231] The actual error syndrome s is input to the 4·m-bit-width input of the byte error position signal generator 11. The byte error position signal BPs1 is output by the 1-bit-width output of the byte error position signal generator 11 connected to the first input of the byte error correction value generator 511.

[0232] The components s1, s2, s3 of the error syndrome s are input to the second 3·m-bit-width input of the byte error correction value generator 511. The byte error correction value generator 511 provides the byte error correction value a(1) at its output. cor The output of the byte error correction value generator 511 is connected to the first input of the XOR circuit 521. The byte value of the first byte that may be incorrect is input to the second input of the XOR circuit 521.

Number

Number

Number

[0233] The actual error syndrome s is input to the 4·m-bit-width input of the byte error position signal generator 1i. The byte error position signal BPs i is output by the 1-bit-width output of the byte error position signal generator 1i connected to the first input of the byte error correction value generator 51i.

[0234] The second 3·m-bit wide input to the byte error correction value generator 51i receives the components s1, s2, s3 of the error syndrome s. The byte error correction value generator 51i provides, at its output, the byte error correction value a(i). cor The output of the byte error correction value generator 51i is connected to the first input of the XOR circuit 52i. The second input of the XOR circuit 52i receives the byte value [Number] of the i-th byte that may be in error. [Number] The XOR circuit 52i generates a component-by-component XOR operation between the byte value cor that may be in error and the byte error correction value a(i), and provides, at its output, the value [Number] The byte error correction value a(i) cor is - 0 when the i-th byte is correct and BPs i = 0, and - not 0 when the i-th byte is in error and BPs i = 1.

[0235] The actual error syndrome s is input to the 4·m-bit wide input of the byte error position signal generator 1N-1. The byte error position signal BPs N-1 is output at the 1-bit wide output of the byte error position signal generator 1N-1 that is connected to the first input of the byte error correction value generator 51N-1.

[0236] The second 3·m-bit wide input to the byte error correction value generator 51N-1 receives the components s1, s2, s3 of the error syndrome s. The byte error correction value generator 51N-1 provides, at its output, the byte error correction value a(N-1). coris provided. The output of the byte error correction value generator 51N-1 is connected to the first input of the XOR circuit 52N-1. The byte value of the (N-1)-th byte that may be incorrect is input to the second input of the XOR circuit 52N-1. [Number] The XOR circuit 52N-1 generates an XOR operation for each component between the byte value that may be incorrect [Number] and the byte error correction value a(N-1) cor and outputs a value [Number] The byte error correction value a(N-1) cor is - 0 when the (N-1)-th byte is correct and BPs N-1 = 0, and - not 0 when the (N-1)-th byte is incorrect and BPs N-1 = 1.

[0237] Accordingly, the byte corrector 530 includes the byte error position signal generator 10 and the byte error correction value generator 510, the byte corrector 531 includes the byte error position signal generator 11 and the byte error correction value generator 511, the byte corrector 53i includes the byte error position signal generator 1i and the byte error correction value generator 51i, and the byte corrector 53N-1 includes the byte error position signal generator 1N-1 and the byte error correction value generator 51N-1. Correspondingly, the byte correctors 530, 531, …, 53i, …, 53N-1 can be called byte correctors for two-byte errors.

[0238] In this example, the byte corrector for two-byte errors outputs byte error correction values for the two incorrect byte positions. For byte positions without errors, the byte error correction value is 0.

[0239] For the incorrect byte position i, a(i) cor = a(i) holds.

[0240] For the correct byte position j, a(j) cor = 0 holds.

[0241] Here, a(i) is the byte error correction value of the i-th byte.

[0242] To specifically represent that the byte error position signal generator generates corresponding byte error position signals according to the four components s1, s2, s3, s4 of the error syndrome s, and the byte error correction value generator generates corresponding byte error correction values according to the three components s1, s2, s3 of this error syndrome s, FIG. 5 shows, as an example, two input lines, namely, an input line for inputting the components s1, s2, s3, s4 and an additional input line for inputting the components s1, s2, s3. These lines can also be integrated with respect to the components s1, s2, s3.

[0243] For r = 0, …, N - 1, the byte error correction value generator 51r is connected to the m-bit wide output of the XOR circuit 52r that is its m-bit wide input, and in the case of a 2-byte error,

Equation

[0244] In the case of a 2-byte error, when the j-th and k-th bytes are incorrect, the byte error correction value generator 51j outputs the byte error correction value

Equation

Equation

[0245] Byte error correction value generator FIG. 6 shows a possible form of the byte error correction value generator 51r, where r can take values from 0 to N-1.

[0246] The byte error correction value generator 51r includes - two multipliers 61, 66 each having first and second m-bit width inputs and an m-bit width output, - two XOR circuits 63, 64 each having a first m-bit width input, a second m-bit width input, and an m-bit width output, - a constant multiplier 67 having first and second m-bit width inputs and an m-bit width output, the second input of which is input with a constant value α 2r is input to the constant multiplier 67, - a squarer 62 having an m-bit width input and an m-bit width output, - an inverter 65 having an m-bit width input and an m-bit width output, - an AND circuit 68 having a first 1-bit width input, a second m-bit width input, and an m-bit width output and

[0247] The value of component s1 is input to the first input of multiplier 61, and the value of component s3 is input to the second input of multiplier 61. Multiplier 61 generates the value s1·s3 in the Galois field GF(2 m ) and outputs the value s1·s3 at its output. The output of multiplier 61 is connected to the first input of XOR circuit 63.

[0248] The second input of XOR circuit 63 is connected to the output of squarer 62, and the value of component s2 is input to the input of squarer 62. Thus, squarer 62 outputs the value [Number] is output. The XOR circuit 63 generates an XOR operation for each component of the values input to its two inputs, and with its output, the value [Number] is output. The output of the XOR circuit 63 is connected to the first input of the multiplier 66.

[0249] The value of the component s3 is input to the first input of the XOR circuit 64. The value of the component s1 is input to the first input of the constant multiplier 67, and the constant α 2r is input to the second input of the constant multiplier 67. The constant multiplier 67 realizes the operation α m ·s1 in the Galois field GF(2 2r ). The constant multiplier can be implemented, for example, using XOR gates.

[0250] With the output of the XOR circuit 64, the value s3 + α 2r s1 is provided and sent to the input of the inverter 65. The inverter 65, with its output, provides the value [Number] .

[0251] The output of the inverter 65 is connected to the first input of the multiplier 66. Thus, the multiplier 66, with its output, provides the value [Number] . Here, a(r) is the byte error correction value for the r-th byte. The value of the byte error position signal BPsr is input to the first input of the AND circuit 68. The second input of the AND circuit 68 is connected to the output of the multiplier 66.

[0252] The AND circuit realizes a bitwise AND operation between the m bits input to its second input and the byte error position signal BPsr, and thereby, with its output, provides the value

Number

[0253] Byte error correction value generator, alternative embodiment FIG. 7 shows a further possible form of the byte error correction value generator 51r, which is described with respect to the r-th byte as in FIG. 6. Here, r can take values from 0 to (N - 1).

[0254] The byte error correction value generator 51r shown in FIG. 7 includes - Three multipliers 71, 75, 76 each having a first m-bit width input, a second m-bit width input, and an m-bit width output, - Two XOR circuits 72, 77 each having a first m-bit width input, a second m-bit width input, and an m-bit width output, - A constant multiplier 78 having a first m-bit width input, a second m-bit width input, and an m-bit width output, where a constant value α 2r is input to the second input of the constant multiplier 78, - A squarer 73 having an m-bit width input and an m-bit width output, - Two inverters 74, 79 having an m-bit width input and an m-bit width output, - An AND circuit 710 having a first 1-bit width input, a second m-bit width input, and an m-bit width output and includes.

[0255] The value of component s1 is input to the first input of multiplier 71, and the value of component s3 is input to the second input of multiplier 71. Multiplier 71 generates the value s1·s3 in the Galois field GF(2 m ) and provides the value s1·s3 at its output. The output of multiplier 71 is connected to the first input of XOR circuit 72.

[0256] The second input of XOR circuit 72 is connected to the output of squarer 73, and the value of component s2 is input to the input of squarer 73. Thus, squarer 73 provides the value at its output

Number

Number

Number

[0257] The output of the inverter 74 is connected to the first input of the multiplier 75, and the value of the component s3 is input to the second input of the multiplier 75. Further, the output of the inverter 74 is connected to the first input of the multiplier 76, and the value of the component s1 is input to the second input of the multiplier 76.

[0258] The multiplier 76, with its output, the value

Number

Number

[0259] The multiplier 75, with its output, the value

Number

[0260] The output of constant multiplier 78 is connected to the second input of XOR circuit 77. XOR circuit 77 outputs, at its output, the value [Number] is provided. The output of XOR circuit 77 is connected to the input of inverter 79.

[0261] Inverter 79 outputs, at its output, the value [Number] is provided. The output of inverter 79 is connected to the second input of AND circuit 710.

[0262] The value of byte error position signal BPsr is input to the first input of AND circuit 710. AND circuit 710 realizes a bitwise AND operation between the m bits input to its second input and the byte error position signal BPsr. Thereby, AND circuit 710 outputs, at its output, the value [Number] is provided.

[0263] The portion shown in FIG. 7 including multipliers 71, 75, 76, XOR circuit 72, and squarer 73 outputs, at the outputs of multipliers 75 and 76, the values [Number] and [Number] Output these, which are determined only by the values of components s1, s2, and s3 and have no relation to the byte position r. This part of the circuit is the same for all byte error correction value generators 510, 511, …, 51N-1 shown in FIG. 5. Therefore, it is possible to provide only one such circuit part and use the output signals of multipliers 71, 75, and 76 for all byte error correction value generators 510 to 51N-1. In that case, for various byte positions 0 to N-1, only the remaining part 711 of the circuit shown in FIG. 7 can be realized respectively, and part 711 includes an XOR circuit 77, a constant multiplier 78, an inverter 79, and an AND circuit 710.

[0264] Regarding correctable byte positions, for example, for all correctable byte positions, or for a part of the correctable byte positions, one option is to realize the byte error correction value generator using at most three multiplications. In that case, the three multiplications can be implemented using three multipliers. Also, in particular, it is also an option to perform further multiplication of a constant by a constant multiplier.

[0265] Correction of 1-byte and 2-byte errors, FIG. 8 FIG. 8 shows an exemplary circuit for correcting 1-byte errors and 2-byte errors, where these circuits can be used to determine the byte error position signal for 2-byte errors and to correct 2-byte errors.

[0266] The circuit shown in FIG. 8 is, for example, - When there are 2-byte errors, the 2-byte errors are corrected, - When there is 1-byte error, the 1-byte error is corrected, - When there is no error, no correction is performed configured as such.

[0267] For this purpose, FIG. 8 - N byte error correction value generators 810, …, 81i, …, 81N-1 for correcting 1 byte error, each having an input of 2·m bit width for inputting components s1, s2, and an output of m bit width for outputting an m bit width byte error correction value, - N byte correctors 530, …, 53i, …, 53N-1 for correcting 2 byte errors (the same as described in FIG. 5), each having an input of 4·m bit width for inputting components s1, s2, s3, s4, and an output of m bit width for outputting an m bit width byte error correction value, - N multiplexers 820, …, 82i, … 82N-1, - A first input of m bit width (0 input), - A second input of m bit width (1 input), - A control input of 1 bit width capable of inputting a binary control signal st, and - An output of m bit width N multiplexers 820, …, 82i, … 82N-1 each having the above, - N AND circuits 830, …, 83i, …, 83N-1 each having a first input of 1 bit width for inputting a binary error signal E, a second input of m bit width, and an output of m bit width, - N XOR circuits 840, …, 84i, …, 84N-1 each having a first input of m bit width, a second input of m bit width, and an output of m bit width including.

[0268] Line 85 transmits components s1, s2 and is connected to each input of byte error correction value generators 810, …, 81i, …, 81N-1.

[0269] Line 86 transmits components s1, s2, s3, s4 and is connected to each input of byte correctors 530, …, 53i, …, 53N-1.

[0270] When there is a 1 byte error at byte position 0, byte error correction value generator 810 outputs the incorrect 0th byte at its output [Number] Provide the correct byte error correction value for. This also applies to further byte error correction value generators. Therefore, the byte error correction value generator 81i outputs the incorrect i-th byte in the case of a one-byte error at byte position i [Number] Provide the correct byte error correction value for. The byte error correction value generator 81N-1 outputs the incorrect (N-1)-th byte in the case of a one-byte error at byte position (N-1) [Number] Provide the correct byte error correction value for.

[0271] Possible implementations of the byte error correction value generator for correcting one-byte errors will be described in connection with FIG. 10.

[0272] Regarding possible implementations of the byte correctors 530 to 53N-1, for example, the position signal generator described in connection with FIG. 2 and the byte error correction value generator described in connection with FIGS. 6 and 7 can be mentioned.

[0273] The output of the byte error correction value generator 810 is connected to the first input of the multiplexer 820. The output of the byte corrector 530 is connected to the second input of the multiplexer 820. When the value of the control signal st is 0, the multiplexer 820 connects its 0 input (the first input) to its output. When the value of the control signal st is 1, the multiplexer 820 connects its 1 input (the second input) to its output.

[0274] The binary error signal E is input to the first input of the AND circuit 830. The output of the multiplexer 820 is connected to the second input of the AND circuit 830. The output of the AND circuit 830 is connected to the first input of the XOR circuit 840. A byte that may be incorrect is input to the second input of the XOR circuit 840

Number

Number

[0275] The AND circuit 830 enables a component - by - component AND operation between the m - digit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 830 outputs an m - component value of 0. When the error signal E = 1, the AND circuit 830 outputs the value input to its second input.

[0276] These embodiments similarly apply to the remaining byte positions.

[0277] The output of the byte error correction value generator 81i is connected to the first input of the multiplexer 82i. The output of the byte error correction value generator 53i is connected to the second input of the multiplexer 82i. When the value of the control signal st is 0, the multiplexer 82i connects its 0 - input (first input) to its output. When the value of the control signal st is 1, the multiplexer 82i connects its 1 - input (second input) to its output.

[0278] The binary error signal E is input to the first input of the AND circuit 83i. The output of the multiplexer 82i is connected to the second input of the AND circuit 83i. The output of the AND circuit 83i is connected to the first input of the XOR circuit 84i. A byte that may be incorrect is input to the second input of the XOR circuit 84i

Number

Number

[0279]

[0280] The AND circuit 83i enables an AND operation for each component between the m - digit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 83i outputs m component values of 0. When the error signal E = 1, the AND circuit 83i outputs the value input to its second input.

[0281] The output of the byte error correction value generator 81N - 1 is connected to the first input of the multiplexer 82N - 1. The output of the byte error correction value generator 53N - 1 is connected to the second input of the multiplexer 82N - 1. When the value of the control signal st is 0, the multiplexer 82N - 1 connects its 0 input (the first input) to its output. When the value of the control signal st is 1, the multiplexer 82N - 1 connects its 1 input (the second input) to its output.

[0281]

Number

[0282] The AND circuit 83N-1 enables bit-by-bit AND operations between the m-bit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 83N-1 outputs an m-component value of 0. When the error signal E = 1, the AND circuit 83N-1 outputs the value input to its second input.

[0283] The error signal E - takes the value 1 if a 1-byte error or 2-byte error has occurred, - takes the value 0 if no error has occurred.

[0284] The control signal st - takes the value 0 if a 1-byte error has occurred, - takes the value 1 if a 2-byte error has occurred.

[0285] Circuit for correcting errors of three or more bytes Figure 9 shows a circuit for correcting 1-byte errors, 2-byte errors, …, t-byte errors. In this circuit, the elements described in Figure 8 can be used in the same way.

[0286] The circuit shown in Figure 9 - corrects a 1-byte error if there is a 1-byte error, - corrects a 2-byte error if there is a 2-byte error, - and similarly for - corrects a t-byte error if there is a t-byte error, - and does not perform correction if there is no error making this possible.

[0287] As an example, the case where a t-byte error correction and (t + 1)-byte error detection code are used is described. Here, in particular, t > 2 holds.

[0288] The circuit according to Figure 9 - the N byte error correction value generators 810 to 81N-1 according to Figure 8, -N byte correctors 530 to 53N - 1 according to FIG. 8 (as also described in FIG. 5), and similarly hereinafter, -components s1, s2, …, s 2t N byte error correction value generators 910, …, 91i, …, 91N - 1 for correcting t byte errors, each having an input with a 2·t·m bit width for inputting and an output with an m bit width for outputting an m bit width byte error correction value, -N multiplexers 920, …, 92i, …, 92N - 1, -a first input with an m bit width (0 input), -a second input with an m bit width (1 input), -similarly hereinafter, a t-th input with an m bit width ((t - 1) input), -a control input to which a control signal st that can take t different values is input, and -an output with an m bit width N multiplexers 920, …, 92i, …, 92N - 1 each having, -a first input with a 1 bit width for inputting a binary error signal E, a second input with an m bit width, and N AND circuits 930, …, 93i, …, 93N - 1 each having an output with an m bit width, and -N XOR circuits 940, …, 94i, …, 94N - 1 each having a first input with an m bit width, a second input with an m bit width, and an output with an m bit width are included.

[0289] When the control signal st has a value of 0, one 0 input of the multiplexers 920 to 92N - 1 is connected to its output. Correspondingly, by the corresponding control signal st taking values of 0 to (t - 1), a connection between one of the inputs 0 to (t - 1) and the output can be established. For example, when st = (t - 1) = 3 holds, the third input (2 input) of the multiplexer is connected to its output.

[0290] Line 95 transmits components s1, s2 and is connected to each input of byte error correction value generators 810, …, 81i, …, 81N - 1.

[0291] Line 96 transmits components s1, s2, s3, s4 and is connected to each input of byte correctors 530, …, 53i, …, 53N-1.

[0292] Finally, line 97 is shown, and based on line 97, components s1, s2, …, s 2t are connected to each input of byte error correction value generators 910, …, 91i, …, 91N-1.

[0293] Byte error correction value generator 810 provides, at its output, the correct byte error correction value for a one-byte error at byte position 0 for the incorrect 0th byte

Number

Number

Number

[0294] Byte corrector 530 provides, at its output, the correct byte error correction value for a two-byte error for the incorrect 0th byte

Number

Number

Number

[0295] The output of the byte error correction value generator 910 is connected to the first input (input 0) of the multiplexer 920. The output of the byte corrector 530 is connected to the second input (input 1) of the multiplexer 920. Correspondingly, the output of the byte error correction value generator 910 is connected to the t-th input ((t-1) input) of the multiplexer 920.

Number

Number

Number

[0296] For bytes that are not incorrect, the byte error correction values assigned to their byte positions are masked with the value 0 respectively.

[0297] The output of the byte error correction value generator 810 is connected to the first input (input 0) of the multiplexer 920. The output of the byte corrector 530 is connected to the second input (input 1) of the multiplexer 920. Correspondingly, the output of the byte error correction value generator 910 is connected to the t-th input ((t-1) input) of the multiplexer 920.

[0298] A binary error signal E is input to the first input of the AND circuit 930. The output of the multiplexer 920 is connected to the second input of the AND circuit 930. The output of the AND circuit 930 is connected to the first input of the XOR circuit 940. A byte value

Number

Number

[0299] The AND circuit 930 enables a component - by - component AND operation between the m - digit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 930 outputs an m - component value of 0. When the error signal E = 1, the AND circuit 930 outputs the value input to its second input.

[0300] These embodiments similarly apply to the remaining byte positions.

[0301] The output of the byte error correction value generator 81i is connected to the first input (0 - input) of the multiplexer 92i. The output of the byte error correction value generator 53i is connected to the second input (1 - input) of the multiplexer 92i. Correspondingly, the output of the byte error correction value generator 91i is connected to the t - th input ((t - 1)-input) of the multiplexer 92i.

[0302] A binary error signal E is input to the first input of the AND circuit 93i. The output of the multiplexer 92i is connected to the second input of the AND circuit 93i. The output of the AND circuit 93i is connected to the first input of the XOR circuit 94i. A byte

Number

Number

[0303] The AND circuit 93i enables an AND operation for each component of the m-digit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 93i outputs m component values of 0. When the error signal E = 1, the AND circuit 93i outputs the value input to its second input.

[0304] The output of the byte error correction value generator 81N-1 is connected to the first input (0 input) of the multiplexer 92N-1. The output of the byte error correction value generator 53N-1 is connected to the second input (1 input) of the multiplexer 92N-1. Correspondingly, the output of the byte error correction value generator 91N-1 is connected to the t-th input ((t-1) input) of the multiplexer 92N-1.

[0305] The binary error signal E is input to the first input of the AND circuit 93N-1. The output of the multiplexer 92N-1 is connected to the second input of the circuit 93N-1. The output of the AND circuit 93N-1 is connected to the first input of the XOR circuit 94N-1. The byte value

Number

Number

[0306] The AND circuit 93N-1 enables a component-by-component AND operation between the m-bit value input to its second input and the error signal E. When the error signal E = 0, the AND circuit 93N-1 outputs m component values of 0. When the error signal E = 1, the AND circuit 93N-1 outputs the value input to its second input.

[0307] The error signal E - takes the value 1 when a 1-byte error, 2-byte error, …, or t-byte error has occurred, - takes the value 0 when no error has occurred.

[0308] The control signal st - takes the value 0 when a 1-byte error has occurred, - takes the value 1 when a 2-byte error has occurred, - and similarly hereinafter, - takes the value (t - 1) when a t-byte error has occurred and.

[0309] Byte error corrector for 1-byte error FIG. 10 shows an exemplary circuit related to the byte error correction value generator 81i for the i-th byte as described in relation to FIG. 8.

[0310] The byte error correction value generator 81i - includes a constant multiplier 101 having - a first input with a width of m bits, - a constant value α i as a second input with a width of m bits to be input, and - an output with a width of m bits the constant multiplier 101, - an XOR circuit 102 having a first input with a width of m bits, a second input with a width of m bits, and an output with a width of m bits, - a NOR circuit 103 having an input with a width of m bits and an output with a width of 1 bit, - and an AND circuit 104 having a first input with a width of 1 bit, a second input with a width of m bits, and an output with a width of m bits and.

[0311] Furthermore, FIG. 10 shows the multiplexer 82i and the byte error correction value generator 53i from FIG. 8 (and FIG. 5).

[0312] The constant multiplier 101, the XOR circuit 102, and the NOR circuit 103 form the byte error position signal generator 105, and for example, generate a byte error position signal indicating whether there is a 1-byte error at the i-th byte position.

Number

[0313] When a 1-byte error occurs at byte position i, the output of the AND circuit 104 provides the m-dimensional byte error correction value a(i). cor If a 1-byte error occurs at a different byte position j from i, the byte error position signal BPs i = 0, and thus the output of the AND circuit 104 also becomes 0.

[0314] Component s1 is input to the first input of the constant multiplier 101, and the constant α i is input. The output of the constant multiplier 101 is connected to the first input of the XOR circuit 102. Component s2 is input to the second input of the XOR circuit 102. The output of the XOR circuit 102 is connected to the input of the NOR circuit 103. The output of the NOR circuit 103 is connected to the first input of the AND circuit 104. Component s1 is input to the second input of the AND circuit 104. The output of the AND circuit 104 is connected to the first input of the multiplexer 82i.

[0315] The second input of the multiplexer 82i is connected to the output of the byte error correction value generator 53i.

[0316] Therefore, the byte error correction value for a 1-byte error is provided to the first input of the multiplexer 82i, and the byte error correction value for a 2-byte error is provided to the second input of the multiplexer 82i.

[0317] Correspondingly, the control signal st for the multiplexer 82i is - 0 when there is a 1-byte error, connecting the first input (0 input) of the multiplexer 82i to its output, or - 1 when there is a 2-byte error, connecting the second input (1 input) of the multiplexer 82i to its output.

[0318] When there is no error, the value of the control signal st is arbitrary. For example, it can be set to 0 as described below by way of example.

[0319] When there is no error, the value of the error signal E is 0. This was previously explained in connection with FIG. 8. Based on the AND circuit 83i connected downstream that logically ANDs the signal at the output of the multiplexer 82i with the error signal E for each component, when the error signal E = 0 (i.e., when there is no error), it is guaranteed that a value of 0 is provided at the output of the AND circuit 83i regardless of the signal at the output of the multiplexer 82i. Therefore, the correction of the i-th byte is not performed.

[0320] Circuit for determining the error signal FIG. 11 shows an exemplary circuit for determining the error signal E, such as the one used in the circuit shown in FIG. 8 for example.

[0321] The configuration shown in FIG. 11 is - a multiplier 111 having a first m-bit width input, a second m-bit width input, and an m-bit width output, - an XOR circuit 113 having a first m-bit width input, a second m-bit width input, and an m-bit width output, - a squarer 112 having an m-bit width input and an m-bit width output, -an OR circuit 114 having an input with an -m-bit width and an output with a 1-bit width, -an OR circuit 116 having an input with an -m-bit width and an output with a 1-bit width, -an OR circuit 115 having a first binary input, a second binary input, and a binary output and.

[0322] The value of component s1 is input to the first input of multiplier 111. The value of component s3 is input to the second input of multiplier 111. The output of multiplier 111 is connected to the first input of XOR circuit 113.

[0323] Component s1 is also input to the input of OR circuit 116. The output of OR circuit 116 is connected to the second input of OR circuit 115.

[0324] Component s2 is input to the input of squarer 112. The output of squarer 112 is connected to the second input of XOR circuit 113.

[0325] The output of XOR circuit 113 is connected to the input of OR circuit 114, and the output of OR circuit 114 is connected to the first input of OR circuit 115.

[0326] The control signal st is provided by the output of OR circuit 114, and the error signal E is provided by the output of OR circuit 115.

[0327] The control signal st

Number

[0328] holds.

Number

[0329] The error signal E takes the value 0 when the control signal st is 0 and when the value of component s1 is 0. In this case, there is neither a 1-byte error nor a 2-byte error.

[0330] When the value of the control signal st is 1, in the circuit according to FIG. 8, 2-byte correction is performed using byte correctors 530 to 53N-1.

[0331] When the value of the control signal st is 0, in the circuit according to FIG. 8, first, 1-byte correction is performed using byte error correction value generators 810 to 81N-1. When the error signal E is 0 and thus there is neither a 1-byte error nor a 2-byte error, all AND circuits 830 to 83N-1 output the value 0, and thus, the

Number

[0332] When a 3-byte error is recognized, for example, error correction can be interrupted. Such interruption of error correction can be performed at the system level.

[0333] Circuit for recognizing a 3-byte error FIG. 12 shows an exemplary circuit for recognizing a 3-byte error. For this purpose, the circuit includes - four multipliers 121, 122, 123, 124 each having a first m-bit width input and a second m-bit width and a third m-bit width output, respectively, - three squarers 125, 126, 127 each having an m-bit width input and an m-bit width output, respectively, - three XOR circuits 128, 129, 1210 each having a first m-bit width input, a second m-bit width input, and an m-bit width output, respectively, - an OR circuit 1211 having an m-bit width input and a binary output, and the OR circuit 1211 performs an OR operation for each m-bit component input to its input.

[0334] The value of component s1 is input to the first input of multiplier 121 and the second input of multiplier 123.

[0335] The value of component s2 is input to the input of squarer 126.

[0336] The value of component s3 is input to the input of squarer 125 and the second input of multiplier 122.

[0337] The value of component s4 is input to the input of squarer 127.

[0338] The value of component s5 is input to the second input of multiplier 121 and the first input of multiplier 124.

[0339] The output of multiplier 121 is connected to the first input of XOR circuit 128. The output of squarer 125 is connected to the second input of XOR circuit 128. The output of XOR circuit 128 is connected to the first input of multiplier 122. The output of multiplier 122 is connected to the first input of XOR circuit 129.

[0340] The output of squarer 127 is connected to the first input of multiplier 123. The output of multiplier 123 is connected to the first input of XOR circuit 1210.

[0341] The output of squarer 126 is connected to the second input of multiplier 124, and the output of multiplier 124 is connected to the second input of XOR circuit 1210. The output of XOR circuit 1210 is connected to the second input of XOR circuit 129. The output of XOR circuit 129 is connected to the input of OR circuit 1211, and signal Err3 is provided at the output of OR circuit 1211. Based on signal Err3, a 3-byte error can be determined.

[0342] Signal Err3

Number

[0343] Correspondingly, the signal Err3 [Number] takes the value 0 when the following holds. [Explanation of Signs]

[0344] 10, 11, …, 1i, …, 1N-1 Byte Error Position Signal Generator s1, s2, s3, s4 Syndrome Components BPs0 Byte Error Position Signal 210 Subcircuit 220 Constant Multiplier 230 Constant Multiplier 240 XOR Circuit 250 NOR Circuit

Claims

1. A circuit configuration for determining at least two byte error position signals in parallel to identify at least one byte error in a binary sequence containing a plurality of bytes, wherein the binary sequence in the case of no error is a codeword of an error code, wherein each of the at least two byte error position signals can be determined using components of the error syndrome of the error code to indicate whether the byte of the binary sequence associated with the byte error position signal is incorrect, the circuit configuration is configured to determine at least one byte error correction value, and based on the byte error correction value, the incorrect byte position identified by the byte error position signal can be corrected, the circuit configuration is configured to correct one of the byte errors by calculating the byte error position signal with the byte error correction value for the incorrect byte, the circuit configuration includes a plurality of byte error position signal generators corresponding to each byte position, each byte error position signal generator is coupled to components of the error syndrome of the error code, and each byte error position signal generator outputs the byte error correction value for each respective byte position, the at least one byte error position signal and / or at least one byte error correction value are determined in parallel, the error code is a t-byte error correction code, and at least (t + 1) byte error correction values are determined in parallel, where t is a natural number, the circuit configuration in which the at least (t + 1) byte error correction values are determined using at most three Galois field multipliers, where t ≧ 2.

2. The circuit configuration according to claim 1, wherein the byte error position signal can be determined using components of the error syndrome of the error code, and the byte error position signal is configured to indicate that there are correctable errors for at least two bytes among the bytes of the binary sequence.

3. The circuit configuration according to claim 1 or 2, wherein at least (t + 1) byte error position signals are determined in parallel.

4. The circuit configuration according to any one of claims 1 to 3, wherein the binary sequence has two byte errors.

5. The circuit configuration according to any one of claims 1 to 4, wherein each byte of the binary sequence has m bits, where m ≧ 2 holds.

6. The circuit configuration according to any one of claims 1 to 5, wherein the binary sequence has at least t correctable bytes.

7. wherein the error syndrome has at least 2·t components s １ , s ２ , …, s ２ｔ , each component including m bits respectively, and m ≥ 2, the circuit configuration according to any one of claims 1 to 6.

8. A circuit configuration for determining at least two byte error position signals in parallel to identify at least one byte error in a binary sequence containing a plurality of bytes, The binary sequence in the case of no error is the codeword of the error code, In order to indicate whether the byte of the binary sequence associated with the byte error position signal is incorrect, each of the at least two byte error position signals can be determined using components of the error syndrome of the error code, The circuit configuration determines at least one byte error correction value and is configured such that the incorrect byte position identified by the byte error position signal can be corrected based on the byte error correction value, The circuit configuration is configured to correct one of the byte errors by calculating the byte error position signal with the byte error correction value for the incorrect byte, The circuit configuration includes a plurality of byte error position signal generators corresponding to each byte position, each byte error position signal generator is coupled to the components of the error syndrome of the error code, and each byte error position signal generator outputs the byte error correction value for each respective byte position, α is a primitive element of the Galois field GF(2^m), and s1, s2, s3 are components of the error syndrome, In the case of a 2-byte error, the byte error correction value of the i-th byte is 【Mathematics 3】 Determined according to, the circuit configuration.

9. A circuit configuration for determining at least two byte error position signals in parallel to identify at least one byte error in a binary sequence containing a plurality of bytes, The binary sequence in the case of no error is the codeword of the error code, In order to indicate whether the byte of the binary sequence associated with the byte error position signal is incorrect, each of the at least two byte error position signals can be determined using components of the error syndrome of the error code, The circuit configuration determines at least one byte error correction value and is configured such that the incorrect byte position identified by the byte error position signal can be corrected based on the byte error correction value, The circuit configuration is configured to correct one of the byte errors by calculating the byte error position signal with respect to the incorrect byte and the byte error correction value. The circuit configuration includes a plurality of byte error position signal generators corresponding to respective byte positions, each byte error position signal generator being coupled to a component of the error syndrome of the error code, and each byte error position signal generator outputting the byte error correction value for the respective byte position. A circuit configuration in which, in the case of a two-byte error, the correction of the correctable byte is determined according to three components of the error syndrome and the byte error position signal.

10. The circuit configuration according to any one of claims 1 to 9, wherein the byte error position signal has a first value when a byte related to the byte error position signal is incorrect, and has a second value when a byte related to the byte error position signal is not incorrect.

11. The circuit configuration according to any one of claims 1 to 10, wherein at least one of the byte error position signals is determined with respect to at least one correct byte.

12. The circuit configuration according to any one of claims 1 to 11, wherein the binary sequence includes data bytes and check bytes, and the data bytes and / or the check bytes constitute correctable bytes.

13. A circuit configuration for correcting at least one byte error in a binary sequence including a plurality of bytes, wherein the binary sequence in the case of no error is a codeword of an error code. The circuit configuration is configured to determine at least one byte error position signal using components of the error syndrome of the error code, so that it is possible to determine whether a byte of the binary sequence is incorrect by the byte error position signal. The circuit configuration determines at least one byte error correction value, and based on the byte error correction value, the incorrect byte position identified by the byte error position signal is correctable, and at least one of the byte error correction values is determined with respect to at least one correct byte. The circuit configuration is configured to correct one of the byte errors by calculating the byte error position signal with respect to the incorrect byte and the byte error correction value. The circuit configuration includes a plurality of byte error position signal generators corresponding to respective byte positions, each byte error position signal generator being coupled to a component of the error syndrome of the error code, each byte error position signal generator outputting the byte error correction value for the respective byte position, wherein at least one byte error position signal and / or at least one byte error correction value are determined in parallel, wherein the error code is a t-byte error correction code, and at least (t + 1) byte error correction values are determined in parallel, where t is a natural number, wherein the at least (t + 1) byte error correction values are determined using at most three Galois field multipliers, where t ≧ 2, circuit configuration. **Claim 14** The circuit configuration according to claim 13, wherein at least (t + 1) byte error position signals are determined in parallel. **Claim 15** The circuit configuration according to claim 13 or 14, configured to correct t-byte errors. **Claim 16** The circuit configuration according to claim 15, further configured to correct one-byte errors. **Claim 17** The circuit configuration according to claim 15 or 16, further configured to correct τ-byte errors, where t ≧ τ > 2 holds. **Claim 18** A circuit configuration for correcting at least one byte error in a binary sequence including a plurality of bytes, wherein the binary sequence in the absence of errors is a codeword of an error code, wherein the circuit configuration is configured to determine at least one byte error position signal using a component of the error syndrome of the error code, whereby it is possible to determine whether a byte of the binary sequence is in error by the byte error position signal, wherein the circuit configuration determines at least one byte error correction value, and based on the byte error correction value, the incorrect byte position identified by the byte error position signal can be corrected, and at least one of the byte error correction values is determined for at least one correct byte, wherein the circuit configuration is configured to correct one of the byte errors by operating the byte error position signal with the byte error correction value for the incorrect byte, The circuit configuration includes a plurality of byte error position signal generators corresponding to respective byte positions, each byte error position signal generator being coupled to components of the error syndrome of the error code, each byte error position signal generator outputting the byte error correction value for the respective byte position, α is a primitive element of the Galois field GF(2^m), and s1, s2, s3 are components of the error syndrome, In the case of a 2-byte error, the byte error correction value of the i-th byte is, [Number 3] A circuit configuration determined according to. **Claim 19**: A circuit configuration for correcting at least one byte error in a binary sequence including a plurality of bytes, wherein the binary sequence in the error-free case is a codeword of an error code, The circuit configuration is configured to determine at least one byte error position signal using components of the error syndrome of the error code, so that it is possible to determine whether a byte of the binary sequence is in error by the byte error position signal, The circuit configuration determines at least one byte error correction value, and based on the byte error correction value, the incorrect byte position identified by the byte error position signal can be corrected, and at least one of the byte error correction values is determined for at least one correct byte, The circuit configuration is configured to correct one of the byte errors by calculating the byte error position signal with the byte error correction value for the incorrect byte, The circuit configuration includes a plurality of byte error position signal generators corresponding to respective byte positions, each byte error position signal generator being coupled to components of the error syndrome of the error code, each byte error position signal generator outputting the byte error correction value for the respective byte position, In the case of a 2-byte error, the correction of the correctable byte is determined according to three components of the error syndrome and the byte error position signal. A circuit configuration. **Claim 20** α is a primitive element of the Galois field GF(2 ｍ ), and s １ , s ２ , s ３ , s ４ are components of the error syndrome, In the case of a 2-byte error, the i-th byte is a correctable byte, The byte error position signal for the i-th byte is, 【Number 1】 takes a first value when holds, The byte error position signal for the i-th byte is, 【Number 2】 takes a second value when holds, If the byte error position signal associated with the i-th byte takes the first value, then the i-th byte is incorrect. The circuit configuration according to any one of claims 13 to 19.

21. A method of a circuit configuration for determining at least two byte error position signals in parallel by the circuit configuration according to any one of claims 1 to 12 in order to identify at least one byte error in a binary sequence including a plurality of bytes, The binary sequence in the case of no error is a codeword of an error code. In order to indicate whether the byte of the binary sequence associated with the byte error position signal is incorrect, each of the at least two byte error position signals is determined using a component of the error syndrome of the error code. The method can determine at least one byte error correction value, and based on the byte error correction value, correct the incorrect byte position identified by the byte error position signal. The method corrects one of the byte errors by calculating the byte error position signal with respect to the incorrect byte and the byte error correction value.

22. A method of a circuit configuration for correcting at least one byte error in a binary sequence including a plurality of bytes by the circuit configuration according to any one of claims 13 to 20, wherein the binary sequence in the case of no error is a codeword of an error code, and the method includes: Determining at least one byte error position signal using a component of the error syndrome of the error code, and determining whether the byte of the binary sequence is incorrect by the byte error position signal; Determining at least one byte error correction value, based on the byte error correction value, correcting the incorrect byte position identified by the byte error position signal, and determining at least one of the byte error correction values for at least one correct byte; Correcting one of the byte errors by calculating the byte error position signal with respect to the incorrect byte and the byte error correction value.

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