Data interleaving method and data interleaving apparatus

Abstract

The embodiment of this application discloses a data interleaving method and a data interleaving device. The method in the embodiment of this application includes the following steps: delaying n data streams separately based on n delay lines, where n is a positive integer divisible by p, where p is an integer greater than 1, the delay value of each delay line is any delay value in a delay value set, the delay value set includes p delay values, the minimum delay value in the delay value set is 0, the difference between every two adjacent delay values ​​in the delay value set arranged in ascending order is V symbols, the number of delay lines corresponding to each delay value in the delay value set is n / p, where V is an integer greater than or equal to 34; obtaining L*m symbols from each of the n delayed data streams to obtain L first symbol sets; and interleaving the L first symbol sets separately to obtain L second symbol sets, where the number of symbols in the second symbol set is the same as the number of symbols in the first symbol set.

Description

Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202111034610.X, titled "Data Interleaving Method and Data Interleaving Apparatus", filed with the China National Intellectual Property Administration on September 3, 2021, and Chinese Patent Application No. 202210290884.3, titled "Data Interleaving Method and Data Interleaving Apparatus", filed with the China National Intellectual Property Administration on March 23, 2022. All of these Chinese patent applications are hereby incorporated by reference in their entirety.

[0002] This application relates to the field of communications, and in particular, to a data interleaving method and a data interleaving apparatus.

Background Art

[0003] Optical communication systems and optical transport networks (OTNs), which are continuously promoted by 5G, cloud computing, big data, artificial intelligence, etc., are developing towards larger capacity and ultra-high speed. The transmitted data is corrected by forward error correction (FEC) encoding. This can solve the transmitted bit errors and restore the original data transmitted on the transmitting side from the received data.

[0004] Currently, a cascade FEC transmission solution is provided. The transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and transmits the data obtained by the first FEC encoding to the transmitting processing module. The transmitting processing module performs a second FEC encoding on the data obtained by the first FEC encoding and transmits the data obtained by the second FEC encoding to the data receiving side via a channel. Specifically, the transmitting processing module receives a plurality of data streams. First, it separately performs convolutional interleaving on the plurality of data streams. Then, it performs a second FEC encoding on each data stream obtained by the convolutional interleaving. It should be understood that in order to improve performance, one data stream on which the second FEC encoding is performed needs to be from a plurality of codewords obtained by the first FEC encoding. However, this needs to be implemented by convolutional interleaving with high latency, and the application effect is not ideal in scenarios that require low latency. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0005] Embodiments of this application provide a data interleaving method and a data interleaving device, so that as a result, good performance of the cascade FEC solution can be implemented in scenarios where low latency is used.

[0006] According to a first aspect, this application provides a data interleaving method. The method includes the following steps: delaying n data streams separately based on n delay lines, where n is a positive integer divisible by p, p is an integer greater than 1, the delay value of each delay line is any delay value within a set of delay values, the set of delay values contains p delay values, the minimum delay value within the set of delay values is 0, the difference between every other adjacent delay value among the p delay values in the set of delay values set in ascending order is V symbols, V is an integer of 34 or more, and the number of delay lines corresponding to each delay value within the set of delay values is n / p; obtaining L*m symbols from each of the n delayed data streams to obtain L first symbol sets, where each first symbol set contains n*m symbols, L is an integer of 1 or more, and m is an integer of 1 or more; and separately interleaving the L first symbol sets to obtain L second symbol sets, where the number of symbols in each second symbol set is the same as the number of symbols in each first symbol set.

[0007] In this implementation, all of the n data streams are codewords obtained by outer code encoding. After the n data streams are separately delayed, data interleaving is further performed on the n delayed data streams. According to the delay processing solution provided in this application, the n symbols output from the n delayed data streams at the same moment can be from a plurality of different outer codewords by using low latency. This helps to reduce the data interleaving latency while ensuring good performance. In other words, the solution combining the delay processing and data interleaving in this application uses low overall latency and is applicable to application scenarios that require low latency.

[0008] In some possible implementations, p = 4, n is divisible by 16, the n delay lines include at least one group of delay lines, each group of delay lines includes 16 adjacent delay lines, and among the n delay lines, the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15 in group k of the delay lines satisfy the first condition, 0 ≤ k < n / 16, and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15 are non - negative integers less than 16, not equal to each other, and the first condition is that the difference between the delay value of delay line a0 and the delay value of delay line a1 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a3 is 2V symbols, the difference between the delay value of delay line a4 and the delay value of delay line a5 is 2V symbols the difference between the delay value of delay line a6 and the delay value of delay line a7 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a9 is 2V symbols, the difference between the delay value of delay line a 10 and the delay value of delay line a 11 is 2V symbols, the difference between the delay value of delay line a 12 and the delay value of delay line a 13 is 2V symbols, the difference between the delay value of delay line a 14 and the delay value of delay line a 15 is 2V symbols, that is.

[0009] In this implementation form, the client side has an 8*100G interface with each lane of 100 Gb / s and uses the "100G RS-FEC" mode. When the above-mentioned first condition is satisfied and V≥68, among the 16 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 32 data streams are delayed, symbol a0 and symbol a1 are from two different RS codeword symbols, symbol a2 and symbol a3 are from two different RS codeword symbols,..., symbol a 14 and symbol a 15 are from two different RS codeword symbols. This delay design pattern realizes the good performance of the cascade FEC solution, shortens the overall latency of the transmission solution, is easy to implement, and facilitates the subsequent use of the interleaving solution with short latency.

[0010] In some possible implementation forms, in each group of 16 delay lines among the n delay lines, the number of delay lines with delay values of 0 symbol, V symbols, 2V symbols, and 3V symbols is all 4.

[0011] In some possible implementation forms, the delay values of delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 and delay line a 15 in group k of the delay lines among the n delay lines satisfy the second condition, and the second condition is the delay values of delay line a0, delay line a4, delay line a8, and delay line a 12 are not equal to each other, the delay values of delay line a1, delay line a5, delay line a9, and delay line a 13 are not equal to each other, and the delay values of delay line a2, delay line a6, delay line a 10The delay value, and delay line a 14 The delay values are not equal to each other. The delay value of delay line a3, the delay value of delay line a7, the delay value of delay line a 11 The delay value, and delay line a 15 The delay values are not equal to each other.

[0012] In this implementation form, the client side has a 1*800G interface or a 2*400G interface with each lane of 100 Gb / s. When the second condition is satisfied and V≥68, among the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 16 data streams are delayed, symbol a0, symbol a4, symbol a8, and symbol a 12 are from four different RS codeword symbols, and symbol a1, symbol a5, symbol a9, and symbol a 13 are from four different RS codeword symbols, and symbol a2, symbol a6, symbol a 10 , and symbol a 14 are from four different RS codeword symbols, and symbol a3, symbol a7, symbol a 11 , and symbol a 15 are from four different RS codeword symbols. This delay design pattern implements good performance of the cascade FEC solution, shortens the overall latency of the transmission solution, and facilitates the subsequent use of the interleaving solution that is easy to implement and has low latency.

[0013] In some possible implementation forms, among the delay lines in the n delay lines, the delay values of delay line a0, delay line a2, delay line a4, delay line a6, delay line a8, delay line a 10 , delay line a 12 and delay line a 14 satisfy the third condition, and the third condition is The difference between the delay value of delay line a0 and the delay value of delay line a4 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a6 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a12 The difference from the delay value of is 2V symbols, and the delay line a 10 The difference between the delay value of the delay line and the delay line a 14 The difference from the delay value of is 2V symbols.

[0014] In this implementation form, the client side has a 4*200G interface with each lane of 100Gb / s. When the first and third conditions are met and V≧68, among the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 16 data streams are delayed, symbol a0, symbol a1, symbol a4, and symbol a5 are from 4 different RS codeword symbols, symbol a2, symbol a3, symbol a6, and symbol a7 are from 4 different RS codeword symbols, symbol a8, symbol a9, symbol a 12 、and symbol a 13 are from 4 different RS codeword symbols, symbol a 10 、symbol a 11 、symbol a 14 、and symbol a 15 are from 4 different RS codeword symbols, symbol a

[0015] In some possible implementation forms, the first delay value set {A} is the delay values of delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 、delay line a 11 、delay line a 12 、delay line a 13 、delay line a 14 、and delay line a 15 in the delay line group k in n delay lines in sequence. The first delay value set {A} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0}, {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V}, {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0}, {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V}, {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0}, {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V}, {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0}, {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V}, {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V}, {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V}, {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of the following.

[0016] In this implementation, the client side has a 1*800G interface, a 2*400G interface, a 4*200G interface, or an 8*100G interface (including "100G RS-FEC-Int" and "100G RS-FEC" modes), each with 100 Gb / s lanes. When the aforementioned first set of delay values {A} is satisfied and V ≥ 68, in the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) among the 16 data streams are delayed, symbol a0, symbol a1, symbol a4, symbol a5, symbol a8, symbol a9, symbol a 12 , and symbol a 13 are from 8 different RS codeword symbols, and symbol a2, symbol a3, symbol a6, symbol a7, symbol a 10 , symbol a11 , symbol a 14 , and symbol a 15 are from 8 different RS codeword symbols. This delay design pattern facilitates the subsequent use of an interleaving solution that is easy to implement and has low latency in order to implement the good performance of the cascade FEC solution and shorten the overall latency of the transmission solution.

[0017] In some possible implementation forms, among the delay lines in n delay lines, the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 and delay line a 15 satisfy the fourth condition, and the fourth condition is that the delay value of delay line a0 and the delay value of delay line a2 are equal or have a difference of 2V symbols, the delay value of delay line a1 and the delay value of delay line a3 are equal or have a difference of 2V symbols, the delay value of delay line a2 and the delay value of delay line a4 are equal or have a difference of 2V symbols, the delay value of delay line a3 and the delay value of delay line a5 are equal or have a difference of 2V symbols, the delay value of delay line a4 and the delay value of delay line a6 are equal or have a difference of 2V symbols, the delay value of delay line a5 and the delay value of delay line a7 are equal or have a difference of 2V symbols, the delay value of delay line a8 and the delay value of delay line a 10 are equal or have a difference of 2V symbols, the delay value of delay line a9 and the delay value of delay line a 11 are equal or have a difference of 2V symbols, delay line a 10 and the delay value of delay line a 12 are equal or have a difference of 2V symbols, delay line a 11 and the delay value of delay line a 13The delay value is equal to or has a difference of 2V symbols from Delay line a 12 The delay value of 14 is equal to or has a difference of 2V symbols from the delay value of delay line a Delay line a 13 The delay value of 15 is equal to or has a difference of 2V symbols from the delay value of delay line a That's what it is

[0018] In some possible implementation forms, the second set of delay values {B} is the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 in the delay line group k in n delay lines, 11 the delay line a 12 the delay line a 13 the delay line a 14 the delay line a 15 sequentially includes the delay values of, and the second set of delay values {B} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of.

[0019] In some possible implementations, the sequence number value set {C} sequentially includes the values of a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 a 11 a 12 a 13 a 14 and a 15 and the value set {C} is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 12, 13}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 14, 15, 12, 13}, {0, 1, 2, 3, 6, 7, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15}, {0, 1, 2, 3, 6, 7, 4, 5, 8, 9, 10, 11, 14, 15, 12, 13}, {0, 1, 2, 3, 6, 7, 4, 5, 10, 11, 8, 9, 12, 13, 14, 15}, {0, 1, 2, 3, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13}, {2, 3, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {2、3、0、1、4、5、6、7、8、9、10、11、14、15、12、13}、 {2、3、0、1、4、5、6、7、10、11、8、9、12、13、14、15}、 {2、3、0、1、4、5、6、7、10、11、8、9、14、15、12、13}、 {2、3、0、1、6、7、4、5、8、9、10、11、12、13、14、15}、 {2、3、0、1、6、7、4、5、8、9、10、11、14、15、12、13}、 {2、3、0、1、6、7、4、5、10、11、8、9、12、13、14、15}、 {2、3、0、1、6、7、4、5、10、11、8、9、14、15、12、13}、 {0、3、1、2、4、7、5、6、8、11、9、10、12、15、13、14}、 {0、3、1、2、4、7、5、6、8、11、9、10、13、14、12、15}、 {0、3、1、2、4、7、5、6、9、10、8、11、12、15、13、14}、 {0、3、1、2、4、7、5、6、9、10、8、11、13、14、12、15}、 {0、3、1、2、5、6、4、7、8、11、9、10、12、15、13、14}、 {0、3、1、2、5、6、4、7、8、11、9、10、13、14、12、15}、 {0、3、1、2、5、6、4、7、9、10、8、11、12、15、13、14}、 {0、3、1、2、5、6、4、7、9、10、8、11、13、14、12、15}、 {1、2、0、3、4、7、5、6、8、11、9、10、12、15、13、14}、 {1、2、0、3、4、7、5、6、8、11、9、10、13、14、12、15}、 {1、2、0、3、4、7、5、6、9、10、8、11、12、15、13、14}、 {1、2、0、3、4、7、5、6、9、10、8、11、13、14、12、15}、 {1, 2, 0, 3, 5, 6, 4, 7, 8, 11, 9, 10, 12, 15, 13, 14}, {1, 2, 0, 3, 5, 6, 4, 7, 8, 11, 9, 10, 13, 14, 12, 15}, {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 12, 15, 13, 14}, and {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 13, 14, 12, 15} includes one of the following.

[0020] In some possible implementations, each first symbol set includes n first symbol subsets, each first symbol subset includes m symbols arranged in sequence, and each second symbol set includes r second symbol subsets, each second symbol subset includes c symbols, r is an integer greater than 1, c is an integer greater than 1, n * m = r * c, and the c symbols in each second symbol subset correspond to the c symbols distributed in c first symbol subsets in the first symbol set.

[0021] In some possible implementations, n = 32, and the serial number values of the 32 first symbol subsets are b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 b 20 b 21 b 22 b 23 b 24 b 25 b 26 b 27 b 28 b 29 b 30 and b 31including b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 , b 12 , b 13 , b 14 , and b 15 are respectively equal in order to the delay line serial numbers a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15 , and b 16 , b 17 , b 18 , b 19 , b 20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 are respectively equal in order to the delay line serial numbers a0 + 16, a1 + 16, a2 + 16, a3 + 16, a4 + 16, a5 + 16, a6 + 16, a7 + 16, a8 + 16, a9 + 16, a 10 +16, a 11 +16, a 12 +16, a 13 +16, a 14 +16, and a 15 +16.

[0022] In some possible implementations, n = 32, m = 1, c = 8, r = 4, and 8 symbols in each second symbol subset satisfy the fifth condition, and the fifth condition is each of the 8 symbols in each second symbol subset is respectively the first symbol subset b0 in the first symbol set, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12, and the first symbol subset b 13 from Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from Each of the 4 symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12and the first symbol subset b 13 from four of the first symbol subsets in 13 , and the other four symbols in each second symbol subset are, respectively, the first symbol subset b in the first symbol set 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and the first symbol subset b 29 from four of the first symbol subsets in 29 , the four symbols in each second symbol subset are, respectively, the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b in the first symbol set 12 and the first symbol subset b 13 from four of the first symbol subsets in 13 , and the other four symbols in each second symbol subset are, respectively, the first symbol subset b in the first symbol set 18 the first symbol subset b 19 the first symbol subset b 22 the first symbol subset b 23 the first symbol subset b 26 the first symbol subset b 27 the first symbol subset b 30 and the first symbol subset b 31 from four of the first symbol subsets in 31 , the four symbols in each second symbol subset are, respectively, the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set10 1. The first symbol subset b 11 1. The first symbol subset b 14 1. And from the four first symbol subsets in the first symbol subset b 15 Among them, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 16 1. The first symbol subset b 17 1. The first symbol subset b 20 1. The first symbol subset b 21 1. The first symbol subset b 24 1. The first symbol subset b 25 1. The first symbol subset b 28 1. And from the four first symbol subsets in the first symbol subset b 29 Among them, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set Among them, and each of the four symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 1. The first symbol subset b 11 1. The first symbol subset b 14 1. And from the four first symbol subsets in the first symbol subset b 15 Among them, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 18 1. The first symbol subset b 19 1. The first symbol subset b 22 1. The first symbol subset b 23 1. The first symbol subset b 26 1. The first symbol subset b 27 1. The first symbol subset b 30 1. And from the four first symbol subsets in the first symbol subset b 31 Among them, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set Includes any one of them

[0023] In some possible implementation forms, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x where x = i + j * 4, 0 ≤ i < 4, and 0 ≤ j < 8.

[0024] In some possible implementation forms, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x where [Number] , 0 ≤ i < 4, 0 ≤ j < 8, and Y % Z represents the remainder obtained by dividing Y by Z [Number] represents the quotient obtained by dividing Y by Z.

[0025] In some possible implementation forms, n = 32, m = 1, c = 16, r = 2, and the 16 symbols in each second symbol subset satisfy the sixth condition, where the sixth condition is 8 symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 and b 13 in the first symbol set, and the other 8 symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b 20 , b 21 , b 24, the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 , and the first symbol subset b 13 from, and each of the other 8 symbols in each second symbol subset is respectively from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from, and each of the other 8 symbols in each second symbol subset is respectively from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b25 , the first symbol subset b 28 , and from the first symbol subset b 29 and, and each of the 8 symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 and from, and each of the other 8 symbols in each second symbol subset is respectively the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 and from, includes any one of them.

[0026] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b x and from,

Number

Number

[0027] In some possible implementation forms, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x and

Number

Number

[0028] In some possible implementation forms, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x and

Number

Number

[0029] In some possible implementation forms, n = 32, m = 3, c = 12, r = 8, and the 12 symbols in each second symbol subset satisfy the seventh condition, where the seventh condition is each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 and the first symbol subset b 13from, and each of the other four symbols in each second symbol subset is from one of the four first symbol subsets b in the first symbol set 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and the first symbol subset b 29 from within the four first symbol subsets, each of the six symbols in each second symbol subset is from one of the six first symbol subsets b0, b1, b4, b5, b8, b9 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the six first symbol subsets b 12 and the first symbol subset b 13 in, and each of the other six symbols in each second symbol subset is from one of the six first symbol subsets b 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and the first symbol subset b 29 from within the six first symbol subsets, each of the four symbols in each second symbol subset is from one of the four first symbol subsets b0, b1, b4, b5, b8, b9 in the first symbol set, and the first symbol subset b 12 and the first symbol subset b13 from four first symbol subsets in 16 and the other eight symbols in each second symbol subset are respectively the first symbol subset b in the first symbol set 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and the first symbol subset b 29 and are from each of the eight symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 and the first symbol subset b 13 and are from, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 18 the first symbol subset b 19 the first symbol subset b 22 the first symbol subset b 23 the first symbol subset b 26 the first symbol subset b 27 the first symbol subset b 30 and the first symbol subset b 31 and are from four first symbol subsets in each of the six symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 and the first symbol subset b13 from six first symbol subsets in 13 , and each of the other six symbols in each second symbol subset is the first symbol subset b in the first symbol set 18 the first symbol subset b 19 the first symbol subset b 22 the first symbol subset b 23 the first symbol subset b 26 the first symbol subset b 27 the first symbol subset b 30 and the first symbol subset b 31 from six first symbol subsets in 31 , each of the four symbols in each second symbol subset is the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b in the first symbol set 12 and the first symbol subset b 13 from four first symbol subsets in 13 , and each of the other eight symbols in each second symbol subset is the first symbol subset b in the first symbol set 18 the first symbol subset b 19 the first symbol subset b 22 the first symbol subset b 23 the first symbol subset b 26 the first symbol subset b 27 the first symbol subset b 30 and the first symbol subset b 31 from each of the eight symbols in each second symbol subset is the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 the first symbol subset b 11, the first symbol subset b 14 , and from the first symbol subset b 15 , and each of the other four symbols in each second symbol subset is, respectively, the first symbol subset b in the first symbol set 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and from the four first symbol subsets in the first symbol subset b 29 , and each of the six symbols in each second symbol subset is, respectively, the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set , the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and from the six first symbol subsets in the first symbol subset b 15 , and each of the other six symbols in each second symbol subset is, respectively, the first symbol subset b in the first symbol set 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and from the six first symbol subsets in the first symbol subset b 29 , and each of the six symbols in each second symbol subset is, respectively, the first symbol subset b in the first symbol set The four symbols in each second symbol subset are respectively from the first symbol subsets b2, b3, b6, b7, b 10 , b 11 , b 14 , and b 15 of the four first symbol subsets in the first symbol set, and the other eight symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b 20 , b 21 , b 24 , b 25 , b 28 , and b 29 of the first symbol set, The eight symbols in each second symbol subset are respectively from the first symbol subsets b2, b3, b6, b7, b 10 , b 11 , b 14 , and b 15 of the first symbol set, and the other four symbols in each second symbol subset are respectively from the first symbol subsets b 18 , b 19 , b 22 , b 23 , b 26 , b 27 , b 30 , and b 31from four first symbol subsets in each of the six symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from six first symbol subsets in 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from six first symbol subsets in, and each of the four symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from four first symbol subsets in, and each of the other eight symbols in each second symbol subset is from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26, the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from includes any one of

[0030] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is the symbol in the first symbol subset b in the first symbol set x%32 inside the symbol

Number

Number

Number

[0031] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is the symbol in the first symbol subset b in the first symbol set x%32 inside the symbol

Number

Number

Number

[0032] In some possible implementation forms, n = 32, m = 3, c = 12, r = 8, and the 12 symbols in each second symbol subset satisfy the eighth condition, and the eighth condition is 4 symbols in each second symbol subset are respectively from symbol 0 in the first symbol subset k1 in the first symbol set, symbol 0 in the first symbol subset k1 + 8 in the first symbol set, symbol 0 in the first symbol subset k1 + 16 in the first symbol set, and symbol 0 in the first symbol subset k1 + 24 in the first symbol set, and the other 4 symbols in each second symbol subset are respectively from symbol 1 in the first symbol subset k2 in the first symbol set, symbol 1 in the first symbol subset k2 + 8 in the first symbol set, symbol 1 in the first symbol subset k2 + 16 in the first symbol set, and symbol 1 in the first symbol subset k2 + 24 in the first symbol set, and the other 4 symbols in each second symbol subset are respectively from symbol 2 in the first symbol subset k3 in the first symbol set, symbol 2 in the first symbol subset k3 + 8 in the first symbol set, symbol 2 in the first symbol subset k3 + 16 in the first symbol set, and symbol 2 in the first symbol subset k3 + 24 in the first symbol set, where k1, k2, and k3 are not equal to each other, and 0 ≦ k1 < 8, 0 ≦ k2 < 8, and 0 ≦ k3 < 8.

[0033] In some possible implementation forms, the symbol j in the second symbol subset i in the second symbol set is from the symbol x%32 in the first symbol subset b

Number

Number

Number

[0034] In some possible implementations, the m symbols in the first symbol subset h within the first symbol set are from the delay data stream h, where 0 ≦ h ≦ n - 1, and V is an integer greater than or equal to 68.

[0035] In some possible implementations, V = Q * d, where Q represents the number of memory elements in the delay line, d represents the number of symbols stored in each memory element, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0036] In some possible implementations, each first symbol set is a first symbol matrix, each first symbol matrix contains n rows and m columns of symbols, each second symbol set is a second symbol matrix, each second symbol matrix contains r rows and c columns of symbols, and the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix.

[0037] In some possible implementations, the n delay lines include g groups of delay lines, each group of delay lines contains p delay lines, the delay values of the p delay lines in each group of delay lines are respectively the p delay values in the delay value set, each first symbol set is a first symbol matrix, each first symbol matrix contains n rows and m columns of symbols, each second symbol set is a second symbol matrix, each second symbol matrix contains r rows and c columns of symbols, the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix, and g is an integer greater than 1.

[0038] In some possible implementation forms, n symbols in each column of the first symbol matrix include g groups, each of the g groups includes p symbols, g is an integer greater than 1, c symbols in each row of the second symbol matrix include s groups, each of the s groups includes p symbols, s is an integer greater than 1, one group of p symbols in the second symbol matrix is from one group of p symbols in the first symbol matrix, and a total of 2 p symbols in any two groups in each row of the second symbol matrix are from different rows of the first symbol matrix.

[0039] In some possible implementation forms, n = 32, m = 1, r = 4, c = 8, p = 4, g = 8, and s = 2, and 8 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a and 4 symbols in group b in the first symbol matrix, where 0 ≤ a < 4 and 4 ≤ b < 8.

[0040] In some possible implementation forms, the symbol at row i and column j of the second symbol matrix corresponds to the symbol at row x%32 and column 0 of the first symbol matrix, where 0 ≤ i < 4 and 0 ≤ j < 8,

Number

Number

[0041] In some possible implementation forms, n = 32, m = 2, r = 4, c = 16, p = 4, g = 8, and s = 4. The 16 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a in column 0 of the first symbol matrix, 4 symbols in group b in column 0 of the first symbol matrix, 4 symbols in group e in column 1 of the first symbol matrix, and 4 symbols in group f in column 1 of the first symbol matrix. a, b, e, and f are not equal to each other, and 0 ≤ a < 4, 0 ≤ e < 4, 4 ≤ b < 8, 4 ≤ f < 8.

[0042] In some possible implementation forms, the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x%32 and column

Number

Number

Number

[0043] In some possible implementation forms, n = 32, m = 3, r = 8, c = 12, p = 4, g = 8, and s = 3. The 12 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a in column 0 of the first symbol matrix, 4 symbols in group b in column 1 of the first symbol matrix, and 4 symbols in group e in column 2 of the first symbol matrix. a, b, and e are not equal to each other, and 0 ≤ a < 4 and 4 ≤ e < 8, or 0 ≤ e < 4 and 4 ≤ a < 8.

[0044] In some possible implementation forms, the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x%32 and column [Number] where 0 ≤ i < 8 and 0 ≤ j < 12, [Number] and Y%Z represents the remainder obtained by dividing Y by Z, [Number] and represents the quotient obtained by dividing Y by Z.

[0045] In some possible implementation forms, the first forward error correction (FEC) encoding is performed on all of the n data streams, and all A codewords obtained by the first FEC encoding are distributed among the n data streams, where A consecutive symbols within each data stream are from A different first FEC codewords, A is an integer greater than or equal to 1, the n delay lines include g groups of delay lines, each group of delay lines includes p delay lines, the delay values of the p delay lines within each group of delay lines are respectively the p delay values within a set of delay values, g is an integer greater than or equal to 1, n = p * g, and A * p symbols within each delayed group of the p data streams are from A * p different first FEC codewords, and the A * p symbols include A consecutive symbols of each of the p data streams.

[0046] In some possible implementation forms, each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of n rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, the first symbol matrix includes g first symbol sub-matrices, each first symbol sub-matrix includes symbols of p rows and m columns, the second symbol matrix includes g second symbol sub-matrices, each second symbol sub-matrix includes symbols of r0 rows and c columns, r0 is an integer greater than or equal to 1, c is an integer greater than or equal to 1, r = r0 * g, p * m = r0 * c, the second symbol sub-matrix t is obtained by interleaving the first symbol sub-matrix t, 0 ≤ t < g, and the c symbols in each row of each second symbol matrix are from c different codewords.

[0047] In some possible implementation forms, the c symbols in each row of the second symbol sub-matrix t are from the c symbols in the first symbol sub-matrix t, and the c symbols in the second symbol sub-matrix t are distributed in the maximum A columns of the first symbol sub-matrix t.

[0048] In some possible implementation forms, the symbols in the first symbol sub-matrix t are arranged in order, the symbols in rows 0 to p - 1 of each column of the first symbol sub-matrix t are p symbols arranged in order, in two adjacent columns of the first symbol sub-matrix t, the symbols in rows p - 1 of the previous column to row 1 of the next column are two symbols arranged in order, the c symbols in row 0 of the second symbol sub-matrix t are from the c symbols in group 0 arranged in the order starting from row 0 and column 0 of the first symbol sub-matrix t, and the rest can be estimated by analogy until the c symbols in row r0 - 1 of the second symbol sub-matrix t are from the last group of the c symbols arranged in the order starting from row 0 and column 0 of the first symbol sub-matrix t.

[0049] In some possible implementation forms, A = 2, n = 8, p = 8, and g = 1, or A = 2, n = 16, p = 8, and g = 2.

[0050] In some possible implementation forms, m = 9, r = 8*g, and c = 9, m = 5, r = 4*g, and c = 10, m = 11, r = 8*g, and c = 11, m = 3, r = 2*g, and c = 12, m = 13, r = 8*g, and c = 13, m = 7, r = 4*g, and c = 14, m = 15, r = 8*g, and c = 15, or m = 2, r = g, and c = 16.

[0051] In some possible implementation forms, the delay values of the p delay lines in each delay line group increase or decrease sequentially by only V symbols.

[0052] In some possible implementation forms, n = 32, and the serial number values of the 32 symbols output each time after 32 data streams are delayed are b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 、b 11 、b 12 、b 13 、b 14 、b 15 、b 16 、b 17 、b 18 、b 19 、b 20 、b 21 、b 22 、b 23 、b 24 、b 25 、b 26 、b 27 、b 28 、b 29 、b 30 、and b 31including, among the 32 symbols output each time after 32 data streams are delayed, 16 symbols in group 0 are from 16 different codewords, and 16 symbols in group 1 among the 32 symbols output each time after 32 data streams are delayed are from 16 different codewords, The 16 symbols in group 0 include symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , symbol b 16 , symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 ; the 16 symbols in group 1 include symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , and symbol b 31 ; or The 16 symbols in group 0 include symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , and symbol b 31including, the 16 symbols in Group 1 are symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 16 , symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 .

[0053] In some possible implementations, each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of 32 rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, the 16 rows of symbols in Group 0 in the first symbol matrix are sequentially the symbols in row 0, the symbols in row 1, the symbols in row 4, the symbols in row 5, the symbols in row 8, the symbols in row 9, the symbols in row 12, the symbols in row 13, the symbols in row 16, the symbols in row 17, the symbols in row 20, the symbols in row 21, the symbols in row 24, the symbols in row 25, the symbols in row 28, and the symbols in row 29, the 16 rows of symbols in Group 1 in the first symbol matrix are sequentially the symbols in row 2, the symbols in row 3, the symbols in row 6, the symbols in row 7, the symbols in row 10, the symbols in row 11, the symbols in row 14, the symbols in row 15, the symbols in row 18, the symbols in row 19, the symbols in row 22, the symbols in row 23, the symbols in row 26, the symbols in row 27, the symbols in row 30, and the symbols in row 31, The 16 symbols in 16 rows within Group 0 are arranged in order. The symbols in rows 0 to 15 of each column among the 16 symbols in 16 rows within Group 0 are 16 symbols arranged in order. In two adjacent columns of the 16 symbols in 16 rows within Group 0, the symbols in rows 15 of the previous column to row 0 of the next column are two symbols arranged in order. The c symbols in row 0 among the r / 2 rows of symbols within Group 0 in the second symbol matrix are from c symbols within Group 0 arranged in the order starting from row 0 and column 0 among the 16 symbols in 16 rows within Group 0. The rest can be inferred by analogy until the c symbols in row r / 2 - 1 among the r / 2 rows of symbols within Group 0 in the second symbol matrix are from the last group of c symbols arranged in the order starting from row 0 and column 0 among the 16 symbols in 16 rows within Group 0, and The 16 symbols in 16 rows within Group 1 are arranged in order. The symbols in rows 0 to 15 of each column among the 16 symbols in 16 rows within Group 1 are 16 symbols arranged in order. In two adjacent columns of the 16 symbols in 16 rows within Group 1, the symbols in rows 15 of the previous column to row 0 of the next column are two symbols arranged in order. The c symbols in row 0 among the r / 2 rows of symbols within Group 1 in the second symbol matrix are from c symbols within Group 0 arranged in the order starting from row 0 and column 0 among the 16 symbols in 16 rows within Group 0. The rest can be inferred by analogy until the c symbols in row r / 2 - 1 among the r / 2 rows of symbols within Group 1 in the second symbol matrix are from the last group of c symbols arranged in the order starting from row 0 and column 0 among the 16 symbols in 16 rows within Group 1.

[0054] In some possible implementations, before the step of separately delaying n data streams based on n delay lines, the method further includes a step of performing lane rearrangement on the n data streams so that the n data streams can be arranged in a preset order, or after the step of separately delaying n data streams based on n delay lines and before the step of obtaining L*m symbols from each of the n delayed data streams to obtain L first symbol sets, the method further includes a step of performing lane rearrangement on the n data streams so that the n data streams can be arranged in a preset order.

[0055] In some possible implementations, before the step of separately delaying n data streams based on n delay lines, the method further includes a step of performing lane despreading on the n data streams to obtain n aligned lane data streams.

[0056] In some possible implementations, all of the n data streams are data streams obtained by a first FEC encoding. After the step of separately interleaving the L first symbol sets to obtain L second symbol sets, the method further includes a step of performing a second FEC encoding on r second symbol subsets within each second symbol set to obtain L*r codewords.

[0057] According to a second aspect, this application provides a data interleaving apparatus. The data interleaving apparatus includes a delay unit and an interleaver. The delay unit is configured to separately delay n data streams based on n delay lines, where n is a positive integer divisible by p, p is an integer greater than 1, the delay value of each delay line is any delay value within a set of delay values, the set of delay values includes p delay values, the minimum delay value within the set of delay values is 0, the difference between two adjacent delay values among the p delay values in the set of delay values set in ascending order is a V symbol, V is an integer of 34 or more, the number of delay lines corresponding to each delay value within the set of delay values is n / p, and the interleaver is configured to obtain L*m symbols from each of the n delayed data streams to obtain L first symbol sets, each first symbol set includes n*m symbols, L is an integer of 1 or more, m is an integer of 1 or more, and to separately interleave the L first symbol sets to obtain L second symbol sets, and the number of symbols within each second symbol set is the same as the number of symbols in each first symbol set.

[0058] In some possible implementations, p = 4, n is divisible by 16, the n delay lines include at least one group of delay lines, each group of delay lines includes 16 adjacent delay lines, and the delay values of the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、delay line a 11 、delay line a 12 、delay line a 13 、delay line a 14 and delay line a 15 in the group k of delay lines among the n delay lines satisfy the first condition, 0 ≦ k < n / 16, and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 and a 15is a non - negative integer less than 16 and not equal to each other. The first condition is that the difference between the delay value of delay line a0 and the delay value of delay line a1 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a3 is 2V symbols, the difference between the delay value of delay line a4 and the delay value of delay line a5 is 2V symbols the difference between the delay value of delay line a6 and the delay value of delay line a7 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a9 is 2V symbols, delay line a 10 's delay value and delay line a 11 's delay value is 2V symbols, delay line a 12 's delay value and delay line a 13 's delay value is 2V symbols, delay line a 14 's delay value and delay line a 15 's delay value is 2V symbols, which is the case.

[0059] In some possible implementation forms, in each group of 16 delay lines among n delay lines, the number of delay lines with delay values of 0 symbols, V symbols, 2V symbols, and 3V symbols is all 4.

[0060] In some possible implementation forms, among the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 and a 15 in group k of delay lines among n delay lines satisfy the second condition. The second condition is that the delay value of delay line a0, the delay value of delay line a4, the delay value of delay line a8, and the delay value of delay line a 12The delay values are not equal to each other, and the delay value of delay line a1, the delay value of delay line a5, the delay value of delay line a9, and the delay value of delay line a 13 The delay values are not equal to each other, and the delay value of delay line a2, the delay value of delay line a6, the delay value of delay line a 10 The delay value, and the delay value of delay line a 14 The delay values are not equal to each other, and the delay value of delay line a3, the delay value of delay line a7, the delay value of delay line a 11 The delay value, and the delay value of delay line a 15 The delay values are not equal to each other.

[0061] In some possible implementations, among the n delay lines, the delay lines a0, a2, a4, a6, a8, a 10 In the group k of delay lines, and the delay lines a 12 And the delay lines a 14 The delay values satisfy a third condition, and the third condition is The difference between the delay value of delay line a0 and the delay value of delay line a4 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a6 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a 12 The delay value is 2V symbols, and the difference between the delay value of delay line a 10 The delay value and the delay value of delay line a 14 The delay value is 2V symbols.

[0062] In some possible implementations, the first set of delay values {A} is composed of the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 In the group k of delay lines among the n delay lines, and the delay lines a 11 And the delay lines a 12 And the delay lines a 13 And the delay lines a 14 And the delay lines a 15 The delay values are sequentially included, and the first set of delay values {A} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0}, {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V}, {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0}, {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V}, {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0}, {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V}, {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of them.

[0063] In some possible implementations, the delay values of delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 and a 15 in group k of delay lines in n delay lines satisfy the fourth condition, and the fourth condition is the delay value of delay line a0 and the delay value of delay line a2 are equal or have a difference of 2V symbols, the delay value of delay line a1 and the delay value of delay line a3 are equal or have a difference of 2V symbols, the delay value of delay line a2 and the delay value of delay line a4 are equal or have a difference of 2V symbols, the delay value of delay line a3 and the delay value of delay line a5 are equal or have a difference of 2V symbols, the delay value of delay line a4 and the delay value of delay line a6 are equal or have a difference of 2V symbols, The delay value of delay line a5 and the delay value of delay line a7 are equal or have a difference of 2V symbols, the delay value of delay line a8 and the delay value of delay line a 10 are equal or have a difference of 2V symbols, the delay value of delay line a9 and the delay value of delay line a 11 are equal or have a difference of 2V symbols, delay line a 10 and the delay value of delay line a 12 are equal or have a difference of 2V symbols, delay line a 11 and the delay value of delay line a 13 are equal or have a difference of 2V symbols, delay line a 12 and the delay value of delay line a 14 are equal or have a difference of 2V symbols, delay line a 13 and the delay value of delay line a 15 are equal or have a difference of 2V symbols, which is the case.

[0064] In some possible implementation forms, the second delay value set {B} is the delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , and delay line a 15 sequentially including the delay values, and the second delay value set {B} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V}, {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of them.

[0065] In some possible implementations, the sequence number value set {C} sequentially includes the values of a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 a 11 a 12 a 13 a 14 and a 15 and the value set {C} is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 12, 13}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 14, 15, 12, 13}, {0、1、2、3、6、7、4、5、8、9、10、11、12、13、14、15}、 {0、1、2、3、6、7、4、5、8、9、10、11、14、15、12、13}、 {0、1、2、3、6、7、4、5、10、11、8、9、12、13、14、15}、 {0、1、2、3、6、7、4、5、10、11、8、9、14、15、12、13}、 {2、3、0、1、4、5、6、7、8、9、10、11、12、13、14、15}、 {2、3、0、1、4、5、6、7、8、9、10、11、14、15、12、13}、 {2、3、0、1、4、5、6、7、10、11、8、9、12、13、14、15}、 {2、3、0、1、4、5、6、7、10、11、8、9、14、15、12、13}、 {2、3、0、1、6、7、4、5、8、9、10、11、12、13、14、15}、 {2、3、0、1、6、7、4、5、8、9、10、11、14、15、12、13}、 {2、3、0、1、6、7、4、5、10、11、8、9、12、13、14、15}、 {2、3、0、1、6、7、4、5、10、11、8、9、14、15、12、13}、 {0、3、1、2、4、7、5、6、8、11、9、10、12、15、13、14}、 {0、3、1、2、4、7、5、6、8、11、9、10、13、14、12、15}、 {0、3、1、2、4、7、5、6、9、10、8、11、12、15、13、14}、 {0、3、1、2、4、7、5、6、9、10、8、11、13、14、12、15}、 {0、3、1、2、5、6、4、7、8、11、9、10、12、15、13、14}、 {0、3、1、2、5、6、4、7、8、11、9、10、13、14、12、15}、 {0、3、1、2、5、6、4、7、9、10、8、11、12、15、13、14}、 {0, 3, 1, 2, 5, 6, 4, 7, 9, 10, 8, 11, 13, 14, 12, 15}, {1, 2, 0, 3, 4, 7, 5, 6, 8, 11, 9, 10, 12, 15, 13, 14}, {1, 2, 0, 3, 4, 7, 5, 6, 8, 11, 9, 10, 13, 14, 12, 15}, {1, 2, 0, 3, 4, 7, 5, 6, 9, 10, 8, 11, 12, 15, 13, 14}, {1, 2, 0, 3, 4, 7, 5, 6, 9, 10, 8, 11, 13, 14, 12, 15}, {1, 2, 0, 3, 5, 6, 4, 7, 8, 11, 9, 10, 12, 15, 13, 14}, {1, 2, 0, 3, 5, 6, 4, 7, 8, 11, 9, 10, 13, 14, 12, 15}, {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 12, 15, 13, 14}, and {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 13, 14, 12, 15} includes one of them.

[0066] In some possible implementations, each first symbol set includes n first symbol subsets, each first symbol subset includes m symbols arranged in sequence, and each second symbol set includes r second symbol subsets, each second symbol subset includes c symbols, r is an integer greater than 1, c is an integer greater than 1, n*m = r*c, and the c symbols in each second symbol subset correspond to the c symbols distributed in the c first symbol subsets in the first symbol set.

[0067] In some possible implementations, n = 32, and the serial number values of the 32 first symbol subsets are b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 b 11 b 12 b 13 b 14 b 15 b16 , b 17 , b 18 , b 19 , b 20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 includes b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 , b 12 , b 13 , b 14 , and b 15 are respectively equal in order to the delay line serial numbers a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15 , and b 16 , b 17 , b 18 , b 19 , b 20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 are respectively equal in order to the delay line serial numbers a0 + 16, a1 + 16, a2 + 16, a3 + 16, a4 + 16, a5 + 16, a6 + 16, a7 + 16, a8 + 16, a9 + 16, a 10 + 16, a 11 + 16, a 12 + 16, a 13 + 16, a 14 + 16, and a 15 + 16 in sequence.

[0068] In some possible implementations, n = 32, m = 1, c = 8, r = 4, and the 8 symbols in each second symbol subset satisfy the fifth condition, where the fifth condition includes any one of the following conditions: The 8 symbols in each second symbol subset are respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, and the first symbol subset b 12 , and the first symbol subset b 13 in the first symbol set, The 8 symbols in each second symbol subset are respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 in the first symbol set, The 8 symbols in each second symbol subset are respectively from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 in the first symbol set, The 8 symbols in each second symbol subset are respectively from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26, the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from Each of the four symbols in each second symbol subset is from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and the first symbol subset b 13 in the first symbol set, and the other four symbols in each second symbol subset are from the first symbol subsets b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 in the first symbol set, and Each of the four symbols in each second symbol subset is from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and the first symbol subset b 13 in the first symbol set, and the other four symbols in each second symbol subset are from the first symbol subsets b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23, the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 are from four first symbol subsets in, Each of the four symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 are from four first symbol subsets in, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 are from four first symbol subsets in, and Each of the four symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 are from four first symbol subsets in, and each of the other four symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 18, the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from four first symbol subsets in includes any one of

[0069] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x , where x = i + j * 4, 0 ≤ i < 4, and 0 ≤ j < 8

[0070] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x , where

Number

Number

[0071] In some possible implementations, n = 32, m = 1, c = 16, r = 2, and the 16 symbols in each second symbol subset satisfy the sixth condition, and the sixth condition is Each of the eight symbols in each second symbol subset is from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 , and the first symbol subset b 13 in the first symbol set, and each of the other eight symbols in each second symbol subset is from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 in the first symbol set, Each of the eight symbols in each second symbol subset is from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 , and the first symbol subset b 13 in the first symbol set, and each of the other eight symbols in each second symbol subset is from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 in the first symbol set, Each of the 8 symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 11 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 14 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 15 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 16 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 17 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 20 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 21 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 24 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 25 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 28 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 29 in the first symbol set, and each of the 8 symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 11 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 14 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 15 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 18 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 19 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 22 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 23 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 26 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 27 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 30 in the first symbol set, and each of the other 8 symbols in each second symbol subset is from the first symbol subset b 31 in the first symbol set, includes any one of them.

[0072] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x and [Number] , where 0 ≤ i < 2, 0 ≤ j < 16, and Y%Z represents the remainder obtained by dividing Y by Z, [Number] represents the quotient obtained by dividing Y by Z.

[0073] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x and [Number] , where 0 ≤ i < 2, 0 ≤ j < 16, and Y%Z represents the remainder obtained by dividing Y by Z, [Number] represents the quotient obtained by dividing Y by Z.

[0074] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b in the first symbol set x and [Number] , where 0 ≤ i < 2, 0 ≤ j < 16, and Y%Z represents the remainder obtained by dividing Y by Z, [Number] represents the quotient obtained by dividing Y by Z.

[0075] In some possible implementations, n = 32, m = 3, c = 12, r = 8, and 12 symbols in each second symbol subset satisfy the seventh condition, where the seventh condition is 8 symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13 in the first symbol set, and the other 4 symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b 20 , b 21 , b 24 , b 25 , b 28 , and b 29 in 4 first symbol subsets in the first symbol set, 6 symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13 in 6 first symbol subsets in the first symbol set, and the other 6 symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from six first symbol subsets within, each of the four symbols in each second symbol subset is from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and the first symbol subset b 13 from four first symbol subsets in, and each of the other eight symbols in each second symbol subset is from the first symbol subsets b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from, each of the eight symbols in each second symbol subset is from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and the first symbol subset b 13 from, and each of the other four symbols in each second symbol subset is from the first symbol subsets b 18 , the first symbol subset b 19 , the first symbol subset b22 , from the four first symbol subsets b in 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 and are from the four first symbol subsets in Each of the six symbols in each second symbol subset is respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b in the first symbol set, 12 , and the first symbol subset b 13 and are from the six first symbol subsets in 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 and are from the six first symbol subsets in Each of the four symbols in each second symbol subset is respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b in the first symbol set, 12 , and the first symbol subset b 13 and are from the four first symbol subsets in 18, the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from, Each of the 8 symbols in each second symbol subset is respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from, and each of the other 4 symbols in each second symbol subset is respectively from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from the 4 first symbol subsets in, Each of the 6 symbols in each second symbol subset is respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15from six first symbol subsets in and, the other six symbols in each second symbol subset are respectively, the first symbol subset b in the first symbol set 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and, the first symbol subset b 29 from six first symbol subsets in it, the four symbols in each second symbol subset are respectively, the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 the first symbol subset b 11 the first symbol subset b 14 and, the first symbol subset b 15 from four first symbol subsets in and, the other eight symbols in each second symbol subset are respectively, the first symbol subset b in the first symbol set 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and, the first symbol subset b 29 from it, the eight symbols in each second symbol subset are respectively, the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 the first symbol subset b11 , the first symbol subset b 14 , and from the first symbol subset b 15 , and among the other four symbols in each second symbol subset, each is from the first symbol subset b in the first symbol set 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and from the four first symbol subsets in the first symbol subset b 31 , and each of the six symbols in each second symbol subset is from the first symbol subsets b2, b3, b6, b7, b in the first symbol set , the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and from the six first symbol subsets in the first symbol subset b 15 , and among the other six symbols in each second symbol subset, each is from the first symbol subset b in the first symbol set 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and from the six first symbol subsets in the first symbol subset b 31 , and from the six first symbol subsets in the first symbol subset b, and Each of the four symbols in each second symbol subset is from one of the first symbol subsets b2, b3, b6, b7, b 10 in the first symbol subset in the first symbol set, the first symbol subset b 11 in the first symbol subset in the first symbol set, the first symbol subset b 14 in the first symbol subset in the first symbol set, and the first symbol subset b 15 from the four first symbol subsets in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 18 in the first symbol subset in the first symbol set, the first symbol subset b 19 in the first symbol subset in the first symbol set, the first symbol subset b 22 in the first symbol subset in the first symbol set, the first symbol subset b 23 in the first symbol subset in the first symbol set, the first symbol subset b 26 in the first symbol subset in the first symbol set, the first symbol subset b 27 in the first symbol subset in the first symbol set, the first symbol subset b 30 in the first symbol subset in the first symbol set, and the first symbol subset b 31 from the first symbol set, including any one of them.

[0076] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is the symbol x%32 in the first symbol subset b

Number

Number

Number

[0077] In some possible implementation forms, symbol j in the second symbol subset i in the second symbol set is the symbol in the first symbol subset b in the first symbol set x%32 in the

Number

Number

Number

[0078] In some possible implementation forms, n = 32, m = 3, c = 12, r = 8, and the 12 symbols in each second symbol subset satisfy the eighth condition, and the eighth condition is Each of the four symbols in each second symbol subset is respectively from the symbol 0 in the first symbol subset k1, the symbol 0 in the first symbol subset k1 + 8, the symbol 0 in the first symbol subset k1 + 16, and the symbol 0 in the first symbol subset k1 + 24 in the first symbol set, and each of the other four symbols in each second symbol subset is respectively from the symbol 1 in the first symbol subset k2, the symbol 1 in the first symbol subset k2 + 8, the symbol 1 in the first symbol subset k2 + 16, and the symbol 1 in the first symbol subset k2 + 24 in the first symbol set, and each of the other four symbols in each second symbol subset is respectively from the symbol 2 in the first symbol subset k3, the symbol 2 in the first symbol subset k3 + 8, the symbol 2 in the first symbol subset k3 + 16, and the symbol 2 in the first symbol subset k3 + 24 in the first symbol set, including that k1, k2, and k3 are not equal to each other, 0 ≤ k1 < 8, 0 ≤ k2 < 8, and 0 ≤ k3 < 8.

[0079] In some possible implementations, the symbol j in the second symbol subset i in the second symbol set is the symbol x%32 in the first symbol subset b

Number

Number

Number

[0080] In some possible implementation forms, the m symbols in the first symbol subset h within the first symbol set are from the delay data stream h, where 0 ≦ h ≦ n - 1, and V is an integer greater than or equal to 68.

[0081] In some possible implementation forms, V = Q * d, where Q represents the number of memory elements in the delay line, d represents the number of symbols stored in each memory element, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0082] In some possible implementation forms, each first symbol set is a first symbol matrix, each first symbol matrix contains n rows and m columns of symbols, each second symbol set is a second symbol matrix, each second symbol matrix contains r rows and c columns of symbols, and the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix.

[0083] In some possible implementation forms, the n delay lines include g groups of delay lines, each group of delay lines contains p delay lines, the delay values of the p delay lines in each group of delay lines are respectively the p delay values in the delay value set, each first symbol set is a first symbol matrix, each first symbol matrix contains n rows and m columns of symbols, each second symbol set is a second symbol matrix, each second symbol matrix contains r rows and c columns of symbols, the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix, and g is an integer greater than 1.

[0084] In some possible implementation forms, n symbols in each column of the first symbol matrix include g groups, each of the g groups includes p symbols, g is an integer greater than 1, c symbols in each row of the second symbol matrix include s groups, each of the s groups includes p symbols, s is an integer greater than 1, one group of p symbols in the second symbol matrix is from one group of p symbols in the first symbol matrix, and a total of two p symbols in any two groups in each row of the second symbol matrix are from different rows of the first symbol matrix.

[0085] In some possible implementation forms, n = 32, m = 1, r = 4, c = 8, p = 4, g = 8, and s = 2, and 8 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a and 4 symbols in group b in the first symbol matrix, where 0 ≤ a < 4 and 4 ≤ b < 8.

[0086] In some possible implementation forms, the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x%32 and column 0 of the first symbol matrix, where 0 ≤ i < 4 and 0 ≤ j < 8,

Number

Number

[0087] In some possible implementation forms, n = 32, m = 2, r = 4, c = 16, p = 4, g = 8, and s = 4. The 16 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a in column 0 of the first symbol matrix, 4 symbols in group b in column 0 of the first symbol matrix, 4 symbols in group e in column 1 of the first symbol matrix, and 4 symbols in group f in column 1 of the first symbol matrix. a, b, e, and f are not equal to each other, and 0 ≤ a < 4, 0 ≤ e < 4, 4 ≤ b < 8, 4 ≤ f < 8.

[0088] In some possible implementation forms, the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x % 32 and column

Number

Number

Number

[0089] In some possible implementation forms, n = 32, m = 3, r = 8, c = 12, p = 4, g = 8, and s = 3. The 12 symbols in one row of the second symbol matrix respectively correspond to 4 symbols in group a in column 0 of the first symbol matrix, 4 symbols in group b in column 1 of the first symbol matrix, and 4 symbols in group e in column 2 of the first symbol matrix. a, b, and e are not equal to each other, and 0 ≤ a < 4 and 4 ≤ e < 8, or 0 ≤ e < 4 and 4 ≤ a < 8.

[0090] In some possible implementations, the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x%32 and column [Number] where 0 ≤ i < 8 and 0 ≤ j < 12, [Number] and Y%Z represents the remainder obtained by dividing Y by Z, [Number] and represents the quotient obtained by dividing Y by Z.

[0091] In some possible implementations, the first forward error correction (FEC) encoding is performed on all of the n data streams, all A codewords obtained by the first FEC encoding are distributed among the n data streams, A consecutive symbols within each data stream are from A different first FEC codewords, A is an integer greater than or equal to 1, the n delay lines include g groups of delay lines, each group of delay lines includes p delay lines, the delay values of the p delay lines within each group of delay lines are respectively p delay values within a set of delay values, g is an integer greater than or equal to 1, n = p*g, A*p symbols within each delayed group of the p data streams are from A*p different first FEC codewords, and the A*p symbols include A consecutive symbols of each of the p data streams.

[0092] In some possible implementation forms, each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of n rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, the first symbol matrix includes g first symbol sub-matrices, each first symbol sub-matrix includes symbols of p rows and m columns, the second symbol matrix includes g second symbol sub-matrices, each second symbol sub-matrix includes symbols of r0 rows and c columns, r0 is an integer greater than or equal to 1, c is an integer greater than or equal to 1, r = r0 * g, p * m = r0 * c, the second symbol sub-matrix t is obtained by interleaving the first symbol sub-matrix t, 0 ≤ t < g, and the c symbols in each row of each second symbol matrix are from c different codewords.

[0093] In some possible implementation forms, the c symbols in each row of the second symbol sub-matrix t are from the c symbols in the first symbol sub-matrix t, and the c symbols in the second symbol sub-matrix t are distributed in the maximum A columns of the first symbol sub-matrix t.

[0094] In some possible implementation forms, the symbols in the first symbol sub-matrix t are arranged in order, the symbols in rows 0 to p - 1 of each column of the first symbol sub-matrix t are p symbols arranged in order, in two adjacent columns of the first symbol sub-matrix t, the symbols in rows p - 1 of the previous column to row 1 of the next column are two symbols arranged in order, the c symbols in row 0 of the second symbol sub-matrix t are from the c symbols in group 0 arranged in the order starting from row 0 and column 0 of the first symbol sub-matrix t, and the rest can be estimated by analogy until the c symbols in row r0 - 1 of the second symbol sub-matrix t are from the last group of the c symbols arranged in the order starting from row 0 and column 0 of the first symbol sub-matrix t.

[0095] In some possible implementation forms, A = 2, n = 8, p = 8, and g = 1, or A = 2, n = 16, p = 8, and g = 2.

[0096] In some possible implementation forms, m = 9, r = 8*g, and c = 9, m = 5, r = 4*g, and c = 10, m = 11, r = 8*g, and c = 11, m = 3, r = 2*g, and c = 12, m = 13, r = 8*g, and c = 13, m = 7, r = 4*g, and c = 14, m = 15, r = 8*g, and c = 15, or m = 2, r = g, and c = 16.

[0097] In some possible implementation forms, the delay values of the p delay lines in each delay line group increase or decrease sequentially by only V symbols.

[0098] In some possible implementation forms, n = 32, and the serial number values of the 32 symbols output each time after 32 data streams are delayed are b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 、b 11 、b 12 、b 13 、b 14 、b 15 、b 16 、b 17 、b 18 、b 19 、b 20 、b 21 、b 22 、b 23 、b 24 、b 25 、b 26 、b 27 、b 28 、b 29 、b 30 、and b 31including, among the 32 symbols output each time after 32 data streams are delayed, the 16 symbols in group 0 are from 16 different codewords, and the 16 symbols in group 1 among the 32 symbols output each time after 32 data streams are delayed are from 16 different codewords, The 16 symbols in group 0 include symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , symbol b 16 , symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 ; and the 16 symbols in group 1 include symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , and symbol b 31 ; or The 16 symbols in group 0 include symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , and symbol b 31including, the 16 symbols in Group 1 are symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 16 , symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 .

[0099] In some possible implementations, each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of 32 rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, the 16 rows of symbols in Group 0 in the first symbol matrix are sequentially the symbols of row 0, the symbols of row 1, the symbols of row 4, the symbols of row 5, the symbols of row 8, the symbols of row 9, the symbols of row 12, the symbols of row 13, the symbols of row 16, the symbols of row 17, the symbols of row 20, the symbols of row 21, the symbols of row 24, the symbols of row 25, the symbols of row 28, and the symbols of row 29, the 16 rows of symbols in Group 1 in the first symbol matrix are sequentially the symbols of row 2, the symbols of row 3, the symbols of row 6, the symbols of row 7, the symbols of row 10, the symbols of row 11, the symbols of row 14, the symbols of row 15, the symbols of row 18, the symbols of row 19, the symbols of row 22, the symbols of row 23, the symbols of row 26, the symbols of row 27, the symbols of row 30, and the symbols of row 31, The 16 symbols in row 0 of the group are arranged in order, and the symbols in rows 0 to 15 of each column in the 16 symbols in row 0 of the group are 16 symbols arranged in order. In two adjacent columns of the 16 symbols in row 0 of the group, the symbols in rows 15 of the previous column to row 0 of the next column are two symbols arranged in order. The c symbols in row 0 of the r / 2 rows of symbols in row 0 of the group in the second symbol matrix are from the c symbols in row 0 of the group starting from row 0 and column 0 of the 16 symbols in row 0 of the group. The rest can be inferred by analogy until the c symbols in row r / 2 - 1 of the r / 2 rows of symbols in row 0 of the group in the second symbol matrix are from the last group of c symbols arranged in order starting from row 0 and column 0 of the 16 symbols in row 0 of the group, and The 16 symbols in row 0 of the group are arranged in order, and the symbols in rows 0 to 15 of each column in the 16 symbols in row 0 of the group are 16 symbols arranged in order. In two adjacent columns of the 16 symbols in row 0 of the group, the symbols in rows 15 of the previous column to row 0 of the next column are two symbols arranged in order. The c symbols in row 0 of the r / 2 rows of symbols in row 0 of the group in the second symbol matrix are from the c symbols in row 0 of the group starting from row 0 and column 0 of the 16 symbols in row 0 of the group. The rest can be inferred by analogy until the c symbols in row r / 2 - 1 of the r / 2 rows of symbols in row 0 of the group in the second symbol matrix are from the last group of c symbols arranged in order starting from row 0 and column 0 of the 16 symbols in row 0 of the group.

[0100] In some possible implementation forms, the data interleaving device further includes a lane rearrangement unit. Before the n data streams are separately delayed based on n delay lines, the lane rearrangement unit is configured to perform lane rearrangement on the n data streams so that the n data streams can be arranged in a preset order, or after the n data streams are separately delayed based on n delay lines and before L first symbol sets are obtained by obtaining L*m symbols from each of the delayed n data streams, the lane rearrangement unit is configured to perform lane rearrangement on the n data streams so that the n data streams can be arranged in a preset order.

[0101] In some possible implementation forms, the data interleaving device further includes a lane dequeue unit. Before the n data streams are separately delayed based on n delay lines, the lane dequeue unit is configured to perform lane dequeue processing on the n data streams to obtain n aligned lane data streams.

[0102] In some possible implementation forms, the data interleaving device further includes an encoder. All of the n data streams are data streams obtained by first FEC encoding. After L second symbol sets are obtained by separately interleaving the L first symbol sets, the encoder is configured to perform second FEC encoding on r second symbol subsets in each second symbol set to obtain L*r codewords.

[0103] In this embodiment of the present application, all of the n data streams are codewords obtained by outer code encoding. After the n data streams are separately delayed, data interleaving is further performed on the n delayed data streams. According to the delay processing solution provided in this application, the n symbols output from the n delayed data streams at the same moment can be from a plurality of different outer codewords by using low latency. This helps to reduce the data interleaving latency while ensuring good performance. In other words, the solution combining the delay processing and data interleaving in this application uses low overall latency and is applicable to application scenarios that require low latency.

Brief Description of the Drawings

[0104]

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Figure 32

Embodiments for Carrying Out the Invention

[0105] Embodiments of this application provide a data interleaving method and a data interleaving apparatus. It should be noted that in the specification, claims, and the foregoing accompanying drawings of this application, the terms "first" and "second" are intended to distinguish similar objects, but do not limit a specific order or sequence. The foregoing terms are interchangeable when appropriate. Therefore, it should be understood that the embodiments described in this application can be implemented in an order other than the content described in this application. In addition, "include", "have", and any other variations thereof are intended to include non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units is not necessarily limited to the explicitly listed steps or units, and may include other steps or units not explicitly listed or specific to the process, method, product, or device.

[0106] FIG. 1 is a schematic diagram of a communication system to which the embodiments of this application are applied. As shown in FIG. 1, the communication system includes a transmitting device 01, a transmitting-side processing module 02, a channel transmission medium 03, a receiving-side processing module 04, and a receiving device 05. For example, the communication system is a data center network. The transmitting device 01 and the receiving device 05 may be devices such as switches or routers. The transmitting device 01 is also called a host chip located on the transmitting side, the receiving device 05 is also called a host chip located on the receiving side, and the channel transmission medium 03 may be an optical fiber. The transmitting device 01 may be connected to the transmitting-side processing module 02 via an attachment unit interface (AUI), and the receiving device 05 may be connected to the receiving-side processing module 04 via the AUI. The transmitting-side processing module 02 and the receiving-side processing module 04 may be optical modules, electrical modules, or other modules that process data in the data transmission process. For example, the processing module may be an 800LR module (the 800LR module is a coherent optical module). Further, the transmitting device 01, the transmitting-side processing module 02, the channel transmission medium 03, the receiving-side processing module 04, and the receiving device 05 in the communication system may all support two-way transmission or may support one-way transmission. This is not specifically limited in this specification.

[0107] Figure 2 is a schematic diagram of the data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from the transmitting device 01 to the receiving device 05, the transmitting device 01 is configured to perform outer code encoding on the data and then transmit the data obtained by the outer code encoding to the transmitting side processing module 02. The transmitting side processing module 02 is configured to perform inner code encoding on the data obtained by the outer code encoding, obtain the data obtained by the outer code encoding and the inner code encoding, and transmit the data obtained by the outer code encoding and the inner code encoding to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the data obtained by the outer code encoding and the inner code encoding to the receiving side processing module 04. The receiving side processing module 04 is configured to perform inner code decoding on the data obtained by the outer code encoding and the inner code encoding and transmit the data obtained by the inner code decoding to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the data obtained by the inner code decoding.

[0108] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance between the execution entity that performs operations on the data and the channel transmission medium 03. The execution entity that performs operations on the inner code is close to the channel transmission medium, and the execution entity that performs operations on the outer code is far from the channel transmission medium. In this embodiment of this application, after being transmitted from the transmission-side device 01, the data is transmitted to the channel transmission medium 03 via the transmission-side processing module 02, and then transmitted from the channel transmission medium 03 to the reception-side device 05 via the reception-side processing module 04. The data encoded by the transmission-side device 01 is farther from the channel transmission medium 03 than the data encoded by the transmission-side processing module 02, and the data decoded by the reception-side device 05 is farther from the channel transmission medium 03 than the data decoded by the reception-side processing module 04. Therefore, the data encoded by the transmission-side device 01 is called the data obtained by outer code encoding, the data encoded by the transmission-side processing module 02 is called the data obtained by inner code encoding, the data decoded by the reception-side device 05 is called the data obtained by outer code decoding, and the data decoded by the reception-side processing module 04 is called the data obtained by inner code decoding. In an imaginable implementation form, in order to form a cascade FEC transmission solution, the FEC encoding method is used for both inner code encoding and outer code encoding. For example, the transmission-side device 01 may perform outer code encoding using the RS code, and the transmission-side processing module 02 may perform inner code encoding using the Hamming code.

[0109] The foregoing content is an example of an application scenario of the data interleaving method provided in the embodiments of this application, and it should be noted that it does not constitute a limitation on the application scenarios of the data interleaving method. Those skilled in the art can know that as the service requirements change, the application scenarios of the data interleaving method can be adjusted based on the application requirements. In the embodiments of this application, the application scenarios are not enumerated one by one.

[0110] In the foregoing transmission solution where cascaded FEC is used, in this application, since a data interleaving solution including "delay" and "interleaving" is designed, the entire cascaded FEC solution has good performance and low latency. In this way, the cascaded FEC transmission solution can be applied to a large number of transmission scenarios, and is particularly applicable to transmission scenarios that require low transmission latency, such as low-latency data center interconnection scenarios. Data interleaving is implemented using the transmission-side processing module 02.

[0111] FIG. 3(a) is a schematic data processing diagram of a transmission-side processing module according to an embodiment of this application. As shown in FIG. 3(a), after the Physical Medium Attachment (PMA) sublayer of the transmission-side processing module performs de-muxing processing on data from a plurality of synchronized client lanes, n Physical Coding Sublayer (PCS) or FEC lane data streams obtained by outer coding may be obtained. The n aligned lane data streams are obtained by performing alignment lock and lane de-skew processing. Then, based on the alignment marker, lane reorder is performed on the data of the n lanes, so that the data of the n lanes can be arranged in the specified order. The n lane data streams obtained by lane reorder are sent to a designed delay and interleaving processor for interleaving with the defective data, and then sent to an inner encoder for inner coding. After data processing is performed on the data stream obtained by inner coding, the data stream obtained by data processing is sent to and transmitted by a channel transmission medium. The data processing may include modulation mapping, channel interleaving, polarization distribution, DSP framing, etc. In this specification, n is a positive integer greater than 1.

[0112] Figure 3(b) is another schematic data processing diagram of the transmission-side processing module according to an embodiment of this application. As shown in Figure 3(b), alignment lock and lane deskew processing are performed on n PCS or FEC lane data streams from the PMA sublayer to obtain n aligned lane data streams. The n lane data streams are directly sent to a delay and interleaving processor designed to interleave with the fault data, and then sent to an inner encoder for inner coding.

[0113] In some actual scenarios, the lane deskew processing module uses First Input First Output (FIFO) to buffer the data. Considering the case where the delay line in the designed delay processing is implemented using a memory element, in order to reduce the complexity and power consumption of the hardware implementation form, the lane deskew processing and the delay processing can be implemented together. As a result, a set of FIFOs is used to implement both the deskew processing and the delay processing.

[0114] Figure 3(c) is yet another schematic data processing diagram of the transmission-side processing module according to an embodiment of this application. As shown in Figure 3(c), for n PCS or FEC lane data streams from the PMA sublayer, alignment lock is first performed, lane deskew processing and designed delay processing are performed based on the lane alignment marker, then lane rearrangement is performed based on the lane alignment marker, and designed interleaving processing is performed. The data ordered by interleaving is sent to an inner encoder for inner coding.

[0115] FIG. 3(d) is yet another schematic data processing diagram of a transmission-side processing module according to an embodiment of this application. As shown in FIG. 3(d), for n PCS or FEC lane data streams from the PMA sublayer, alignment locking is first performed, lane de-skew processing and design delay processing are performed based on lane alignment markers, and then design interleaving processing is performed. The data ordered by interleaving is transmitted to an inner encoder for inner coding.

[0116] FIG. 4(a) is a schematic data processing diagram of a reception-side processing module according to an embodiment of this application. As shown in FIG. 4(a), the reception-side processing module receives a data stream from a channel transmission medium. When the data stream of the transmission-side processing module is obtained by data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the reception-side processing module first performs corresponding inverse data processing on the data stream, and then transmits the processed data stream to an inner decoder for decoding. The data stream obtained by inner decoding is sent to a de-interleaving and inverse delay processor for processing to obtain n lane data streams, and then the n lane data streams are sent to the PMA sublayer. The PMA sublayer multiplexes the data stream and transmits the multiplexed data stream to the reception-side device for outer decoding. The de-interleaving and inverse delay processing in the reception-side processing module are inverse operations of the interleaving and delay processing in the transmission-side processing module. De-interleaving is the inverse operation of interleaving in the transmission-side processing module, and inverse delay is the inverse operation of delay in the transmission-side processing module.

[0117] Figure 4(b) is another schematic data processing diagram of the receiving - side processing module according to an embodiment of this application. As shown in Figure 4(b), the receiving - side processing module receives a data stream from the channel transmission medium. After de - interleaving processing is performed on the data stream obtained by inner - code decoding, n lane data streams are obtained and sent to the PMA sub - layer. In this specification, the de - interleaving processing in the receiving - side processing module is the reverse operation of the interleaving processing in the transmitting - side processing module. In the data processing procedure shown in Figure 4(b), no reverse - delay processing is performed on the n lane data streams obtained by performing de - interleaving processing on the data stream obtained by inner - code decoding, and it should be understood that the n lane data streams are directly sent to the PMA sub - layer. In other words, the n lane data streams sent to the PMA sub - layer are not aligned and there is a delay between the lane data streams. The PMA sub - layer multiplexes the n lane data streams and sends the processed data stream to the receiving - side device. Compared with the data processing shown in Figure 4(a), the data processing shown in Figure 4(b) has lower power consumption and lower hardware implementation complexity.

[0118] Hereinafter, the delay and interleaving processing in the transmitting - side processing module will be described in detail. Those skilled in the art can know that the de - interleaving and reverse - delay processing of the receiving - side processing module are the inverse operations of the delay and interleaving processing in the transmitting - side processing module, and the details will not be described again in this specification.

[0119] First, several specific scenarios to which the embodiments of this application can be applied will be provided below.

[0120] FIG. 5 is a schematic diagram of 32 PCS lane data streams of a 1*800G interface used by a transmitting device. As shown in FIG. 5, the transmitting device performs KP4RS(544, 514) outer code encoding on one transmit channel of the 800GE service data stream to obtain 32 PCS lane data streams. In PCS lane data streams 0 to 15, each data stream is separated by 68 symbols, that is, each data stream has 68 consecutive symbols, and there are a total of 16*68 = 1088 symbols including two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. Similarly, in PCS lane data streams 16 to 31, each data stream is separated by 68 symbols, and there are a total of 16*68 = 1088 symbols including two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. The 32 PCS lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface 800GAUI-8.

[0121] Based on the schematic data processing diagrams of the transmission-side processing module shown in FIGS. 3(a) to 3(d), the transmission-side processing module performs alignment lock on the lane data stream by using the known alignment markers of the PCS lanes. The known alignment markers for 32 lanes are different (see Ethernet Technology Consortium 800G Specification). Next, the transmission-side processing module performs lane de-skew processing on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers, lane reorder is performed on the data of n = 32 lanes, so that the data of n = 32 lanes can be arranged in a specified order. One order is that the lane data streams are sorted from 0 to 31 from top to bottom, which is the same as FIG. 5.

[0122] FIG. 6 is a schematic diagram of 32 PCS lane data streams of a 2*400G interface used by the transmission-side device. As shown in FIG. 6, the transmission-side device performs KP4RS(544, 514) outer code encoding on two channels through which the 400GE service data stream is transmitted, to obtain a total of 32 PCS lane data streams in two channels, and each channel includes 16 PCS lane data streams. In PCS lane data streams 0 to 15 or PCS lane data streams 16 to 31, each data stream is separated by 68 symbols, and there are a total of 16*68 = 1088 symbols including two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. The 32 PCS lane data streams are processed in the PMA sublayer and then transmitted to the transmission-side processing module via the attachment unit interface 2*400GAUI-4.

[0123] Based on the schematic data processing diagrams of the transmission - side processing module shown in FIGS. 3(a) to 3(d), the transmission - side processing module performs alignment lock on 16 lane data streams using known alignment markers in PCS lanes 0 - 15 or PCS lanes 16 - 31. PCS lanes 0 - 15 can be considered as PCS lanes 0 - 15 of 400G channel 0, and PCS lanes 16 - 31 can be considered as PCS lanes 0 - 15 of 400G channel 1. The known alignment markers of the 16 lanes of 400G channel 0 are the same as those of the 16 lanes of 400G channel 1. Next, the transmission - side processing module performs lane de - skew processing on 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers in PCS lanes 0 - 15 or PCS lanes 16 - 31, lane reorder is performed on the data of 16 lanes, so that the data of 16 lanes can be arranged in a specified order. Finally, the data of 32 lanes can be arranged in a specified order. One order is that the lane data streams are sorted from top to bottom from 0 to 31, which is the same as FIG. 6.

[0124] To obtain 32 aligned lane data streams, the specific implementation form of performing lane de-skew processing on 32 lane data streams by the transmitting-side processing module is that the lane de-skew processing defined in the existing standard (see Clause 120 of IEEE 802.3) is performed on the data of 16 lanes based on known alignment markers from PCS lane 0 to 15 or from PCS lane 16 to 31. As a result, it should be understood that there is no skew or latency between the PCS lane data streams of 400G channel 0 or 400G channel 1. Further, the alignment marker is used to enable the symbol alignment of two channels of the PCS lane data stream. In this case, the PCS lane data stream of channel 0 and the PCS lane data stream of channel 1 may or may not have skew. Considering the case where the RS symbol contains 10 bits, in the aligned PCS lane data stream, the number of skew bits between the PCS lane data stream of channel 0 and the PCS lane data stream of channel 1 is a multiple of 10.

[0125] FIG. 7 is a schematic diagram of 32 PCS lane data streams of a 4*200G interface used by a transmitting device. As shown in FIG. 7, the transmitting device performs KP4RS(544, 514) outer code encoding on four transmitted channels of a 200GE service data stream to obtain a total of 32 PCS lane data streams in four channels, and each channel includes eight PCS lane data streams. In PCS lane data streams 0-7, PCS lane data streams 8-15, PCS lane data streams 16-23, or PCS lane data streams 24-31, each data stream is separated by 136 symbols, and there are a total of 8*136 = 1088 symbols including two RS codewords. Two adjacent symbols within each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. The 32 PCS lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface 4*200GAUI-2.

[0126] Based on the schematic data processing diagrams of the transmission-side processing module shown in FIGS. 3(a) to 3(d), the transmission-side processing module performs alignment lock on eight lane data streams using known alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31 can be considered as PCS lanes 0 to 7 of channels 0, 1, 2, or 3 of 200G respectively. Next, the transmission-side processing module performs lane de-skew processing on 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers in PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31, lane reordering is performed on the data of eight lanes so that the data of eight lanes can be arranged in a specified order. Finally, the data of 32 lanes can be arranged in a specified order. One order is that the lane data streams are sorted from top to bottom from 0 to 31, which is the same as FIG. 7.

[0127] To obtain 32 aligned lane data streams, the specific implementation form in which the transmission-side processing module performs lane deskewing processing on 32 lane data streams is that the lane deskewing processing defined in the existing standard (see IEEE 802.3, Clause 120) is performed on the data of 8 lanes based on known alignment markers of PCS lanes 0 to 7, PCS lanes 8 to 15, PCS lanes 16 to 23, or PCS lanes 24 to 31. Thus, it should be understood that there is no skew or latency between the PCS lane data streams of 200G channels 0, 1, 2, or 3. Further, the alignment marker is used to enable the symbol alignment of the four channels of the PCS lane data stream. In this case, the PCS lane data streams of channels 0, 1, 2, and 3 may or may not have skew. Considering the case where the RS symbol contains 10 bits, in the aligned PCS lane data stream, the number of skew bits between the PCS lane data streams of channels 0, 1, 2, and 3 is a multiple of 10.

[0128] FIG. 8 is a schematic diagram of 32 PCS lane data streams of an 8*100G interface used by a transmitting device. As shown in FIG. 8, the transmitting device performs KP4RS(544, 514) outer code encoding on 8 transmitted channels of a 100GE service data stream to obtain a total of 32 FEC lane data streams in 8 channels, and each channel includes 4 FEC lane data streams. When the "100G RS-FEC-Int" mode in which 2 KP4RS(544, 514) codewords are interleaved is used, in FEC lane data streams 0 to 3, FEC lane data streams 4 to 7, FEC lane data streams 8 to 11, FEC lane data streams 12 to 15, FEC lane data streams 16 to 19, FEC lane data streams 20 to 23, FEC lane data streams 24 to 27, or FEC lane data streams 28 to 31, each data stream is separated by 272 symbols and there are a total of 4*272 = 1088 symbols including 2 RS codewords. Two adjacent symbols within each FEC lane data stream are from different RS codewords, and two symbols at the same position in two adjacent FEC lane data streams are from different RS codewords. The 32 FEC lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface 8*100GAUI-1.

[0129] FIG. 9 is another schematic diagram of 32 PCS lane data streams of an 8*100G interface used by a transmitting device. As shown in FIG. 9, different from the scenario in FIG. 8, in this scenario, the transmitting device uses the "100G RS-FEC" mode. In FEC lane data streams 0-3, FEC lane data streams 4-7, FEC lane data streams 8-11, FEC lane data streams 12-15, FEC lane data streams 16-19, FEC lane data streams 20-23, FEC lane data streams 24-27, or FEC lane data streams 28-31, each data stream is separated by 136 symbols, and there are a total of 4*136 = 544 symbols including one RS codeword. The 32 FEC lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface 8*100G AUI-1.

[0130] Based on the schematic data processing diagrams of the transmission-side processing module shown in FIGS. 3(a) to 3(d), the transmission-side processing module performs alignment lock on four lane data streams using known alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31. FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31 can each be considered as FEC lanes 0 to 3 in 100G channels 0, 1, 2, 3, 4, 5, 6, or 7. Next, the transmission-side processing module performs lane de-skew processing on 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment markers in FEC lanes 0 to 3, FEC lanes 4 to 7, FEC lanes 8 to 11, FEC lanes 12 to 15, FEC lanes 16 to 19, FEC lanes 20 to 23, FEC lanes 24 to 27, or FEC lanes 28 to 31, lane reordering is performed on the data of four lanes so that the data of the four lanes can be arranged in a specified order. Finally, the data of 32 lanes can be arranged in a specified order. One order is that the lane data streams are sorted from top to bottom from 0 to 31, which is the same as that in FIGS. 8 and 9.

[0131] To obtain 32 aligned lane data streams, the specific implementation form in which the transmitting - side processing module performs lane de - skew processing on 32 lane data streams is that the lane de - skew processing defined in the existing standard (refer to IEEE 802.3 Clause 91 or Clause 161) is performed on the data of four lanes based on known alignment markers of FEC lanes 0 - 3, FEC lanes 4 - 7, FEC lanes 8 - 11, FEC lanes 12 - 15, FEC lanes 16 - 19, FEC lanes 20 - 23, FEC lanes 24 - 27, or FEC lanes 28 - 31. It should be understood that there is no skew or latency between the PCS lane data streams of 100G channels 0, 1, 2, 3, 4, 5, 6, or 7. Further, the alignment marker is used to enable the symbol alignment of eight channels of the FEC lane data stream. In this case, the FEC lane data streams of channels 0, 1, 2, 3, 4, 5, 6, and 7 may or may not have skew. Considering the case where an RS symbol contains 10 bits, in the aligned FEC lane data stream, the number of skew bits between the FEC lane data streams of channels 0, 1, 2, 3, 4, 5, 6, and 7 is a multiple of 10.

[0132] In some specific scenarios, an 800G or 1.6T interface is used, and the transmitting device performs KP4RS(544, 514) outer code encoding on the service data stream to be transmitted to obtain n PCS lane data streams. All A outer code words are distributed among the n lane data streams. Specifically, in the n PCS lane data streams, each data stream is separated by B symbols, and there are a total of n*B symbols including A RS code words, where n*B = A*544. The consecutive symbols within each PCS lane data stream are from A different RS code words, and the A symbols at the same position in A consecutive PCS lane data streams are from A different RS code words. The integer A can be 2, 4, etc. The n PCS lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface. Some possible combinations of parameters are as follows: "n = 8, A = 2, B = 136", "n = 16, A = 2, B = 68", "n = 8, A = 4, B = 272", and "n = 16, A = 4, B = 136". Based on the schematic data processing diagram of the transmitting processing module shown in FIG. 3(b), the transmitting processing module performs alignment locking on the n lane data streams using the known alignment markers of the n PCS lanes. Next, the transmitting processing module performs lane de-skew processing on the n lane data streams to obtain n aligned lane data streams.

[0133] FIG. 10 is a schematic flowchart of a data interleaving method according to an embodiment of this application.

[0134] 1001: Individually delay the n data streams based on n delay lines.

[0135] FIG. 11 is a schematic structural diagram of a delay device according to an embodiment of this application for delaying n data streams. As shown in FIG. 11, the delay device includes n delay lines that correspond one-to-one to n data streams. Each data stream is delayed using the corresponding delay line and then transmitted to an interleaver for data interleaving. It should be noted that the delay value in this application is calculated in units of symbols, and a symbol can include one or more bits. The larger the number of symbols included in the delay value of the delay line, the greater the delay (also called latency) by which the data stream is delayed using the delay line. FIG. 12 is a schematic structural diagram of a delay line according to an embodiment of this application. As shown in FIG. 12, the delay line may include Q storage elements D, and each storage element D may store d symbols, where both Q and d are integers. When the delay line does not include a storage element, the delay of the delay line is 0 symbols, that is, it should be understood that the transmission is transparent without delay.

[0136] In this embodiment, it should be noted that n is a positive integer divisible by p, and p is an integer greater than 1. The delay value of each delay line is any delay value within a set of delay values, and the set of delay values includes p delay values. The minimum delay value within the set of delay values is 0, and the difference between two adjacent delay values among the p delay values within the delay values set in ascending order is V symbols, where V = Q * d. The number of delay lines corresponding to each delay value within the set of delay values is n / p, and V is an integer of 34 or more. In some exemplary implementations, V may alternatively be an integer of 68 or more. For example, n = 32, p = 4, the set of delay values includes four delay values: 0, V, 2V, and 3V, the delay value of each delay line can be only one of the four delay values, and the number of delay lines corresponding to each of the four delay values 0, V, 2V, and 3V is 8.

[0137] In some possible implementation forms, before the n data streams are separately delayed based on n delay lines, lane rearrangement is performed on the n data streams to enable the n data streams to be arranged in a preset order. In some other possible implementation forms, after the n data streams are separately delayed based on n delay lines, lane rearrangement is performed on the n data streams to enable the n data streams to be arranged in a preset order. As an example, 32 data streams are used. The 32 data streams can be sorted from 0 to 31 from top to bottom. Of course, it may be simply extended when the data streams are sorted in another order. Specific implementation forms are known to those skilled in the art and will not be described again in detail herein. It should be understood that different delay line distribution rules are correspondingly designed based on different sorts of the n data streams, and the delay can be further reduced as long as the performance is guaranteed. The delay line distribution rules provided in this application will be described in detail subsequently.

[0138] In some possible implementation forms, before the n data streams are separately delayed based on n delay lines, lane despreading processing is further performed on the n data streams to obtain n aligned lane data streams. When the n data streams are multiple channels of a service data stream, the n sampled lane data streams satisfy the following constraints, that is, there is no skew among the multiple lane data streams within each channel of the service data stream, and the lane data streams between the channels of the service data stream are symbol-aligned. In some specific implementation forms, the lane despreading processing module uses a first-in first-out (FIFO) to buffer data. Considering the case where the delay lines in the designed delay processing are implemented using memory elements, in order to reduce the complexity and power consumption of the hardware implementation form, the lane despreading processing and the delay processing can be implemented together, and as a result, a set of FIFOs is used to implement both the despreading processing and the delay processing.

[0139] It should be further noted that the n data streams input to the delay device are all the data streams for which FEC encoding is performed, that is, the aforementioned data streams obtained by outer code encoding. Specifically, the outer code encoding can use the RS code, and the n data streams obtained by the outer code encoding can include multiple RS codewords. In actual applications, another encoding method can be alternatively used to perform the outer code encoding. For the sake of easy explanation, the RS codeword is uniformly used below to represent the codeword generated after the outer code encoding.

[0140] 1002: To obtain L first symbol sets, L*m symbols are obtained from each of the n delayed data streams.

[0141] The interleaver can obtain L*m symbols from each of n delayed data streams and obtain L first symbol sets, where L is an integer greater than or equal to 1 and m is an integer greater than or equal to 1. In other words, each first symbol set contains n*m symbols. The interleaver can obtain n*m symbols each time to obtain the first symbol set, and can repeat obtaining n*m symbols over L times to obtain L first symbol sets. Alternatively, the interleaver may read out L*n*m symbols once to obtain L first symbol sets. It should be understood that L buffers may be arranged in the interleaver and are each configured to store one of the L first symbol sets. Specifically, each first symbol set can include a plurality of first symbol subsets. For example, each first symbol set includes n first symbol subsets, and each first symbol subset includes m symbols arranged in sequence. In another example, each first symbol set includes m first symbol subsets, and each first symbol subset includes n symbols arranged in sequence. For ease of explanation, in the following, an example where each first symbol set includes n first symbol subsets for the purpose of explanation is used. Those skilled in the art can directly derive another description method where the first symbol set includes m first symbol subsets, and the following does not provide a detailed description with reference to another description method. Optionally, the m symbols in the first symbol subset h within the first symbol set are from the delayed data stream h, where 0≦h≦n-1.

[0142] It should be noted that the first symbol subset is a concept simply introduced for ease of explanation. In actual applications, the first symbol set is a whole without division, and each first symbol subset can be considered as one or more symbols selected from the first symbol set.

[0143] In a conceivable implementation form, the first symbol set is presented in the form of a data stream. Specifically, the symbols in the first symbol set are arranged to form a data stream. In another conceivable implementation form, the first symbol set is presented in the form of a symbol matrix. Specifically, the first symbol set is represented as a first symbol matrix, and the first symbol matrix includes symbols of n rows and m columns. The m symbols in each row of the first symbol matrix can be understood as a first symbol subset. In other words, the first symbol matrix is essentially a set of a plurality of symbols, and the introduction of the first symbol matrix is only for the purpose of explanation in another dimension. The symbols in the first symbol subset within the first symbol set may alternatively be simply converted into the symbols of the rows and columns of the first symbol matrix. For ease of explanation, only one form of the first symbol set or the first symbol matrix is used in the following description. Those skilled in the art can directly derive other forms of description based on the aforementioned correspondence between the first symbol set and the first symbol matrix.

[0144] 1003: Interleave L first symbol sets separately to obtain L second symbol sets.

[0145] The interleaver interleaves L first symbol sets separately to obtain L second symbol sets. Each second symbol set may include a plurality of second symbol subsets. For example, each second symbol set includes r second symbol subsets, and each second symbol subset includes c symbols. In another example, each second symbol set includes c second symbol subsets, and each second symbol subset includes r symbols. r is an integer greater than 1, c is an integer greater than 1, and n*m = r*c. Specifically, the number of symbols in the first symbol set is the same as the number of symbols in the second symbol set. For ease of explanation, hereinafter, an example in which each second symbol set includes r second symbol subsets for the purpose of explanation is used. Those skilled in the art can directly derive another description method in which the second symbol set includes c second symbol subsets, and another description method will not be described in detail hereinafter with reference thereto. Specifically, the c symbols in each second symbol subset correspond to c symbols dispersed in c first symbol subsets in the first symbol set. As a result, the c symbols in each second symbol subset are from as many different RS codewords as possible in order to achieve a better data interleaving effect. The data interleaving rules provided in this application will be described in detail hereinafter.

[0146] It should be noted that the second symbol subset is a concept simply introduced for ease of explanation. In actual application, the second symbol set is a whole without division, and each second symbol subset can be considered as one or more symbols selected from the second symbol set.

[0147] In a conceivable implementation form, the second symbol set is presented in the form of a data stream. Specifically, the symbols in the second symbol set are arranged to form a data stream. In another conceivable implementation form, the second symbol set is presented in the form of a symbol matrix. Specifically, the second symbol set is represented as a second symbol matrix, and the second symbol matrix includes r rows and c columns of symbols. The c symbols in each row of the second symbol matrix can be understood as a second symbol subset. The c symbols in each row of the second symbol matrix correspond to the c symbols distributed in the c rows of the first symbol matrix. In other words, the second symbol matrix is essentially a set of a plurality of symbols, and the introduction of the second symbol matrix is only for explanation in another dimension. The symbols in the second symbol subset within the second symbol set may simply be transformed alternatively to the symbols in the rows and columns of the second symbol matrix. For ease of explanation, only one form of the second symbol set or the second symbol matrix is used in the following description. A person skilled in the art can directly derive other forms of explanation based on the foregoing correspondence relationship between the second symbol set and the second symbol matrix.

[0148] It should be noted that after the interleaver interleaves L first symbol sets separately to obtain L second symbol sets, the interleaver outputs the L second symbol sets to the encoding device. Further, the encoding device performs FEC encoding separately on the r second symbol subsets in each second symbol set to obtain L*r codewords, that is, performs the inner code encoding described above. In a conceivable implementation form, the encoding device performs FEC encoding separately on the r second symbol subsets in each of the L second symbol sets by using Hamming codes to obtain L*r Hamming codewords.

[0149] In this embodiment of this application, all of the n data streams are codewords obtained by outer code encoding. After the n data streams are separately delayed, data interleaving is further performed on the n delayed data streams. According to the delay processing solution provided in this application, the n symbols output from the n delayed data streams at the same moment can be from a plurality of different outer codewords by using low latency. This helps to reduce the data interleaving latency while ensuring good performance. In other words, the solution combining the delay processing and data interleaving in this application uses low overall latency and is applicable to application scenarios that require low latency.

[0150] The following describes a specific implementation form for delaying the n data streams provided in this application.

[0151] Note that, for the sake of explanation, an example where n is divisible by 16 and p = 4 is used below. The n delay lines include at least one group, and each group includes 16 adjacent delay lines. In other words, in this application, a group of 16 delay lines is used as the granularity to explain the delay line distribution rule. It should be understood that the data stream corresponds one-to-one to the delay lines, and the order of the n delay lines is consistent with the order of the corresponding n data streams. When the data streams obtained by lane rearrangement are arranged in the order of 0, 1, 2, 3..., the delay lines are also arranged in the order of 0, 1, 2, 3.... When the data streams are arranged in another order, the delay lines are also arranged in the corresponding order. Further, the delay line group k (0 ≦ k < n / 16) includes delay lines 16*k, delay line 16*k + 1,..., and delay line 16*k + 15. There are multiple constraints satisfied by four adjacent delay lines. For example, delay line 16*k and delay line 16*k + 1 satisfy the design constraints, delay line 16*k + 2 and delay line 16*k + 3 satisfy another design constraint, or delay line 16*k and delay line 16*k + 3 satisfy the design constraints, and delay line 16*k + 1 and delay line 16*k + 2 satisfy another design constraint. Considering the non-unique delay line selection order in the description of the delay line rule, in order to facilitate the description of the delay line distribution rule provided in this application, the serial numbers of the 16 delay lines in each group are respectively a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 、and a 15 、and are represented as such, and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 、and a 15 are not equal to each other and are non-negative integers less than 16. In other words, the serial number values of a0~a 15 may correspond one-to-one to 1 to 0 to 15, that is, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} in order. Also, a0~a15 The serial number values do not necessarily sequentially range from 0 to 15, and may be, for example, {0, 3, 1, 2, 4, 7, 5, 6, 8, 11, 9, 10, 12, 15, 13, 14}

[0152] When n is 32 or more, it should be understood that the n delay lines include a plurality of groups, for example, delay line group 0 and delay line group 1. The serial numbers a0 to a of delay line group 0 15 The values are selected from 0 to 15, and the serial numbers a0 to a of delay line group 1 15 The values are selected from 16 to 31, and 16 serial numbers are used as one group. The rest can be estimated by analogy. For ease of explanation, regardless of the specific delay line group, in the following description, the serial numbers a0 to a of the delay line group 15 When the values are selected from 0 to 15 are used for explanation, the actual serial numbers of the delay line group are a0 to a 15 Based on which it is 16*k + each serial number, where 0 ≤ k < n / 16. That is, the serial number values of delay line group k are a0 + 16*k, a1 + 16*k,..., and a 15 + 16*k. In addition, the 16 delay lines in different groups may be numbered in the same order or in different orders. As an example, n = 32 is used. The serial number values a0 to a of the 16 delay lines in group 0 included in the 32 delay line values 15 Are {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, that is, sequentially 0 to 15 for the enemy. The 16 delay lines in group 1 may be numbered in the order of 0 to 15 that coincides with delay line group 0, or in a different order. This is not specifically limited in this specification.

[0153] In an imaginable implementation form, in delay line group k (0 ≤ k < n / 16), delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 , delay line a 11 , delay line a 12, delay line a 13 , delay line a 14 , and delay line a 15 The delay values of satisfy the first condition. Specifically, the first condition is that the difference between the delay value of delay line a0 and the delay value of delay line a1 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a3 is 2V symbols, the difference between the delay value of delay line a4 and the delay value of delay line a5 is 2V symbols the difference between the delay value of delay line a6 and the delay value of delay line a7 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a9 is 2V symbols, delay line a 10 the difference between the delay value of and the delay value of delay line a 11 is 2V symbols, delay line a 12 the difference between the delay value of and the delay value of delay line a 13 is 2V symbols, delay line a 14 the difference between the delay value of and the delay value of delay line a 15 is 2V symbols, That's what it is.

[0154] The client side has an 8*100G interface with each 100Gb / s lane and should note that it uses the "100G RS-FEC" mode. When the above-mentioned first condition is satisfied and V≧68, among the 16 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 32 data streams are delayed, symbol a0 and symbol a1 are from two different RS codeword symbols, symbol a2 and symbol a3 are from two different RS codeword symbols,..., symbol a 14 and symbol a 15It is from two different RS codeword symbols. This delay design aspect is easy to implement and has a short latency to implement the good performance of the cascade FEC solution and shorten the overall latency of the transmission solution, facilitating the subsequent use of the interleaving solution with short latency.

[0155] Based on the above description, in each group of 16 delay lines, the number of delay lines with delay values of 0 symbol, V symbols, 2V symbols, and 3V symbols is all 4.

[0156] Based on the above description, in delay line group k (0 ≦ k < n / 16), the delay values of delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、delay line a 11 、delay line a 12 、delay line a 13 、delay line a 14 、delay line a 15 satisfy the second condition. Specifically, the second condition is that the delay values of delay line a0, delay line a4, delay line a8, and delay line a 12 are not equal to each other, the delay values of delay line a1, delay line a5, delay line a9, and delay line a 13 are not equal to each other, the delay values of delay line a2, delay line a6, delay line a 10 and delay line a 14 are not equal to each other, and the delay values of delay line a3, delay line a7, delay line a 11 and delay line a 15 are not equal to each other.

[0157] It should be noted that the client side has a 1*800G interface or a 2*400G interface with each lane of 100 Gb / s. When the second condition is satisfied and V≥68, among the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 16 data streams are delayed, symbol a0, symbol a4, symbol a8, and symbol a 12 are from four different RS codeword symbols, symbol a1, symbol a5, symbol a9, and symbol a 13 are from four different RS codeword symbols, symbol a2, symbol a6, symbol a 10 , and symbol a 14 are from four different RS codeword symbols, symbol a3, symbol a7, symbol a 11 , and symbol a 15 are from four different RS codeword symbols. This delay design pattern facilitates the subsequent use of an interleaving solution that is easy to implement and has low latency in order to implement good performance of the cascade FEC solution and shorten the overall latency of the transmission solution.

[0158] Based on the above description, the delay values of delay lines a0, a2, a4, a6, a8, a 10 , a 12 , a 14 in delay line group k (0≤k<n / 16) satisfy the third condition. Specifically, the third condition is that the difference between the delay value of delay line a0 and the delay value of delay line a4 is 2V symbols, the difference between the delay value of delay line a2 and the delay value of delay line a6 is 2V symbols, the difference between the delay value of delay line a8 and the delay value of delay line a 12 is 2V symbols, and the difference between the delay value of delay line a 10 and the delay value of delay line a 14 is 2V symbols.

[0159] It should be noted that the client side has a 4 * 200G interface with each lane of 100 Gb / s. When the first and third conditions are met and V ≥ 68, among the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) in the 16 data streams are delayed, symbol a0, symbol a1, symbol a4, and symbol a5 are from four different RS codeword symbols, symbol a2, symbol a3, symbol a6, and symbol a7 are from four different RS codeword symbols, symbol a8, symbol a9, symbol a 12 、and symbol a 13 are from four different RS codeword symbols, symbol a 10 、symbol a 11 、symbol a 14 、and symbol a 15 are from four different RS codeword symbols. This delay design pattern facilitates the subsequent use of an interleaving solution that is easy to implement and has low latency in order to implement good performance of the cascade FEC solution and shorten the overall latency of the transmission solution.

[0160] Based on the foregoing description, the first delay value set {A} sequentially includes the delay values of delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 、delay line a 11 、delay line a 12 、delay line a 13 、delay line a 14 、and delay line a 15 in the delay line group k (0 ≤ k < n / 16), and the first delay value set {A} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of them.

[0161] It should be noted that the client side has a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface (including "100G RS-FEC-Int" and "100G RS-FEC" modes) each with 100 Gb / s lanes. When the aforementioned first set of delay values {A} is satisfied and V ≥ 68, in the 32 symbols output each time after the data streams 0 to 15 (or data streams 16 to 31) among the 16 data streams are delayed, symbol a0, symbol a1, symbol a4, symbol a5, symbol a8, symbol a9, symbol a 12 , and symbol a 13 are from 8 different RS codeword symbols, and symbol a2, symbol a3, symbol a6, symbol a7, symbol a 10 , symbol a 11 , symbol a 14 , and symbol a 15It is from 8 different RS codeword symbols. This delay design pattern facilitates the subsequent use of an interleaving solution that is easy to implement and has low latency in order to implement the good performance of the cascade FEC solution and shorten the overall latency of the transmission solution.

[0162] Based on the foregoing description, in delay line group k (0 ≦ k < n / 16), the delay values of delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , a 15 satisfy the fourth condition. Specifically, the fourth condition is that the delay value of delay line a0 and the delay value of delay line a2 are equal or have a difference of 2V symbols, the delay value of delay line a1 and the delay value of delay line a3 are equal or have a difference of 2V symbols, the delay value of delay line a2 and the delay value of delay line a4 are equal or have a difference of 2V symbols, the delay value of delay line a3 and the delay value of delay line a5 are equal or have a difference of 2V symbols, the delay value of delay line a4 and the delay value of delay line a6 are equal or have a difference of 2V symbols, the delay value of delay line a5 and the delay value of delay line a7 are equal or have a difference of 2V symbols, the delay value of delay line a8 and the delay value of a 10 are equal or have a difference of 2V symbols, the delay value of delay line a9 and the delay value of a 11 are equal or have a difference of 2V symbols, the delay value of a 10 and the delay value of a 12 are equal or have a difference of 2V symbols, the delay value of a 11 and the delay value of a 13 are equal or have a difference of 2V symbols, the delay value of a12 The delay value of 12 and delay line a 14 are equal or have a difference of 2V symbols, Delay line a 13 The delay value of 13 and delay line a 15 are equal or have a difference of 2V symbols, This is the case.

[0163] Based on the first set of delay values {A} and the fourth condition, the second set of delay values {B} is for delay lines a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , and delay line a 15 sequentially includes the delay values, and the second set of delay values {B} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V}, {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V}, {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V}, {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V}, {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V}, {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V}, {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} includes one of the following.

[0164] Based on the above description, the serial number value set {C} of the delay line sequentially includes the values of a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15 , and the serial number value set {C} is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 12, 13}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 12, 13, 14, 15}, {0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 8, 9, 14, 15, 12, 13}, {0, 1, 2, 3, 6, 7, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15}, {0, 1, 2, 3, 6, 7, 4, 5, 8, 9, 10, 11, 14, 15, 12, 13}, {0, 1, 2, 3, 6, 7, 4, 5, 10, 11, 8, 9, 12, 13, 14, 15}, {0, 1, 2, 3, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13}, {2, 3, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}, {2, 3, 0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 12, 13}, {2、3、0、1、4、5、6、7、10、11、8、9、12、13、14、15}、 {2、3、0、1、4、5、6、7、10、11、8、9、14、15、12、13}、 {2、3、0、1、6、7、4、5、8、9、10、11、12、13、14、15}、 {2、3、0、1、6、7、4、5、8、9、10、11、14、15、12、13}、 {2、3、0、1、6、7、4、5、10、11、8、9、12、13、14、15}、 {2、3、0、1、6、7、4、5、10、11、8、9、14、15、12、13}、 {0、3、1、2、4、7、5、6、8、11、9、10、12、15、13、14}、 {0、3、1、2、4、7、5、6、8、11、9、10、13、14、12、15}、 {0、3、1、2、4、7、5、6、9、10、8、11、12、15、13、14}、 {0、3、1、2、4、7、5、6、9、10、8、11、13、14、12、15}、 {0、3、1、2、5、6、4、7、8、11、9、10、12、15、13、14}、 {0、3、1、2、5、6、4、7、8、11、9、10、13、14、12、15}、 {0、3、1、2、5、6、4、7、9、10、8、11、12、15、13、14}、 {0、3、1、2、5、6、4、7、9、10、8、11、13、14、12、15}、 {1、2、0、3、4、7、5、6、8、11、9、10、12、15、13、14}、 {1、2、0、3、4、7、5、6、8、11、9、10、13、14、12、15}、 {1、2、0、3、4、7、5、6、9、10、8、11、12、15、13、14}、 {1、2、0、3、4、7、5、6、9、10、8、11、13、14、12、15}、 {1、2、0、3、5、6、4、7、8、11、9、10、12、15、13、14}、 {1, 2, 0, 3, 5, 6, 4, 7, 8, 11, 9, 10, 13, 14, 12, 15}, {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 12, 15, 13, 14}, and {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 13, 14, 12, 15} includes one of the following.

[0165] In the following, some specific data interleaving implementations provided in this application will be described.

[0166] It should be noted that the following implementations are described using the example of n = 32. The first symbol set includes 32 first symbol subsets. The n delay lines include two groups, namely, delay line group 0 and delay line group 1. Specifically, the sequential number values of the 32 first symbol subsets are b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 , b 12 , b 13 , b 14 , b 15 , b 16 , b 17 , b 18 , b 19 , b 20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 10 10 , b 11 , b 12 , b 13 , b 14 , and b 15 are respectively the sequential number values a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10 、 a 11 、 a 12 、 a 13 、 a 14 、 and a 15 are equal to b in order. 16 、 b 17 、 b 18 、 b 19 、 b 20 、 b 21 、 b 22 、 b 23 、 b 24 、 b 25 、 b 26 、 b 27 、 b 28 、 b 29 、 b 30 、 and b 31 are respectively equal to the delay line serial numbers a0 + 16, a1 + 16, a2 + 16, a3 + 16, a4 + 16, a5 + 16, a6 + 16, a7 + 16, a8 + 16, a9 + 16, a 10 + 16, a 11 + 16, a 12 + 16, a 13 + 16, a 14 + 16, and a 15 + 16 in order. The delay line serial numbers a0~a of delay line group 0 15 and the delay line serial numbers a0~a of delay line group 1 15 can both be any one within the above-mentioned serial number set {C}, and it should be understood that the delay line serial numbers a0~a of delay line group 0 15 and the delay line serial numbers a0~a of delay line group 1 15 may be the same or different.

[0167] It should be noted that the client side has a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with each lane of 100Gb / s (including "100G RS-FEC-Int" and "100G RS-FEC" modes). When the aforementioned first set of delay values {A} is satisfied and V≧68, among the 32 symbols output each time after 32 data streams are delayed, symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , and symbol b 16 ; and symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 (or symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , symbol b 31 ) are from 16 different RS codeword symbols. Among the 32 symbols, symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , and symbol b 16 ; and symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , and symbol b 29 (or symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b26 , symbol b 27 , symbol b 30 , symbol b 31 ) is from 16 different RS codeword symbols. This delay design pattern facilitates the subsequent use of an interleaving solution that is easy to implement and has low latency in order to implement the good performance of the cascade FEC solution and shorten the overall latency of the transmission solution.

[0168] The first data interleaving implementation form: n = 32, m = 1, c = 8, and r = 4. Specifically, each first symbol set includes 32 first symbol subsets, and each first symbol subset includes 1 symbol. Each second symbol set includes 4 second symbol subsets, and each second symbol subset includes 8 symbols.

[0169] The 8 symbols in each second symbol subset satisfy the fifth condition. Specifically, the fifth condition is the following condition, that is, the 8 symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and the first symbol subset b 13 in the first symbol set, the 8 symbols in each second symbol subset are respectively from the first symbol subsets b2, b3, b6, b7, b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 in the first symbol set, the 8 symbols in each second symbol subset are respectively from the first symbol subset b16 1. The first symbol subset b 17 1. The first symbol subset b 20 1. The first symbol subset b 21 1. The first symbol subset b 24 1. The first symbol subset b 25 1. The first symbol subset b 28 1. And the first symbol subset b 29 from, Each of the 8 symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 18 1. The first symbol subset b 19 1. The first symbol subset b 22 1. The first symbol subset b 23 1. The first symbol subset b 26 1. The first symbol subset b 27 1. The first symbol subset b 30 1. And the first symbol subset b 31 from, Each of the 4 symbols in each second symbol subset is respectively the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b in the first symbol set 12 1. And the first symbol subset b 13 from the 4 first symbol subsets in, and each of the other 4 symbols in each second symbol subset is respectively the first symbol subset b in the first symbol set 16 1. The first symbol subset b 17 1. The first symbol subset b 20 1. The first symbol subset b 21 1. The first symbol subset b 24 1. The first symbol subset b 25 1. The first symbol subset b 28 1. And the first symbol subset b 29from four first symbol subsets in each of the four symbols in each second symbol subset is respectively from the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12 , and the first symbol subset b 13 from four first symbol subsets in 18 , and each of the other four symbols in each second symbol subset is respectively from the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from four first symbol subsets in each of the four symbols in each second symbol subset is respectively from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from four first symbol subsets in 16 , and each of the other four symbols in each second symbol subset is respectively from the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b25 , the first symbol subset b 28 , and from four first symbol subsets in the first symbol subset b 29 , and each of the four symbols in each second symbol subset is from the first symbol subsets b2, b3, b6, b7, b in the first symbol set, and 10 , the first symbol subset b 11 , the first symbol subset b 14 , and from four first symbol subsets in the first symbol subset b 15 , and each of the other four symbols in each second symbol subset is from the first symbol subset b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and from four first symbol subsets in the first symbol subset b 31 , and is from four first symbol subsets in b , and includes any one of them.

[0170] In an imaginable implementation form, the symbol j in the second symbol subset i in the second symbol set is from the first symbol subset b x in the first symbol set, where x = i + j * 4, 0 ≦ i < 4, and 0 ≦ j < 8. Specifically, the second symbol set shown in Table 1 can be obtained according to the data interleaving rule, and each row represents one second symbol subset. As shown in Table 1, the number x in row i and column j is such that the symbol j in the second symbol subset i in the second symbol set obtained by interleaving is from the first symbol subset bx It indicates that it is from the symbols inside. It should be noted that the transposition of the positions of any two rows in Table 1 also belongs to the data interleaving rules provided in this application, and the transposition of the 8-digit positions of each row in Table 1 also belongs to the data interleaving rules provided in this application.

[0171]

Table 1

[0172] In another possible implementation form, the symbol j in the second symbol subset i within the second symbol set is from the first symbol subset b within the first symbol set x and

Number

Number

[0173]

Table 2

[0174] Second data interleaving implementation form: n = 32, m = 1, c = 16, and r = 2. Specifically, each first symbol set includes 32 first symbol subsets, and each first symbol subset includes one symbol. Each second symbol set includes two second symbol subsets, and each second symbol subset includes 16 symbols.

[0175] The 16 symbols in each second symbol subset satisfy the sixth condition. Specifically, the sixth condition is the following condition, that is, Eight symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13 in the first symbol set, and the other eight symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b 20 , b 21 , b 24 , b 25 , b 28 , and b 29 in the first symbol set, and Eight symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13from and each of the other eight symbols in each second symbol subset is from the first symbol subset b in the first symbol set 18 the first symbol subset b 19 the first symbol subset b 22 the first symbol subset b 23 the first symbol subset b 26 the first symbol subset b 27 the first symbol subset b 30 and the first symbol subset b 31 from and each of the eight symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 the first symbol subset b 11 the first symbol subset b 14 and the first symbol subset b 15 from and each of the other eight symbols in each second symbol subset is from the first symbol subset b in the first symbol set 16 the first symbol subset b 17 the first symbol subset b 20 the first symbol subset b 21 the first symbol subset b 24 the first symbol subset b 25 the first symbol subset b 28 and the first symbol subset b 29 from and and each of the eight symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b in the first symbol set 10 the first symbol subset b 11 the first symbol subset b 14 and the first symbol subset b15 from, and each of the other 8 symbols in each second symbol subset is the first symbol subset b in the first symbol set 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from, includes any one of them.

[0176] In an imaginable implementation form, the symbol j in the second symbol subset i in the second symbol set is the first symbol subset b in the first symbol set x from,

Number

Number

[0177]

Table 3

[0178] In another possible implementation, the symbol j in the second symbol subset i within the second symbol set is from the first symbol subset b within the first symbol set x and

Number

Number

[0179]

Table 4

[0180] In another possible implementation, the symbol j in the second symbol subset i within the second symbol set is from the first symbol subset b x and

Number

Number

[0181]

Table 5

[0182] The third data interleaving implementation form: n = 32, m = 3, c = 12, and r = 8. Specifically, each first symbol set includes 32 first symbol subsets, and each first symbol subset includes 3 symbols. Each second symbol set includes 8 second symbol subsets, and each second symbol subset includes 12 symbols.

[0183] The 12 symbols within each second symbol subset satisfy the seventh condition. Specifically, the seventh condition is the following condition, that is, Each of the 8 symbols within each second symbol subset is respectively the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b 12, and the first symbol subset b 13 from, and the other four symbols in each second symbol subset are respectively the first symbol subset b in the first symbol set 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from the four first symbol subsets within, each of the six symbols in each second symbol subset is respectively the first symbol subset b0, the first symbol subset b1, the first symbol subset b4, the first symbol subset b5, the first symbol subset b8, the first symbol subset b9, the first symbol subset b in the first symbol set 12 , and the first symbol subset b 13 from the six first symbol subsets in, and the other six symbols in each second symbol subset are respectively the first symbol subset b in the first symbol set 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from the six first symbol subsets within, The four symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13 of the four first symbol subsets in, and the other eight symbols in each second symbol subset are respectively from the first symbol subsets b 16 , b 17 , b 20 , b 21 , b 24 , b 25 , b 28 , and b 29 in the first symbol set, The eight symbols in each second symbol subset are respectively from the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 , and b 13 in the first symbol set, and the other four symbols in each second symbol subset are respectively from the first symbol subsets b 18 , b 19 , b 22 , b 23 , b 26 , b 27 , b 30 , and b 31 of the four first symbol subsets in, Each of the six symbols in each second symbol subset is from one of the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 13 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 18 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 19 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 22 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 23 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 26 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 27 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 30 in the first symbol set, and each of the other six symbols in each second symbol subset is from one of the first symbol subsets b 31 in the first symbol set, and each of the four symbols in each second symbol subset is from one of the first symbol subsets b0, b1, b4, b5, b8, b9, b 12 in the first symbol set, and each of the other four symbols in each second symbol subset is from one of the first symbol subsets b 13 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 18 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 19 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 22 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 23 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 26 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 27 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b 30 in the first symbol set, and each of the other eight symbols in each second symbol subset is from one of the first symbol subsets b31 from each of the 8 symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from, and each of the other 4 symbols in each second symbol subset is from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and the first symbol subset b 29 from the 4 first symbol subsets in, each of the 6 symbols in each second symbol subset is from the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from the 6 first symbol subsets in, and each of the other 6 symbols in each second symbol subset is from the first symbol subset b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b25 , the first symbol subset b 28 , and from six first symbol subsets within the first symbol subset b 29 , and each of the four symbols in each second symbol subset is respectively from the first symbol subsets b2, b3, b6, b7, b within the first symbol set, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and from four first symbol subsets within the first symbol subset b 15 , and each of the other eight symbols in each second symbol subset is respectively from the first symbol subsets b 16 , the first symbol subset b 17 , the first symbol subset b 20 , the first symbol subset b 21 , the first symbol subset b 24 , the first symbol subset b 25 , the first symbol subset b 28 , and from the first symbol subsets b 29 and each of the eight symbols in each second symbol subset is respectively from the first symbol subsets b2, b3, b6, b7, b within the first symbol set, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and from the first symbol subsets b 15 and each of the other four symbols in each second symbol subset is respectively from the first symbol subsets b 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from four first symbol subsets in Each of the six symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15 from six first symbol subsets in 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from six first symbol subsets in Each of the four symbols in each second symbol subset is respectively the first symbol subset b2, the first symbol subset b3, the first symbol subset b6, the first symbol subset b7, the first symbol subset b 10 , the first symbol subset b 11 , the first symbol subset b 14 , and the first symbol subset b 15from four first symbol subsets in, and each of the other eight symbols in each second symbol subset is the first symbol subset b in the first symbol set 18 , the first symbol subset b 19 , the first symbol subset b 22 , the first symbol subset b 23 , the first symbol subset b 26 , the first symbol subset b 27 , the first symbol subset b 30 , and the first symbol subset b 31 from, includes any one of them.

[0184] In an imaginable implementation form, the symbol j in the second symbol subset i in the second symbol set is the first symbol subset b in the first symbol set x%32 in the symbol

Number

Number

Number

Number

[0185]

Table 6

[0186] In another possible implementation, the symbol j in the second symbol subset i within the second symbol set is the symbol within the first symbol subset b within the first symbol set x%32 within

Number

Number

Number

Number

[0187]

Table 7

[0188] In another possible implementation, the 12 symbols in each second symbol subset satisfy an eighth condition, and the eighth condition is that 4 symbols in each second symbol subset are respectively from symbol 0 in the first symbol subset k1 in the first symbol set, symbol 0 in the first symbol subset k1 + 8 in the first symbol set, symbol 0 in the first symbol subset k1 + 16 in the first symbol set, and symbol 0 in the first symbol subset k1 + 24 in the first symbol set, and the other 4 symbols in each second symbol subset are respectively from symbol 1 in the first symbol subset k2 in the first symbol set, symbol 1 in the first symbol subset k2 + 8 in the first symbol set, symbol 1 in the first symbol subset k2 + 16 in the first symbol set, and symbol 1 in the first symbol subset k2 + 24 in the first symbol set, and the other 4 symbols in each second symbol subset are respectively from symbol 2 in the first symbol subset k3 in the first symbol set, symbol 2 in the first symbol subset k3 + 8 in the first symbol set, symbol 2 in the first symbol subset k3 + 16 in the first symbol set, and symbol 2 in the first symbol subset k3 + 24 in the first symbol set, where k1, k2, and k3 are not equal to each other, and the delay values of delay line 16k1 + z1 and delay line 16k1 + z1 + 2 in the n delay lines are equal or have a difference of 2V symbols.

[0189] The symbol j of the second symbol subset i of the second symbol set is from the symbol x%32 of the first symbol subset b

Number

Number

Number

Number

[0190]

Table 8

[0191] The following provides some specific embodiments for explaining the complete procedure of the data interleaving method shown in FIG. 10.

[0192] Embodiment 1: n = 32, the 32 delay lines include two groups, and each group includes 16 delay lines. The consecutive number values a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 , a 11 , a 12 , a 13 , a 14 , and a 15is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}. The 32 first symbol subsets b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 , b 11 , b 12 , b 13 , b 14 , b 15 , b 16 , b 17 , b 18 , b 19 , b 20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 have sequential number values of {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}.

[0193] Figures 13A and 13B are schematic distribution diagrams of 32 delay lines according to an embodiment of this application. As shown in Figures 13A and 13B, the 32 data streams respectively correspond to 32 delay lines, and the delay lines may each include 0, Q, 2Q, or 3Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, or 3V symbols, where V = Q * d. In each group of 16 delay lines, delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , delay line a 15The delay values are {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, 3V, V, 3V, V}. Correspondingly, the number of delay symbols of delay lines 0 to 31 are respectively {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}. Specifically, the delay element outputs d symbols from the memory element at the right end of each delay line, and 32 * d symbols are obtained. Correspondingly, the symbols stored in the memory element in each delay line are shifted d symbols to the right. Also, d symbols are obtained from each of the 32 data streams and are separately written into the memory elements at the left ends of the 32 delay lines. When the delay line includes 0 memory elements (for example, delay lines 0, 2, 5, 7, 16, 18, 21, and 23 in FIGS. 13A and 13B), it should be understood that the d symbols output from the delay line are the d symbols obtained from the corresponding PCS or FEC lane data stream by the current operation. It should be understood that d symbols are output from each delay line in one delay operation. When d ≤ L * m, φ delay operations can be repeatedly performed to obtain φ * d symbols, where φ * d ≥ L * m and φ is a positive integer.

[0194] The interleaver obtains L * m symbols from each of the 32 delayed data streams to obtain L first symbol sets. Each first symbol set includes 32 first symbol subsets, and each first symbol subset includes m symbols. The m symbols in the first symbol subset h (0 ≤ h < 32) of each first symbol set are from the delayed data stream h. The interleaver separately interleaves the L first symbol sets to obtain L second symbol sets, and the second symbol sets include r * c symbols. Each second symbol set includes r second symbol subsets, and each second symbol subset includes c symbols, and 32 * m = r * c.

[0195] The first symbol set may alternatively be a symbol matrix including 32 rows by m columns of symbols, which should be noted is called the first symbol matrix. The second symbol set may alternatively be a symbol matrix including r rows and c columns of symbols, which is called the second symbol matrix. In this case, the L*m symbols obtained from the delay data stream h are respectively sent to the columns m of the rows h of the L first symbol matrices. The m symbols within each row h of the first symbol matrices are from the delay data stream h. The interleaver interleaves 32*m symbols in each of the L first symbol matrices to obtain L second symbol matrices, and the second symbol matrices include r rows and c columns of symbols.

[0196] FIG. 14 is a schematic diagram of interleaving L first symbol matrices according to an embodiment of this application. As shown in FIG. 14, in an imaginable implementation form, the interleaver includes L interleaving sub-units, and the L interleaving sub-units respectively interleave the L first symbol matrices to obtain L second symbol matrices. Specifically, the data division unit

Number

[0197] In one example, the first symbol matrix includes symbols of 32 rows and 1 column, the second symbol matrix includes symbols of 2 rows and 16 columns, and L = 1, Q = 68, d = 1. Specifically, the interleaver obtains 1 symbol from each of the 32 delay data streams, each memory element D in the delay line stores d = 1 symbol, and each symbol includes 10 bits. V = Q*d = 68, and the delay value of each delay line is 0 symbol, 68 symbols, 136 symbols, or 204 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 9.

[0198] [Table 9]

[0199] The symbol in the i-th row and j-th column (0 ≦ i < 2, 0 ≦ j < 16) of the second symbol matrix is from the symbol in the b x =x-th row of the first symbol matrix, and is a non-negative integer

Number

Number

[0200]

Table 10

[0201] The above example provides an implementation form with L = 1. Based on this, the implementation form with L > 1 can be further extended. This is an extension of the application scenario. For specific implementation forms, please refer to the above description. Details will not be described again in this specification. Several typical parameter combinations are provided below.

[0202] L = 2, d = 2, Q = 34, and V = Q * d = 68. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 2, and inner code encoding is performed to obtain 2 * L = 4 codewords.

[0203] L = 3, d = 3, Q = 24, and V = Q * d = 72. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 3, and inner code encoding is performed to obtain 2 * L = 6 codewords.

[0204] L = 4, d = 4, Q = 17, and V = Q * d = 68. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 4, and inner code encoding is performed to obtain 2 * L = 8 codewords.

[0205] L = 5, d = 5, Q = 14, and V = Q * d = 70. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 5, and inner code encoding is performed to obtain 2 * L = 10 codewords.

[0206] L = 6, d = 6, Q = 12, and V = Q * d = 72. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 6, and inner code encoding is performed to obtain 2 * L = 12 codewords.

[0207] L = 8, d = 8, Q = 9, and V = Q * d = 72. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 8, and inner code encoding is performed to obtain 2 * L = 16 codewords.

[0208] L = 12, d = 12, Q = 6, and V = Q * d = 72. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 12, and inner code encoding is performed to obtain 2 * L = 24 codewords.

[0209] L = 16, d = 16, Q = 5, and V = Q * d = 80. The interleaver outputs L matrices of 2 * 16 second symbol matrices, where L = 16, and inner code encoding is performed to obtain 2 * L = 32 codewords.

[0210] Hereinafter, L = 5 is used as an example for explanation. The first symbol matrix contains symbols in 32 rows and 1 column, and the second symbol matrix contains symbols in 2 rows and 16 columns. The interleaver can use the structure shown in FIG. 14. Specifically, the interleaver includes 5 interleaving sub-units. Each memory element D in the delay line can store d = 5 symbols. Each symbol contains 10 bits, and the delay value of each delay line is 0 symbols, 70 symbols, 140 symbols, or 210 symbols. Specifically, the delay values of 32 delay lines can be shown in Table 11.

[0211]

Table 11

[0212] FIG. 15 is a schematic diagram of data interleaving in a scenario where L = 5 according to an embodiment of this application. Based on the interleaving rule provided in the scenario where L = 1, specifically, the symbol in the i-th row and j-th column (0 ≤ i < 2, 0 ≤ j < 16) of the second symbol matrix is from the symbol in the b x = x-th row of the first symbol matrix, and a non-negative integer

Number

Number

[0213] In this embodiment, when L = 1 and d = 1, the highest delay among the 32 delay lines is 3V = 3Q * d = 3 * 68 * 1 = 204 symbols, that is, 2040 bits. When L = 5 and d = 5, the highest delay among the 32 delay lines is 3V = 3Q * d = 3 * 14 * 5 = 210 symbols, that is, 2100 bits. The required delay is small. When Hamming(170, 160) is used for inner code encoding, each Hamming codeword has 160 information bits, which is a total of 16 symbols. In the case of a 1 * 800G interface, 2 * 400G interface, 4 * 200G interface, or 8 * 100G interface with each lane at 100 Gb / s on the client side, the 16 symbols within each Hamming information bit are from 16 different outer codewords. This ensures good performance of the entire cascaded FEC solution. In some scenarios that require ultra-low latency, it should be understood that a smaller value of V can be used. In this case, the 16 symbols within each Hamming codeword are from less than 16 different outer codewords. The performance deteriorates slightly, but the overall transmission latency for the solution is low.

[0214] Embodiment 2: n = 32, the 32 delay lines include two groups, and each group includes 16 delay lines. The sequential number values of a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 、and a 15 in each group of 16 delay lines are {0, 3, 1, 2, 4, 7, 5, 6, 8, 11, 9, 10, 12, 15, 13, 14}. The 32 first symbol subsets b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 、b 11 、b 12 、b 13 、b 14 、b 15 、b 16 、b 17 、b 18 、b 19 、b20 , b 21 , b 22 , b 23 , b 24 , b 25 , b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 The serial numbers of are {0, 3, 1, 2, 4, 7, 5, 6, 8, 11, 9, 10, 12, 15, 13, 14, 16, 19, 17, 18, 20, 23, 21, 22, 24, 27, 25, 26, 28, 31, 29, 30}

[0215] Figures 16A and 16B are another schematic distribution diagrams of 32 delay lines according to an embodiment of this application. As shown in Figures 16A and 16B, 32 data streams respectively correspond to 32 delay lines, and the delay lines may include 0, Q, 2Q, or 3Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, or 3V symbols, where V = Q * d. In each group of 16 delay lines, delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , delay line a 15The delay values are {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, 3V, V, 3V, V}. Correspondingly, the number of delay symbols from delay lines 0 to 31 are respectively {0, 0, 2V, 2V, 2V, 2V, 0, 0, V, V, 3V, 3V, 3V, 3V, V, V, 0, 0, 2V, 2V, 2V, 2V, 0, 0, V, V, 3V, 3V, 3V, 3V, V, V}. Specifically, the delay element outputs d symbols from the memory element at the right end of each delay line, and 32 * d symbols are obtained. Correspondingly, the symbols stored in the memory element in each delay line are shifted rightward by d symbols. Also, d symbols are obtained from each of the 32 data streams and are separately written into the memory elements at the left ends of the 32 delay lines. When a delay line includes 0 memory elements (e.g., delay lines 0, 1, 6, 7, 16, 17, 22, and 23 in FIGS. 16A and 16B), it should be understood that the d symbols output from the delay line are the d symbols obtained from the corresponding PCS or FEC lane data stream by the current operation. It should be understood that d symbols are output from each delay line in one delay operation. When d ≤ L * m, φ delay operations can be repeatedly performed to obtain φ * d symbols, where φ * d ≥ L * m and φ is a positive integer.

[0216] The interleaver obtains L * m symbols from each of the 32 delayed data streams to obtain L sets of first symbols. Each set of first symbols includes 32 first symbol subsets, and each first symbol subset includes m symbols. The m symbols within the first symbol subset h (0 ≤ h < 32) of each set of first symbols are from the delayed data stream h. The interleaver separately interleaves the L sets of first symbols to obtain L sets of second symbols, and each set of second symbols includes r * c symbols. Each set of second symbols includes r second symbol subsets, and each second symbol subset includes c symbols, and 32 * m = r * c.

[0217] The first symbol set may alternatively be a symbol matrix including 32 rows and m columns of symbols, which should be noted to be called the first symbol matrix. The second symbol set may alternatively be a symbol matrix including r rows and c columns of symbols, which is called the second symbol matrix. In this case, the L*m symbols obtained from the delay data stream h are respectively sent to the columns m of the rows h of the L first symbol matrices. The m symbols within each row h of the first symbol matrices are from the delay data stream h. The interleaver interleaves 32*m symbols in each of the L first symbol matrices to obtain L second symbol matrices, and the second symbol matrices include r rows and c columns of symbols.

[0218] As shown in FIG. 14, in an imaginable implementation form, the interleaver includes L interleaving sub-units, and the L interleaving sub-units separately interleave the L first symbol matrices to obtain L second symbol matrices. Specifically, the data division unit

Number

[0219] In one example, the first symbol matrix includes symbols of 32 rows and 3 columns, the second symbol matrix includes symbols of 8 rows and 12 columns, and L = 1, Q = 24, d = 3. Specifically, the interleaver obtains 3 symbols from each of the 32 delay data streams, and each memory element D in the delay line stores d = 3 symbols, and each symbol includes 10 bits. V = Q*d = 72, and the delay value of each delay line is 0 symbol, 72 symbols, 144 symbols, or 216 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 12.

[0220] [Table 12]

[0221] The symbol in the i-th row and j-th column (0 ≤ i < 8, 0 ≤ j < 12) of the second symbol matrix is from the symbol in the row b x%32 and column [Number] of the first symbol matrix, [Number] where Y%Z represents the remainder obtained by dividing Y by Z, [Number] and [Number] [Number] represents the quotient obtained by dividing Y by Z. The data interleaving rule can be represented using Table 13 below. In Table 13, the number x in row i and column j indicates that the symbol in row i and column j of the second symbol matrix is from the symbol in row x%32 and column [Number] of the first symbol matrix, where 0 ≤ i < 8, 0 ≤ j < 12, and 0 ≤ x < 96. Correspondingly, the symbol in row i and column j (0 ≤ i < 8, 0 ≤ j < 12) of the second symbol matrix is from the symbol in row x%32 and column [Number] where Y%Z represents the remainder obtained by dividing Y by Z, [Number] represents the quotient obtained by dividing Y by Z. The data interleaving rule can be represented using Table 14 below. In Table 14, the number x in row i and column j indicates that the symbol in row i and column j of the second symbol matrix is from the symbol in row x%32 and column [Number] It is from the symbols of, where 0 ≤ i < 8, 0 ≤ j < 12, and 0 ≤ x < 96. After the interleaver outputs the second symbol matrix, the inner code encoding device separately performs inner code encoding on the 12 symbols in each row of the second symbol matrix to obtain 8 codewords. When Hamming(128, 120) is used for inner code encoding, inner code encoding is performed on the total 96 symbols of 960 bits output by the interleaver, and 8 inner codewords of a total of 8 * 128 = 1024 bits can be obtained.

[0222] [Table 13]

[0223] [Table 14]

[0224] The foregoing example provides an implementation form with L = 1. Based on this, the implementation form with L > 1 can be further extended. This is an extension of the applicable scenario. For specific implementation forms, please refer to the foregoing description. Details will not be described again in this specification. Several typical parameter combinations are provided below.

[0225] L = 2, d = 6, Q = 12, V = Q * d = 72. The interleaver outputs L = 2 second symbol matrices of 8 * 12, and inner code encoding is performed to obtain 8 * L = 16 codewords.

[0226] L = 3, d = 9, Q = 8, V = Q * d = 72. The interleaver outputs L = 3 second symbol matrices of 8 * 12, and inner code encoding is performed to obtain 8 * L = 24 codewords.

[0227] L = 4, d = 12, Q = 6, and V = Q * d = 72. The interleaver outputs L = 4 second symbol matrices of 8 * 12, and inner code encoding is performed to obtain 8 * L = 32 codewords.

[0228] In the following, L = 4 is used as an example for explanation. The first symbol matrix contains 32 rows × 3 columns of symbols, and the second symbol matrix contains 8 rows × 12 columns of symbols. The interleaver can use the structure shown in FIG. 14. Specifically, the interleaver includes four interleaving sub-units. The four second symbol matrices can be obtained by performing interleaving on the four first symbol matrices using the four interleaving sub-units. Each memory element D in the delay line can store d = 12 symbols. Each symbol contains 10 bits, and the delay value of each delay line is 0 symbols, 72 symbols, 144 symbols, or 216 symbols. After the interleaver outputs the four second symbol matrices, the inner code encoding device performs inner code encoding on the 12 symbols in each row of the four second symbol matrices to obtain 8 * L = 32 codewords. When Hamming(128, 120) is used for inner code encoding, inner code encoding is performed on the 384 symbols of a total of 3840 bits output by the interleaver, and 32 inner codewords of a total of 32 * 128 = 4096 bits can be obtained.

[0229] In this embodiment, the highest delay among the 32 delay lines is 3Q*d = 216 symbols, that is, 2160 bits. The required delay is small. When Hamming(128, 120) is used for inner code encoding, each Hamming codeword has 120 information bits, which is a total of 12 symbols. For a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with 100 Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from 12 different outer codewords. This ensures good performance of the overall cascaded FEC solution. It should be understood that in some scenarios that require ultra-low latency, a smaller value of V can be used. In this case, the 12 symbols within each Hamming information bit are from less than 12 different outer codewords. The performance deteriorates slightly, but the overall transmission latency corresponding to the solution is low.

[0230] Embodiment 3: n = 32, the 32 delay lines include two groups, and each group includes 16 delay lines. The consecutive number values a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a 10 、a 11 、a 12 、a 13 、a 14 、and a 15 of the 16 delay lines in each group are {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}. The 32 first symbol subsets b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 、b 11 、b 12 、b 13 、b 14 、b 15 、b 16 、b 17 、b 18 、b 19 、b 20 、b 21 、b 22 、b 23 、b 24 、b 25, b 26 , b 27 , b 28 , b 29 , b 30 , and b 31 The serial numbers are {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}

[0231] FIG. 17A and FIG. 17B are another schematic distribution diagrams of 32 delay lines according to an embodiment of this application. As shown in FIG. 17A and FIG. 17B, 32 data streams respectively correspond to 32 delay lines. The delay lines may include 0, Q, 2Q, or 3Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, or 3V symbols, where V = Q * d. In each group of 16 delay lines, delay line a0, delay line a1, delay line a2, delay line a3, delay line a4, delay line a5, delay line a6, delay line a7, delay line a8, delay line a9, delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , delay line a 15The delay values are {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}. Correspondingly, the number of delay symbols from delay lines 0 to 31 are respectively {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0 and 3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}. Specifically, the delay device outputs d symbols from the memory element at the right end of each delay line and obtains 32*d symbols. Correspondingly, the symbols stored in the memory element in each delay line are shifted rightward by d symbols. Also, d symbols are obtained from each of the 32 data streams and are separately written into the memory elements at the left ends of the 32 delay lines. When the delay line includes 0 memory elements (e.g., delay lines 9, 10, 12, 15, 25, 26, 28, and 31 in FIGS. 17A and 17B), it should be understood that the d symbols output from the delay line are the d symbols obtained from the corresponding PCS or FEC lane data stream by the current operation. It should be understood that d symbols are output from each delay line in one delay operation. When d≦L*m, φ delay operations can be repeatedly performed to obtain φ*d symbols, where φ*d≧L*m and φ is a positive integer.

[0232] The interleaver obtains L*m symbols from each of the 32 delayed data streams to obtain L first symbol sets. Each first symbol set includes 32 first symbol subsets, and each first symbol subset includes m symbols. The m symbols in the first symbol subset h (0≦h<32) of each first symbol set are from the delayed data stream h. The interleaver separately interleaves the L first symbol sets to obtain L second symbol sets, and the second symbol set includes r*c symbols. Each second symbol set includes r second symbol subsets, and each second symbol subset includes c symbols, and 32*m = r*c.

[0233] The first symbol set may alternatively be a symbol matrix including 32 rows by m columns of symbols, which should be noted to be called the first symbol matrix. The second symbol set may alternatively be a symbol matrix including r rows and c columns of symbols, which is called the second symbol matrix. In this case, the L*m symbols obtained from the delay data stream h are respectively sent to the columns m of the rows h of the L first symbol matrices. The m symbols within each row h of the first symbol matrices are from the delay data stream h. The interleaver interleaves 32*m symbols in each of the L first symbol matrices to obtain L second symbol matrices, and the second symbol matrices include r rows and c columns of symbols.

[0234] As shown in FIGS. 17A and 17B, in one possible implementation, the interleaver includes L interleaving subunits, and the L interleaving subunits separately interleave the L first symbol matrices to obtain L second symbol matrices. Specifically, the data splitting unit

Number

[0235] In one example, the first symbol matrix includes symbols of 32 rows and 3 columns, the second symbol matrix includes symbols of 8 rows and 12 columns, and L = 2, Q = 12, d = 6. Specifically, the interleaver obtains 6 symbols from each of the 32 delay data streams, each memory element D in the delay line stores d = 6 symbols, and each symbol includes 10 bits. V = Q*d = 72, and the delay value of each delay line is 0 symbol, 72 symbols, 144 symbols, or 216 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 15.

[0236]

Table 15

[0237] The symbol in the i-th row and j-th column (0 ≦ i < 8, 0 ≦ j < 12) of the second symbol matrix is from the symbol in the row b x%32 = x % 32 and column

Number

Number

Number

[0238]

Table 16

[0239] In Table 16, the number x in row i and column j indicates that the symbol in row i and column j of the second symbol matrix is from the symbol in row x % 32 and column

Number

[0240] In this embodiment, the highest delay among the 32 delay lines is 3V = 3Q * d = 216 symbols, that is, 2160 bits. The required delay is small. When Hamming(128, 120) is used for inner code encoding, each Hamming codeword has 120 bits of information bits, which is a total of 12 symbols. In the case of a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with 100 Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from at least 10 different outer code codewords. This ensures good performance of the cascaded FEC solution.

[0241] It should be noted that the foregoing example provides an implementation form where L = 2. Based on this, other implementation forms using the value of L can be further extended. This is an extension of the applicable scenario. For specific implementation forms, refer to the foregoing description. Details will not be described again in this specification.

[0242] Embodiment 4: Different from Embodiment 3, Embodiment 4 uses a different interleaving rule. The first symbol matrix includes 32 rows and 3 columns of symbols, the second symbol matrix includes 8 rows and 12 columns of symbols, and L = 2, Q = 12, d = 6. Specifically, the interleaver obtains 6 symbols from each of the 32 delayed data streams, each memory element D in the delay line stores d = 6 symbols, and each symbol includes 10 bits. V = Q * d = 72, and the delay value of each delay line is 0 symbol, 72 symbols, 144 symbols, or 216 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 15 of Embodiment 3. The symbol in the i-th row and j-th column (0 ≤ i < 8, 0 ≤ j < 12) of the second symbol matrix is from the symbol in the row b x%32 = x % 32 and column

Number

Number

Mathematics

[0243]

Table 17

[0244] In Table 17, the number x in row i and column j indicates that the symbol in row i and column j of the second symbol matrix is from the symbol in row x%32 and column

Mathematics

[0245] After the interleaver outputs two second symbol matrices, the inner code encoding device performs inner code encoding on the 12 symbols in each row of the two second symbol matrices to obtain 16 codewords. When Hamming(128, 120) is used for inner code encoding, inner code encoding is performed on the total 192 symbols of 1920 bits output by the interleaver, and 16 inner codewords of a total of 16 * 128 = 2048 bits can be obtained.

[0246] In this embodiment, the highest delay among the 32 delay lines is 3V = 3Q * d = 216 symbols, that is, 2160 bits. The required delay is small. When Hamming(128, 120) is used for inner code encoding, each Hamming codeword has 120 information bits, which is a total of 12 symbols. In the case of a 1 * 800G interface, 2 * 400G interface, 4 * 200G interface, or 8 * 100G interface with 100 Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from 12 different outer codewords. This ensures good performance of the entire cascaded FEC solution.

[0247] Embodiment 5: n = 32, the 32 delay lines include two groups, and each group includes 16 delay lines.

[0248] As shown in FIGS. 13A and 13B, the 32 data streams respectively correspond to 32 delay lines. The delay lines may include 0, Q, 2Q, or 3Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, or 3V symbols, where V is an integer greater than or equal to 68. Specifically, the delay device outputs d symbols from the memory element at the right end of each delay line to obtain 32 * d symbols. Correspondingly, the symbols stored in the memory elements in each delay line are shifted rightward by only d symbols. Also, d symbols are obtained from each of the 32 data streams and are separately written into the memory elements at the left end of the 32 delay lines. It should be understood that when the delay line includes 0 memory elements, the d symbols output from the delay line are the d symbols obtained from the corresponding PCS or FEC lane data stream by the current operation. It should be understood that d symbols are output from each delay line in one delay operation. When d ≤ L * m, φd ≥ L * m, and when φ is a positive integer, φ delay operations can be repeatedly performed to obtain φd symbols.

[0249] The interleaver obtains L*m symbols from each of 32 delayed data streams to obtain L first symbol sets. Each first symbol set includes 32 first symbol subsets, and each first symbol subset includes m symbols. The m symbols within the first symbol subset h (0 ≦ h < 32) of each first symbol set are from the delayed data stream h. The interleaver separately interleaves the L first symbol sets to obtain L second symbol sets, and the second symbol sets include r*c symbols. Each second symbol set includes r second symbol subsets, each second symbol subset includes c symbols, and 32*m = r*c.

[0250] The first symbol set may alternatively be a symbol matrix including symbols in 32 rows and m columns, and it should be noted that it is called the first symbol matrix. The second symbol set may alternatively be a symbol matrix including r rows and c columns of symbols, and it is called the second symbol matrix. In this case, the L*m symbols obtained from the delayed data stream h are respectively sent to the columns m of row h of the L first symbol matrices. The m symbols within row h of each first symbol matrix are from the delayed data stream h. The interleaver interleaves 32*m symbols in each of the L first symbol matrices to obtain L second symbol matrices, and the second symbol matrices include r rows and c columns of symbols.

[0251] As shown in FIG. 14, in a possible implementation form, the interleaver includes L interleaving sub-units, and the L interleaving sub-units separately interleave the L first symbol matrices to obtain L second symbol matrices. Specifically, the data division unit

Number

[0252] In one example, the first symbol matrix includes symbols of 32 rows and 16 columns, the second symbol matrix includes symbols of 32 rows and 16 columns, and L = 1, Q = 9, and d = 8. Specifically, the interleaver obtains 16 symbols from each of the 32 delay data streams, each memory element D in the delay line stores d = 8 symbols, and each symbol includes 10 bits. V = Q*d = 72, and the delay value of each delay line is 0 symbol, 72 symbols, 144 symbols, or 204 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 18.

[0253]

Table 18

[0254] The rule for interleaving the first symbol matrix to obtain the second symbol matrix may be shown in Table 19. The number k in the i-th row and j-th column of the table indicates that the symbol in the i-th row and j-th column of the second symbol matrix is from the symbol in the k-th row and j-th column of the first symbol matrix. It should be noted that any transposition of the positions of two rows in Table 19 also belongs to the data interleaving rules provided in this application.

[0255]

Table 19

[0256] In another example, the first symbol matrix includes 32 rows and 12 columns of symbols, the second symbol matrix includes 32 rows and 12 columns of symbols, and L = 1, Q = 12, d = 6. Specifically, the interleaver obtains 12 symbols from each of the 32 delayed data streams, each memory element D in the delay line stores d = 6 symbols, and each symbol includes 10 bits. V = Q * d = 72, and the delay value of each delay line is 0 symbol, 72 symbols, 144 symbols, or 216 symbols. Specifically, the delay values of the 32 delay lines can be shown in Table 20.

[0257]

Table 20

[0258] The rule for interleaving the first symbol matrix to obtain the second symbol matrix may be represented in Table 21. The number k in the i-th row and j-th column of the table indicates that the symbol in the i-th row and j-th column of the second symbol matrix is from the symbol in the k-th row and j-th column of the first symbol matrix. It should be noted that any transposition of the positions of two rows in Table 21 also belongs to the data interleaving rule provided in this application.

[0259]

Table 21

[0260] In this embodiment, the highest delay among the 32 delay lines is 3Q*d = 240 symbols, that is, 2400 bits. The required delay is small. Referring to the delay values in Table 16 and the interleaving rules in Table 17, when Hamming(170, 160) is used for inner code encoding, each Hamming codeword has 160 information bits, which is a total of 16 symbols. For a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with each lane of 100 Gb / s on the client side, the 16 symbols within each Hamming information bit are from 16 different outer code codewords. This ensures good performance of the entire cascade FEC solution. However, referring to the delay values in Table 18 and the interleaving rules in Table 19, when Hamming(128, 120) is used for inner code encoding, each Hamming codeword has 120 information bits, which is a total of 12 symbols. For a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with each lane of 100 Gb / s on the client side, the 12 symbols within each Hamming information bit are from 12 different outer code codewords. This ensures good performance of the entire cascade FEC solution.

[0261] The foregoing embodiments have been provided for the cases where the inner code information symbol length c is 8, 12, or 16 symbols. It should be noted that the cases where the inner code information symbol length c is 9, 10, 11, 13, 14, or 15 may be further extended. After the 32 data streams are delayed, among the 32 symbols output each time, the 16 symbols of group 0 are from 16 different RS codeword symbols. The 16 symbols of group 0 are symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 、symbol b 13 、symbol b 16 、symbol b 17 、symbol b 20 、symbol b 21, symbol b 24 , symbol b 25 , symbol b 28 , symbol b 29 include. After 32 data streams are delayed, 16 symbols in group 1 out of the 32 symbols output each time are from 16 different RS codeword symbols. The 16 symbols in group 1 are symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , symbol b 31 include.

[0262] Alternatively, the 16 symbols in group 0 are symbol b0, symbol b1, symbol b4, symbol b5, symbol b8, symbol b9, symbol b 12 , symbol b 13 , symbol b 18 , symbol b 19 , symbol b 22 , symbol b 23 , symbol b 26 , symbol b 27 , symbol b 30 , and symbol b 31 include. The 16 symbols in group 1 are symbol b2, symbol b3, symbol b6, symbol b7, symbol b 10 , symbol b 11 , symbol b 14 , symbol b 15 , symbol b 16 , symbol b 17 , symbol b 20 , symbol b 21 , symbol b 24 , symbol b 25 , symbol b 28 , symbol b 29includes.

[0263] In connection with the foregoing features, the interleaver may be designed such that in each row, the c symbols output by the interleaver are from c different RS codeword symbols. Below, b i = i is used as an example for explaining the interleaving method. The first symbol matrix includes 32 rows and m columns, the second symbol matrix includes r rows and c columns, and 32 * m = r * c. The 16 rows of symbols in group 0 of the first symbol matrix sequentially include the symbols in rows 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, and 29, and the 16 rows of symbols in group 1 of the first symbol matrix sequentially include the symbols in rows 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, and 31.

[0264] Specifically, among the 16 rows of symbols in group 0, the symbols from row 0 to row 15 in each column are 16 symbols arranged in that order. Among the adjacent two columns in the rows of the 16 symbols in group 0, the symbols from row 15 of the previous column to row 0 of the next column are two symbols arranged in order. Among the c symbols in row 0 of the r / 2 rows of symbols in group 0 of the second symbol matrix, the c symbols are from among the c symbols in group 0 arranged in the order starting from row 0 and column 0 of the 16 rows of symbols in group 0, and the rest can be inferred by analogy until the c symbols in row r / 2 - 1 of the r / 2 rows of symbols in group 0 of the second symbol matrix are from the last group of the c symbols arranged in the order starting from row 0 and column 0 of the 16 rows of symbols in group 0. That is, as one row of the second symbol matrix, c symbols are sequentially obtained from the 16 rows of symbols in group 0 from top to bottom and then from left to right, and a total of r / 2 rows of the second symbol matrix are obtained.

[0265] Similarly, the 16 symbols in Group 1 are arranged in order, and each column of the 16 symbols in Group 1 from row 0 to row 15 is composed of 16 symbols arranged in order. Among the adjacent two columns of the rows of the 16 symbols in Group 1, the symbols from row 15 of the previous column to row 0 of the subsequent column are two symbols arranged in order. Among the r / 2 rows of the symbols in Group 1 of the second symbol matrix, the c symbols in row 0 are from c symbols in Group 0 arranged in the order starting from row 0 and column 0 of the 16 rows of the symbols in Group 1. The rest can be inferred by analogy until the c symbols in row r / 2 - 1 of the r / 2 rows of the symbols in Group 1 of the second symbol matrix are from the last group of c symbols arranged in the order starting from row 0 and column 0 of the 16 rows of the symbols in Group 1. In other words, the c symbols are sequentially obtained from the 16 rows of symbols in Group 1 row by row from top to bottom and then column by column from left to right as one row of the second symbol matrix, and a total of r / 2 rows of the second symbol matrix are obtained.

[0266] More specifically, the following provides some typical parameter combinations: {m = 9, r = 32, c = 9}, {m = 5, r = 16, c = 10}, {m = 11, r = 32, c = 11}, {m = 13, r = 32, c = 13}, {m = 7, r = 16, c = 14}, and {m = 15, r = 32, c = 15}.

[0267] It should be noted that in addition to the data interleaving method described above, this application further provides another data interleaving method based on the grouping of data streams, which will be described below.

[0268] FIG. 18 is a schematic diagram for grouping data streams according to an embodiment of this application. As shown in FIG. 18, n data streams include g groups, and each group includes p data streams. g is an integer greater than or equal to 1, p is an integer greater than or equal to 1, and n = g * p. Specifically, data stream 0, data stream 1,..., and data stream p - 1 belong to the same group. Data stream p, data stream p + 1,..., and data stream 2p - 1 belong to the same group. By analogy, data stream (g - 1)p, data stream (g - 1)p + 1,..., and data stream n - 1 belong to the same group. Correspondingly, the n delay lines in the delay element also correspondingly include g groups, and each group includes p delay lines. The g delay line groups correspond one-to-one to the g data stream groups. The p delay lines in each delay line group respectively include 0 memory elements, Q memory elements, 2Q memory elements,..., and (p - 1)Q memory elements. Each memory element is used to store d symbols. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. In other words, the p delay lines in each delay line group respectively correspond to p delay values, which are respectively 0 symbols, V symbols, 2V symbols,..., and (p - 1)V symbols, where V = Q * d.

[0269] FIG. 19 is a schematic structural diagram of a delay line group according to an embodiment of this application. As shown in FIG. 19, delay line 0 has (p - 1) memory elements. Then, based on the order within the group, for each delay line, Q memory elements are reduced in that order. Specifically, delay line p - 1 has 0 memory elements. FIG. 20 is another schematic structural diagram of a delay line group according to an embodiment of this application. As shown in FIG. 20, delay line 0 has 0 memory elements. Then, based on the order within the group, for each delay line, Q memory elements are increased in that order. Specifically, delay line p - 1 has (p - 1) memory elements. It should be understood that FIGS. 19 and 20 merely provide two examples of delay line allocation within the group. In actual applications, if each of the p delay lines in each delay line group corresponds to p delay values, the above-described method of sequentially decreasing or increasing delay line allocation may not be used. Details are not enumerated one by one in this specification.

[0270] Based on the above-described grouping of delay lines, correspondingly, the first symbol matrix and the second symbol matrix also need to be grouped. FIG. 21(a) is a schematic diagram of grouping the first symbol matrix and the second symbol matrix according to an embodiment of this application. As shown in FIG. 21(a), the n symbols in each column of the first symbol matrix include g groups, and each group includes p symbols. The c symbols in each row of the second symbol matrix include s groups, and each group includes p symbols. g is an integer greater than 1, s is an integer greater than 1, and p is an integer greater than or equal to 1. Specifically, one group of p symbols in the second symbol matrix is from one group of p symbols in the first symbol matrix, and the total two p symbols of any two groups in each row of the second symbol matrix are from different rows of the first symbol matrix. For example, if the p symbols of group 0 in row 0 of the second symbol matrix are from the p symbols of group 0 in column 0 of the first symbol matrix, the symbols of another group in row 0 of the second symbol matrix cannot be from the symbols of group 0 in all columns of the first symbol matrix.

[0271] Figure 21(b) is another schematic diagram showing the grouping of the first symbol matrix and the second symbol matrix according to an embodiment of this application. As shown in Figure 21(b), the first symbol matrix includes g first symbol sub-matrices, each first symbol sub-matrix includes p rows and m columns, g, p, and m are integers greater than or equal to 1, and n = p * g. The second symbol matrix includes g second symbol sub-matrices, each second symbol sub-matrix includes r0 rows and c columns, r0 and c are integers greater than or equal to 1, r = r0 * g, and p * m = r0 * c. To obtain the second symbol sub-matrix i, interleaving is performed on the first symbol sub-matrix i (0 ≤ i < g). The c symbols in each row of each second symbol matrix are from c different codewords.

[0272] Considering several specific scenarios, the transmitting device performs KP4RS(544, 514) outer code encoding on the service data stream to be transmitted to obtain n PCS lane data streams, and all A outer code words are distributed to the n lane data streams. Specifically, in the n PCS lane data streams, each data stream is separated by B symbols, and there are a total of n*B symbols including A RS code words, where n*B = A*544. The consecutive symbols within each PCS lane data stream are from A different RS code words, and the A symbols at the same position in A consecutive PCS lane data streams are from A different RS code words. The integer A can be 2, 4, etc. The n PCS lane data streams are processed in the PMA sublayer and then transmitted to the transmitting processing module via the attachment unit interface. In the transmitting processing module, n aligned lane data streams are obtained through lane dequeue processing. The delay device shown in FIG. 18 is used. The delay device includes g groups of delay lines, and the p delay lines in each group of delay lines respectively correspond to p delay values, which are 0 symbol, V symbol, 2V symbol,..., and (p - 1)V symbol respectively, where V = Q*d. When V≧b, the A*p symbols in the symbols output from each group of p delay lines are from A*p different RS outer code words, and each delay line provides A consecutive symbols.

[0273] The interleaver obtains L*m symbols from each of n delayed data streams to obtain L first symbol sets. Each first symbol set includes n first symbol subsets, and each first symbol subset includes m symbols. The m symbols within the first symbol subset h (0 ≦ h < n) of each first symbol set are from the delayed data stream h. The interleaver interleaves the L first symbol sets separately to obtain L second symbol sets, and the second symbol sets include r*c symbols. Each second symbol set includes r second symbol subsets, and each second symbol subset includes c symbols, and n*m = r*c. The first symbol set may alternatively be a symbol matrix including n rows and m columns of symbols, and it should be noted that it is called the first symbol matrix. The second symbol set may alternatively be a symbol matrix including r rows and c columns of symbols, and it is called the second symbol matrix. In this case, the L*m symbols obtained from the delayed data stream h are respectively sent to the columns m of row h of the L first symbol matrices. The m symbols within row h of each first symbol matrix are from the delayed data stream h. The interleaver interleaves n*m symbols in each of the L first symbol matrices to obtain L second symbol matrices, and the second symbol matrices include r rows and c columns of symbols.

[0274] L*m symbols are obtained from each of the n delayed data streams to obtain L first symbol matrices. The interleaver shown in FIG. 21(b) is used to separately interleave the L first symbol matrices to obtain L second symbol matrices. The first symbol matrix includes g first symbol submatrices, and the second symbol matrix includes g second symbol submatrices. Interleaving is performed on each first symbol submatrix to obtain the second symbol submatrix. Specifically, the c symbols in each row of the second symbol submatrix are from the c symbols in the first symbol submatrix, and the c symbols in the first symbol submatrix are distributed in the maximum A columns of the first symbol submatrix.

[0275] In some possible implementations, the symbols in the first symbol submatrix t are arranged in order, the symbols in rows 0 to p-1 of each column of the first symbol submatrix t are p symbols arranged in order, and in two adjacent columns of the first symbol submatrix t, the symbols in rows p-1 of the previous column to row 1 of the next column are two symbols arranged in order. The c symbols in row 0 of the second symbol submatrix t are from the c symbols in group 0 arranged in order starting from row 0 and column 0 of the first symbol submatrix t, and the rest can be estimated by analogy until the c symbols in row r0-1 of the second symbol submatrix t are from the last group of c symbols arranged in order starting from row 0 and column 0 of the first symbol submatrix t. In other words, to form one row of c symbols in the second symbol submatrix, to obtain a total of c symbols, from the top to the bottom, and then from the left to the right,

Number

Number

[0276] The L first symbol matrices input by the interleaver may be respectively stored in the L buffers of the interleaver. It should be noted that the interleaver outputs the L second symbol matrices to the encoder after the interleaving is completed. The encoder performs inner code encoding on the symbols in each row of the L second symbol matrices. Specifically, the L second symbol matrices include L*r rows of symbols, and the encoder can perform inner code encoding on the L*r rows of symbols separately by using L*r independent encoding units.

[0277] Hereinafter, a data interleaving method based on the grouping of data streams will be further described using several specific application scenarios. It should be noted that the number of bits included in one symbol is not limited in this application. In the following example, an example where one symbol includes 10 bits is used for the purpose of explanation.

[0278] Applicable Scenario 1: FIGS. 22A and 22B are schematic diagrams of an applicable scenario of data interleaving according to an embodiment of this application. As shown in FIGS. 22A and 22B, n = 32, m = 3, r = 8, c = 12, p = 4, g = 8, s = 3. Specifically, the first symbol matrix includes symbols of 32 rows and 3 columns, and four symbols in each column form one group. The second symbol matrix includes symbols of 8 rows and 12 columns, and four symbols in each row form one group. The delay element includes 32 delay lines, which form groups every four delay lines. The four delay lines in each group respectively include 0 memory elements, Q memory elements, 2Q memory elements, and 3Q memory elements. Q = 136, d = 1, L = 1. It should be understood that the structural distribution of the four delay lines in each group in FIGS. 22A and 22B is merely an example and can be changed based on the methods described in FIGS. 19 and 20. Details will not be described again in this specification.

[0279] Specifically, the interleaver obtains d = 1 symbol from the memory element at the right end of each delay line and obtains 32 symbols. Correspondingly, the symbol stored in the memory element in each delay line is shifted rightward by only d = 1 symbol. Also, d = 1 symbol is obtained from each of the 32 data streams and written separately into the memory elements at the left ends of the 32 delay lines. The 32 symbols output by the delay element each time are stored in one column of the buffer of the interleaver. The above operations are repeated three times, and a total of 32 * 3 = 96 symbols, that is, the first symbol matrix is written into the buffer of the interleaver. The interleaver interleaves the first symbol matrix to obtain 8 * 12 symbols, that is, the second symbol matrix.

[0280] Each group of four symbols in each row of the 12 symbols of the second symbol matrix is from one group of four symbols in one column of the first symbol matrix, and it should be noted that each group of any two symbols in each row of the three groups of three symbols of the second symbol matrix is from two groups of symbols in different rows of the first symbol matrix. In an implementable form, the 12 symbols in one row of the second symbol matrix respectively correspond to the four symbols in group a of column 0 of the first symbol matrix, the four symbols in group b of column 1 of the first symbol matrix, and the four symbols in group e of column 2 of the first symbol matrix, where a, b, and e are not equal to each other, 0 ≤ a < 4 and 4 ≤ e < 8, or 0 ≤ e < 4 and 4 ≤ a < 8.

[0281] Furthermore, the symbol in the i-th row and j-th column of the second symbol matrix corresponds to the symbol in the (x % 32)-th row

Number

Number

Number

Number

[0282]

Table 22

[0283] Furthermore, the interleaver outputs a second symbol matrix to the encoder, and the encoder performs inner code encoding on 120 symbols each with a total of 12 bits per row of the second symbol matrix to obtain 8 codewords. In an implementable form, the inner code encoding is performed using Hamming(128, 120), and 8 * 128 = 1024 bits are obtained by the inner code encoding. In another implementable form, the inner code encoding is performed using BCH(136, 120), and 8 * 136 = 1088 bits are obtained by the inner code encoding.

[0284] In application scenario 1, the convolutional interleaver has 32 delay lines, the maximum delay is 3V = 3Q * d = 408 symbols, and the delay is low. When Hamming(128, 120) is used for inner code encoding, each Hamming information bit becomes a total of 12 symbols. For a 1 * 800G interface, 2 * 400G interface, 4 * 200G interface, or 8 * 100G interface with 100Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from 12 different outer code codewords. This ensures good performance of the entire cascaded FEC solution.

[0285] Application scenario 2: FIGS. 23A and 23B are schematic diagrams of another application scenario of data interleaving according to an embodiment of this application. As shown in FIGS. 23A and 23B, different from the aforementioned application scenario 1, in this application scenario 2, Q = 46 and d = 3. Specifically, the delay element outputs d = 3 symbols from the memory element at the right end of each delay line to obtain 32 * 3 = 96 symbols. Correspondingly, the symbols stored in the memory elements within each delay line are shifted rightward by d = 3 symbols. Also, d = 3 symbols are obtained from each of the 32 data streams and are separately written to the memory elements at the left end of the 32 delay lines. The interleaver can obtain 32 * 3 = 96 symbols at one time and does not need to perform three read operations as in application scenario 1.

[0286] It should be noted that the delay device outputs 96 symbols each time and writes 96 symbols into the buffer of the interleaver. The three symbols from the data stream h (0 ≦ h < 32) output by the delay device are written into row h in the buffer of the interleaver. The writing method is as follows: that is, for the three symbols output by the delay device, the symbol 0, symbol 1, and symbol 2 from the data stream h are written into column 0, column 1, and column 2 of row h in the buffer of the interleaver, respectively. Another writing method is as follows: that is, for the three symbols output by the delay device, the symbol 0, symbol 1, and symbol 2 from the data stream h are written into column 2, column 1, and column 0 of row h in the buffer of the interleaver, respectively.

[0287] The data interleaving method in Application Scenario 2 is the same as the data interleaving method described in Application Scenario 1 above, and will not be described in detail again in this specification. In Application Scenario 2, there are 32 delay lines in the convolutional interleaver, the maximum delay is 3V = 3Q * d = 414 symbols, and the delay is low. When Hamming(128, 120) is used for the inner code encoding, each Hamming information bit becomes a total of 12 symbols. In the case of a 1*800G interface, 2*400G interface, 4*200G interface, or 8*100G interface with 100 Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from 12 different outer codewords. This ensures good performance of the entire cascaded FEC solution.

[0288] Application scenario 3: FIGS. 24A and 24B are schematic diagrams of another application scenario of data interleaving according to an embodiment of this application. As shown in FIGS. 24A and 24B, different from the aforementioned application scenario 1, in this application scenario 3, Q = 12 and d = 12. Specifically, the delay device outputs d = 12 symbols from the memory element at the right end of each delay line, obtaining 32 * 12 = 384 symbols. Correspondingly, the symbols stored in the memory elements within each delay line are shifted rightward by d = 12 symbols. Also, d = 12 symbols are obtained from each of the 32 data streams and are separately written into the memory elements at the left ends of the 32 delay lines. A total of 32 * 12 = 384 symbols are written into the buffer of the interleaver and stored in the four sub-buffers of the interleaver. Each sub-buffer stores 32 * 3 = 96 symbols. In other words, each sub-buffer stores one first symbol matrix. The interleaver interleaves the four first symbol matrices separately to obtain four second symbol matrices, and each second symbol matrix contains 8 * 12 = 96 symbols.

[0289] The 12 symbols from the data stream h (0 ≦ h < 32) output by the delay element are written to row h of the four sub-buffers of the interleaver. Specifically, it should be noted that 3 symbols are written to row h of each sub-buffer. The writing method is as follows: that is, symbol 0, symbol 1, and symbol 2 from the data stream h are separately written to row h of sub-buffer 0, symbol 3, symbol 4, and symbol 5 from the data stream h are separately written to row h of sub-buffer 1, symbol 6, symbol 7, and symbol 8 from the data stream h are separately written to row h of sub-buffer 2, and symbol 9, symbol 10, and symbol 11 from the data stream h are separately written to row h of sub-buffer 3. Another writing method is as follows: that is, symbol 0, symbol 1, and symbol 2 from the data stream h are separately written to row h of sub-buffer 3, symbol 3, symbol 4, and symbol 5 from the data stream h are separately written to row h of sub-buffer 2, symbol 6, symbol 7, and symbol 8 from the data stream h are separately written to row h of sub-buffer 1, and symbol 9, symbol 10, and symbol 11 from the data stream h are separately written to row h of sub-buffer 0. Also, the 3 symbols written to the sub-buffer once may be written to column 0, column 1, and column 2 of row h in the sub-buffer respectively, or may be written to column 2, column 1, and column 0 of row h in the sub-buffer respectively.

[0290] The data interleaving method in application scenario 3 is the same as the data interleaving method described in application scenario 1 above, and will not be described in detail again in this specification. The interleaver outputs a total of 32 rows of symbols, and each row contains 12 symbols. The encoder separately performs FEC encoding on the 32 rows of symbols to obtain a total of 32 inner codewords. In an imaginable implementation form, Hamming(128, 120) is used for inner code encoding, and 32 * 128 = 4096 bits are obtained by inner code encoding.

[0291] In an implementable form, based on application scenario 2 where the interleaver outputs a total of 8 rows of symbols and application scenario 3 where the interleaver outputs a total of 32 rows of symbols, the case where the interleaver outputs a total of 16 or 24 rows of symbols can be further extended. In order to enable 12 symbols of each inner codeword information bit to be from 12 different outer codewords, it is necessary to satisfy V = Q * d ≥ 136, and Q * d is an even number.

[0292] In the scenario where the interleaver outputs a total of 16 rows of symbols, Q = 23 and d = 6. Specifically, the delay element outputs d = 6 symbols from the memory element at the right end of each delay line, obtaining 32 * 6 = 192 symbols. A total of 192 symbols are written into the buffer of the interleaver and stored in two sub-buffers of the interleaver. Each sub-buffer stores 96 symbols. In other words, each sub-buffer stores one first symbol matrix. The interleaver interleaves the two first symbol matrices separately to obtain two second symbol matrices, and each second symbol matrix contains 96 symbols. According to the data interleaving method described in the aforementioned application scenario 1, the interleaver outputs a total of 16 rows of symbols, and each row contains 12 symbols. The encoder separately performs FEC encoding on the 16 rows of symbols to obtain a total of 16 inner codewords. In an implementable form, Hamming(128, 120) is used for inner code encoding, and 16 * 128 = 2048 bits are obtained by the inner code encoding.

[0293] In the scenario where the interleaver outputs symbols in a total of 24 rows, Q = 16 and d = 9. Specifically, the delay element outputs d = 9 symbols from the memory element at the right end of each delay line, obtaining 32 * 6 = 288 symbols. A total of 288 symbols are written into the buffer of the interleaver and stored in three sub - buffers of the interleaver. Each sub - buffer stores 96 symbols. In other words, each sub - buffer stores one first symbol matrix. The interleaver interleaves the three first symbol matrices separately to obtain three second symbol matrices, and each second symbol matrix contains 96 symbols. According to the data interleaving method described in the aforementioned application scenario 1, the interleaver outputs symbols in a total of 24 rows, and each row contains 12 symbols. The encoder separately performs FEC encoding on the 24 - row symbols to obtain a total of 24 inner - code codewords. In an assumable implementation form, Hamming(128, 120) is used for inner - code encoding, and 24 * 128 = 3072 bits are obtained by inner - code encoding.

[0294] In application scenario 3, the convolutional interleaver has 32 delay lines, the maximum delay is 3Q * d = 432 symbols, and the delay is low. When Hamming(128, 120) is used for inner - code encoding, each Hamming information bit becomes a total of 12 symbols. In the case of a 1 * 800G interface, 2 * 400G interface, 4 * 200G interface, or 8 * 100G interface with 100 Gb / s per lane on the client side, the 12 symbols within each Hamming information bit are from 12 different outer - code codewords. This ensures good performance of the entire cascaded FEC solution.

[0295] Applicable Scenario 4: FIGS. 25A and 25B are schematic diagrams of another applicable scenario of data interleaving according to an embodiment of this application. As shown in FIGS. 25A and 25B, in this applicable scenario 4, Q = 17 and d = 8. Specifically, the delay device outputs d = 8 symbols from the memory element at the right end of each delay line to obtain 32 * 8 = 256 symbols. Correspondingly, the symbols stored in the memory elements within each delay line are shifted rightward by d = 8 symbols. Also, d = 8 symbols are obtained from each of the 32 data streams and are separately written to the memory elements at the left ends of the 32 delay lines. A total of 32 * 8 = 256 symbols are written to the buffer of the interleaver and stored in 8 sub-buffers of the interleaver. Each sub-buffer stores 32 * 1 = 32 symbols. In other words, each sub-buffer stores one first symbol matrix. The interleaver separately interleaves the 8 first symbol matrices to obtain 8 second symbol matrices, and each second symbol matrix contains 4 * 8 = 32 symbols.

[0296] It should be noted that the 8 symbols from the data stream h (0 ≤ h < 32) output by the delay device are written to row h of the 8 sub-buffers of the interleaver. Specifically, one symbol is written to row h of each sub-buffer. The writing method is as follows: That is, the symbol t (0 ≤ t < 8) from the data stream h is written to row h of sub-buffer t. Another writing method is as follows: That is, the symbol t (0 ≤ t < 8) from the data stream h is written to row h of sub-buffer 7 - t.

[0297] Each group of four symbols in each row of the eight symbols of the second symbol matrix is from one group of four symbols in column 0 of the first symbol matrix, and it should be noted that two groups of two symbols in the second symbol matrix are from two groups of two symbols in different rows of the first symbol matrix. In an implementable form, the eight symbols in one row of the second symbol matrix respectively correspond to four symbols in group a of column 0 of the first symbol matrix and four symbols in group b of column 0 of the first symbol matrix, where 0 ≦ a < 4 and 4 ≦ b < 8.

[0298] Furthermore, the symbol at row i and column j of the second symbol matrix corresponds to the symbol at row x and column 0 of the first symbol matrix.

Number

Number

[0299]

Table 23

[0300] The interleaver outputs a total of 32 rows of symbols, and each row contains 12 symbols. The encoder separately performs FEC encoding on the 32 rows of symbols to obtain a total of 32 inner codewords. In an implementable form, Hamming(87, 80) is used for inner code encoding, and 32 * 87 = 2784 bits are obtained by inner code encoding. In another implementable form, BCH(94, 80) is used for inner code encoding, and 32 * 94 = 3008 bits are obtained by inner code encoding.

[0301] In application scenario 4, there are 32 delay lines in the convolutional interleaver, and the maximum delay is 3Q*d=408 symbols, so the delay is low. If Hamming (87, 80) is used for the inner code encoding, each Hamming information bit has a total of 8 symbols. For 1*800G interfaces, 2*400G interfaces, 4*200G interfaces, or 8*100G interfaces with each lane of 100Gb / s at the client side, the 8 symbols in each Hamming information bit are from 8 different outer code codewords. This ensures good performance of the entire cascaded FEC solution.

[0302] Application Scenario 5: Figures 26A and 26B are schematic diagrams of another application scenario of data interleaving according to an embodiment of this application. As shown in Figures 26A and 26B, in this application scenario 5, Q=9 and d=16. Specifically, the delay outputs d=16 symbols from the rightmost storage element of each delay line, obtaining 32*16=512 symbols. Correspondingly, the symbols stored in the storage elements in each delay line are shifted rightward by d=16 symbols. Also, d=16 symbols are obtained from each of the 32 data streams and written separately into the leftmost storage elements of the 32 delay lines. A total of 32*16=512 symbols are written into the buffer of the interleaver and stored in 8 sub-buffers of the interleaver. Each sub-buffer stores 32*2=64 symbols, in other words, each sub-buffer stores one first symbol matrix. The interleaver interleaves the eight first symbol matrices separately to obtain eight second symbol matrices, each of which includes 4*16=64 symbols.

[0303] The 16 symbols from the data stream h (0 ≦ h < 32) output by the delay device are written to row h of the 8 sub-buffers of the interleaver. Specifically, it should be noted that 2 symbols are written to row h of each sub-buffer. The writing method is as follows: That is, symbol 0 and symbol 1 from the data stream h are separately written to row h of sub-buffer 0, symbol 2 and symbol 3 from the data stream h are separately written to row h of sub-buffer 1, symbol 4 and symbol 5 from the data stream h are separately written to row h of sub-buffer 2, symbol 6 and symbol 7 from the data stream h are separately written to row h of sub-buffer 3, symbol 8 and symbol 9 from the data stream h are separately written to row h of sub-buffer 4, symbol 10 and symbol 11 from the data stream h are separately written to row h of sub-buffer 5, symbol 12 and symbol 13 from the data stream h are separately written to row h of sub-buffer 6, and symbol 14 and symbol 15 from the data stream h are separately written to row h of sub-buffer 7. Another writing method is as follows: That is, symbol 0 and symbol 1 from the data stream h are separately written to row h of sub-buffer 7, symbol 2 and symbol 3 from the data stream h are separately written to row h of sub-buffer 6, symbol 4 and symbol 5 from the data stream h are separately written to row h of sub-buffer 5, symbol 6 and symbol 7 from the data stream h are separately written to row h of sub-buffer 4, symbol 8 and symbol 9 from the data stream h are separately written to row h of sub-buffer 3, symbol 10 and symbol 11 from the data stream h are separately written to row h of sub-buffer 2, symbol 12 and symbol 13 from the data stream h are separately written to row 1 of sub-buffer 6, and symbol 14 and symbol 15 from the data stream h are separately written to row h of sub-buffer 0. Also, the 2 symbols written to the sub-buffer once may be written to column 0 and column 1 of row h in the sub-buffer respectively, or may be written to column 1 and column 0 of row h in the sub-buffer respectively.

[0304] Each group of four symbols in each row of the 16 symbols of the second symbol matrix is from one group of four symbols in one column of the first symbol matrix, and it should be noted that each group of any two symbols in each row of the four-symbol groups of the second symbol matrix is from two groups of symbols in different rows of the first symbol matrix. In an implementable form, the 16 symbols in one row of the second symbol matrix correspond to the four symbols in group a of column 0 of the first symbol matrix, the four symbols in group b of column 0 of the first symbol matrix, the four symbols in group e of column 1 of the first symbol matrix, and the four symbols in group f of column 1 of the first symbol matrix, respectively, where a, b, e, and f are not equal to each other, 0 ≦ a < 4, 0 ≦ e < 4, 4 ≦ b < 8, and 4 ≦ f < 8.

[0305] Furthermore, the symbol at the i-th row and j-th column of the second symbol matrix corresponds to the symbol at row x%32 and column

Number

Number

Number

[0306]

Table 24

[0307] The interleaver outputs a total of 32 rows of symbols, with each row containing 16 symbols. The encoder separately performs FEC encoding on the 32 rows of symbols to obtain a total of 32 inner codewords. In an implementable form, Hamming(170, 160) is used for inner code encoding, and 32 * 170 = 5440 bits are obtained through inner code encoding.

[0308] In an implementable form, based on application scenario 8 where the interleaver outputs a total of 32 rows of symbols, the case where the interleaver outputs a total of 4, 8, 12, 16, 20, 24, or 28 rows of symbols can be further extended. In order to enable 16 symbols of each inner codeword information bit to be from 16 different outer codewords, it is necessary to satisfy Q * d ≥ 136, and Q * d is an even number.

[0309] In the scenario where the interleaver outputs a total of 8 rows of symbols, Q = 34 and d = 4. Specifically, the delay element outputs d = 4 symbols from the memory element at the right end of each delay line, obtaining 32 * 4 = 128 symbols. A total of 128 symbols are written into the buffer of the interleaver. The interleaver interleaves one first symbol matrix to obtain one second symbol matrix. According to the data interleaving method described in application scenario 1 above, the interleaver outputs a total of 8 rows of symbols, with each row containing 16 symbols. The encoder separately performs FEC encoding on the 8 symbol rows to obtain a total of 8 inner codewords. In an implementable form, inner code encoding is performed using Hamming(170, 160), and 8 * 170 = 1360 bits are obtained through inner code encoding.

[0310] In the scenario where the interleaver outputs symbols in a total of 16 rows, Q = 17 and d = 8. Specifically, the delay element outputs d = 8 symbols from the memory element at the right end of each delay line, obtaining 32 * 8 = 256 symbols. A total of 256 symbols are written into the buffer of the interleaver and stored in two sub-buffers of the interleaver. Each sub-buffer stores 128 symbols. In other words, each sub-buffer stores one first symbol matrix. The interleaver interleaves the two first symbol matrices separately to obtain two second symbol matrices, and each second symbol matrix contains 128 symbols. According to the data interleaving method described in the aforementioned application scenario 1, the interleaver outputs symbols in a total of 16 rows, and each row contains 16 symbols. The encoder separately performs FEC encoding on the 16 rows of symbols to obtain a total of 16 inner codewords. In an assumable implementation form, the inner code encoding is performed using Hamming(170, 160), and 16 * 170 = 2720 bits are obtained by the inner code encoding.

[0311] In application scenario 5, there are 32 delay lines in the convolutional interleaver, the maximum delay is 3Q * d = 432 symbols, and the delay is low. When Hamming(170, 160) is used for the inner code encoding, each Hamming information bit has a total of 16 symbols. In the case of a 1 * 800G interface, 2 * 400G interface, 4 * 200G interface, or 8 * 100G interface with 100Gb / s per lane on the client side, the 16 symbols within each Hamming information bit are from 16 different outer codewords. This ensures good performance of the overall cascaded FEC solution.

[0312] Application scenario 6: FIG. 27 is a schematic diagram of yet another application scenario of data interleaving according to an embodiment of this application. As shown in FIG. 27, A = 2, B = 136, n = 8, p = 8, g = 1. Specifically, the transmitting device performs KP4RS(544, 514) outer code encoding on the service data stream to be transmitted in order to obtain 8 PCS lane data streams, and distributes them to 8 lane data streams for every two outer code words. Specifically, in the 8 PCS lane data streams, each data stream is separated by 136 symbols, and there are a total of 1088 symbols including two RS code words. Two adjacent symbols within each PCS lane data stream are from two different RS code words, and two symbols at the same position in two adjacent PCS lane data streams are from two different RS code words. The 8 data streams respectively correspond to 8 delay lines. The delay line includes 0, Q, 2Q, 3Q, 4Q, 5Q, 6Q, or 7Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, 3V symbols, 4V symbols, 5V symbols, 6V symbols, or 7V symbols, where V = Q * d ≧ 136. d symbols are output from each delay line in one delay operation. When d ≦ L * m, φ delay operations can be repeatedly performed to obtain φ * d symbols, where φ * d ≧ L * m and φ is a positive integer. For ease of hardware implementation, the integer d is usually selected as a multiple of the integer m. It should be understood that the structural distribution of the 8 delay lines in FIG. 27 is merely an example and can be changed based on the methods described in FIGS. 19 and 20. Details are not described again in this specification.

[0313] As shown in FIG. 27, in this embodiment, L = 3, d = 6, Q = 23, m = 2, and c = 16 are used. The interleaver obtains 6 symbols from each of the 8 delayed data streams in order to obtain 3 first symbol matrices. Each first symbol matrix includes a total of 16 symbols in 8 rows and 2 columns, and each second symbol matrix includes a total of 16 symbols in 1 row and 16 columns. The 16 symbols in one row of the second symbol matrix are from the 8 rows and 2 columns of the first symbol matrix. A possible interleaving rule is that the symbol in column j of the second symbol matrix corresponds to the symbol in row x%8 and column

Number

Number

Number

Number

[0314] The foregoing example provides an implementation form with L = 3. Based on this, the implementation form with L ≥ 1 can be further extended. This is an extension of the application scenario. For specific implementation forms, please refer to the foregoing description. Details will not be described again in this specification. Several typical parameter combinations are provided below.

[0315] L = 1, d = 2, Q = 68, V = Q * d = 136. The interleaver outputs L 1 * 16 second symbol matrices, where L = 1, and inner code encoding is performed to obtain one inner codeword.

[0316] L = 2, d = 4, Q = 34, V = Q * d = 136. The interleaver outputs L 1 * 16 second symbol matrices, where L = 2, and inner code encoding is performed to obtain two inner codewords.

[0317] L = 4, d = 8, Q = 17, V = Q * d = 136. The interleaver outputs L 1 * 16 second symbol matrices, where L = 4, and inner code encoding is performed to obtain four inner codewords.

[0318] L = 5, d = 10, Q = 14, V = Q * d = 140. The interleaver outputs L 1 * 16 second symbol matrices, where L = 5, and inner code encoding is performed to obtain five inner codewords.

[0319] L = 6, d = 12, Q = 12, V = Q * d = 144. The interleaver outputs L 1 * 16 second symbol matrices, where L = 6, and inner code encoding is performed to obtain six inner codewords.

[0320] L = 7, d = 14, Q = 10, V = Q * d = 140. The interleaver outputs L 1 * 16 second symbol matrices, where L = 7, and inner code encoding is performed to obtain seven inner codewords.

[0321] L = 8, d = 16, Q = 9, and V = Q * d = 144. The interleaver outputs L = 8 second symbol matrices of 1 * 16, and inner code encoding is performed to obtain 8 inner codewords.

[0322] In application scenario 6, when Hamming(170, 160) is used to perform inner code encoding, the total 16 symbols within each Hamming information bit are from 16 different outer codewords. Therefore, the performance of the overall cascade FEC solution is good. When BCH(176, 160) is used to perform inner code encoding, the total 16 symbols of each BCH information bit are from 16 different outer codewords. Therefore, the performance of the overall cascade FEC solution is good.

[0323] Application scenario 7: FIG. 28 is a schematic diagram of yet another application scenario of data interleaving according to an embodiment of this application. As shown in FIG. 28, A = 2, B = 136, n = 8, p = 8, and g = 1. The eight data streams respectively correspond to eight delay lines. The delay lines include 0, Q, 2Q, 3Q, 4Q, 5Q, 6Q, or 7Q memory elements D, and each memory element D may store d symbols. In other words, the delay values of the delay lines may be 0, V symbols, 2V symbols, 3V symbols, 4V symbols, 5V symbols, 6V symbols, or 7V symbols, where V = Q * d ≥ 136. It should be understood that the structural distribution of the eight delay lines in FIG. 28 is merely an example and can be changed based on the methods described in FIGS. 19 and 20. Details will not be described again in this specification.

[0324] Unlike Application Scenario 6, in this embodiment, as shown in FIG. 28, L = 2, d = 6, Q = 23, m = 3, and c = 12 are used. The interleaver obtains 6 symbols from each of the 8 delayed data streams to obtain two first symbol matrices. Each first symbol matrix contains a total of 24 symbols in 8 rows and 3 columns, and each second symbol matrix contains a total of 24 symbols in 2 rows and 12 columns. Twelve symbols in one row of the second symbol matrix are from 12 of the 16 symbols in two columns of the first symbol matrix. A possible interleaving rule is that the symbol in row i and column j of the second symbol matrix corresponds to the symbol in row x%8 and column [Number] such that x = i * 12 + j, 0 ≤ i < 2, 0 ≤ j < 16, where Y%Z represents the remainder obtained by dividing Y by Z, [Number] and [Number] represents the quotient obtained by dividing Y by Z. After the interleaver outputs two second symbol matrices, the inner code encoding device performs inner code encoding on the 12 symbols in each row of the two second symbol matrices to obtain 4 inner codewords. When Hamming(128, 120) is used for inner code encoding, inner code encoding is performed on the 48 symbols of a total of 480 bits output by the interleaver, and 4 inner codewords of a total of 4 * 128 = 512 bits can be obtained.

[0325] The above example provides an implementation form with L = 2. Based on this, the implementation form with L ≥ 1 can be further extended. This is an extension of the application scenario. For specific implementation forms, please refer to the above description. Details will not be described again in this specification. Some typical parameter combinations are provided below.

[0326] When L = 1, d = 3, Q = 46, and V = Q * d = 138. The interleaver outputs L2 * 12 second symbol matrices. Since L = 1, inner code encoding is performed to obtain two inner codewords.

[0327] When L = 3, d = 9, Q = 16, and V = Q * d = 144. The interleaver outputs L2 * 12 second symbol matrices. Since L = 3, inner code encoding is performed to obtain six inner codewords.

[0328] When L = 4, d = 12, Q = 6, and V = Q * d = 144. The interleaver outputs L2 * 12 second symbol matrices. Since L = 4, inner code encoding is performed to obtain eight inner codewords.

[0329] When L = 5, d = 15, Q = 10, and V = Q * d = 150. The interleaver outputs L * 2 * 12 second symbol matrices. Since L = 5, inner code encoding is performed to obtain ten inner codewords.

[0330] When L = 6, d = 18, Q = 8, and V = Q * d = 144. The interleaver outputs L2 * 12 second symbol matrices. Since L = 6, inner code encoding is performed to obtain twelve inner codewords.

[0331] When L = 7, d = 21, Q = 7, and V = Q * d = 147. The interleaver outputs L2 * 12 second symbol matrices. Since L = 7, inner code encoding is performed to obtain fourteen inner codewords.

[0332] When L = 8, d = 24, Q = 6, and V = Q * d = 144. The interleaver outputs L2 * 12 second symbol matrices. Since L = 8, inner code encoding is performed to obtain sixteen inner codewords.

[0333] In Application Scenario 7, when Hamming(128, 120) is used to perform inner code encoding, the total 12 symbols in each Hamming information bit are from 12 different outer codewords. Therefore, the performance of the overall cascaded FEC solution is good.

[0334] It should be noted that the aforementioned Application Scenarios 6 and 7 provide cases where the inner code information symbol length c is 16 and 12 symbols, and other cases where the inner code information symbol length is 9, 10, 11, 13, 14, and 15 can be further extended. After 8 data streams are delayed, the 16 symbols output each time are from 16 different RS codeword symbols. The 16 symbols are from 8 delayed data streams, and each data stream provides 2 symbols. In relation to the aforementioned features, the interleaver may be designed such that the c symbols output by the interleaver in each row are from c different RS codeword symbols. One interleaving method is that the first symbol matrix includes 8 rows and m columns, the second symbol matrix includes r rows and c columns, and 8 * m = r * c. The c symbols in one row of the second symbol matrix are from c of the total 16 symbols in 2 columns of the first symbol matrix. The following provides a specific interleaving method. The c symbols are sequentially obtained from the 8 * m symbols in the first symbol matrix from top to bottom and then left to right as one row of the second symbol matrix, and a total of r rows of the second symbol matrix are obtained. More specifically, the following provides some typical parameter combinations: {m = 9, r = 8 * g, c = 9}, {m = 5, r = 4 * g, c = 10}, {m = 11, r = 8 * g, c = 11}, {m = 13, r = 8 * g, c = 13}, {m = 7, r = 4 * g, c = 14}, and {m = 15, r = 8 * g, c = 15}.

[0335] Applicable Scenario 8: FIG. 29 is a schematic diagram of yet another applicable scenario of data interleaving according to an embodiment of this application. As shown in FIG. 29, A = 2, B = 68, n = 16, p = 8, and g = 2. Specifically, the transmitting device performs KP4RS(544, 514) outer code encoding on the service data stream to be transmitted to obtain 16 PCS lane data streams, which are distributed to 16 lane data streams for every two outer codewords. Specifically, in the 16 PCS lane data streams, each data stream is separated by 68 symbols, and there are a total of 1088 symbols including two RS codewords. Two adjacent symbols within each PCS lane data stream are from two different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from two different RS codewords. The 16 data streams respectively correspond to 16 delay lines. The delay device includes 16 delay lines, which can be divided into two groups of delay lines. One group is formed by every 8 delay lines. Each group of delay lines includes 0, Q, 2Q, 3Q, 4Q, 5Q, 6Q, or 7Q memory elements D, and each memory element D may store d symbols. In other words, the delay value of the delay line may be 0, V symbols, 2V symbols, 3V symbols, 4V symbols, 5V symbols, 6V symbols, or 7V symbols, where V = Q * d ≧ 68. d symbols are output from each delay line in one delay operation. When d ≦ L * m, φ delay operations can be repeatedly performed to obtain φ * d symbols, where φ * d ≧ L * m and φ is a positive integer. For ease of hardware implementation, the integer d is usually selected as a multiple of the integer m. It should be understood that the structural distribution of each group of the 8 delay lines in FIG. 29 is merely an example and can be changed based on the methods described in FIGS. 19 and 20. Details will not be described again in this specification.

[0336] As shown in Fig. 29, in this embodiment, L = 3, d = 6, Q = 12, m = 2, and c = 16 are used. The interleaver obtains 6 symbols from each of the 16 delayed data streams and obtains 3 first symbol matrices. The first symbol matrix includes 2 first symbol sub - matrices, and each first symbol sub - matrix includes a total of 16 symbols in 8 rows and 2 columns. Correspondingly, the second symbol matrix includes 2 second symbol sub - matrices, and each second symbol sub - matrix includes a total of 16 symbols in 1 row and 16 columns. For the two groups of the interleaver, each group of the interleaver interleaves 3 first symbol sub - matrices into 3 second symbol sub - matrices. The 16 symbols in 1 row of the second symbol sub - matrix are from the 8 rows and 2 columns of the first symbol sub - matrix. A possible interleaving rule is that the symbol in column j of the second symbol sub - matrix corresponds to the symbol in row x%8 and column

Number

Number

Claims

1. Separately delaying n data streams based on n delay lines, where n is a positive integer divisible by p, p is an integer greater than 1, the delay value of each delay line is any delay value within a set of delay values, the set of delay values contains p delay values, the minimum delay value within the set of delay values is 0, the difference between two adjacent delay values among the p delay values in the set of delay values set in ascending order is V symbols, V is an integer of 34 or more, and the number of delay lines corresponding to each delay value within the set of delay values is n / p; Obtaining L*m symbols from each of the n delayed data streams to obtain L sets of first symbols, where each set of first symbols contains n*m symbols, L is an integer of 1 or more, and m is an integer of 1 or more; Separately interleaving the L sets of first symbols to obtain L sets of second symbols, where the number of symbols in each set of second symbols is the same as the number of symbols in each set of first symbols; comprising A data interleaving method, where p = 4, n is divisible by 16, the n delay lines include at least one group of delay lines, and each group of delay lines includes 16 adjacent delay lines.

2. Delay line a within delay line group k in the n delay lines 0 , delay line a 1 , delay line a 2 , delay line a 3 , delay line a 4 , delay line a 5 , delay line a 6 , delay line a 7 , delay line a 8 , delay line a 9 , delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 and delay line a 15 satisfy the first condition, 0 ≦ k < n / 16, and a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , a 7 , a 8 , a 9 , a 10 , a 11 , a 12 , a 13 , a 14 and a 15 are non - negative integers less than 16, not equal to each other, and the first condition is Delay line a 0 between the delay value of 1 and the delay value of delay line a is a 2V symbol, Delay line a 2 The delay value of and delay line a 3 The difference between the delay values is 2V symbols, Delay line a 4 between the delay value of 5 and the delay value of delay line a is 2V symbol Delay line a 6 The delay value of and delay line a 7 The difference between the delay values of is a 2V symbol, Delay line a 8 between the delay value of 9 and the delay value of delay line a is 2V symbols, Delay line a 10 The delay value of and delay line a 11 The difference between the delay values is 2V symbols, Delay line a 12 between the delay value of 13 and the delay value of delay line a is 2V symbols, Delay line a 14 The delay value of and delay line a 15 The difference between the delay values is 2V symbols, The method according to claim 1, wherein...

3. In each group of delay lines among the n delay lines, the number of delay lines with delay values of 0 symbol, V symbols, 2V symbols, and 3V symbols is all 4. The method according to claim 2.

4. Delay line a within delay line group k in the n delay lines 0 , delay line a 1 , delay line a 2 , delay line a 3 , delay line a 4 , delay line a 5 , delay line a 6 , delay line a 7 , delay line a 8 , delay line a 9 , delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 and the delay value of delay line a 15 satisfies the second condition, The second condition is that the delay value of delay line a 0 the delay value of delay line a 4 the delay value of delay line a 8 the delay value of delay line a 12 are not equal to each other, and the delay value of delay line a 1 the delay value of delay line a 5 the delay value of delay line a 9 the delay value of delay line a 13 are not equal to each other, and the delay value of delay line a 2 the delay value of delay line a 6 the delay value of delay line a 10 the delay value of delay line a 14 are not equal to each other, and the delay value of delay line a 3 the delay value of delay line a 7 the delay value of delay line a 11 the delay value of delay line a 15 are not equal to each other. The method according to claim 2.

5. Delay line a within delay line group k in the n delay lines 0 , delay line a 2 , delay line a 4 , delay line a 6 , delay line a 8 , delay line a 10 , delay line a 12 and the delay value of delay line a 14 satisfies the third condition The third condition is that the delay value of delay line a 0 and the delay value of delay line a 4 have a difference of 2V symbols, and the delay value of delay line a 2 and the delay value of delay line a 6 have a difference of 2V symbols, and the delay value of delay line a 8 and the delay value of delay line a 12 have a difference of 2V symbols, and the delay value of delay line a 10 and the delay value of delay line a 14 have a difference of 2V symbols The method according to claim 2.

6. The first set of delay values {A} is for the delay lines a within the delay line group k in the n delay lines 0 , delay line a 1 , delay line a 2 , delay line a 3 , delay line a 4 , delay line a 5 , delay line a 6 , delay line a 7 , delay line a 8 , delay line a 9 , delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 , and the delay line a 15 sequentially includes the delay values, and the first set of delay values {A} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, V, 3V, 2V, 0, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {0, 2V, 3V, V, 2V, 0, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 0, 2V, 3V, V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {V, 3V, 2V, 0, 3V, V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 0, 2V, 3V, V, 2V, 0} {2V, 0, V, 3V, 0, 2V, 3V, V, V, 3V, 2V, 0, 3V, V, 0, 2V} {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 0, 2V, V, 3V, 2V, 0} {2V, 0, V, 3V, 0, 2V, 3V, V, 3V, V, 2V, 0, V, 3V, 0, 2V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 0, 2V, 3V, V, 2V, 0} {2V, 0, 3V, V, 0, 2V, V, 3V, V, 3V, 2V, 0, 3V, V, 0, 2V} {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 0, 2V, V, 3V, 2V, 0} {2V, 0, 3V, V, 0, 2V, V, 3V, 3V, V, 2V, 0, V, 3V, 0, 2V} {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, V, 3V, 2V, 0, 3V, V} {3V, V, 0, 2V, V, 3V, 2V, 0, 0, 2V, 3V, V, 2V, 0, V, 3V} {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, V, 3V, 0, 2V, 3V, V} {3V, V, 0, 2V, V, 3V, 2V, 0, 2V, 0, 3V, V, 0, 2V, V, 3V} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0} {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, V, 3V, 2V, 0, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 0, 2V, 3V, V, 2V, 0, V, 3V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, V, 3V, 0, 2V, 3V, V} {3V, V, 2V, 0, V, 3V, 0, 2V, 2V, 0, 3V, V, 0, 2V, V, 3V} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} The method according to claim 2, comprising one of the above.

7. Delay line a within delay line group k in the n delay lines 0 , delay line a 1 , delay line a 2 , delay line a 3 , delay line a 4 , delay line a 5 , delay line a 6 , delay line a 7 , delay line a 8 , delay line a 9 , delay line a 10 , delay line a 11 , delay line a 12 , delay line a 13 , delay line a 14 and the delay value of delay line a 15 satisfies the fourth condition The fourth condition is that the delay value of the delay line a 0 and the delay value of the delay line a 2 are equal or have a difference of 2V symbols, Delay line a 1 The delay value of and delay line a 3 The delay value of is equal to or has a difference of 2V symbols, Delay line a 2 and the delay value of 4 the delay line a are equal or have a difference of 2V symbols, Delay line a 3 The delay value of and delay line a 5 The delay value of is equal to or has a difference of 2V symbols, Delay line a 4 The delay value of and the delay line a 6 The delay value of are equal or have a difference of 2V symbols, Delay line a 5 The delay value of and delay line a 7 The delay value of is equal to or has a difference of 2V symbols, Delay line a 8 The delay value of and delay line a 10 The delay value of is equal to or has a difference of 2V symbols, Delay line a 9 The delay value of and delay line a 11 The delay value of is equal to or has a difference of 2V symbols, Delay line a 10 The delay value of and the delay line a 12 The delay value of are equal or have a difference of 2V symbols, Delay line a 11 The delay value of and delay line a 13 The delay value of is equal to or has a difference of 2V symbols, Delay line a 12 The delay value of and delay line a 14 The delay value of is equal to or has a difference of 2V symbols, Delay line a 13 The delay value of and delay line a 15 The delay value of is equal to or has a difference of 2V symbols The method according to claim 2, wherein...

8. The second delay value set {B} is for the delay line a within the delay line group k in the n delay lines 0 , the delay line a 1 , the delay line a 2 , the delay line a 3 , the delay line a 4 , the delay line a 5 , the delay line a 6 , the delay line a 7 , the delay line a 8 , the delay line a 9 , the delay line a 10 , the delay line a 11 , the delay line a 12 , the delay line a 13 , the delay line a 14 , and the delay line a 15 sequentially includes the delay values, and the second delay value set {B} is {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 0, 2V, 2V, 0, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V} {0, 2V, 2V, 0, 2V, 0, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0} {V, 3V, V, 3V, 3V, V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V} {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {V, 3V, V, 3V, 3V, V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {V, 3V, 3V, V, 3V, V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {V, 3V, 3V, V, 3V, V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 0, 2V, 0, 2V, 2V, 0, 3V, V, 3V, V, V, 3V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, V, 3V, 3V, V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, V, 3V, 3V, V, 3V, V, V, 3V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, V, 3V, V, 3V, 3V, V}, {2V, 0, 2V, 0, 0, 2V, 0, 2V, 3V, V, 3V, V, V, 3V, V, 3V}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, {3V, V, V, 3V, V, 3V, 3V, V, 2V, 0, 2V, 0, 0, 2V, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 0, 2V, 2V, 0, 2V, 0}, {3V, V, 3V, V, V, 3V, V, 3V, 0, 2V, 2V, 0, 2V, 0, 0, 2V}, {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 0, 2V, 0, 2V, 2V, 0}, and {3V, V, 3V, V, V, 3V, V, 3V, 2V, 0, 2V, 0, 0, 2V, 0, 2V} The method according to claim 7, comprising one of the above.

9. The sequential number value set {C} includes the values of a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 and a 15 in sequence, and the sequential number value set {C} is ｛0、1、2、3、4、5、6、7、8、9、10、11、12、13、14、15｝、 ｛0、1、2、3、4、5、6、7、8、9、10、11、14、15、12、13｝、 ｛0、1、2、3、4、5、6、7、10、11、8、9、12、13、14、15｝、 ｛0、1、2、3、4、5、6、7、10、11、8、9、14、15、12、13｝、 ｛0、1、2、3、6、7、4、5、8、9、10、11、12、13、14、15｝、 ｛0、1、2、3、6、7、4、5、8、9、10、11、14、15、12、13｝、 ｛0、1、2、3、6、7、4、5、10、11、8、9、12、13、14、15｝、 ｛0、1、2、3、6、7、4、5、10、11、8、9、14、15、12、13｝、 ｛2、3、0、1、4、5、6、7、8、9、10、11、12、13、14、15｝、 ｛2、3、0、1、4、5、6、7、8、9、10、11、14、15、12、13｝、 ｛2、3、0、1、4、5、6、7、10、11、8、9、12、13、14、15｝、 ｛2、3、0、1、4、5、6、7、10、11、8、9、14、15、12、13｝、 ｛2、3、0、1、6、7、4、5、8、9、10、11、12、13、14、15｝、 ｛2、3、0、1、6、7、4、5、8、9、10、11、14、15、12、13｝、 ｛2、3、0、1、6、7、4、5、10、11、8、9、12、13、14、15｝、 ｛2、3、0、1、6、7、4、5、10、11、8、9、14、15、12、13｝、 ｛0、3、1、2、4、7、5、6、8、11、9、10、12、15、13、14｝、 ｛0、3、1、2、4、7、5、6、8、11、9、10、13、14、12、15｝、 ｛0、3、1、2、4、7、5、6、9、10、8、11、12、15、13、14｝、 ｛0、3、1、2、4、7、5、6、9、10、8、11、13、14、12、15｝、 ｛0、3、1、2、5、6、4、7、8、11、9、10、12、15、13、14｝、 ｛0、3、1、2、5、6、4、7、8、11、9、10、13、14、12、15｝、 ｛0、3、1、2、5、6、4、7、9、10、8、11、12、15、13、14｝、 ｛0、3、1、2、5、6、4、7、9、10、8、11、13、14、12、15｝、 ｛1、2、0、3、4、7、5、6、8、11、9、10、12、15、13、14｝、 ｛1、2、0、3、4、7、5、6、8、11、9、10、13、14、12、15｝、 ｛1、2、0、3、4、7、5、6、9、10、8、11、12、15、13、14｝、 ｛1、2、0、3、4、7、5、6、9、10、8、11、13、14、12、15｝、 ｛1、2、0、3、5、6、4、7、8、11、9、10、12、15、13、14｝、 ｛1、2、0、3、5、6、4、7、8、11、9、10、13、14、12、15｝、 {1, 2, 0, 3, 5, 6, 4, 7, 9, 10, 8, 11, 12, 15, 13, 14}, and ｛1、2、0、3、5、6、4、7、9、10、8、11、13、14、12、15｝ The method according to claim 2, comprising one of the following.

10. Each first symbol set includes n first symbol subsets, each first symbol subset includes m symbols arranged in sequence, and Each second symbol set includes r second symbol subsets, each second symbol subset includes c symbols, r is an integer greater than 1, c is an integer greater than 1, n * m = r * c, and the c symbols in each second symbol subset correspond to the c symbols distributed in c first symbol subsets in the first symbol set. The method according to claim 1.

11. The m symbols in the first symbol subset h in the first symbol set are from the delay data stream h, 0 ≦ h ≦ n - 1, and V is an integer of 68 or more. The method according to claim 1.

12. Each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of n rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, and the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix. The method according to claim 1.

13. The n delay lines include g delay line groups, each delay line group includes p delay lines, the delay values of the p delay lines in each delay line group are respectively the p delay values in the delay value set, each first symbol set is a first symbol matrix, each first symbol matrix includes symbols of n rows and m columns, each second symbol set is a second symbol matrix, each second symbol matrix includes symbols of r rows and c columns, the c symbols in each row of the second symbol matrix correspond to the c symbols distributed in c rows of the first symbol matrix, and g is an integer greater than 1. The method according to claim 1.

14. A first forward error correction (FEC) encoding is performed on all of the n data streams, and all A codewords obtained by the first FEC encoding are distributed to the n data streams, and A consecutive symbols within each data stream are from A different first FEC codewords, where A is an integer greater than or equal to 1, the n delay lines include g groups of delay lines, each group of delay lines includes p delay lines, the delay values of the p delay lines within each group of delay lines are respectively the p delay values within the delay value set, g is an integer greater than or equal to 1, n = p * g, and A * p symbols within each delayed group of p data streams are from A * p different first FEC codewords, and the A * p symbols include A consecutive symbols of each of the p data streams. The method according to claim 1.

15. A data interleaving device comprising a delay device and an interleaver, wherein the data interleaving device is configured to implement the method according to any one of claims 1 to 14. The data interleaving device.

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