Light-emitting device and image forming apparatus

Abstract

To provide a light emitting device which can improve a degree of freedom in arrangement of a light emitting part as compared with a case that wiring to each light emitting part is same when the light emitting device includes a plurality of light emitting parts.SOLUTION: A light emitting device includes a plurality of first light emitting parts arranged along a first direction at an interval, a second light emitting part arranged in a position deviated from each of the first light emitting parts along a second direction and the first direction, first wiring 301 which is electrically connected to each first light emitting part on a semiconductor layer, and second wiring 302 electrically connected to each second light emitting part, the second wiring 302 being arranged with an insulation layer 303 interposed therebetween.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a light-emitting device and an image forming apparatus.

Background Art

[0002] Regarding a light-emitting device such as a latent image forming device or a charge eliminating device for forming a latent image in an image forming apparatus, the technique described in Patent Document 1 below has been conventionally known.

[0003] Patent Document 1 describes a configuration in which a first light-emitting element row and a second light-emitting element row are arranged in a staggered manner in a light-emitting element head, and a light-emitting signal is supplied to odd-numbered light-emitting thyristors from a φI terminal, and to even-numbered light-emitting thyristors from a φIe terminal. As described in FIG. 6 of Patent Document 1, the wiring leading to odd-numbered light-emitting thyristors is arranged so as to pass between even-numbered light-emitting thyristors.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When there are a plurality of light-emitting units, the technical problem of the present invention is to improve the degree of freedom compared to the case where the wiring to each light-emitting unit is the same.

Means for Solving the Problems

[0006] In order to solve the above technical problem, the light-emitting device according to the invention described in claim 1 is a plurality of first light-emitting units arranged at intervals along a predetermined first direction, A plurality of second light-emitting portions arranged at intervals along the first direction, the second light-emitting portions being arranged at positions shifted from the first light-emitting portion with respect to a second direction intersecting the first direction and being arranged at positions shifted with respect to each of the first light-emitting portions along the first direction. For each of the first light-emitting portions, a first wiring electrically connected by a semiconductor layer. A second wiring electrically connected to each of the second light-emitting portions, the second wiring being arranged with an insulating layer interposed therebetween and the substrate in a third direction intersecting the first direction and the second direction with respect to a portion passing between the first light-emitting portions. a first control element that outputs a control signal for controlling the blinking of the first light-emitting unit through the first wiring; a second control element that outputs a control signal for controlling the blinking of the second light-emitting unit through the second wiring; Comprising 、 adjusting the currents flowing through the first control element and the second control element according to the difference in the parasitic capacitance between the first wiring and the second wiring Characterized in that.

[0007] In order to solve the above technical problem, Claim 2 The light-emitting device according to the invention described in A first light-emitting portion, A second light-emitting portion, A first wiring electrically connected to the first light-emitting portion, the first wiring being arranged facing the first layer, A second wiring electrically connected to the second light-emitting portion, a portion of the second wiring arranged facing a second layer that is less conductive to current than the first layer being between the substrate and a portion passing between the first light-emitting portions. A first control element that outputs a control signal for controlling the blinking of the first light-emitting portion through the first wiring, A second control element that outputs a control signal for controlling the blinking of the second light-emitting portion through the second wiring, Comprising The difference in the lighting timings of the first light-emitting portion and the second light-emitting portion caused by the difference between the first wiring and the second wiring is adjusted by adjusting the current flowing through the first control element and the second control element. characterized by the following.

[0008] Claim 3 The invention described in Claim 2 in the light-emitting device described in a plurality of first light-emitting units, a plurality of second light-emitting units, characterized by comprising.

[0009] Claim 4 The invention described in Claim 2 or 3 in the light-emitting device described in The adjustment is an adjustment such that the current flowing through the second wiring is delayed.

[0010] To solve the above technical problem, Claim 5 the light-emitting device of the invention described in a substrate, a first light-emitting unit including a thyristor structure in which a semiconductor is stacked on the substrate, a second light-emitting unit having the same layer structure as the first light-emitting unit on the substrate, a first wiring electrically connected to the gate layer of the thyristor structure of the first light-emitting unit, the first wiring being disposed facing the gate layer, a second wiring electrically connected to the gate layer of the thyristor structure of the second light-emitting unit, the portion of the second wiring facing the high-permittivity layer outside the thyristor structure being disposed between the substrate and the portion passing between the first light-emitting units, a first control element that outputs a control signal for controlling the blinking of the first light-emitting unit through the first wiring, a second control element that outputs a control signal for controlling the blinking of the second light-emitting unit through the second wiring, comprising 、 there are a plurality of the first light-emitting units and the second light-emitting units, the difference in the lighting timings of the first light-emitting unit and the second light-emitting unit caused by the difference between the first wiring and the second wiring is adjusted by adjusting the currents flowing through the first control element and the second control element this characterized by the above.

[0011] Claim 6 The invention described inClaims 1 to 5 In the light-emitting device according to any one of a first connection line to which all of the first control elements are electrically connected; a second connection line to which all of the second control elements are electrically connected; a first resistance element connected to the first connection line; a second resistance element connected to the second connection line, the second resistance element having a resistance value different from that of the first resistance element, characterized by comprising.

[0012] Claim 7 The invention described in Claim 6 In the light-emitting device according to making the resistance value of the first resistance element larger than the resistance value of the second resistance element characterized by.

[0013] Claim 8 The invention described in Claims 1 to 5 In the light-emitting device according to any one of each light-emitting part constituted by a light-emitting thyristor; each control element constituted by a transistor; characterized by comprising adjusting the area of a metal wiring on a gate semiconductor that connects the collector of each control element and the gate of each light-emitting part characterized by.

[0014] Claim 9 The invention described in Claims 1 to 5 In the light-emitting device according to any one of each control element constituted by a transistor characterized by comprising adjusting the collector current of each control element when it is on characterized by.

[0015] Claim 10 The invention described in Claim 9 In the light-emitting device according to a first connection line to which all of the first control elements are electrically connected; A second connection line to which all of the second control elements are electrically connected, A first resistor element connected to the first connection line, A second resistor element connected to the second connection line, wherein the resistance value with respect to the first resistor element is adjusted according to the collector current, Characterized by comprising.

[0016] Claim 11 The invention according to [reference number], Claim 9 In the light-emitting device according to [reference number], Adjusting the transistor characteristics of the second control element with respect to the transistor characteristics of the first control element according to the collector current Characterized by.

[0017] Claim 12 The invention according to [reference number], Claim 11 In the light-emitting device according to [reference number], Adjusting the transistor characteristics by adjusting the length in the width direction intersecting the longitudinal direction of the wiring Characterized by.

[0018] Claim 13 The invention according to [reference number], Claim 11 In the light-emitting device according to [reference number], Adjusting the transistor characteristics by adjusting the distance between the set thyristor that generates a signal and is connected to the transistor and the transistor Characterized by.

[0019] In order to solve the above technical problem, Claim 14 The image forming apparatus according to the invention described in [reference number], An image holding means, A charging means for charging the surface of the image holding means, A latent image forming apparatus configured by the light-emitting device according to any one of claims 1 to 13 for forming a latent image on the charged image holding means, and Characterized by comprising.

Advantages of the Invention

[0020] According to the invention described in claim 1, 2,5,14 when there are a plurality of light emitting units, the degree of freedom can be improved as compared with the case where the wirings to each light emitting unit are the same. Also, Claim 1 According to the invention described in claim 1, the difference in the light emission timings of each light emitting unit can be suppressed as compared with the case where the currents flowing through the first control element and the second control element are not adjusted according to the difference in the parallel capacitances between the first wiring and the second wiring. Claim 3 According to the invention described in claim 1, the complication of the configuration can be suppressed as compared with the case where the lighting timing is changed for each light emitting unit.

[0021] Claim 4 According to the invention described in claim 1, the difference in the light emission timings between the first light emitting unit and the second light emitting unit can be suppressed by delaying the signal flowing through the second wiring with less delay. Also, Claim 5 According to the invention described in claim 1, in a plurality of light emitting units, the difference in the light emission timings of the light emitting units can be suppressed. Claim 6 According to the invention described in claim 1, the difference in the light emission timings between the first light emitting unit and the second light emitting unit can be suppressed by making the resistance values of the second resistance element and the first resistance element different.

[0022] Claim 7 According to the invention described in claim 1, the time constant of the first connection line can be made larger than the time constant of the second connection line, and the delay on the first connection line side can be increased. Claim 8 According to the invention described in claim 1, the area of the metal wiring can be increased to increase the parasitic capacitance and increase the delay. Claim 9 According to the invention described in claim 1, the lighting delay can be adjusted by adjusting the collector current when the transistor is on. Claim 10 According to the invention described in claim 1, the collector current can be adjusted by making the resistance values of the second resistance element and the first resistance element different, and the difference in the light emission timings between the first light emitting unit and the second light emitting unit can be suppressed.

[0023] Claim 11 According to the invention described in , the collector current can be adjusted by adjusting the transistor characteristics, and the difference in the light emission timings between the first light emitting section and the second light emitting section can be suppressed. Claim 12 According to the invention described in , the transistor characteristics can be adjusted by adjusting the length in the width direction, and the collector current can be adjusted. Claim 13 According to the invention described in , the collector current can be adjusted by adjusting the distance between the set thyristor and the transistor.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Best Mode for Carrying Out the Invention

[0025] Next, with reference to the drawings, examples as specific examples of embodiments of the present invention will be described, but the present invention is not limited to the following examples. For the ease of understanding the following description, in the drawings, the front-rear direction (width direction of the medium) is the X-axis direction, the left-right direction (conveying direction of the medium) is the Y-axis direction, and the up-down direction is the Z-axis direction. The directions or sides indicated by the arrows X, -X, Y, -Y, Z, -Z are respectively the front, rear, right, left, upper, lower, or front side, rear side, right side, left side, upper side, lower side. In addition, in the figures, those with "·" in "○" mean arrows from the back to the front of the paper surface, and those with "×" in "○" mean arrows from the front to the back of the paper surface. In the following description using the drawings, for the ease of understanding, illustrations other than the members necessary for the description are appropriately omitted.

Example

[0026] (Description of the overall configuration of the printer U in Example 1) FIG. 1 is an overall explanatory view of the image forming apparatus according to Example 1. In FIG. 1, as an example of the image forming apparatus according to Example 1 of the present invention, a printer U includes a printer main body U1, a feeder unit U2 as an example of a supply device for supplying a medium to the printer main body U1, an operation unit UI for a user to perform operations, and a finisher U3 as an example of a post-processing device for post-processing the medium discharged from the printer main body U1.

[0027] (Description of the marking configuration in Example 1) In FIG. 1, the main body U1 of the printer includes a control unit C (an example of control means) that controls the printer U, and a communication unit (not shown) that receives image information transmitted from a print image server COM, which is an example of an information transmission device connected to the outside of the printer U via a dedicated cable (not shown). The main body U1 also includes a marking unit U1a, which is an example of a recording means for recording an image on a medium. The print image server COM is connected via a cable or a line such as a LAN (Local Area Network), and a personal computer PC, which is an example of an image transmission device that transmits information on an image to be printed by the printer U, is connected thereto. The marking unit U1a includes photoreceptors Py, Pm, Pc, Pk for each color of Y (yellow), M (magenta), C (cyan), and K (black) as an example of image holding means, and a photoreceptor Po for giving gloss to an image when printing a photographic image or the like. The photoreceptors Py to Po are each configured with a dielectric whose surface is photosensitive.

[0028] In FIG. 1, around the black photoreceptor Pk, along the rotation direction of the photoreceptor Pk, a charger CCk, which is an example of a charging means, an exposure device LPHk, which is an example of a latent image forming means, a developing device Gk, which is an example of a developing means, a primary transfer roll T1k, which is an example of a primary transfer means, and a photoreceptor cleaner CLk, which is an example of a cleaning means for the image holding means, are arranged. Similarly, around the other photoreceptors Py, Pm, Pc, Po, chargers CCy, CCm, CCc, CCo, exposure devices LPHy, LPHm, LPHc, LPHo, developing devices Gy, Gm, Gc, Go, primary transfer rolls T1y, T1m, T1c, T1o, and photoreceptor cleaners CLy, CLm, CLc, CLo are arranged. On the upper part of the marking unit U1a, toner cartridges Ky, Km, Kc, Kk, Ko, which are an example of a developer storage means, are detachably supported. The toner cartridges Ky to Ko store a developer that is supplied to the developing devices Gy to Go.

[0029] Below each photoreceptor Py to Po, an intermediate transfer means, which is an example of an image holding means, the intermediate transfer belt B, is disposed. The intermediate transfer belt B is sandwiched between the photoreceptors Py to Po and the primary transfer rolls T1y to T1o. The back surface of the intermediate transfer belt B is supported by a drive roll Rd, which is an example of a drive means, a tension roll Rt, which is an example of a tension applying means, a walking roll Rw, which is an example of a meandering prevention means, a plurality of idler rolls Rf, which are examples of follower means, a backup roll T2a, which is an example of an opposing means for secondary transfer, and a plurality of retract rolls R1, which are examples of movable means, and the primary transfer rolls T1y to T1o. On the surface of the intermediate transfer belt B, in the vicinity of the drive roll Rd, a belt cleaner CLB, which is an example of a cleaning means of the intermediate transfer means, is disposed.

[0030] Opposite the backup roll T2a, with the intermediate transfer belt B interposed therebetween, a secondary transfer roll T2b, which is an example of a secondary transfer member, is disposed. Further, in contact with the backup roll T2a is a contact control T2c, which is an example of a contact means, for applying a voltage having a polarity opposite to the charging polarity of the developer to the backup roll T2a. The backup roll T2a, the secondary transfer roll T2b, and the contact control T2c constitute a secondary transfer device T2, which is an example of the secondary transfer means of Example 1. The primary transfer rolls T1y to T1o, the intermediate transfer belt B, the secondary transfer device T2, etc. constitute a transfer device T1, B, T2, which is an example of the transfer means of Example 1.

[0031] Below the secondary transfer device T2, a paper feed tray TR1, which is an example of a housing means, is provided. The paper feed tray TR1 houses a recording sheet S, which is an example of a medium. Diagonally upward to the right of the paper feed tray TR1, a pickup roll Rp, which is an example of a picking means, and a separating roll Rs, which is an example of a separating means, are disposed. A transport path SH, along which the recording sheet S is transported from the separating roll Rs, extends. A plurality of transport rolls Ra, which are examples of transport means for transporting the recording sheet S downstream along the transport path SH, are disposed. On the downstream side of the separating roll Rs, a burr removing device Bt, which is an example of a means for removing unnecessary parts, is arranged. The burr removing device Bt sandwiches the recording sheet S with a preset pressure and conveys it downstream to remove the unnecessary parts at the edges of the recording sheet S, that is, to remove burrs.

[0032] On the downstream side of the burr removing device Bt, a double feed detecting device Jk is arranged. The double feed detecting device Jk measures the thickness of the passing recording sheet S and detects a state where a plurality of recording sheets S are overlapped, that is, double feed. On the downstream side of the double feed detecting device Jk, a correcting roll Rc, which is an example of a means for correcting the posture, is arranged. The correcting roll Rc corrects the inclination of the recording sheet S with respect to the conveyance direction, that is, so-called skew. On the downstream side of the correcting roll Rc, a registration roll Rr, which is an example of an adjusting means for adjusting the conveyance timing of the recording sheet S to the secondary transferrer T2, is arranged. Also, on the downstream side of the registration roll Rr, a sheet guide SG1, which is an example of a means for guiding the medium, is arranged. Note that the feeder unit U2 is also provided with paper feed trays TR2, TR3, etc. having the same configuration as the paper feed tray TR1, the pickup roll Rp, the separating roll Rs, and the conveyance roll Ra. The conveyance paths SH from the paper feed trays TR2, TR3 merge into the conveyance path SH of the main body U1 of the printer upstream of the double feed detecting device Jk.

[0033] A plurality of conveyance belts HB, which are an example of a means for conveying the medium, are arranged on the downstream side in the conveyance direction of the recording sheet S with respect to the secondary transfer roll T2b. On the downstream side in the conveyance direction of the recording sheet S with respect to the conveyance belt HB, a fixing device F, which is an example of a fixing means, is arranged. In the finisher U3 on the downstream side of the fixing device F, a decurler Hd, which is an example of a means for correcting the curvature, is arranged. The decurler Hd applies pressure to the recording sheet S to correct the curvature of the recording sheet S, that is, so-called curl. On the downstream side of the decurler Hd, a conveyance path SH extends toward a discharge tray TRh as an example of a loading means. At the downstream end of the conveyance path SH, a discharge roll Rh as an example of a discharging means is arranged.

[0034] On the downstream side of the decurler Hd, a reversing path SH2 as an example of a conveyance path branching from the conveyance path SH is formed. At the branch portion between the conveyance path SH and the reversing path SH2, a first gate GT1 as an example of a conveyance direction switching means is arranged. A plurality of switchback rolls Rb as an example of a conveyance means capable of forward and reverse rotation are arranged on the reversing path SH2. On the upstream side of the switchback roll Rb, a connection path SH3 as an example of a conveyance path that branches from the upstream portion of the reversing path SH2 and merges downstream of the branch portion of the conveyance path SH with the reversing path SH2 is formed. At the branch portion between the reversing path SH2 and the connection path SH3, a second gate GT2 as an example of a conveyance direction switching means is arranged.

[0035] On the downstream side of the reversing path SH2, below the fixing device F, a folding path SH4 for reversing the conveyance direction of the recording sheet S, so-called switchback, is arranged. A switchback roll Rb as an example of a conveyance means capable of forward and reverse rotation is arranged on the folding path SH4. Also, at the entrance of the folding path SH4, a third gate GT3 as an example of a conveyance direction switching means is arranged. Note that the conveyance path SH on the downstream side of the folding path SH4 merges with the conveyance path SH of the paper feed tray TR1.

[0036] (Marking operation) In the printer U, when the image information transmitted from the personal computer PC is received via the print image server COM, a job, which is an image forming operation, is started. When the job is started, the photoreceptors Py~Po, the intermediate transfer belt B, etc. rotate. The photoreceptors Py~Po are rotationally driven by a drive source (not shown). The chargers CCy~CCo have a preset voltage applied thereto to charge the surfaces of the photoreceptors Py~Po. This is an example of a latent image forming device. As an example of a light emitting device, exposure machines LPHy to LPHo output lights Ly, Lm, Lc, Lk, Lo for writing a latent image, and write an electrostatic latent image on the charged surface of photoreceptors Py to Po according to control signals from a control unit C. Developers Gy to Go develop the electrostatic latent images on the surfaces of photoreceptors Py to Po. Toner cartridges Ky to Ko supply the developer consumed during development in developers Gy to Go.

[0037] Primary transfer rolls T1y to T1o are applied with a primary transfer voltage having a polarity opposite to the charging polarity of the developer, and transfer the visible images on the surfaces of photoreceptors Py to Po to the surface of an intermediate transfer belt B. Photoreceptor cleaners CLy to CLo remove and clean the developer remaining on the surfaces of photoreceptors Py to Po after primary transfer. When passing through the primary transfer area facing photoreceptors Py to Po, images are transferred and laminated in the order of O, Y, M, C, K, and pass through a secondary transfer area Q4 facing a secondary transfer device T2. In the case of a monochromatic image, only an image of one color is transferred and sent to the secondary transfer area Q4.

[0038] A pickup roll Rp feeds out a recording sheet S from paper feed trays TR1 to TR3 where the supply of the recording sheet S is performed according to the size of the received image information, the designation of the recording sheet S, and the size and type of the accommodated recording sheet S. A separating roll Rs separates and separates the recording sheets S sent out from the pickup roll Rp one by one. A burr removing device Bt applies a preset pressure to the passing recording sheet S to remove burrs. A double feed detection device Jk detects double feeding of the recording sheet S by detecting the thickness of the passing recording sheet S. A correction roll Rc corrects skew by bringing the passing recording sheet S into contact with a wall surface (not shown).

[0039] The registration roll Rr feeds the recording sheet S in time with the image on the surface of the intermediate transfer belt B being sent to the secondary transfer area Q4. The sheet guide SG1 guides the recording sheet S sent out by the registration roll Rr to the secondary transfer area Q4. In the secondary transfer device T2, a secondary transfer voltage having the same polarity as the charge polarity of the developer set in advance is applied to the backup roll T2a via the contact roll T2c, and the image on the intermediate transfer belt B is transferred to the recording sheet S. The belt cleaner CLB removes and cleans the developer remaining on the surface of the intermediate transfer belt B after the image has been transferred in the secondary transfer area Q4. The conveyor belt HB conveys the recording sheet S, onto which an image has been transferred by the secondary transfer device T2, downstream while holding the recording sheet S on its surface.

[0040] The fixing device F has a heating roll Fh as an example of a heating member and a pressure roll Fp as an example of a pressure member. A heater h as an example of a heat source is housed inside the heating roll Fh. The fixing device F heats and presses the recording sheet S passing through a fixing area Q5 where the heating roll Fh and the pressure roll Fp come into contact with each other, thereby fixing an unfixed image on the surface of the recording sheet S. The heating roll Fh and the pressure roll Fp constitute the fixing members Fp, Fh of the first embodiment. The decurler Hd applies pressure to the recording sheet S that has passed through the fixing device F to remove the curvature, or so-called curl, of the recording sheet S.

[0041] When double-sided printing is to be performed on the recording sheet S that has passed through the decurler Hd, the first gate GT1 is activated and the sheet is transported to the reversing path SH2, switched back at the return path SH4, and sent again through the transport path SH to the registration roll Rr, where printing is performed on the second side. When the recording sheet S is discharged onto the discharge tray TRh with the side on which the image is recorded facing up, that is, when the recording sheet S is discharged face-up, the recording sheet S is transported along the transport path SH and discharged onto the discharge tray TRh by the discharge roll Rh.

[0042] On the other hand, when it is discharged such that the surface on which the image is recorded becomes the lower surface, that is, in the case of so-called face-down discharge, it is once carried into the reversing path SH2 from the conveyance path SH. Then, after the rear end in the conveyance direction of the recording sheet S passes through the second gate GT2, the forward rotation of the switchback roll Rb stops. Then, the second gate GT2 switches, the switchback roll Rb rotates reversely, and the recording sheet S is conveyed through the connection path SH3 and conveyed to the discharge tray TRh. The discharged recording sheet S is stacked on the discharge tray TRh.

[0043] (Explanation of the latent image forming device) In the first embodiment, as the exposure machines (print heads) LPHy to LPHo, a recording device using an LED print head (LPH: LED Print Head) in which a plurality of light emitting diodes (LED: Light Emitting Diode) are arranged in the main scanning direction to form a light emitting element array in response to the demand for miniaturization of the device is adopted. Further, in a light emitting chip equipped with a self-scanning type light emitting element array (SLED) in which a plurality of light emitting elements are provided in a row on a substrate and sequentially controlled to light up, a light emitting silicon controlled rectifier connected in series with the light emitting diode is used. The silicon controlled rectifier has an anode, a cathode, and at least one gate, and becomes an on state when a voltage is applied between the anode and the cathode while a voltage of a certain level or more is applied to the gate, and maintains the on state while a current equal to or greater than the holding current flows between the anode and the cathode.

[0044] FIG. 2 is a cross-sectional view of the latent image forming device of the first embodiment. FIG. 3 is a top view of the light emitting portion of the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of print heads LPHy to LPHo as an example of a light-emitting device. The print heads LPHy to LPHo include a housing 61 as an example of a frame, a light-emitting device 65 as an example of a light-emitting means main body, and a rod lens array 64 as an example of an optical means. The light-emitting device 65 includes a light source unit 63 having a plurality of light-emitting elements. The rod lens array 64 forms an image of the light emitted from the light source unit 63 on the surfaces of photoreceptors Py to Po to expose the photoreceptors Py to Po. The light-emitting device 65 includes a circuit board 62 on which a light source unit 63, a signal generation circuit 110 (see FIG. 3) for driving the light source unit 63, etc. are mounted.

[0045] The housing 61 is formed of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set such that the light-emitting surface, which is the surface for emitting the light of the light-emitting elements of the light source unit 63, becomes the focal plane of the rod lens array 64. Further, the rod lens array 64 is arranged along the axial direction (main scanning direction) of the photoreceptors Py to Po.

[0046] (Light-emitting device 65) In FIG. 3, the light source unit 63 includes, as an example, 20 light-emitting chips C1 to C20 on the circuit board 62. The light-emitting chips C1 to C20 are configured to be arranged in two rows in a staggered manner in the X direction, which is the main scanning direction. In the first embodiment, a total of 20 light-emitting chips Ck (C1 to C20) are used, but the number is not limited to this and can be appropriately changed according to the design and specifications.

[0047] The light-emitting device 65 includes a signal generation circuit 110 for driving the light source unit 63. The signal generation circuit 110 is configured of, for example, an integrated circuit (IC). Note that the light-emitting device 65 may not be equipped with the signal generation circuit 110. In this case, the signal generation circuit 110 is provided outside the light-emitting device 65, and supplies a control signal for controlling the light-emitting chips C1 to C20 via a cable or the like. Here, the light-emitting device 65 is described as including the signal generation circuit 110.

[0048] FIG. 4 is an explanatory diagram of the configuration of the light-emitting chip of Example 1. FIG. 5 is an explanatory diagram of the configuration of the signal generation circuit of Example 1 and the configuration of the wiring (lines) on the circuit board. In FIG. 4, the light-emitting chip Ck is constituted by a semiconductor laminate provided on a semiconductor substrate 80 having a rectangular surface shape as an example. And on the surface of the substrate 80, a plurality of light-emitting elements (in Example 1, light-emitting thyristors L1, L2, L3,...) are arranged in a staggered pattern along the long side on one long side.

[0049] In Example 1, the light-emitting thyristors L1 to L20 include a plurality of first light-emitting portions (first light-emitting thyristors) L1, L3, L5,..., L19 arranged at intervals along the main scanning direction which is a predetermined first direction, and a plurality of second light-emitting portions (second light-emitting thyristors) L2, L4, L6,..., L20 arranged at intervals along the main scanning direction. The second light-emitting thyristors L2, L4,..., L20 are arranged at positions shifted from the first light-emitting thyristors L1, L3,..., L19 with respect to the sub-scanning direction (an example of the second direction) intersecting the main scanning direction, and are arranged at positions shifted along the main scanning direction with respect to each of the first light-emitting thyristors L1, L3,..., L19. Hereinafter, when n is a natural number, the first light-emitting thyristors L1, L3,..., L19 may be denoted as "first light-emitting thyristor L2n - 1", and the second light-emitting thyristors L2, L4,..., L20 may be denoted as "second light-emitting thyristor L2n". In Example 1, the case of being constituted by two rows of light-emitting thyristors L1 to L20 is exemplified, but it is also possible to have three or more rows. Also, the number of light-emitting thyristors is not limited to 20, and can be arbitrarily changed according to the design, specifications, etc.

[0050] In FIGS. 4 and 5, the light-emitting chip Ck includes terminals (φ1 terminal, φ2 terminal, Vg terminal, VI terminal, φWa terminal, φWb terminal, and φR terminal), which are a plurality of bonding pads for taking in various control signals and the like, at both ends of the surface of the substrate 80 in the long-side direction. Note that these terminals are provided in the order of the φWa terminal, φ1 terminal, VI terminal, and Vg terminal from one end of the substrate 80, and in the order of the φR terminal, φWb terminal, and φ2 terminal from the other end of the substrate 80. And the light-emitting unit 102 is provided between the Vg terminal and the φ2 terminal. Further, a back surface electrode (not shown) is provided as the Vsub terminal on the back surface of the substrate 80. Note that various control signals and terminals are conventionally known as described in, for example, Japanese Patent Application Laid-Open No. 2020-049720, etc., and thus detailed descriptions thereof are omitted.

[0051] (Light-emitting chip Ck) FIG. 6 is an example of an equivalent circuit diagram for explaining the configuration of the light-emitting chip of Example 1. In FIG. 6, each element described below is represented by a widely used circuit symbol. Note that the positions of the respective terminals (φ1 terminal, φ2 terminal, φWa terminal, φR terminal, VI terminal, Vg terminal) are different from those in FIG. 4, but are shown at the left end in the figure for convenience of explanation. And the Vsub terminal is provided as a back surface electrode on the back surface of the substrate 80. Here, the light-emitting chip Ck will be described by taking the light-emitting chip C1 as an example in relation to the signal generation circuit 110, and descriptions of the other light-emitting chips C2 to C20 are omitted.

[0052] The light-emitting chip Ck includes light-emitting thyristors L1, L2, L3,..., transfer thyristors T1, T2, T3,..., coupling transistors Qt1, Qt2, Qt3,..., set thyristors W1, W2, W3,..., and setting transistors Qw1, Qw2, Qw3,.... Note that when the light-emitting thyristors L1, L2, L3,... are not distinguished from each other, they are denoted as the light-emitting thyristor L. The same applies to the others. The transfer thyristor T, the coupling transistor Qt, the set thyristor W, and the setting transistor Qw are arranged along the arrangement of the light-emitting thyristor L (FIG. 4). The transfer thyristor T is an example of a transfer element, and the set thyristor W is an example of a setting element. In the first embodiment 1, a light-emitting device is constituted by a light-emitting thyristor L, resistors RI1, RI2, and resistor Rn.

[0053] And the light-emitting chip Ck includes turn-off thyristors RT1, RT2. When not distinguishing between the turn-off thyristors RT1, RT2 respectively, it is denoted as the turn-off thyristor RT. Furthermore, the light-emitting chip Ck includes a plurality of resistors. Regarding the resistors, no distinguishing numbers such as light-emitting thyristors L1, L2, L3,... are given.

[0054] The light-emitting thyristor L, the transfer thyristor T, the set thyristor W, and the turn-off thyristor RT are thyristors having a pnpn structure. The transfer thyristor T is a four-terminal element having an anode, a first gate Gtf, a second gate Gts, and a cathode as shown in the transfer thyristor T1. In FIG. 6, the first gate Gtf is denoted as (Gtf). The same applies to others. Also, no reference numerals are given to other equivalent elements. The same applies to others. The set thyristor W is a four-terminal element having an anode, a first gate Gwf, a second gate Gws, and a cathode as shown in the set thyristor W1. On the other hand, the light-emitting thyristor L is a three-terminal element having an anode, a gate Gl, and a cathode as shown in the light-emitting thyristor L1. Similarly, the turn-off thyristor RT is a three-terminal element having an anode, a gate Gr, and a cathode as shown in the turn-off thyristor RT1.

[0055] The coupling transistor Qt and the setting transistor Qw are pnp bipolar transistors. The odd-numbered coupling transistor Qt is a four-terminal element having an emitter E, a base B, a first collector Cf, and a second collector Cs as shown in the coupling transistor Qt1. The even-numbered coupling transistor Qt is a three-terminal element having an emitter E, a base B, and a collector C as shown in the coupling transistor Qt2. That is, the odd-numbered coupling transistor Qt is a multi-collector, and the even-numbered coupling transistor Qt is a single collector. Also, the setting transistor Qw is a three-terminal element having an emitter E, a base B, and a collector C as shown in the setting transistor Qw1. Therefore, the setting transistor Qw is also a single collector.

[0056] And the light-emitting chip Ck includes a plurality of wirings for connecting the above elements. The light-emitting chip Ck includes a power line 71 connected to the Vg terminal. A power supply voltage Vg is supplied to the power line 71 from the power supply voltage supply unit 170 via the Vg terminal connected by the power supply line 200b. The light-emitting chip Ck includes transfer signal lines 72a and 72b connected to the φ1 terminal and the φ2 terminal via resistors R1 and R2, respectively. Transfer signals φ1 and φ2 are respectively transmitted to the φ1 terminal and the φ2 terminal from the transfer signal generation unit 120 via the transfer signal lines 201 and 202. Also, the light-emitting chip Ck includes setting signal lines 73a and 73b connected to the φWa terminal and the φWb terminal via resistors R3 and R4, respectively. Setting signals φWa1 and φWb1 are transmitted to the φWa terminal and the φWb terminal from the setting signal generation unit 130 via the setting signal lines 203a-1 and 203b-1. The resistors R1, R2, R3, and R4 are current limiting resistors provided to maintain the voltage.

[0057] And the light-emitting chip Ck includes lighting signal lines 75a and 75b connected to the VI terminal via resistors RI1 and RI2, respectively. A lighting voltage VI is supplied to the VI terminal from the lighting voltage supply unit 150. The lighting signal lines 75a and 75b are an example of lighting voltage lines, and the lighting voltage VI is an example of a lighting voltage. Furthermore, the light-emitting chip Ck includes extinction signal lines 76a and 76b each connected to the φR terminal via resistors Rr1 and Rr2. An extinction signal φR is transmitted from the extinction signal generation unit 140 to the φR terminal through the extinction signal line 204.

[0058] The light-emitting chip Ck includes a Vsub terminal at the back electrode of the substrate 80. A reference voltage Vsub is supplied from the reference voltage supply unit 160 to the Vsub terminal through the power supply line 200a. The Vsub terminal is an example of a reference voltage line.

[0059] FIG. 7 is an explanatory diagram of the main part of the light-emitting chip of Example 1. FIG. 7A is a plan view, FIG. 7B is a cross-sectional view taken along line VIIB-VIIB of FIG. 7A, FIG. 7C is a cross-sectional view taken along line VIIC-VIIC of FIG. 7A, and FIG. 7D is a cross-sectional view taken along line VIID-VIID of FIG. 7A. In FIG. 7, in the light-emitting chip Ck of Example 1, first wirings 301 extending from the collectors (C) of first setting transistors (an example of the first control elements) Qw1, Qw3,... are respectively connected to the first light-emitting thyristors L1, L3,..., L19. Second wirings 302 extending from the collectors (C) of second setting transistors (an example of the second control elements) Qw2, Qw4,... are respectively connected to the second light-emitting thyristors L2, L4,..., L20.

[0060] In FIG. 7B, the first wiring 301 is formed by being laminated on the substrate 80. An insulating layer 303 is further laminated on the surface side of the first wiring 301. That is, the first wiring 301 is configured to supply current inside the lamination. In FIG. 7C, a partial section of the second wiring 302 is composed of a metal material laminated on the further surface of the insulating layer 303 laminated on the substrate 80, and supplies current to the second light-emitting thyristor L2n. The second wiring 302 of Example 1 is arranged on the surface side so as to pass between the first light-emitting thyristors L2n-1 and cover a part of the outer edge of the first light-emitting thyristor L2n-1, and is arranged on the surface side with the insulating layer 303 interposed therebetween so as not to conduct electricity with the electrode portion 304 of the outer edge of the first light-emitting thyristor L2n-1.

[0061] FIG. 8 is an explanatory diagram of the circuit of Example 1, FIG. 8A is an explanatory diagram of the laminated structure of the portion of the first wiring, and FIG. 8B is an explanatory diagram of the laminated structure of the portion of the second wiring. In FIG. 8A, the setting transistor Qw has a so-called pnp-type transistor structure. On the surface of the conductive substrate 80, a p-type semiconductor 211 functioning as an emitter, an n-type semiconductor 212 functioning as a base, and a p-type semiconductor (first layer) 213 functioning as a collector are laminated, and the first wirings 301 and 302 made of metal are laminated on the surface of the p-type semiconductor 213. On the other hand, in FIG. 8B, in the portion where the second wiring 302 passes between the first light-emitting thyristors L2n-1, an insulating layer 303 is laminated on the surface of the substrate 80, and the second wiring 302 is laminated on the surface of the insulating layer (second layer) 303.

[0062] Therefore, in the light-emitting chip Ck of Example 1, different configurations are adopted for the first wiring 301 and the second wiring 302. Compared with the case where the wirings are the same, the degree of freedom in arranging the first light-emitting thyristor L2n-1 and the second light-emitting thyristor L2n increases. Therefore, without sacrificing the area of the light-emitting thyristor L, a staggered arrangement as shown in FIG. 4 can be adopted, and more light-emitting thyristors L can be arranged in the main scanning direction. Further, in the light-emitting chip Ck of Example 1 that employs the insulating layer 303, even when the second wiring 302 is wired near the other semiconductor layers 211 to 213, it is suppressed that the signal of the second wiring 302 is transmitted to a portion where transmission is not desired.

[0063] Further, in the light-emitting chip Ck of Example 1, the first wiring 301 and the second wiring 302 have different laminated structures with respect to the lamination direction as an example of the third direction, and thus have different electrical resistivity and permittivity. Specifically, in FIG. 8A, a capacitance is added between the base (n-type semiconductor 212) and the collector (p-type semiconductor 213). On the other hand, in FIG. 8B, a capacitance is added between the second wiring 302, the insulating layer 303, and the substrate 80. Although the thicknesses and materials of the semiconductors 211 to 213 and the insulating layer 303 are different, usually, the dielectric constant of FIG. 8B is lower and the electrode interval of the capacitor is wider, so the capacitance per unit area becomes smaller. Therefore, the delay (lighting delay) from when the lighting start signal is input until the light-emitting thyristor starts lighting is more likely to be smaller for the second light-emitting thyristor L2n passing through the second wiring 302 in the middle. Note that if the length of the second wiring 302 is long, the delay of the second light-emitting thyristor L2n may be large. Hereinafter, basically, the case where the delay of the second light-emitting thyristor L2n is small will be assumed for explanation, but it goes without saying that when the delay of the second light-emitting thyristor L2n is large, the magnitude and increase / decrease will have the opposite relationship.

[0064] Since the delays of the first light-emitting thyristor L2n-1 and the second light-emitting thyristor L2n are different, the light-emitting timings are different. By simply delaying the input timing of the signal to the set thyristor W by this delay difference, but changing the lighting timing for each of the light-emitting thyristors L requires a large amount of memory, which complicates the configuration and causes problems such as cost increase and control complexity.

[0065] The delay from when the signal (set signal) for turning on each light-emitting thyristor L is input until it lights up has two main elements, and the sum of them is the delay. The first element is the delay until each set thyristor W turns on. The second element is the delay until the setting transistor Qw charges the gate of the light-emitting thyristor L and the light-emitting thyristor L turns on.

[0066] The first element is determined by the time constant of the setting signal lines 73a and 73b. Therefore, setting and adjustment are possible by making the resistance values of the second resistance element R3 and the first resistance element R4 connected to the second setting signal line (second connection line) 73a and the first setting signal line (first connection line) 73b different. The second element is determined by the parallel capacitance of wirings 301 and 302 connecting the collector of the setting transistor Qw and the gate of the glow thyristor L, and the collector current value of the setting transistor Qw for charging the same.

[0067] Therefore, as an example, by increasing the resistance value of the second resistor element R3, the time constant can be increased, and the small delay of the second glow thyristor L2n can be increased. That is, according to the difference in the parallel capacitance between the first wiring 301 and the second wiring 302, the currents flowing through the first setting transistor Qw2n-1 and the second setting transistor Qw2n can be adjusted. Along with this, the delay difference from the first glow thyristor L2n-1 is suppressed, the difference in the light emission timing of each glow thyristor L is adjusted, and it is possible to turn on each glow thyristor L at the target timing. Also, compared to a configuration in which a memory is installed corresponding to each individual glow thyristor, it is possible to suppress the complication of the configuration, the increase in cost, and the complication of control.

[0068] FIG. 9 is an explanatory diagram of an example of the stacked structure of the set thyristor and the coupling transistor of Example 1, FIG. 9A is a plan view, and FIG. 9B is a cross-sectional view. In FIG. 9, the set thyristor W of Example 1 has a so-called pnpn structure, and the p-type semiconductor 211 and the n-type semiconductor 212 on the surface of the substrate 80 are shared with those of the setting transistor Qw, and on the surface of the n-type semiconductor 212, a p-type semiconductor 223, an n-type semiconductor 224, and a cathode electrode 225 are laminated.

[0069] When suppressing the aforementioned delay difference, as an example of the corresponding method for the second element, it can also be realized by increasing the area of the second wiring 302. Specifically, in the plan view of FIG. 9A, by widening the width Wa of the second wiring 302, the area can be increased, the parasitic capacitance can be increased, and the collector current value can be adjusted.

[0070] It is also possible to achieve this by reducing the collector current when the setting transistor Qw connected to the second light-emitting thyristor L2n is on. As a method of reducing the collector current, increasing the resistance R3 can be mentioned. It is also possible to achieve this by reducing the capability of the setting transistor Qw. As a method of reducing the capability of the setting transistor Qw, for example, in the plan view of FIG. 9A, by reducing the width Wb of the setting transistor Qw or increasing the distance (interval) La between the setting transistor Qw and the set thyristor W, the characteristics of the setting transistor Qw can be degraded and the collector current can be decreased.

[0071] Therefore, when it is necessary to change the structure of some wiring on the wiring layout between the first light-emitting thyristor L2n-1 and the second light-emitting thyristor L2n, compared with the case where the structures other than the signal to the gate layer in the wirings to the first light-emitting thyristor L2n-1 and the second light-emitting thyristor L2n are made different between the first light-emitting thyristor L2n-1 and the second light-emitting thyristor L2n, the light emission of the light-emitting thyristor L becomes stable. Since the signal line to the gate layer is just a set signal, there is no need for a large current to flow, and also, even if the resistance changes, the impedance for light emission does not change, so the light emission efficiency does not decrease.

[0072] FIG. 10 is an explanatory diagram of another example of the arrangement of the light-emitting part in the present invention. Note that the present invention is not limited to the configuration in which the light-emitting thyristors L are arranged in a staggered pattern as exemplified in the first embodiment. For example, as shown in FIG. 10, when the light-emitting thyristors L are arranged in a dense planar manner instead of in a row, with respect to the first light-emitting thyristor L1' on the outer peripheral side and the second light-emitting thyristor L2' on the inner side, the second wiring 302' to the second light-emitting thyristor L2' is also applicable when it is arranged to pass between the first light-emitting thyristors L1' in the same manner as in the first embodiment.

[0073] (Modified example) As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Modification examples (H01) to (H010) of the present invention are illustrated below. (H01) In the above embodiment, the printer U as an example of an image forming apparatus is illustrated. However, the present invention is not limited thereto. For example, it may be configured by a copying machine, a FAX, or a multifunction machine having a plurality or all of these functions. Further, the present invention is not limited to an electrophotographic image forming apparatus, and can be applied to any image forming apparatus such as an inkjet method or a thermal transfer method.

[0074] (H02) In the above embodiment, a configuration in which five-color developers are used as the printer U is illustrated. However, the present invention is not limited thereto. For example, it is also applicable to a monochromatic image forming apparatus or a multicolor image forming apparatus having four or less or six or more colors. (H03) In the above embodiment, the endless belt-shaped intermediate transfer belt B is illustrated as an example of the image holding means. However, the present invention is not limited thereto. For example, it is also applicable to a cylindrical intermediate transfer drum, a photosensitive drum, or a photosensitive belt. Further, the present invention is also applicable to a configuration in which an image is directly recorded on the recording sheet S from the photosensitive member without having an intermediate transfer member.

[0075] (H04) In the above embodiment, a configuration in which the second wiring 302 that sends a lighting / extinguishing signal to the second light-emitting thyristor L2n affects the light amount of the first light-emitting thyristor L2n-1 is illustrated. However, the present invention is not limited thereto. The present invention is applicable to any wiring in which a delay may occur. (H05) In the above embodiment, the structure of the light-emitting thyristor is illustrated as the light-emitting unit. However, the present invention is not limited thereto. For example, the light-emitting unit may be only a light-emitting diode. Further, the wiring can also be applied to a configuration that supplies current to each of the light-emitting units, for example, the configuration described in Japanese Patent Application Laid-Open No. 2020-123603. Further, the present invention is not limited to the configuration of an LED head including a light-emitting diode or the like. For example, the present invention is also applicable to a configuration having a laminated substrate such as a vertical cavity surface emitting laser (VCSEL).

[0076] (H06) In the above embodiments, although the case where there are a plurality of first light-emitting thyristors L2n-1 and second light-emitting thyristors L2n is exemplified, it is not limited thereto. It is also applicable to the case where there is one first light-emitting thyristor L2n-1 and one second light-emitting thyristor L2n. Further, for example, by combining (H05) and (H06), the light-emitting part is composed of VCSELs, and in the case where there is one first VCSEL and one second VCSEL, etc., modified examples may be appropriately combined. (H07) In the above embodiments, although the configuration in which one wiring 301, 302 is provided for one light-emitting thyristor L is exemplified, it is not limited thereto. For example, it is also applicable to a configuration in which one wiring branches and is connected to a plurality of light-emitting thyristors, and the lighting and extinguishing of a plurality of light-emitting thyristors are controlled simultaneously through one wiring.

[0077] (H08) In the above embodiments, although the first control element (first coupling transistor) and the second control element (second coupling transistor) are shown to be different from each other, it is not limited thereto. For example, it is also applicable to a configuration in which the first control element and the second control element are the same and the same signal is sent to the first wiring and the second wiring. (H09) In the above embodiments, although the case of a print head used in an image forming apparatus is exemplified as an example of the light-emitting device, it is not limited thereto. It may be applied to a light-emitting element array used for optical transmission, and in that case, it may be combined with an optical transmission path. The light emitted from the first light-emitting part and the light emitted from the second light-emitting part may be put into the same optical transmission path or different optical transmission paths. Further, it may be applied to a light-emitting substrate used for optical measurement. The light-receiving elements for receiving the light emitted from the first light-emitting part and the second light-emitting part may be configured on the same substrate, and a lens through which the light emitted from the first light-emitting part and the second light-emitting part passes before reaching an object may be added. In the above embodiment, the light-emitting unit is applied to each of the thyristors, and an example of a configuration in which the first wiring 301 is connected to the first thyristors L1, L3, …, L19 is illustrated, but the present invention is not limited thereto. For example, a configuration for supplying current to a group of light-emitting elements may be used.

Explanation of Signs

[0078] 73a … Second connection line 73b … First connection line 80 … Substrate 301 … First wiring 302 … Second wiring 303 … Insulation layer 211~213 … Semiconductor layer CCy, CCm, CCc, CCk, CCo … Charging means L1, L3, L2n-1 … First light-emitting unit L2, L4, L2n … Second light-emitting unit La … Distance between set thyristor and transistor LPHy~LPHo … Light-emitting device, latent image forming device Py, Pm, Pc, Pk, Po … Image holding means Qw1, Qw3, Qw2n-1 … First control element Qw2, Qw4, Qw2n … Second control element R3 … Second resistance element R4 … First resistance element U … Image forming apparatus W … Set thyristor Wb … Length in the width direction

Claims

1. A plurality of first light-emitting units arranged at intervals along a predetermined first direction; A plurality of second light-emitting units arranged at intervals along the first direction, the second light-emitting units being arranged at positions shifted from the first light-emitting units with respect to a second direction intersecting the first direction and being arranged at positions shifted with respect to each of the first light-emitting units along the first direction; A first wiring electrically connected to each of the first light-emitting units by a semiconductor layer; A second wiring electrically connected to each of the second light-emitting units, the second wiring being arranged with an insulating layer interposed therebetween and the substrate in a third direction intersecting the first direction and the second direction with respect to a portion passing between the first light-emitting units; A first control element that outputs a control signal for controlling the blinking of the first light-emitting units through the first wiring; A second control element that outputs a control signal for controlling the blinking of the second light-emitting units through the second wiring; Comprising; Adjusting the current flowing through the first control element and the second control element according to the difference in the parallel capacitance between the first wiring and the second wiring A light-emitting device characterized by the above.

2. A first light-emitting unit; A second light-emitting unit; A first wiring electrically connected to the first light-emitting unit, the first wiring being arranged facing a first layer; A second wiring electrically connected to the second light-emitting unit, a portion of the second wiring arranged facing a second layer that is more difficult to pass current through than the first layer being between the substrate and the portion passing between the first light-emitting units; A first Control element that outputs a control signal for controlling the blinking of the first light-emitting unit through the first wiring; A second control element that outputs a control signal for controlling the blinking of the second light-emitting unit through the second wiring; Comprising; The difference in the lighting timings of the first light-emitting unit and the second light-emitting unit caused by the difference between the first wiring and the second wiring is adjusted by adjusting the current flowing through the first control element and the second control element A light-emitting device characterized by the above.

3. A plurality of first light-emitting units; A plurality of second light-emitting units; The light-emitting device according to claim 2, characterized by comprising the above.

4. The light-emitting device according to claim 2 or 3, wherein the adjustment is an adjustment such that the current flowing through the second wiring is delayed.

5. A substrate; A first light-emitting part including a thyristor structure in which a semiconductor is laminated on the substrate; A second light-emitting part having the same layer structure as the first light-emitting part on the substrate; A first wiring electrically connected to the gate layer of the thyristor structure of the first light-emitting part, the first wiring being disposed facing the gate layer; A second wiring electrically connected to the gate layer of the thyristor structure of the second light-emitting part, the portion of the second wiring facing the layer with high permittivity outside the thyristor structure being disposed between the substrate and the portion passing between the first light-emitting parts; A first control element that outputs a control signal for controlling the blinking of the first light-emitting part through the first wiring; A second control element that outputs a control signal for controlling the blinking of the second light-emitting part through the second wiring; Comprising; There are a plurality of the first light-emitting parts and the second light-emitting parts; The difference in lighting timings of the first light-emitting part and the second light-emitting part caused by the difference between the first wiring and the second wiring is adjusted by adjusting the current flowing through the first control element and the second control element A light-emitting device characterized by the above.

6. A first connection line to which all of the first control elements are electrically connected; A second connection line to which all of the second control elements are electrically connected; A first resistance element connected to the first connection line; A second resistance element connected to the second connection line, the second resistance element having a different resistance value from the first resistance element; The light-emitting device according to any one of claims 1 to 5, characterized by comprising the above.

7. Making the resistance value of the first resistance element larger than the resistance value of the second resistance element The light-emitting device according to claim 6, characterized by the above.

8. Each of the light-emitting parts composed of a light-emitting thyristor; Each of the control elements composed of a transistor; Comprising; Adjusting the area of the metal wiring on the gate semiconductor connecting the collector of each control element and the gate of each light-emitting part The light-emitting device according to any one of claims 1 to 5, characterized by the above.

9. Each of the control elements composed of a transistor; Comprising; Adjusting the collector current when each control element is on The light-emitting device according to any one of claims 1 to 5, characterized by the above.

10. A first connection line to which all of the first control elements are electrically connected; A second connection line to which all of the second control elements are electrically connected; ​ a first resistor element connected to the first connection line; a second resistor element connected to the second connection line, the resistance value of which with respect to the first resistor element is adjusted according to the collector current; The light-emitting device according to claim 9, characterized in that it comprises the above.

11. Adjusting the transistor characteristics of the second control element with respect to the transistor characteristics of the first control element according to the collector current The light-emitting device according to claim 9, characterized in that it is as described above.

12. Adjusting the transistor characteristics by adjusting the length in the width direction intersecting the longitudinal direction of the wiring The light-emitting device according to claim 11, characterized in that it is as described above.

13. Adjusting the transistor characteristics by adjusting the distance between the transistor and a set thyristor connected to the transistor to generate a signal The light-emitting device according to claim 11, characterized in that it is as described above.

14. an image holding means; a charging means for charging the surface of the image holding means; a latent image forming device configured by the light-emitting device according to any one of claims 1 to 13 for forming a latent image on the charged image holding means; An image forming apparatus, characterized in that it comprises the above.

Images