High-Speed Multi-Modulus CMOS Clock Divider

Abstract

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for dividing the frequency of an input signal. The electronic circuit includes a ring oscillator (201). The ring oscillator (201) includes a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillator signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated to provide a selectable division ratio. By using clock partial gating, open-loop clock buffering, and avoiding slow gate logic in the data path, a very high-speed multi-modulus clock divider is achieved.

Description

Technical Field

[0001] An electronic circuit that divides the frequency of an input signal is provided.

Background Art

[0002] A clock divider is used to convert the frequency of an input signal to a lower frequency of an output signal. The ratio of the frequencies of the input signal and the output signal is the division ratio. Clock dividers are widely used in phase-locked loops.

[0003] In a phase-locked loop, the generated clock needs to be divided in order to be compared with a reference clock. It is known to divide the entire clock divider into several stages, in which case the first stage is the fastest and thus the most difficult to design.

[0004] The bottleneck of a clock divider is the maximum speed at which the clock divider can operate while providing a stable division ratio in view of process / voltage / temperature (PVT) variations when there is device aging or degradation.

[0005] FIG. 1 is a simplified schematic diagram of an example 100 of a three-stage CMOS logic circuit according to the prior art. This circuit is composed of four gate inverters 110, 120, 130, 140 connected in series. The outputs of the second gate inverter 120 and the fourth gate inverter 140 are connected to the inputs 152, 154 of a NAND gate 150, and its output 156 is connected to the input of the first gate inverter 110. Each gate inverter has complementary control signal inputs. As an example, the first gate inverter 110 includes first and second complementary inputs 112, 114. Each of these inputs is driven by an asymmetric clock driver 160. The asymmetric clock driver 160 provides a clock with a duty cycle higher than 50 percent, so that each PMOS transistor and NMOS transistor in the gate inverter is on for at least 50 percent of the clock cycle. This is to improve the maximum operating speed. In any case, the maximum speed is limited by the propagation delay through the NAND gate 150. To speed up the NAND gate 150, its driving strength can be increased by increasing its size, but this increases the load on nodes div3_stage4 170, especially div3_stage2 172, which becomes a speed bottleneck. If a single frequency division circuit has to be used to provide multiple division ratios, the achievable maximum speed is further reduced due to the complexity of the circuit that requires more combinational logic and gate inverters. SUMMARY OF THE INVENTION

[0006] An electronic circuit is provided.

[0007] The electronic circuit may be a high-speed CMOS logic circuit or suitable for a high-speed CMOS logic circuit.

[0008] The electronic circuit may be a clock divider.

[0009] The electronic circuit may include a ring oscillator. The ring oscillator may include a plurality of gate inverters. At least one of the gate inverters may be configured to receive an oscillation signal and a control signal at two complementary inputs. The electronic circuit may be configured to be partially gated so that the division ratio is selectable.

[0010] The ring oscillator may include at least three gate inverters. The at least three gate inverters may be arranged in series connection. The output of each gate inverter may be applied to the subsequent input of the gate inverters of the ring oscillator.

[0011] The control signal may include a first signal and a second signal. The first signal and the second signal may be opposite to each other.

[0012] The duty cycle of the control signal may be greater than 0.5.

[0013] At least one gate inverter may be partially gated to output a logic high or a logic low according to the logic state of the input signal. The output signal may be made selectable by applying partial gating to either a PMOS or an NMOS.

[0014] The electronic circuit may include interconnections.

[0015] The gate inverter may have a bus holder.

[0016] The electronic circuit may be a tri-modulus clock divider.

[0017] At least one division ratio may be selectable for 3, 4, and 5.

[0018] In another aspect, a clock divider is provided. The clock divider may include a plurality of gate inverters that are subsequently coupled to each other. At least one of the gate inverters may be configured to receive an oscillation signal and a control signal. The clock divider may be configured such that a division ratio is selectable based on the control signal.

[0019] According to yet another aspect, an electronic circuit is provided. The electronic circuit may include a ring oscillator. The ring oscillator may include a plurality of gate inverters. At least one of the gate inverters may be configured to receive an oscillation signal and at least one auxiliary signal in an additional input. The electronic circuit may include a plurality of interconnects. The electronic circuit may provide a selectable division ratio based on at least one auxiliary signal.

[0020] Further aspects and features of the present application will become apparent from the following description of the preferred embodiments with reference to the accompanying drawings.

Brief Description of the Drawings

[0021]

Figure 1

[0022]

Figure 2

[0023]

Figure 3

[0024]

Figure 4

[0025]

Figure 5

[0026]

Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0027] FIG. 2 is a simplified schematic example of an electronic circuit configured as a clock divider 200. The clock divider 200 includes first to sixth gate inverters 205, 210, 215, 220, 225, 230. The first to sixth gate inverters 205, 210, 215, 220, 225, 230 are arranged in series connection and are part of the ring oscillator 201. The clock divider 200 also has certain combinational logic to obtain the required division factors 3, 4, and 5.

[0028] An example of the gate inverter 280 is shown in more detail within the dashed box 290. The gate inverter 280 includes an additional input for controlling its operating state.

[0029] The gate inverter 280 includes two p-metal oxide semiconductor transistors 283, 284, and two n-metal oxide semiconductor transistors 285, 286. The drain of the first PMOS 283 is coupled to the source of the second PMOS 284. The source of the first NMOS 285 is coupled to the drain of the second NMOS 286. A node 282 for providing an output signal Y is disposed between the pair of PMOSs 283, 284 and the pair of NMOSs 285, 286. This means that the output signal Y is provided at the node 282 between the drain of the second PMOS 284 and the drain of the first NMOS 285.

[0030] The input signal A is coupled to the gates of the first PMOS 283 and the second NMOS 286 of the gate inverter 280. The control signals include a first signal CLK and a second signal CLKB. The first signal CLK is coupled to the gate of the first NMOS 285. The second signal CLKB is coupled to the gate of the second PMOS 284. The second signal CLKB is the inverse of the first signal CLK. This means that when CLK is logic "high", CLKB is logic "low".

[0031] In the gate inverter 280 to which the first and second signals CLK are supplied, when the first signal CLK is low and the second signal CLKB is high, CLKB can be in a high-impedance configuration. Similarly, the gate inverter 280 can be in an inverter configuration when the first signal CLK is high and the second signal CLKB is low. In the inverter configuration, the gate inverter 280 can output high when the input signal A is low, and vice versa. The gate inverter 280 can always output high as long as CLK remains low. In this configuration, CLKB is expected to toggle, and the input signal A either toggles or remains low. It is required that both CLKB and the input signal A be low together at some time. The gate inverter 280 can always output low when CLKB remains high. In this configuration, CLK is expected to toggle, and the input signal A either toggles or remains high. It is required that both CLKB and the input signal A be high together at some time.

[0032] The supply voltage 287 is coupled to the source of the first PMOS 283. The source of the second NMOS 286 is coupled to ground 288. The second, fourth, and sixth gate inverters 210, 220, 230 of the clock divider 200 are similar to the gate inverter 280. The first, third, and fifth gate inverters 205, 215, 225 are similar to the gate inverter 280 except that the first signal CLK and the second signal CLKB are exchanged compared to the gate inverter 280.

[0033] The clock divider 200 includes a plurality of interconnections 235, 240, 245, 250. The first interconnection 235 is disposed between ground 236 and node divN_stage7 237. The second interconnection 240 is disposed between ground 236 and node divN_stage7 237. The third interconnection 245 is disposed between ground 236 and node divN_stage7 237. The fourth interconnection 250 is disposed between supply voltage VA11 238 and node divN_stage7 237.

[0034] The interconnections 235, 240, 245, 250 all include a series connection of two PMOSs. The gate of one PMOS of the second to fourth interconnections 240, 245, 250 is coupled to node divN_stage4 239 and thus shared among these interconnections. Also, the gate of the first interconnection 235 is coupled to node divN_stage2 241. Node divN_stage2 241 is also coupled to the second gate of the fourth interconnection 250.

[0035] The selection signal sel<3> 242 is coupled to the second gate of the first interconnection 235. The selection signal sel<4> 243 is coupled to the second gate of the second interconnection 240. The second gate of the third interconnection 245 is coupled to node divN_stage6 244.

[0036] After applying an additional inverter 248 for stabilization, buffering, and / or execution time adjustment, the DIVout 246 of the clock divider 200 is provided at node divN_stage3 247.

[0037] The functional principle of the clock divider 200 depends on the interconnections 235, 240, 245, 250. The first interconnection 235 generates a DIVout high time for one period (1T) (which means DIVout is in the logic state "high"). The second interconnection 240 generates a DIVout high time for two periods (2T). The third interconnection 245 generates a DIVout high time for three periods (3T). The fourth interconnection 250 generates a DIVout low time for two periods (2T) (which means DIVout is in the logic state "low").

[0038] The selection signals sel<3> 242 and sel<4> 243 can be used to switch between different division ratios at DIVout 246. Since the first to third interconnections 235, 240, 245 share the same PMOS (pull-up), the load is reduced so that the low time of DIVout 246 is equal for all division ratios, that is, the low time of DIVout 246 is 2T for all configurations of the selection signals sel<3> 242 and sel<4> 243. As a result, different division ratios are provided by the clock divider 200. The clock divider 200 is a three-factor one, and thus, three different division ratios of 1 / 3, 1 / 4, and 1 / 5 are provided by the selection signals 242, 243. Therefore, the control signal can be used to efficiently modify the operating state of the clock divider 200 so that the division ratio can be different. The clock divider 200 is applicable to a number of applications. The clock divider 200 can operate at a wide range of input clock frequencies from several MHz to GHz. The maximum operating speed of the clock divider 200 can be made very high, approaching nearly 10 GHz.

[0039] According to a further aspect, the duty cycles of the gate inverters 205, 210, 215, 220, 225, 230 may be distorted. This means that a duty cycle greater than 0.5 can be applied so that more "on" time is provided. This can be achieved by buffering the clock signals, i.e., the first signal CLK and the second signal CLKB, by additional inverters having asymmetric pull-up (PMOS) and pull-down (NMOS) strengths. This leads to further increasing the maximum speed of the clock divider 200 (sampling time, the maximum frequency at which the clock divider 200 can operate).

[0040] Figure 3 shows a schematic diagram of the processing signal 300 of the clock divider 200. Time in ns is shown on the x-axis. The y-axis shows the amplitude of each signal that switches between "high" and "low".

[0041] Clk_stg1n3 312 and clkb_stg1n3 314 are the clock signal and the inverted clock signal used to gate the gate inverters 205, 210, 215, 220, 225, 230 of the clock divider 200. The clock signal frequency is 10 GHz in Figure 3.

[0042] divN_stage1~divN_stage7 320 are the output signals of the gate inverters 205, 210, 215, 220, 225, 230 of the clock divider 200 as described above.

[0043] sel<4>322 is one of the selection signals for selecting among different division ratios Div-3, Div-4, and Div-5 of the clock divider 200. Therefore, the output signal of the gate inverter, that is, the signals divN_stage1~divN_stage7 320, changes corresponding to the switching of sel<4>322 at different times among Div-3, Div-4, and Div-5. DIVout324 shows the divided output of the new silicon simulation, and DIVout326 shows the divided output after 10 years of aging. They provide different ratios between logic "high" and logic "low" based on the state of sel<3>, especially sel<4>322, so that the clock divider 200 provides different division ratios. From the comparison between DIVout324 of the clock divider 200 and the "aged" DIVout326, it is clear that the clock divider 200 provides a stable output signal for the division ratio of 1 / 3 even after 10 years of aging. This means that for the ratio of 1 / 3, the output signal DIVout326 is substantially the same (within an ignorable tolerance range) as the "new" DIVout324. However, for the remaining division ratios 1 / 4 and 1 / 5, DIVout326 is different from the "new" DIVout324. This means that the clock divider 200 still cannot completely provide a constant division ratio at an input clock frequency of 10 GHz within a predefined tolerance range (as required by the industry) during the simulated service life of 10 years considering all (physically meaningful) process / voltage / temperature variations of such a device.

[0044] Figure 4 shows an improved high-speed CMOS logic circuit configured as a clock divider 400. This high-speed divider 400 can divide an input clock signal by factors of 3, 4, and 5 even at a very high input clock rate. Therefore, it is a high-speed multi-factor divider.

[0045] The clock divider 400 includes first to seventh gate inverters 410, 415, 420, 425, 430, 435, 440. The gate inverters 410, 415, 420, 425, 430, 435, 440 of the clock divider 400 are of the same type as those described in detail with reference to the clock divider 200. The clock divider 400 includes an additional inverter 460 disposed in the opposite direction between the node divN_stage2 416 and the node divN_stage2b 470, and is itself coupled to the input of the first gate inverter 410.

[0046] The clock divider 400 also includes a NAND2 445, the first input of which is coupled to the node divN_stage4 426. The second input of the NAND2 445 is coupled to the control signal clkb_stg1n3 427. The output of the NAND2 445 is coupled to the PMOS control input of the first gate inverter 410.

[0047] Furthermore, the clock divider 400 includes a NAND3 450, the first input of which is coupled to the node divN_stage5 431. The second input of the NAND3 450 is coupled to the node divN_stage7 441, and the node divN_stage7 441 is itself coupled to the output of the seventh gate inverter 440. The third input of the NAND3 450 is coupled to the control signal clk_stg2n4 442. The output of the NAND3 450 is coupled to the PMOS control input of the second gate inverter 415.

[0048] The control signal 480 is provided based on the clock signal CLK and the inverted clock signal CLKB, as well as the selection signals sel<3>481 and sel<4>482. Also in this case, different division ratios of the clock divider 400 can be selected based on the selection signals sel<3>481 and sel<4>482.

[0049] The DIVout495 of the clock divider 400 is provided at node divN_stage2b 470 after applying execution time adjustment, stabilization, and / or buffering using additional inverters 491, 492, 493.

[0050] NAND2 445 generates a DIVout495 high time of two periods (2T). An additional inverter 460 generates a DIVout495 low time of one period (1T). Node divN_stage5 431 generates a DIVout495 low time of two periods (2T). Node divN_stage7 441 generates a DIVout495 low time of three periods (3T). Since NAND2 445 is shared by different coefficients of the clock divider 400, different division ratios have a DIVout495 high time of two periods (2T).

[0051] Furthermore, by using clock gating to the PMOS pull-up of the gate inverter, the low time of its output can be increased for any number of cycles.

[0052] The clock divider 400 provides different coefficients (division ratios), which can be selected by gating only the clock signal CLK (the first control signal) coupled to the NMOS in gate inverter 430 ("half latch") or gate inverter 440. This means that gate inverter 430 or gate inverter 440 is partially gated (half-gated) with the inverted clock signal CLKB (the second control signal), and the incoming input signal pulls to a known state via the PMOS.

[0053] In other words, only one of the PMOS and NMOS (pull-up or pull-down) clocks of the gate inverter is gated. As a result, only one side of the gate inverter is gated, so the driving strength required for gate clocking is even lower, and the power consumption is low. Since the PMOS size is at least twice as large as the NMOS, when the driving strengths are equal, if only the NMOS is gated, the power consumption can be further reduced. By using half gating, it is very simple and compact compared to the case where both the PMOS and NMOS are gated. According to a further aspect, when both are gated, the gate inverter becomes "tri-state" with an undefined output. For example, since the data entering the gate inverter toggles up and down, by gating only the NMOS, the PMOS periodically pulls up the output to a known state. That is, the output signal is defined based on the data entering the gate inverter.

[0054] In the clock divider 400, instead of using combinational logic on the data different from the case of the clock divider 200, three different coefficients (division ratios) are selected by gating the clock. The clock can be a buffered "open loop" that enables breaking through the speed box, that is, it is possible to make the maximum speed at which the clock divider 400 can operate much higher than the maximum speed at which the clock divider 200 can operate.

[0055] The clock dividers 200 and 400 described in this specification can be configured for frequencies higher than high frequencies, for example, frequencies exceeding 100 MHz, preferably frequencies exceeding 1 GHz, more preferably frequencies close to or even more preferably exceeding 10 GHz or radio frequencies. The clock dividers 200 and 400 can be suitable for use in an analog-to-digital converter (ADC) or a phase-locked loop (PLL).

[0056] The clock dividers 200 and 400 can be configured to function robustly over the lifetime of the underlying product (more than 10 years). Due to their robustness, the clock dividers 200 and 400 can be configured to provide predefined specifications for all (physically meaningful) process / voltage / temperature (PVT) variations in the presence of device aging or degradation. In particular, the clock divider 400 can be configured to operate at a frequency exceeding 10 GHz in a 65 nm topology for all (physically meaningful) PVT variations in the presence of device aging or degradation.

[0057] In one usage example, an electronic circuit can be implemented as the clock dividers 200 and 400 within a PLL. The clock generated by the PLL may need to be divided for comparison with a reference clock. To slow it down, the entire clock divider may be divided into several stages, where the first stage may have the highest speed (the operating frequency at which this stage can operate) and is the most difficult to design. In a particular usage example of the PLL, the first-stage clock divider (prescaler) may be required to be a three-factor that provides selectable division ratios of 1 / 3, 1 / 4, and 1 / 5. The present electronic circuit representing the exemplary clock dividers 200 and 400 can be configured to meet these requirements.

[0058] However, the electronic circuit is general and thus is not limited to implementation in an ADC or a PLL.

[0059] FIG. 5 is a simplified schematic diagram of a gate inverter including a bus holder.

[0060] In box 510, the gate inverter is shown according to the gate-level representation. In box 530, the gate inverter is shown according to the transistor representation.

[0061] The box 510 following node 512 shows a ring configuration including a first inverter 516 and a second inverter 518. The output signal Y is provided at node 514.

[0062] In box 530, according to the transistor representation, a first inverter 516 and a second inverter 518 are shown. Each of the first and second inverters 516, 518 includes PMOS 536, 540 and NMOS 538, 542.

[0063] In any case, the first and second inverters 516, 518 provide a capacitive effect. Therefore, the clock can be stopped without weakening or changing the values of the outputs 514, 534 of the gate inverters. Therefore, the crow-bar current is avoided.

[0064] All gate inverters of the clock divider 200 and the clock divider 400 include bus holders. However, generally, the bus holder is optional and not essential for the clock dividers 200, 400.

[0065] FIG. 6 is a simplified schematic diagram of a processing signal 600 according to the clock divider 400. The principle layout of FIG. 6 corresponds to FIG. 3 showing the processing signal 300 of the clock divider 200. Therefore, a comparison of these figures provides a measure of the performance of both examples of the clock dividers 200, 400. Also in this case, time in ns is shown on the x-axis. The y-axis shows the amplitude of each signal that switches between "high" and "low".

[0066] Clk_stg1n3 612 and clkb_stg1n3 614 are clock signals and inverted clock signals used to gate the gate inverters. The clock signal frequency is 11 GHz in FIG. 6.

[0067] divN_stage1~divN_stage7 620 are the output signals of the gate inverters 410, 415, 420, 425, 430, 435, 440 of the clock divider 400.

[0068] sel<4>622 is one of the selection signals for the clock divider 400 to select among different division ratios Div-3, Div-4, and Div-5. Therefore, the output signal of the gate inverter, i.e., the signals divN_stage1~divN_stage7 620, changes corresponding to the switching sel<4> at different times among Div-3, Div-4, and Div-5. DIVout626 shows the division output of the simulation of the new silicon, and DIVout628 shows the division output after 10 years of aging. They provide different ratios between logic "high" and logic "low" based on the states of sel<3> and especially sel<4>622, so that the clock divider 400 provides different division ratios.

[0069] As is evident from the comparison between the "aged" DIVout628 and the "new" DIVout626, both signals are substantially the same for all division ratios 1 / 3, 1 / 4, and 1 / 5 even after a simulated 10-year lifetime and all (physically meaningful) PVT variations. This means that the clock divider 400 achieves a high maximum speed by avoiding the application of slow combinational logic to the data, only by half-gating the gate inverter, and by constructing the clock divider 400 according to an "open-loop" clock buffer configuration. The clock divider 400 can operate at frequencies exceeding 11 GHz and provide a constant division ratio at these frequencies during a lifetime of over 10 years (within an ignorable tolerance range). Therefore, a division ratio is provided at these frequencies even for all (physically meaningful) process / voltage / temperature (PVT) variations in the presence of device aging or degradation.

[0070] Although the present disclosure has been described above with reference to specific examples, it is not limited to these examples, and those skilled in the art will be able to come up with further alternative examples within the scope of the clock divider described in the claims.

Claims

1. An electronic circuit, a ring oscillator, a first set of gate inverters coupled between a first node and a second node, a second set of gate inverters coupled between the second node and a third node, a first switching circuit including a first switch and a second switch coupled in series between a first voltage node and the first node, wherein the first switch has a control terminal coupled to the second node and the second switch has a control terminal coupled to the third node, the first switching circuit; a second switching circuit including a third switch and a fourth switch coupled in series between a second voltage node and the first node, wherein the third switch has a control terminal coupled to the second node and the fourth switch has a control terminal coupled to receive a first selection signal, the second switching circuit; a third switching circuit including a fifth switch and a sixth switch coupled in series between the second voltage node and the first node, wherein the fifth switch has a control terminal coupled to the third node and the sixth switch has a control terminal coupled to receive a second selection signal, the third switching circuit; including the ring oscillator, wherein at least one of the gate inverters is configured to receive an oscillation signal at an inverter input, receive a first clock signal at a first complementary input, and receive a second clock signal, which is an inverted signal of the first clock signal, at a second complementary input, an electronic circuit, wherein a division ratio of the ring oscillator is selectable based on logic levels of the first and second selection signals.

2. The electronic circuit according to claim 1, wherein the electronic circuit is a clock divider.

3. The electronic circuit according to claim 1, wherein the ring oscillator, a third set of gate inverters coupled between the third node and a fourth node, A fourth switching circuit including a seventh switch and an eighth switch coupled in series between the second voltage node and the first node, the seventh switch having a control terminal coupled to the third node, and the eighth switch having a control terminal coupled to the fourth node, the fourth switching circuit; An electronic circuit further including the above. **Claim 4** The electronic circuit according to claim 1, wherein the set of the first and second gate inverters each includes two gate inverters coupled in series. **Claim 5** The electronic circuit according to claim 1, wherein at least one gate inverter outputs a logic high or a logic low according to a logic state of an input signal and is partially gated so as to be selectable by applying partial gating to either a PMOS or an NMOS. **Claim 6** The electronic circuit according to claim 1, wherein a duty cycle of the first or second signal is greater than 0.

5. **Claim 7** The electronic circuit according to claim 1, wherein each of the first, second, third, fourth, fifth, and sixth switches is a transistor. **Claim 8** The electronic circuit according to claim 3, wherein each of the first, second, third, fourth, fifth, sixth, seventh, and eighth switches is a transistor. **Claim 9** The electronic circuit according to claim 1, wherein the set of the first gate inverters includes a first gate inverter that receives a first logic signal at a first complementary input and receives a second logic signal that is an inverted signal of the first logic signal at a second complementary input, and a second gate inverter that receives a third logic signal at the first complementary input and receives a fourth logic signal that is an inverted signal of the third logic signal at the second complementary input, wherein the first and fourth logic signals have the same logic, and the second and third logic signals have the same logic. **Claim 10** The electronic circuit according to claim 1, wherein the gate inverter has a bus holder. **Claim 11** The electronic circuit according to claim 1, wherein the electronic circuit is a three-factor clock divider. **Claim 12** The electronic circuit according to claim 11, wherein at least one division ratio for 3, 4, and 5 is selectable. **Claim 13** A clock divider, N gate inverters connected in series, each of the gate inverters including an input for receiving an oscillation signal, an output for outputting the oscillation signal, a first control input for receiving a first control signal, and a second control input for receiving a second control signal, the N gate inverters; an inverter coupled between the output of the second gate inverter and the input of the first gate inverter; a first logic circuit including a first input coupled to the output of the Nth gate inverter, a second input coupled to the output of the fifth gate inverter, a third input coupled to receive a first clock signal, and an output coupled to the first control input of the second gate inverter, the first logic circuit having an OR function; a second logic circuit including a first input coupled to the output of the fourth gate inverter, a second input coupled to receive a second clock signal which is an inverted signal of the first clock signal, and an output coupled to the first control input of the first gate inverter, the second logic circuit having an AND function; comprising; two adjacent gate inverters being alternately gated by respective first and second control signals; a clock divider configured to be able to select a division ratio based on the first or second control signal.

14. The clock divider according to claim 13, wherein the first input of the first logic circuit is coupled to the output of the seventh gate inverter.

15. The clock divider according to claim 13, wherein the first control signal and the second control signal are opposite to each other.

16. The clock divider according to claim 15, wherein the first and second control inputs of at least one gate inverter are complementary inputs, and the at least one gate inverter is partially gated to output a logic high or a logic low according to the logic state of an input signal, and is selectable by applying partial gating to either PMOS or NMOS.

17. The clock divider according to claim 13, wherein the duty cycle of the first or second control signal is greater than 0.

5.

18. The clock divider according to claim 13, The clock divider, wherein the clock divider is a three-factor clock divider.

19. The clock divider according to claim 18, The clock divider, wherein at least one division ratio can be selected for 3, 4, and 5.

20. The clock divider according to claim 13, The clock divider, wherein the gate inverter has a bus holder.

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