Device

Abstract

To provide a reception device for three differential signals derived from signals transmitted on three lines in compliance with the Channel Physical Layer (C-PHY) of the Mobile Industry Processor Interface (MIPI).SOLUTION: A device 1 includes a first output unit (Rise-side output unit 2) that outputs a first pulse in response to rising of at least one of a plurality of signals, a second output unit (Fall-side output unit 3) that outputs a second pulse in response to falling of at least one of the plurality of signals, a detection unit 4 for detecting a preceding pulse which is first output among the first pulse and the second pulse each time it falls into a state where no pulse is detected, and a selection unit 5 that selects the edge of the preceding pulse detected by the detection unit as the edge of a clock pulse included in a clock.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an apparatus.

Background Art

[0002] Patent Documents 1 to 3 describe that "when the delay circuit 101 receives the input clock signal CKA, it delays the signal by a fixed time td1 to create and output a delayed clock signal CKD. When the OR gate 102 receives the delayed clock signal CKD and the input clock signal CKA, it expands the width of the H level of the input clock signal CKA by a fixed time td1 to create and output an oscillation control signal CT1." [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-051737 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-112427 [Patent Document 3] International Publication No. 2008 / 032701

Summary of the Invention

[0003] In a first aspect of the present invention, an apparatus is provided. The apparatus may include a first output unit that outputs a first pulse in response to at least one of a plurality of signals rising. The apparatus may include a second output unit that outputs a second pulse in response to at least one of a plurality of signals falling. The apparatus may include a detection unit that detects a preceding pulse, which is the first output among the first pulse and the second pulse, each time a non-detection state of a pulse occurs. The apparatus may include a selection unit that selects an edge of the preceding pulse detected by the detection unit as an edge of a clock pulse included in a clock.

[0004] The first output unit may include a plurality of first pulse generators that each generate a reference pulse with a first reference width in response to any one of the corresponding plurality of signals rising. The first output unit may include a first OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of first pulse generators as a first pulse. The second output unit may include a plurality of second pulse generators that each generate a reference pulse with a first reference width in response to any one of the corresponding plurality of signals falling. The second output unit may include a second OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of second pulse generators as a second pulse.

[0005] The first reference width may be a pulse width in which the first pulse and the second pulse overlap at least partially when one rising and one falling of the plurality of signals occur in the interval of the clock pulse.

[0006] The first reference width may be a pulse width greater than the maximum value of the intervals between the rising and falling of the plurality of signals that can occur in the interval of the clock pulse.

[0007] The first reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulse.

[0008] The first reference width may be a pulse width such that when two or more of the plurality of signals rise in the interval of the clock pulse, two or more reference pulses generated corresponding to each of the two or more signals partially overlap to form one first pulse, and when two or more of the plurality of signals fall in the interval of the clock pulse, two or more reference pulses generated corresponding to each of the two or more signals partially overlap to form one second pulse.

[0009] The detection unit may include a pulse detection unit that detects the first pulse and the second pulse output from the first output unit and the second output unit, respectively. The detection unit may include an invalidation unit that invalidates the detection by the pulse detection unit for the pulse output later when the first pulse and the second pulse are partially overlapped and output in each interval of the clock pulse.

[0010] The detection unit may detect a preceding pulse by detecting the first generated pulse among a third pulse with a third reference width generated in response to the output of the first pulse and a fourth pulse with the third reference width generated in response to the output of the second pulse.

[0011] The third reference width may be a pulse width in which the third pulse and the fourth pulse overlap at least partially when a rise and a fall of a plurality of signals occur one by one in an interval of the clock pulse.

[0012] The third reference width may be a pulse width larger than the maximum value of the intervals between the rise and fall of a plurality of signals that may occur in an interval of the clock pulse.

[0013] The third reference width may be a pulse width larger than 0.4 times the reference interval of the clock pulse.

[0014] The detection unit may include a pulse detection unit that detects the third pulse and the fourth pulse, respectively. The detection unit may include an invalidation unit that invalidates the detection by the pulse detection unit for the pulse output later when the third pulse and the fourth pulse are partially overlapped and output in each interval of the clock pulse.

[0015] The plurality of signals may be three differential signals derived from signals transmitted on three lines in accordance with the channel physical layer (C-PHY) of the Mobile Industry Processor Interface (MIPI).

[0016] Note that the above summary of the invention does not enumerate all the necessary features of the present invention. Also, sub - combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0018] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0019] [1. Configuration of Apparatus 1] FIG. 1 shows the apparatus 1 according to the present embodiment.

[0020] The apparatus 1 generates a clock pulse clk from a plurality of signals. For example, the apparatus 1 may generate a clock pulse clk from three signals, and in addition to this, it may read data (for example, video data) from the three signals. The apparatus 1 includes a Rise - side output unit 2, a Fall - side output unit 3, a detection unit 4, a selection unit 5, and a data reading unit 6. These configurations may be composed of logic circuits. Note that in the present embodiment, as an example, since the apparatus 1 conforms to the Mobile Industry Processor Interface (MIPI) Channel Physical Layer (C - PHY), the C - PHY will be described prior to the description of each configuration.

[0021] [1.1. C - PHY] In C-PHY, not only the data to be communicated but also the clock signal is embedded in the signals A, B, and C transmitted via three lines. Each of the signals A, B, and C takes a different value among the three values of High, Middle, and Low, and the three signals A, B, and C as a whole can take the six states of “+x”, “-x”, “+y”, “-y”, “+z”, and “-z” in Table 1 below.

[0022]

Table 1

[0023] The state of the entire signals A, B, and C transitions to a different state every UI (Unit Interval). As a result, the signals A, B, and C as a whole can send 5-value data (also referred to as symbols) in each UI. The UI is a unit time determined on the transmission side of the signals A, B, and C to transmit one symbol, and may have a length of, for example, 12.5 to 1000 ns. Since jitter occurs in the transmitted signals, on the receiving side of the signals A, B, and C, a clock pulse clk is generated based on the change in the signal levels of the received signals A, B, and C, and data is acquired from the signals A, B, and C based on the timing of this clock pulse clk.

[0024] Here, as described above, the signals A, B, and C as a whole take six states and transition to any of the five states different from the original state by state transition, so as a result, 30 (= 6 × 5) types of state transitions can occur. However, the 30 types of state transitions include equivalent state transitions, and the 30 types of state transitions can be grouped into the following three types of state transitions using the differential signals Diff (also referred to as signal Diff (AB) ,Diff (BC) ,Diff (CA) ).

[0025] The first type of state transition is the signal Diff (AB) ,Diff (BC) ,Diff (CA)when all of them cross the voltage 0 (also referred to as zero - crossing). This state transition is, for example, a transition from the state “+x” to the state “-x”. In this case, for signals Diff (AB) , Diff (BC) , Diff (CA) , two of them zero - cross and rise from negative to positive, and the remaining one zero - crosses and falls from positive to negative, or for signals Diff (AB) , Diff (BC) , Diff (CA) , two of them zero - cross and fall from positive to negative, and the remaining one zero - crosses and rises from negative to positive.

[0026] The second type of state transition is when two of the signals Diff (AB) , Diff (BC) , Diff (CA) cross the voltage 0. This state transition is, for example, a transition from the state “+x” to the state “+y”. In this case, for signals Diff (AB) , Diff (BC) , Diff (CA) , one of them zero - crosses and rises from negative to positive, and the other one zero - crosses and falls from positive to negative.

[0027] The third type of state transition is when one of the signals Diff (AB) , Diff (BC) , Diff (CA) crosses the voltage 0. This state transition is, for example, a transition from the state “+x” to the state “-y”. In this case, for signals Diff (AB) , Diff (BC) , Diff (CA) , one of them zero - crosses and rises from negative to positive or falls from positive to negative.

[0028] In the first and second types of state transitions where two or more zero crossings occur, zero crossings can occur before and after within the UI. For example, in the first type of state transition where three zero crossings occur, ideally all zero crossings occur simultaneously, but due to the influence of jitter or the like, zero crossings can occur at intervals within 0.2UI. Also, in the second type of state transition where two zero crossings occur, zero crossings can occur at intervals within 0.4UI.

[0029] In these cases, rising zero crossings do not occur continuously within the UI, and falling zero crossings do not occur continuously within the UI either. For example, if a rising zero crossing occurs first within the UI, then a falling zero crossing will definitely occur next within the same UI. Similarly, if a falling zero crossing occurs first within the UI, then a rising zero crossing will definitely occur next within the same UI. After a rising zero crossing, a rising zero crossing will not occur without a falling zero crossing occurring. Also, after a falling zero crossing, a falling zero crossing will not occur without a rising zero crossing occurring.

[0030] Also, when a second state transition occurs within consecutive UIs, in each of these UIs, the order of the rising zero crossing and the falling zero crossing will be the same. That is, in each of these UIs, a falling zero crossing occurs after a rising zero crossing occurs, or in each of these UIs, a rising zero crossing occurs after a falling zero crossing occurs.

[0031] Also, among consecutive UIs, if a second state transition occurs in the previous UI and a first state transition occurs in the subsequent UI, among the rising and falling zero crossings, the zero crossing that occurs first in the previous UI will occur in the subsequent UI. That is, if a rising zero crossing occurs first and then a falling zero crossing occurs in the previous UI, then a rising zero crossing will occur in the subsequent UI.

[0032] Similarly, in a series of UIs, when a first state transition occurs in a previous UI and a second state transition occurs in a subsequent UI, among the rising and falling zero crossings, the zero crossing that occurs in the previous UI occurs earlier in the subsequent UI. That is, when a rising zero crossing occurs in the previous UI, a falling zero crossing occurs after a rising zero crossing occurs in the subsequent UI.

[0033] In the C-PHY that performs data transmission as described above, the signal Diff (AB) , Diff (BC) , Diff (CA) can generate the clock pulse clk at the zero crossing timing. When multiple zero crossings occur within a UI, the clock pulse clk may be generated at the earliest zero crossing.

[0034] The apparatus 1 according to the present embodiment may obtain three signals Diff (AB) , Diff (BC) , Diff (CA) derived from the signals A, B, and C transmitted on three lines in accordance with C-PHY. For example, the apparatus 1 may obtain the signals Diff (AB) , Diff (BC) , Diff (CA) from a receiving apparatus that receives the signals A, B, and C and generates the signals Diff (AB) , Diff (BC) , Diff (CA) .

[0035] [1.2. Rise-side output unit 2] The Rise-side output unit 2 is an example of the first output unit, and outputs a Rise-side pulse in response to at least one of a plurality of signals Diff (AB) , Diff (BC) , Diff (CA) rising. That the signals Diff (AB) , Diff (BC) , Diff (CA) rise means that the signals Diff (AB) , Diff (BC) , Diff (CA)may cross zero and rise from negative to positive. The Rise side output unit 2 includes three pulse generators 20 (pulse generator 20 (AB) , 20 (BC) , 20 (CA) also referred to as) and an OR gate 21. Note that the subscript symbols within parentheses in the descriptions such as pulse generator 20 (AB) , 20 (BC) , 20 (CA) indicate the corresponding signals among the signals Diff (AB) , Diff (BC) , Diff (CA) .

[0036] The three pulse generators 20 (AB) , 20 (BC) , 20 (CA) generate a reference pulse P (AB) , Diff (BC) , Diff (CA) of a reference width in response to any one of the corresponding signals Diff rising. The reference width of the reference pulse P rise (reference pulse P rise(AB) , P rise(BC) , P rise(CA) also referred to as) is an example of a first reference width and will be described in detail later. Each pulse generator 20 may supply the generated reference pulse P rise to the OR gate 21. rise

[0037] The OR gate 21 is connected to each of the three pulse generators 20. The OR gate 21 is an example of a first OR gate and outputs the logical sum of the reference pulses P rise generated by each of the three pulse generators 20 as a Rise side pulse. The OR gate 21 may supply the Rise side pulse to the detection unit 4. Also, the OR gate 21 may supply the Rise side pulse to the "0" input terminal in the selection unit 5.

[0038] [1.3. Fall side output unit 3] The Fall side output unit 3 is an example of a second output unit and a plurality of signals Diff​(AB) , Diff (BC) , Diff (CA) Outputs a Fall - side pulse in response to at least one of them falling. Signal Diff (AB) , Diff (BC) , Diff (CA) falling means that signal Diff (AB) , Diff (BC) , Diff (CA) may cross zero and fall from positive to negative. The Fall - side output section 3 has three pulse generators 30 (pulse generator 30 (AB) , 30 (BC) , 30 (CA) also called) and an OR gate 31.

[0039] The three pulse generators 30 (AB) , 30 (BC) , 30 (CA) each generate a reference pulse P of a reference width in response to any one of the corresponding signal Diffs falling. Each pulse generator 30 (AB) , Diff (BC) , Diff (CA) . Among them, a reference pulse P fall (P fall(AB) , P fall(BC) , P fall(CA) also called) respectively. Each pulse generator 30 may supply the generated reference pulse P fall to the OR gate 31.

[0040] The OR gate 31 is connected to each of the three pulse generators 30. The OR gate 31 is an example of a second OR gate and outputs the logical sum of the reference pulses P fall generated by each of the three pulse generators 30 as a Fall - side pulse. The OR gate 31 may supply the Rise - side pulse to the detection section 4. Also, the OR gate 31 may supply the Fall - side pulse to the "1" input terminal in the selection section 5.

[0041] [1.4. Reference width of reference pulse P rise , P fall Reference pulse P​rise , P fall The reference width is such that when one rising edge and one falling edge of the signal Diff occur within the interval of the clock pulse clk (AB) , Diff (BC) , Diff (CA) , the Rise - side pulse from the Rise - side output section 2 (here, the reference pulse P rise itself) and the Fall - side pulse from the Fall - side output section 3 (here, the reference pulse P fall itself) may overlap at least partially. For example, the reference width is such that when the signal Diff (AB) rises and the signal Diff (BC) falls within the interval of the clock pulse clk, the reference pulse P (AB) generated by the pulse generator 20 of the Rise - side output section 2 rise(AB) and the reference pulse P (BC) generated by the pulse generator 30 of the Fall - side output section 3 fall(BC) are necessarily partially overlapping.

[0042] Also, the reference width is such that when two or more of the signals Diff (AB) , Diff (BC) , Diff (CA) rise within the interval of the clock pulse clk, the two or more reference pulses P rise generated corresponding to each of the two or more signals partially overlap to form one Rise - side pulse. Also, the reference width is such that when two or more of the signals Diff (AB) , Diff (BC) , Diff (CA) fall within the interval of the clock pulse clk, the two or more reference pulses P fall generated corresponding to each of the two or more signals partially overlap to form one Fall - side pulse. For example, the reference width is such that when two signals Diff (AB) , Diff (BC) rise within the interval of the clock pulse clk, the two signals Diff (AB) , Diff(BC) According to each of them, two pulse generators 20 of the Rise side output unit 2 (AB) , 20 (BC) generate two reference pulses P rise(AB) , P rise(BC) such that they always partially overlap to form one Rise side pulse. Note that when the two signals Diff (AB) , Diff (BC) rise, these rises and the fall of the remaining signal Diff (CA) may occur simultaneously, or the fall of the remaining signal Diff (CA) may occur within the time of the reference width from the previous rise timing.

[0043] Also, the reference width may be a pulse width greater than the maximum value of the interval between the rise and fall of the signals Diff (AB) , Diff (BC) , Diff (CA) that can occur within the interval of the clock pulse clk. The maximum value of the interval between the rise and fall may be 0.4 times the reference interval of the clock pulse clk. Therefore, the reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulse clk. The length of the reference interval may be the length of the UI set by the transmission sources of the signals A, B, and C. In this case, the reference width may be, for example, 0.45UI or 0.5UI or more.

[0044] [1.5. Detection unit 4] Each time the detection unit 4 enters a pulse non-detection state (also referred to as the wait state), it detects the first output leading pulse. The pulse non-detection state may be a state where pulses output from the Rise side output unit 2 and the Fall side output unit 3 are not detected. The detection unit 4 may detect the first output pulse among the Rise side pulses and Fall side pulses output from the Rise side output unit 2 and the Fall side output unit 3 in the non-detection state as the leading pulse. The detection unit 4 includes a pulse detection unit 40 and an inactivation unit 41.

[0045] The pulse detection unit 40 detects the Rise-side pulse and the Fall-side pulse output from the Rise-side output unit 2 and the Fall-side output unit 3, respectively. The pulse detection unit 40 may supply a selection signal Sel to the selection unit 5 to cause the selection unit 5 to make a selection according to which of the Rise-side pulse and the Fall-side pulse is detected. In this embodiment, as an example, when the pulse detection unit 40 detects the Rise-side pulse, it may supply the selection unit 5 with a selection signal Sel indicating "0" to which the Rise-side pulse is input among the "0" and "1" input terminals in the selection unit 5. Similarly, when the pulse detection unit 40 detects the Fall-side pulse, it may supply the selection unit 5 with a selection signal Sel indicating "1" to which the Fall-side pulse is input among the "0" and "1" input terminals in the selection unit 5. When the pulse detection unit 40 detects both the Rise-side pulse and the Fall-side pulse, it may supply the selection unit 5 with a selection signal Sel indicating "0", or may supply a selection signal Sel indicating "1".

[0046] When the invalidation unit 41 outputs a pulse from the Rise-side output unit 2 and a pulse from the Fall-side output unit 3 that partially overlap each other in each interval of the clock pulse clk, the invalidation unit 41 invalidates the detection by the pulse detection unit 40 for the pulse output later. For example, the invalidation unit 41 may invalidate the detection of a pulse output when the detection unit 4 is in a state of detecting a preceding pulse (also referred to as a busy state). Thereby, when the Rise-side pulse and the Fall-side pulse are partially overlapped and output, only the preceding pulse is detected by the pulse detection unit 40. In other words, a pulse output when the detection unit 4 is in a wait state where it has not detected a preceding pulse is detected by the pulse detection unit 40. The invalidation unit 41 may disable the detection function for the pulse output later among the detection function for the Rise-side pulse and the detection function for the Fall-side pulse in the pulse detection unit 40. When the Rise-side pulse and the Fall-side pulse are output simultaneously, the invalidation unit 41 may not invalidate the detection by the pulse detection unit 40, or may invalidate the detection of one of the Rise-side pulse and the Fall-side pulse determined in advance.

[0047] When the detection of one of the Rise-side pulse and the Fall-side pulse is invalidated, that is, when the other pulse is detected first and the detection unit 4 is in a busy state, the detection unit 4 may enter a non-detection state of the pulse, that is, a wait state, in response to the state where the other pulse is not detected. That is, when the detection of the trailing pulse that overlaps the preceding pulse among the Rise-side pulse and the Fall-side pulse is invalidated, the trailing pulse is not detected by the pulse detection unit 40. In this state, if the preceding pulse is not detected (that is, if the detected preceding pulse falls), since neither the Rise-side pulse nor the Fall-side pulse is detected, the detection unit 4 may enter a non-detection state. Thereby, the detection unit 4 may enter a state of waiting for the detection of the next preceding pulse.

[0048] When the detection of a pulse is invalidated by the invalidation unit 41, the invalidation may be canceled in response to the fall of the pulse. For example, when a Rise-side pulse is detected as a preceding pulse and a subsequently rising Fall-side pulse is invalidated, the invalidation of the detection of the Fall-side pulse may be canceled in response to the fall of the Fall-side pulse. Thereby, when, among the Rise-side pulse and the Fall-side pulse, after the other pulse that is output overlapping one of the pulses is invalidated and the other pulse is output again, the other pulse may be detected as a preceding pulse. Note that when the Rise-side pulse and the Fall-side pulse are output without overlapping, since the detection of the subsequent Fall-side pulse is not invalidated by the invalidation unit 41, the subsequent Fall-side pulse may be detected as the next preceding pulse.

[0049] The invalidation unit 41 may detect that a new interval of the clock pulse clk has started, in response to the detection of a Rise-side pulse and a Fall-side pulse by the pulse detection unit 40, or may detect it in response to the output of the clock pulse clk from the device 1, or may detect it in response to the output of the selection signal Sel from the pulse detection unit 40.

[0050] [1.6. Selection unit 5] The selection unit 5 selects the edge of the preceding pulse detected by the detection unit 4 as the edge of the clock pulse clk included in the clock. The selection unit 5 may select either the edge of the Rise-side pulse or the edge of the Fall-side pulse as the edge of the clock pulse clk based on the selection signal Sel from the detection unit 4. In this embodiment, as an example, the selection unit 5 selects the start edge (for example, rising edge) and the end edge (for example, falling edge) of the preceding pulse as the start edge and the end edge of the clock pulse clk, that is, selects the preceding pulse as the clock pulse clk.

[0051] The selection unit 5 may select either the Rise-side pulse input to the "0" input terminal from the Rise-side output unit 2 or the Fall-side pulse input to the "1" input terminal from the Fall-side output unit 3 according to whether the selection signal Sel indicates "0" or "1". In this embodiment, as an example, the selection unit 5 may be a multiplexer.

[0052] The selection unit 5 may supply the selected clock pulse clk to the data reading unit 6. The selection unit 5 may output the clock pulse clk to the outside of the apparatus 1.

[0053] [1.7. Data Reading Unit 6] The data reading unit 6 latches the signals Diff (AB) , Diff (BC) , Diff (CA) . The data reading unit 6 may latch the signals Diff (AB) , Diff (BC) , Diff (CA) respectively in accordance with the clock pulse clk supplied from the selection unit 5. Thereby, for example, the signals Diff (AB) , Diff (BC) , Diff (CA) of the n-th (where n is a natural number) UI may be latched in accordance with the clock pulse clk generated from the signals Diff (AB) , Diff (BC) , Diff (CA) of the (n + α)-th (where α is an integer of 0 or more) UI. Instead of this, the signals Diff (AB) , Diff (BC) , Diff (CA) of the n-th UI may be latched in accordance with the clock pulse clk generated from the signals Diff (AB) , Diff (BC) , Diff (CA) of the (n - α)-th UI.

[0054] The data reading unit 6 may be a D flip-flop provided for each of the signals Diff (AB) , Diff (BC) , Diff (CA) . The data reading unit 6 outputs the latched signal Diff(AB) , Diff (BC) , Diff (CA) The data of (CA) may be output to the outside. For example, the data reading unit 6 may supply the latched data to the display driver of the display.

[0055] According to the above device 1, for a plurality of signals Diff (AB) , Diff (BC) , Diff (CA) Whenever at least one of (AB) , (BC) , (CA) rises or falls, and a non-detection state of the Rise-side pulse and the Fall-side pulse output according thereto occurs, the first output leading pulse is detected and selected as the clock pulse clk. Therefore, among the rising and falling changes of the signal Diff, the clock pulse clk corresponding to the change that occurs first within the same UI can be generated, and it is possible to prevent the clock pulse clk from being erroneously generated according to the change that occurs later. Thereby, the tolerance to jitter, and thus the accuracy of the clock pulse clk, can be improved.

[0056] Also, the Rise-side output unit 2 and the Fall-side output unit 3 include a plurality of pulse generators 20, 30 that generate reference pulses P of a reference width according to the rising or falling of any one of the corresponding signals Diff rise , reference pulse P fall respectively, and OR gates 21, 31 that output the logical sum of the generated reference pulses P rise , logical sum of reference pulse P fall , logical sum of reference pulse P

[0057] Also, the reference pulse P rise , P fallThe reference width is the pulse width at which one rising edge and one falling edge of the signal Diff occur within the interval of the clock pulse clk, and the Rise-side pulse and the Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse occurs first and the other occurs later within the same UI, it is possible to prevent the later-occurring pulse from being erroneously detected as the leading pulse in the next UI.

[0058] Also, the reference width of the reference pulse P rise ,P fall is a pulse width greater than the maximum value of the intervals between the rising edges and falling edges of a plurality of signal Diffs that can occur within the interval of the clock pulse clk. Therefore, when one rising edge and one falling edge of the signal Diff occur within the interval of the clock pulse clk, the Rise-side pulse and the Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse occurs first and the other occurs later within the same UI, it is possible to prevent the later-occurring pulse from being erroneously detected as the leading pulse in the next UI.

[0059] Also, the reference width of the reference pulse P rise ,P fall is a pulse width greater than 0.4 times the reference interval of the clock pulse clk (in this embodiment, 0.4UI as an example). Therefore, when the maximum value of the intervals between the rising edges and falling edges of a plurality of signal Diffs that can occur within the interval of the clock pulse clk is determined to be 0.4 or less of the reference interval, when one rising edge and one falling edge of the signal Diff occur within the interval of the clock pulse clk, the Rise-side pulse and the Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse occurs first and the other occurs later within the same UI, it is possible to prevent the later-occurring pulse from being erroneously detected as the leading pulse in the next UI. Also, for example, the reference pulse P rise ,P fallBy setting the reference width to 0.5 UI or more, even when the interval between the rise and fall of multiple signal Diffs is 0.5 UI, the Rise-side pulse and the Fall-side pulse can partially overlap, preventing a pulse generated later from being erroneously detected as a preceding pulse in the next UI.

[0060] Also, when the Rise-side pulse and the Fall-side pulse partially overlap and are output in each interval of the clock pulse clk, the detection of a pulse output later is invalidated, so that the change that occurs first among the change in the rise of the signal Diff and the change in the fall can be surely detected. Also, when a pulse corresponding to a change that occurs later crosses the next UI, the detection of the pulse is invalidated, so that the change that occurs first in the next UI can be surely detected.

[0061] Also, the reference pulse P rise , P fall has a reference width such that when two or more of the plurality of signal Diffs (AB) , Diff (BC) , Diff (CA) rise, two or more reference pulses P rise , P fall generated corresponding to each of the two or more signal Diffs partially overlap to form a pulse width of one Rise-side pulse. Also, the reference pulse P rise , P fall has a reference width such that when two or more of the plurality of signal Diffs (AB) , Diff (BC) , Diff (CA) fall in the interval of the clock pulse clk, two or more reference pulses P rise , P fall generated corresponding to each of the two or more signal Diffs partially overlap to form a pulse width of one Fall-side pulse. Therefore, when two or more rises occur within the same UI or when two or more falls occur, the reference pulses P rise , P fallIt is possible to prevent it from being erroneously detected as a leading pulse in the following UI.

[0062] [2. Operation Example] FIG. 2 shows the operation waveform of the apparatus 1. In this figure, as an example, the rising edge of the signal Diff (AB) and the falling edge of the signal Diff (BC) occur in sequence, and when the falling edge of the signal Diff (AB) and the rising edge of the signal Diff (BC) occur in sequence in the second UI, the reference pulses P (AB) , 20 (BC) , 30 (AB) , 30 (BC) output from the pulse generators 20 rise(AB) , P rise(BC) , P fall(AB) , P fall(BC) , the Rise side pulse and the Fall side pulse output from the OR gates 21, 31, the selection signal Sel output from the detection unit 4, and the clock pulse clk output from the selection unit 5 are shown. The horizontal axis in the figure indicates time, and the vertical axis indicates the signal level. In this figure, the states "busy" and "wait" of the detection unit 4 at each time point are also shown. Also, in this operation example, the reference width of the reference pulses P rise , P fall may be 0.6UI.

[0063] First, at time t1, Diff (BC) rises, and when the signal Diff (AB), Diff (CA) falls, the reference pulses P rise(BC) , P fall(AB), P fall(CA) from time t1 to time t3 (= t1 + 0.6UI) are output from the pulse generators 20 (BC) , 30 (BC) , 30 (CA)is output from this. As a result, the Rise-side pulse and Fall-side pulse with a pulse width of 0.6UI from time t1 to time t3 are output from OR gates 21 and 31. In this operation example, as an example, as a result of these Rise-side pulse and Fall-side pulse being detected by the pulse detection unit 40, the detection unit 4 enters the busy state and the selection signal Sel of "0" is output from the detection unit 4. As a result, the Rise-side pulse is selected as the clock pulse clk by the selection unit 5 and output. The detection unit 4 enters the wait state in response to the fall of the Rise-side pulse and Fall-side pulse. In this figure, the reference pulse P fall(CA) is not shown.

[0064] Subsequently, when Diff (BC) falls at time t5, the reference pulse P fall(BC) from time t5 to time t7 (= t5 + 0.6UI) is output from the pulse generator 30 (BC) As a result, the Fall-side pulse with a pulse width of 0.6UI from time t5 to time t7 is output from the OR gate 31. Also, as a result of this Fall-side pulse being detected by the pulse detection unit 40, the detection unit 4 enters the busy state and the selection signal Sel of "1" is output from the detection unit 4. As a result, the Fall-side pulse is selected as the clock pulse clk by the selection unit 5 and output. The detection unit 4 enters the wait state in response to the fall of the Fall-side pulse.

[0065] On the other hand, when the signal Diff (AB) rises at time t6 (= t5 + 0.5UI), the reference pulse P rise(AB) from time t6 to time t9 (= t6 + 0.6UI) is output from the pulse generator 20 (AB)It is output from. As a result, a rising edge pulse with a pulse width of 0.6UI is output from the OR gate 21 from time t6 to time t9. Since this rising edge pulse overlaps with the preceding falling edge pulse, as a result of being invalidated by the invalidation unit 41, it is not detected by the pulse detection unit 40. Therefore, the selection signal Sel output from the detection unit 4 and the clock pulse clk output from the selection unit 5 are not affected by the rising edge pulse. When the rising edge pulse falls at time t9, the invalidation of the detection of the rising edge pulse is released.

[0066] Also, at time t8 between time t7 and time t9, when Diff (AB) falls, a reference pulse P with a reference width is output from the pulse generator 30 fall(AB) from time t8. As a result, a falling edge pulse with a pulse width of 0.6UI is output from the OR gate 31 from time t8. Further, as a result of this falling edge pulse being detected by the pulse detection unit 40, the detection unit 4 becomes busy and a selection signal Sel of "1" is output from the detection unit 4. As a result, the falling edge pulse is selected as the clock pulse clk by the selection unit 5 and output. (AB)

[0067] [3. Modification Example] In the above embodiment, the apparatus 1 receives the signals A, B, and C and receives the signals Diff (AB) , Diff (BC) , Diff (CA) from a receiving apparatus that generates them. However, although it has been described as obtaining the signals Diff (AB) , Diff (BC) , Diff (CA) , the apparatus 1 may receive the signals A, B, and C and generate the signals Diff (AB) , Diff (BC) , Diff (CA) . In this case, the apparatus 1 may further include a receiving unit that receives the signals A, B, and C, and a differential circuit unit that generates the signals Diff (AB) , Diff (BC) , Diff (CA) from the received signals A, B, and C. ​

[0068] Also, although the apparatus 1 has been described as conforming to C-PHY, it does not have to conform to C-PHY. In this case, the apparatus 1 may acquire a plurality of signals having a number different from 3, the Rise-side output unit 2 may output a Rise-side pulse in response to at least one of the plurality of signals rising, and the Fall-side output unit 3 may output a Fall-side pulse in response to at least one of the plurality of signals falling.

[0069] Also, for the signal Diff (AB) ,Diff (BC) ,Diff (CA) the maximum value of the interval between the rising and falling edges has been described as being 0.4 times the reference interval (e.g., UI) of the clock pulse clk, but it may be longer than 0.4 times the reference interval. Even in this case, the reference width of the reference pulse P rise ,P fall may be a pulse width larger than the maximum value of the interval between the rising and falling edges of the signal Diff (AB) ,Diff (BC) ,Diff (CA) .

[0070] Also, although the selection unit 5 has been described as selecting the start edge and the end edge of the preceding pulse as the start edge and the end edge of the clock pulse clk, as long as the start edge of the preceding pulse is selected as the start edge of the clock pulse clk, it does not have to select the end edge of the preceding pulse as the end edge of the clock pulse clk. For example, the selection unit 5 may generate a pulse obtained by stretching the preceding pulse, select the start edge of the preceding pulse as the start edge of the clock pulse clk, and select the end edge of the stretched pulse as the end edge of the clock pulse clk.

[0071] Further, although the detection unit 4 has been described as detecting the Rise-side pulse and the Fall-side pulse and detecting the leading pulse that is output first among the Rise-side pulse and the Fall-side pulse, the leading pulse may be detected by detecting the pulse that is generated first among the third pulse with the third reference width that is generated in response to the output of the Rise-side pulse and the fourth pulse with the third reference width that is generated in response to the output of the Fall-side pulse. In this case, the pulse detection unit 40 of the detection unit 4 may detect the third pulse and the fourth pulse respectively, and when the third pulse and the fourth pulse partially overlap and are output in each interval of the clock pulse, the invalidation unit 41 may invalidate the detection by the pulse detection unit 40 for the pulse output later. Here, the third pulse and the fourth pulse may be generated by the output unit 2 or may be generated by the detection unit 4. The third reference width may be a pulse width in which the third pulse and the fourth pulse at least partially overlap when one rising edge and one falling edge of the signals Diff (AB) ,Diff (BC) ,Diff (CA) occur in each interval of the clock pulse clk. Also, the third reference width may be a pulse width greater than the maximum value of the interval between the rising edge and the falling edge of the signals Diff (AB) ,Diff (BC) ,Diff (CA) that can occur in the interval of the clock pulse clk. Also, the third reference width may be a pulse width greater than 0.4 times the reference interval of the clock pulse clk. When the detection unit 4 detects the leading pulse by detecting the third pulse and the fourth pulse with the third reference width in this way, the pulse generators 20 and 30 may generate reference pulses P rise ,P fall with a reference width narrower than the third reference width. As an example, the reference widths of the third pulse and the fourth pulse may be 0.6 UI, and the pulse widths of the reference pulses P rise ,P fall may be 0.25 UI.

[0072] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0073] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly indicated as "before" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience in the description, it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0074] 1 Device 2 Rise-side output unit 3 Fall-side output unit 4 Detection unit 5 Selection unit 6 Data reading unit 20 Pulse generator 21 OR gate 30 Pulse generator 31 OR gate 40 Pulse detection unit 41 Invalidation unit

Claims

1. A first output unit that outputs a first pulse in response to at least one of a plurality of signals rising; A second output unit that outputs a second pulse in response to at least one of the plurality of signals falling; A detection unit that receives the supply of the first pulse and the second pulse, and detects the leading pulse that is output first among the first pulse and the second pulse every time a non-detection state of the pulse occurs; A selection unit that receives the supply of the first pulse and the second pulse, and selects the edge of the leading pulse detected by the detection unit as the edge of the clock pulse included in the clock; Comprising: The first output unit: A plurality of first pulse generators that respectively generate reference pulses with a first reference width in response to any one of the plurality of signals rising; A first OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of first pulse generators as the first pulse; Having: The second output unit: A plurality of second pulse generators that respectively generate reference pulses with the first reference width in response to any one of the plurality of signals falling; A second OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of second pulse generators as the second pulse; An apparatus having.

2. A first output unit that outputs a first pulse in response to at least one of a plurality of signals rising; A second output unit that outputs a second pulse in response to at least one of the plurality of signals falling; A detection unit that detects the leading pulse that is output first among the first pulse and the second pulse every time a non-detection state of the pulse occurs; A selection unit that selects the edge of the leading pulse detected by the detection unit as the edge of the clock pulse included in the clock; Comprising: The first output unit: A plurality of first pulse generators that respectively generate reference pulses with a first reference width in response to any one of the plurality of signals rising; A first OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of first pulse generators as the first pulse; Having: The second output unit: A plurality of second pulse generators that each generate a reference pulse of the first reference width in response to any one of the corresponding signals rising; A second OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of second pulse generators as the second pulse; having; The apparatus, wherein the first reference width is a pulse width greater than 0.4 times the reference interval of the clock pulse. **Claim 3** A first output unit that outputs a first pulse in response to at least one of a plurality of signals rising; A second output unit that outputs a second pulse in response to at least one of the plurality of signals falling; A detection unit that detects a leading pulse that is output first among the first pulse and the second pulse every time a non-detection state of a pulse occurs; A selection unit that selects an edge of the leading pulse detected by the detection unit as an edge of a clock pulse included in a clock; comprising; The detection unit detects the leading pulse by detecting a pulse that is generated first among a third pulse of a third reference width generated in response to the first pulse being output and a fourth pulse of the third reference width generated in response to the second pulse being output. The apparatus, wherein the third reference width is a pulse width greater than 0.4 times the reference interval of the clock pulse. **Claim 4** The apparatus according to claim 3, wherein the third reference width is a pulse width in which the third pulse and the fourth pulse at least partially overlap when a rise and a fall of the plurality of signals occur one by one in the interval of the clock pulse. **Claim 5** The apparatus according to claim 3 or 4, wherein the third reference width is a pulse width greater than a maximum value of an interval between a rise and a fall of the plurality of signals that can occur in the interval of the clock pulse. **Claim 6** The detection unit a pulse detection unit that detects each of the third pulse and the fourth pulse; and an invalidation unit that invalidates detection by the pulse detection unit for a pulse output later when the third pulse and the fourth pulse partially overlap and are output in each interval of the clock pulse. The apparatus according to any one of claims 4 to 5. **Claim 7** The first output unit A plurality of first pulse generators that respectively generate reference pulses with a first reference width in response to any one of the plurality of signals rising; A first OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of first pulse generators as the first pulse; having; The second output unit A plurality of second pulse generators that respectively generate reference pulses with the first reference width in response to any one of the plurality of signals falling; A second OR gate that outputs the logical sum of the reference pulses generated by each of the plurality of second pulse generators as the second pulse; The device according to any one of claims 3 to 6, having.

8. The first reference width is a pulse width in which the first pulse and the second pulse overlap at least partially when one rise and one fall of the plurality of signals occur in the interval of the clock pulse, according to any one of claims 1, 2, and 7. The device described in the item.

9. The first reference width is a pulse width greater than the maximum value of the intervals between the rise and fall of the plurality of signals that can occur in the interval of the clock pulse, according to any one of claims 1, 2, 7, and 8. The device described in the item.

10. The first reference width is such that when two or more of the plurality of signals rise in the interval of the clock pulse, two or more of the reference pulses generated according to each of the two or more signals partially overlap to form one of the first pulses. When two or more of the plurality of signals fall in the interval of the clock pulse, two or more of the reference pulses generated according to each of the two or more signals partially overlap to form one of the second pulses. The device according to any one of claims 1, 2, and 7 to 9, which is a pulse width.

11. The detection unit A pulse detection unit that respectively detects the first pulse and the second pulse output from the first output unit and the second output unit; The device according to any one of claims 1 to 10, further comprising: an invalidation unit that invalidates detection by the pulse detection unit for a pulse output later when the first pulse and the second pulse overlap partially in each interval of the clock pulse.

12. The apparatus according to any one of claims 1 to 11, wherein the plurality of signals are three differential signals derived from signals transmitted on three lines in accordance with the channel physical layer (C-PHY) of a Mobile Industry Processor Interface (MIPI).

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