Analysis device, analysis method, and program

Abstract

To accurately analyze the characteristics of a semiconductor device.SOLUTION: There is provided an analyzer comprising: an electric charge amount analysis unit that, with a semiconductor device set in an on-state and a power supply voltage applied between a first main terminal and a second main terminal set at an initial voltage, when a current flowing between the first main terminal and the second main terminal is stabilized and subsequently the power supply voltage is changed by a displacement voltage smaller than the initial voltage, analyzes a change in the amount of electric charges in any one of the terminals with a device simulator that simulates a transient change in the electric charges in the semiconductor device; and a capacity calculation unit that calculates the terminal capacity of any one of the terminals based on the change in the amount of electric charges analyzed by the electric charge amount analysis unit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an analysis device, an analysis method, and a program.

Background Art

[0002] Conventionally, a method of analyzing the characteristics of a semiconductor device using a circuit simulator or the like is known (see, for example, Patent Document 1). Patent Document 1 Japanese Patent Application Laid-Open No. 9-18010

Summary of the Invention

Problems to be Solved by the Invention

[0003] It is preferable that the characteristics of the semiconductor device can be analyzed accurately.

Means for Solving the Problems

[0004] In order to solve the above problems, in a first aspect of the present invention, there is provided an analysis device for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal. The analysis device may include a charge amount analysis unit that analyzes a change in the charge amount at any terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage after stabilizing the current flowing between the first main terminal and the second main terminal in a state where the semiconductor device is set to an on state and the power supply voltage applied between the first main terminal and the second main terminal is set to an initial voltage, by a device simulator that simulates a transient change in the charge in the semiconductor device. The analysis device may include a capacitance calculation unit that calculates any terminal capacitance based on the change in the charge amount analyzed by the charge amount analysis unit.

[0005] The charge amount analysis unit may change the power supply voltage from the initial voltage and analyze the change in the charge amount when the power supply voltage is changed by the displacement voltage for each changed power supply voltage. The capacitance calculation unit may calculate the terminal capacitance for each power supply voltage based on the change in the charge amount analyzed for each power supply voltage.

[0006] The semiconductor device may have a p-type or n-type contact region that contacts a first main terminal on a semiconductor substrate. The charge amount analysis unit may calculate the charge density in the contact region based on the displacement voltage.

[0007] The semiconductor device may have a drift region disposed below the contact region on the semiconductor substrate. The charge amount analysis unit may further calculate the charge density in at least a part of the drift region based on the displacement voltage.

[0008] The charge amount analysis unit may set the magnitude of the displacement voltage according to the magnitude of the power supply voltage.

[0009] The charge amount analysis unit may set the magnitude of the displacement voltage to a constant value regardless of the magnitude of the power supply voltage.

[0010] The capacitance calculation unit may calculate the terminal capacitance with respect to a voltage obtained by changing the power supply voltage by only the displacement voltage.

[0011] The charge amount analysis unit may analyze a first change in the charge amount when a first displacement voltage is added to a first power supply voltage and a second change in the charge amount when a second displacement voltage is subtracted from a second power supply voltage.

[0012] The voltage obtained by adding the first displacement voltage to the first power supply voltage and the voltage obtained by subtracting the second displacement voltage from the second power supply voltage may be equal.

[0013] The first power supply voltage and the second power supply voltage may be equal.

[0014] The device simulator may have a convergence determination function for determining whether or not the process of analyzing the change in the charge amount converges. The charge amount analysis unit may set the smallest displacement voltage within the range where it is determined that the process of analyzing the change in the charge amount converges.

[0015] In a second aspect of the present invention, there is provided an analysis method for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal. The analysis method includes a charge amount analysis step of setting the semiconductor device to an on state, setting the power supply voltage applied between the first main terminal and the second main terminal to an initial voltage, stabilizing the current flowing between the first main terminal and the second main terminal, and then analyzing, using a device simulator that simulates the transient change of charges in the semiconductor device, the change in the charge amount at any terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage. The analysis method may include a capacitance calculation step of calculating any terminal capacitance based on the change in the charge amount analyzed in the charge amount analysis step.

[0016] In a third aspect of the present invention, there is provided a program for causing a computer to execute the analysis method according to the second aspect.

[0017] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0018]

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Embodiments for Carrying Out the Invention

[0019] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0020] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0021] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0022] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be described as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor having an N-type conductivity type or a P-type conductivity type. In this specification, the SI unit system is used. When units other than the SI unit system are used, they may be converted to the SI unit system for calculation.

[0023] FIG. 1 is a diagram showing an example of an analysis device 10 according to an embodiment of the present invention. The analysis device 10 analyzes the characteristics of a semiconductor device. The semiconductor device has a control terminal, a first main terminal, and a second main terminal. The main current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal. The semiconductor device may have a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The control terminal is, for example, the gate terminal or the base terminal of the transistor element. The first main terminal and the second main terminal are terminals through which the main current flows. The first main terminal is, for example, the emitter terminal or the source terminal of the transistor element. The second main terminal is, for example, the collector terminal or the drain terminal of the transistor element. The analysis device 10 analyzes the terminal capacitance of any terminal of the semiconductor device. The terminal capacitance may be the parasitic capacitance of any terminal. The terminal capacitance may also be the parasitic capacitance between any two terminals.

[0024] The analysis device 10 may be a device realized by a computer. The computer may be provided with a program for causing the computer to function as the analysis device 10. The computer executes the analysis method by the analysis device 10 by executing the program.

[0025] The analysis device 10 includes an input unit 12, a charge amount analysis unit 14, a capacitance calculation unit 16, and an output unit 18. Data regarding the semiconductor device to be analyzed is input to the input unit 12. Such data may be input by a user or the like of the analysis device 10. Such data may include information such as the position, size, shape, impurity concentration, electrical resistance, capacitance, etc. of each part of the semiconductor device.

[0026] The charge amount analysis unit 14 analyzes the charge amount in a predetermined region within the semiconductor device under predetermined analysis conditions. The predetermined analysis conditions may include conditions specifying the control voltage applied to the control terminal and the power supply voltage applied between the first main terminal and the second main terminal. The charge amount analysis unit 14 analyzes the charge of the semiconductor device using a device simulator that can simulate the transient change in the charge amount within the semiconductor device. The transient change is, for example, the change in the charge amount over time within the semiconductor device. The device simulator analyzes, for example, the change in the charge amount over time within the semiconductor device when the power supply voltage is changed. The device simulator may analyze the charge density in a predetermined region within the semiconductor device using, for example, the Poisson equation, and calculate the charge amount in the region by integrating the charge density. The charge amount analysis unit 14 may analyze the charge amount within the semiconductor device using a known simulator.

[0027] The charge amount analysis unit 14 sets the semiconductor device to the on state by setting the control voltage to a predetermined value, and sets the power supply voltage applied between the first main terminal and the second main terminal to a predetermined initial voltage. Then, the charge amount analysis unit 14 analyzes, using the device simulator, the change in the charge amount at any terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage.

[0028] The capacitance calculation unit 16 calculates any terminal capacitance based on the change in the charge amount analyzed by the charge amount analysis unit 14. The capacitance calculation unit 16 may calculate the terminal capacitance based on the change in the charge amount with respect to the displacement voltage. Since the capacitance C is the value obtained by dividing the charge amount Q by the voltage V (C = Q / V), the terminal capacitance can be calculated by dividing the change amount of the charge by the displacement voltage.

[0029] The output unit 18 outputs information regarding the terminal capacitance calculated by the capacitance calculation unit 16. The output unit 18 may display the information regarding the terminal capacitance on a display device, may transmit it to an external device, or may store it in a storage medium.

[0030] FIG. 2 is a cross-sectional view showing an example of a semiconductor device 100 to be analyzed. The semiconductor device 100 in this example has an IGBT, but the structure of the semiconductor device 100 is not limited thereto. The semiconductor device 100 includes a semiconductor substrate 111, a first main terminal 101, a second main terminal 102, and an interlayer insulating film 110. The first main terminal 101 in this example is an emitter electrode, and the second main terminal 102 is a collector electrode. The first main terminal 101 and the second main terminal 102 are formed of a metal material such as aluminum.

[0031] The semiconductor substrate 111 is a substrate formed of a semiconductor material such as silicon, or a compound semiconductor material such as silicon carbide or gallium arsenide. The semiconductor substrate 111 may be in a wafer shape including a plurality of chips, or may be in a shape of individual chips. The semiconductor substrate 111 has an upper surface 113 and a lower surface 115. The semiconductor device 100 in this example is a vertical device in which the first main terminal 101 is provided on the upper surface 113 and the second main terminal 102 is provided on the lower surface 115, but the semiconductor device 100 may be a horizontal device in which the first main terminal 101 and the second main terminal 102 are provided on the same surface.

[0032] The semiconductor substrate 111 in this example has a gate structure portion 105, an emitter region 112, a base region 114, a drift region 116, a buffer region 118, and a collector region 120. The drift region 116 is an N-type region. The emitter region 112 is disposed between the drift region 116 and the upper surface 113. The emitter region 112 is an N+-type contact region that contacts the first main terminal 101. The base region 114 is a P-type contact region that contacts the first main terminal 101. At least a part of the base region 114 is disposed between the emitter region 112 and the drift region 116.

[0033] The collector region 120 is a P+-type region provided in contact with the bottom surface 115. The collector region 120 is electrically connected to the second main terminal 102. The buffer region 118 is an N+-type region provided between the collector region 120 and the drift region 116. The buffer region 118 functions as a field stop layer that prevents the depletion layer 117 spreading from the upper surface 113 side from reaching the collector region 120.

[0034] The gate structure portion 105 is provided at a position facing the base region 114 between the emitter region 112 and the drift region 116. The gate structure portion 105 in this example is of a trench type provided from the upper surface 113 of the semiconductor substrate 111, penetrating through the emitter region 112 and the base region 114 to reach the drift region 116. The gate structure portion 105 in other examples may be of a planar type provided above the upper surface 113 of the semiconductor substrate 111. The gate structure portion 105 is insulated from the first main terminal 101 by the interlayer insulating film 110.

[0035] The gate structure portion 105 has a gate insulating film 104 and a control terminal 103. The control terminal 103 in this example is a gate electrode. The control terminal 103 may be formed of a conductive material such as polysilicon. The control terminal 103 is provided so as to face at least the base region 114. The gate insulating film 104 may be a film formed by thermally oxidizing or thermally nitriding the semiconductor substrate 111. The gate insulating film 104 insulates the control terminal 103 from the semiconductor substrate 111. When a predetermined control voltage is applied to the control terminal 103, an N-type channel region is formed in the surface layer of the base region 114 in contact with the gate insulating film 104. Thereby, the emitter region 112 and the drift region 116 are connected by the channel region, and current flows. In this specification, the state in which a channel region is formed in the base region 114 may be referred to as an on state, and the state in which no channel region is formed may be referred to as an off state.

[0036] FIG. 3 is an example of a circuit 300 schematically showing the semiconductor device 100. The analysis device 10 may analyze the operation of the semiconductor device 100 using the circuit 300. A control voltage V is applied to the control terminal 103 from a power supply 135GE is applied. The first main terminal 101 is connected to a reference potential such as a ground potential. Between the first main terminal 101 and the second main terminal 102, a power supply voltage V CE is applied from the power supply 134. The charge amount analysis unit 14 may analyze the charge amount in the semiconductor device 100 by setting the control voltage V GE and the power supply voltage V CE .

[0037] Let the capacitance between the first main terminal 101 and the second main terminal 102 of the semiconductor device 100 be the inter-terminal capacitance C CE . Similarly, let the capacitance between the first main terminal 101 and the control terminal 103 be the inter-terminal capacitance C GE , and let the capacitance between the second main terminal 102 and the control terminal 103 be the inter-terminal capacitance C GC . The capacitance calculation unit 16 calculates any one of the inter-terminal capacitances C. The inter-terminal capacitance C GC of the semiconductor device may be different between the value in the on state and the value in the off state of the semiconductor device. When the semiconductor device is in the on state, it is difficult to accurately measure or calculate the inter-terminal capacitance C GC if the current density is large. In the following example, an example of accurately calculating the inter-terminal capacitance C GC even when the semiconductor device is in the on state will be described.

[0038] FIG. 4 is a diagram for explaining an operation example of the charge amount analysis unit 14. The charge amount analysis unit 14 sets the control voltage V GE so as to turn on the semiconductor device 100. That is, the charge amount analysis unit 14 sets a control voltage V GE higher than the threshold voltage of the semiconductor device 100. Further, the charge amount analysis unit 14 sets the power supply voltage V CE to a predetermined initial value. Then, after the current I CE between the collector electrode C and the emitter electrode E becomes constant, the charge amount change of the first main terminal 101 when the power supply voltage V CE is changed by the displacement voltage ΔV CE is calculated. The displacement voltage ΔV CE is sufficiently small with respect to the power supply voltage V CE . The displacement voltage ΔV CEmay be, for example, 10% or less of the power supply voltage V, may be 1% or less, or may be 0.1% or less. The current I between the collector electrode C and the emitter electrode E CE being constant means, for example, that the current I between the collector electrode C and the emitter electrode E CE is in a state where it does not substantially change over time at a constant current value, and the current flowing through the control terminal 103 may be substantially zero. Not substantially changing may, for example, refer to a variation width of 20% or less of the average value. Since the control voltage V CE does not change, the inter-terminal capacitance C GE does not change. Therefore, the displacement current due to the minute change ΔV GE of the power supply voltage V CE is only due to the inter-terminal capacitance C CE . The inter-terminal capacitance C GC may be calculated, for example, from the space charge density of the gate oxide film and the drift region, and the change amount ΔQ GC of the charge between the electrodes GC, and then divided by the change amount ΔV GC of the voltage between the electrodes CE (ΔQ CE / ΔV GC CE ) to obtain the value. ) may be calculated.

[0039] The charge amount analysis unit 14 may set the magnitude of the displacement voltage ΔV CE according to the change in the magnitude of the power supply voltage V CE . For example, the displacement voltage ΔV CE may be a voltage obtained by multiplying the power supply voltage V CE by a predetermined coefficient. In another example, the displacement voltage ΔV CE may be a constant voltage regardless of the change in the power supply voltage V CE .

[0040] The charge amount of the terminal may be the charge amount of the contact region in the semiconductor substrate 111 that contacts the terminal. For example, the charge amount of the second main terminal 102 includes the charge amount of the collector region 120 that contacts the second main terminal 102. Also, the charge amount of the first main terminal 101 includes the charge amounts of the emitter region 112 and the base region 114 that contact the first main terminal 101.

[0041] The charge amount analysis unit 14 may calculate the charge amount in the collector region 120 using the Poisson equation represented by the following formula. ∇ 2 ·φ = -q(p - n + N D -N A ) / ε However, ∇ is a differential operator, φ is the electrostatic potential, q is the elementary charge, p is the hole density, n is the electron density, N D is the donor concentration, N A is the acceptor concentration, and ε is the dielectric constant of the semiconductor substrate 111. The dielectric constant ε of the semiconductor substrate 111 is the value obtained by multiplying the dielectric constant ε0 of vacuum by the relative dielectric constant ε r of the semiconductor substrate 111. The term p - n + N D -N A corresponds to the charge density.

[0042] The dielectric constant ε may be given to the charge amount analysis unit 14 as an analysis condition. Also, the electrostatic potential φ at each position in the semiconductor region is determined by the power supply voltage V CE . The charge amount analysis unit 14 calculates, for each position, the charge density when the power supply voltage is V CE and the charge density when the power supply voltage is V CE +ΔV CE using the above Poisson equation. The donor concentration N D and the acceptor concentration N A at each position of the semiconductor substrate 111 may be preset as analysis conditions for the charge amount analysis unit 14. !

[0043] The charge amount analysis unit 14 calculates the sum of the charge densities in the collector region 120. The charge amount analysis unit 14 may integrate the charge density described above. By multiplying the integrated value of the charge density by the elementary charge, the charge amount can be calculated. The charge amount analysis unit 14 may calculate, by transient analysis (constructing a differential equation based on Kirchhoff's law and deriving a solution), the time change of the charge amount when the power supply voltage is changed as shown in FIG. 4. The charge amount analysis unit 14 may calculate the charge amount when the change in the charge amount converges as the charge amount when the power supply voltage is V CE +ΔV CE . The charge amount analysis unit 14 calculates the charge amount when the power supply voltage is V CEThe charge amount when and the power supply voltage is V CE +ΔV CE The difference ΔQ between the charge amount when may be calculated.

[0044] The charge amount analysis unit 14 may further calculate the charge density in at least a part of the drift region 116. The charge density in the drift region 116 can also be analyzed using the Poisson equation from the power supply voltage V CE and the displacement voltage ΔV CE For example, the charge amount analysis unit 14 may calculate the charge density in the drift region 116 within the range where the depletion layer 117 spreads when the power supply voltage V CE is applied. The charge amount analysis unit 14 may integrate the charge density in the said region of the drift region 116 to calculate the charge amount in the said region. The charge amount analysis unit 14 may include the charge amount in the said region in the charge amount of the second main terminal 102. Since the inter-terminal capacitance C GC can change depending on the spreading manner of the depletion layer 117, the inter-terminal capacitance C GC can be analyzed more accurately by considering the charge amount in the said region.

[0045] The capacitance calculation unit 16 calculates the inter-terminal capacitance C CE based on the difference ΔQ of the charge amount calculated by the charge amount analysis unit 14 and the displacement voltage ΔV GC . The capacitance calculation unit 16 may calculate the inter-terminal capacitance C GC by the following formula. C GC =ΔQ / ΔV CE

[0046] FIG. 5 is a diagram showing an example of the C-V characteristics calculated by the capacitance calculation unit 16. In this example, the charge amount analysis unit 14 changes the power supply voltage V CE from the initial voltage, and for each changed power supply voltage V CE [[ID=4I]]analyzes the change ΔQ of the charge amount when the power supply voltage V CE is changed by the displacement voltage ΔV CE . For example, the charge amount analysis unit 14 changes the power supply voltage V CE to 10V, 50V, 100V, 500V, ···, and for each power supply voltage V CEFor the displacement voltage ΔV CE calculate the change in charge amount ΔQ when only the displacement voltage ΔV is changed.

[0047] The capacitance calculation unit 16 calculates the capacitance C between terminals for each power supply voltage V CE based on the change in charge amount ΔQ analyzed for each power supply voltage V CE between terminals. As a result, a C-V characteristic as shown in FIG. 5 is obtained. The capacitance calculation unit 16 may use the calculated capacitance C between terminals GC as the capacitance value at the power supply voltage V. That is, the calculated capacitance C between terminals GC may be used as the capacitance value at the power supply voltage V CE before the change. In another example, the capacitance calculation unit 16 may use the calculated capacitance C between terminals GC as the capacitance value for the power supply voltage V CE +ΔV. That is, the calculated capacitance C between terminals GC may be used as the capacitance value for the power supply voltage V CE after changing the power supply voltage V by the displacement voltage ΔV CE +ΔV GC by the displacement voltage ΔV CE . That is, the calculated capacitance C between terminals CE may be used as the capacitance value for the power supply voltage V CE +ΔV CE after changing the power supply voltage V by the displacement voltage ΔV. The capacitance calculation unit 16 may use the calculated capacitance C between terminals GC as the capacitance value for the power supply voltage V CE +0.5×ΔV. That is, the calculated capacitance C between terminals CE may be used as the capacitance value for the average power supply voltage before and after the change. GC

[0048] FIG. 6 is a diagram showing another operation example of the charge amount analysis unit 14. In this example, the charge amount analysis unit 14 analyzes the first change in charge amount ΔQ1 when the first displacement voltage ΔV CE1 is added to the first power supply voltage V, and the second change in charge amount ΔQ2 when the second displacement voltage ΔV CE1 is subtracted from the second power supply voltage V. CE2 from the second power supply voltage V CE2 .

[0049] The first power supply voltage V CE1 and the second power supply voltage V CE2They may be the same voltage. That is, each voltage may be set so that the power supply voltage before the change is the same. The charge amount analysis unit 14 may calculate the change in charge amount ΔQ1 when the voltage is increased from the power supply voltage V CE and the change in charge amount ΔQ2 when the voltage is decreased from the same power supply voltage V CE . The first displacement voltage ΔV CE1 and the second displacement voltage ΔV CE2 may be the same or different. The charge amount analysis unit 14 may calculate the weighted average of ΔQ1 and ΔQ2 according to the ratio of the first displacement voltage ΔV CE1 and the second displacement voltage ΔV CE2 . In this case, the capacitance calculation unit 16 may use the terminal capacitance C GC calculated from the average value ΔQ of the change in charge amount as the capacitance with respect to the power supply voltage V CE . Even in this case, by changing each power supply voltage from the initial value, the C-V characteristics shown in FIG. 5 can be obtained.

[0050] In another example, the first power supply voltage V CE1 and the second power supply voltage V CE2 may be different voltages. For example, the voltage V CE1 obtained by adding the first displacement voltage ΔV CE1 to the first power supply voltage V CE1 +ΔV CE1 and the voltage V CE2 obtained by subtracting the second displacement voltage ΔV CE2 from the second power supply voltage V CE2 -ΔV CE2 may be set to be equal. That is, each voltage may be set so that the power supply voltage after the change is the same. The first displacement voltage ΔV CE1 and the second displacement voltage ΔV CE2 may be the same or different. The charge amount analysis unit 14 calculates the change in charge amount ΔQ1 when the first displacement voltage ΔV CE1 is added to the first power supply voltage V CE1 and the change in charge amount ΔQ2 when the second displacement voltage ΔV CE2 is subtracted from the second power supply voltage V CE2The change in the amount of charge ΔQ2 when subtracted may be calculated. The capacitance calculation unit 16 calculates the capacitance C between terminals from the average value of the changes in the amount of charge ΔQ1 and ΔQ2 GC as the capacitance with respect to the voltage V CE1 +ΔV CE1 (=V CE2 +ΔV CE2 ). Even in this case, by changing each power supply voltage from the initial value, the C-V characteristics shown in FIG. 5 can be obtained.

[0051] The device simulator of the charge amount analysis unit 14 may have a convergence determination function for determining whether or not the process of analyzing the change in the charge amount converges. The convergence determination function determines that the analysis process does not converge when the charge amount after changing the power supply voltage V CE by the displacement voltage ΔV CE cannot be calculated within the set calculation period or below the set amount of calculation processing. When the displacement voltage ΔV CE is made small, it becomes difficult for the analysis process to converge. On the other hand, the smaller the displacement voltage ΔV CE , the more accurately the C-V characteristics can be analyzed. The charge amount analysis unit 14 may be set so that the displacement voltage is as small as possible within the range where it is determined that the analysis process converges. The charge amount analysis unit 14 may set the smallest displacement voltage within the range where it is determined that the analysis process converges. The set displacement voltage may have a predetermined margin with respect to the smallest displacement voltage that satisfies the conditions. By setting the displacement voltage to be as small as possible, the C-V characteristics can be analyzed with higher accuracy.

[0052] FIG. 7 is a diagram showing an example of general C-V characteristics. The horizontal axis in FIG. 7 indicates V CE , and the vertical axis indicates C GC . The capacitance C GC may start to saturate when the power supply voltage V CE falls below a predetermined saturation voltage. When the power supply voltage V CE is lowered, the voltage at which the capacitance C GC becomes half of the maximum value C max may be used as the saturation voltage. In the example of FIG. 7, the saturation voltage is about 1V.

[0053] Capacity C GC is the maximum value C max The region where the voltage saturates near the saturation voltage corresponds to a region where the semiconductor device 100 is in an off state and the depletion layer does not expand. Since the analysis device 10 analyzes the CV characteristics of the semiconductor device 100 in an on state, the charge amount analysis unit 14 calculates the power supply voltage V CE A lower limit voltage of the fluctuation range of the voltage may be set. The lower limit voltage may be a saturation voltage.

[0054] The charge amount analysis unit 14 calculates the displacement voltage ΔV according to the saturation voltage. CE The charge amount analyzing section 14 may multiply the saturation voltage by a predetermined coefficient to determine the displacement voltage ΔV CE The coefficient may be, for example, 0.2 or less, 0.1 or less, or 0.01 or less. CE The displacement voltage ΔV is sufficiently small compared to the lower limit of the fluctuation range of CE The saturation voltage may be set in advance by a user or the like, or may be analyzed by the charge amount analysis unit 14 based on input information. The saturation voltage may be calculated by analyzing the CV characteristics of the semiconductor device 100 in the off state.

[0055] Fig. 8 is a diagram illustrating a measurement method according to a reference example. In this measurement method, a small signal voltage is applied to the semiconductor device 100, and the current flowing through the semiconductor device 100 is measured to calculate the impedance, thereby measuring the CV characteristics. Fig. 8 is an equivalent circuit showing only the capacitance component of the semiconductor device 100. In the reference example, an AC small signal voltage is applied to a capacitance C whose CV characteristics are to be measured, and the flowing current is measured.

[0056] 9 is a diagram showing an example of the measurement circuit 405 used in the reference example. In this example, the capacitance C GC This example shows how to measure capacitance C, but other capacitances C can also be measured in the same way. GC When measuring the capacitance C, the first main terminal 101 shown in FIG. 8 is connected to the ground potential via an AC guard that allows AC signals to pass. GE and capacity C CE Excluding the capacitance CGC The impedance can be measured.

[0057] In this example, a small signal source 401 and a power supply V are connected in parallel to the second main terminal 102. CC To the capacitor C GC a voltage of V = V CC + V ac is applied. Also, an ammeter 402 is connected to the control terminal 103. Based on the current I measured by the ammeter 402 and the applied voltage V, the capacitor C GC can be calculated as follows. C GC = I / jωV By changing the power supply voltage V CC and measuring the capacitor C GC the C-V characteristics can be obtained. Information regarding the saturation voltage described in FIG. 7 may be obtained from the measurement results of the reference example.

[0058] FIG. 10 is a diagram showing an example of C-V characteristics calculated based on the measurement circuit 405 shown in FIG. 9. In FIG. 10, generally reasonable C-V characteristics are obtained. However, as described above, the C-V characteristics are those when the semiconductor device 100 is in the off state. However, the C-V characteristics of the semiconductor device 100 can change between when the semiconductor device 100 is in the on state and when it is in the off state. The semiconductor device 100 is often used in the on state. Therefore, it is preferable to be able to analyze the C-V characteristics of the semiconductor device 100 in the on state.

[0059] FIG. 11 shows a circuit 420 showing the operation of the semiconductor device 100 in the on state in the reference example. In the circuit 420, the small signal source 401 is omitted. The circuit 420 analyzes the operation of the DC component.

[0060] As shown in FIG. 11, when the semiconductor device 100 is in the on state, the current I C flowing through the second main terminal 102 includes the main current I. Usually, the main current I is very large compared to the currents flowing through each capacitor when the power supply voltage V CE changes.

[0061] In such a case, when analyzing the terminal capacitance C using the equivalent circuit as shown in FIG. 9 GC the current I ac will include not only the current flowing through each capacitance but also the component of the main current I. As a result, the apparent current amount becomes very large, and the terminal capacitance C GC becomes a very large value.

[0062] FIG. 12 shows the analytical value of the terminal capacitance C GC when the semiconductor device 100 is in the on state and the analytical value of the terminal capacitance C GC when it is in the off state. As shown in FIG. 12, the analytical value of the terminal capacitance C GC in the on state is much larger than the analytical value of the terminal capacitance C GC in the off state. Thus, with the analysis method of the reference example, the capacitance when the semiconductor device 100 is in the on state cannot be accurately analyzed.

[0063] FIG. 13 is a diagram analyzing each current waveform from the charge amount calculated by the analysis method described in FIGS. 1 to 6. In FIG. 13, the period during which the power supply voltage changes from V CE to V CE +ΔV CE is defined as the voltage transition period. In FIG. 13, the change in the collector current ΔI c flowing through the second main terminal 102 shown in FIG. 3 and the change in the current ΔI GC flowing through the terminal capacitance C Cgc are shown. The change ΔI c is the difference in the current I c when the power supply voltage is changed. The change ΔI Cgc can be calculated from the integrated value of the charge in the collector region 120.

[0064] As shown in FIG. 13, when the power supply voltage is increased, the collector current I C increases with the increase in the main current. On the other hand, the current I GC flowing through the terminal capacitance C Cgcvaries during the voltage transition period but is approximately 0 outside the voltage transition period. As shown in FIG. 13, the charge amount calculated by the analysis method described in FIGS. 1 to 6 does not include the charge contributing to the collector current I C . Therefore, the C-V characteristics in the on state of the semiconductor device 100 can be accurately analyzed. The C-V characteristics in the on state shown in FIG. 5 have a small difference from the C-V characteristics in the off state shown in FIG. 12 and are generally reasonable values. Since the charge calculated by the analysis method does not include the charge contributing to the collector current I C , the terminal capacitance C C can be calculated without being affected by the collector current I GC .

[0065] FIG. 14 is a flowchart showing an example of an analysis method using the analysis apparatus 10 shown in FIGS. 1 to 6. The analysis method may appropriately perform each process described in FIGS. 1 to 6. The analysis method includes an input stage S1500, a charge amount analysis stage S1502, a capacitance calculation stage S1504, and an output stage S1506.

[0066] The process in the input stage S1500 is the same as the process of the input unit 12. The process in the charge amount analysis stage S1502 is the same as the process of the charge amount analysis unit 14. The process in the capacitance calculation stage S1504 is the same as the process of the capacitance calculation unit 16. The process in the output stage S1506 is the same as the process of the output unit 18.

[0067] FIG. 15 shows a configuration example of a computer 1200 in which multiple aspects of the present invention can be embodied in whole or in part. Programs installed in the computer 1200 can cause the computer 1200 to function as an operation associated with the apparatus according to an embodiment of the present invention or as one or more "parts" of the apparatus, or cause the operation or the one or more "parts" to be executed, and / or cause the computer 1200 to execute a process according to an embodiment of the present invention or a stage of the process. Such a program may be executed by the CPU 1212 to cause the computer 1200 to execute certain operations associated with some or all of the blocks in the flowcharts and block diagrams described herein. Also, the process according to an embodiment of the present invention or a stage of the process may be executed on the cloud.

[0068] The computer 1200 according to the present embodiment includes a CPU 1212, a RAM 1214, a graphic controller 1216, and a display device 1218, which are interconnected by a host controller 1210. The computer 1200 also includes input / output units such as a communication interface 1222, a hard disk drive 1224, a DVD-ROM drive 1226, and an IC card drive, which are connected to the host controller 1210 via an input / output controller 1220. The computer also includes legacy input / output units such as a ROM 1230 and a keyboard 1242, which are connected to the input / output controller 1220 via an input / output chip 1240.

[0069] The CPU 1212 operates according to programs stored in the ROM 1230 and the RAM 1214, thereby controlling each unit. The graphic controller 1216 acquires image data generated by the CPU 1212 in a frame buffer or the like provided in the RAM 1214 or in the graphic controller 1216 itself, and causes the image data to be displayed on the display device 1218.

[0070] The communication interface 1222 communicates with other electronic devices via a network. The hard disk drive 1224 stores programs and data used by the CPU 1212 in the computer 1200. The DVD-ROM drive 1226 reads a program or data from the DVD-ROM 1201 and provides the program or data to the hard disk drive 1224 via the RAM 1214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0071] The ROM 1230 stores internally a boot program etc. executed by the computer 1200 at activation and / or a program depending on the hardware of the computer 1200. The input / output chip 1240 may also connect various input / output units to the input / output controller 1220 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0072] The program is provided by a computer-readable storage medium such as the DVD-ROM 1201 or an IC card. The program is read from the computer-readable storage medium, installed in the hard disk drive 1224, the RAM 1214, or the ROM 1230 which is also an example of a computer-readable storage medium, and executed by the CPU 1212. The information processing described in these programs is read by the computer 1200, bringing about cooperation between the programs and the various types of hardware resources described above. The device or method may be configured by realizing the operation or processing of information according to the use of the computer 1200.

[0073] For example, when communication is executed between the computer 1200 and an external device, the CPU 1212 may execute a communication program loaded in the RAM 1214 and instruct the communication interface 1222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 1212, the communication interface 1222 reads transmission data stored in a transmission buffer area provided in a recording medium such as the RAM 1214, the hard disk drive 1224, the DVD-ROM 1201, or an IC card, transmits the read transmission data to the network, or writes the received data received from the network to a reception buffer area or the like provided on the recording medium.

[0074] Further, the CPU 1212 may cause all or a necessary part of a file or database stored in an external recording medium such as the hard disk drive 1224, the DVD-ROM drive 1226 (DVD-ROM 1201), or an IC card to be read into the RAM 1214 and perform various types of processing on the data on the RAM 1214. The CPU 1212 may then write back the processed data to the external recording medium.

[0075] Various types of information, such as various types of programs, data, tables, and databases, may be stored on a recording medium to be information - processed. The CPU 1212 may perform various types of processing on the data read from the RAM 1214, including various types of operations, information processing, conditional judgment, conditional branch, unconditional branch, search / replacement of information, etc., described throughout this disclosure and specified by the instruction sequence of the program, and write - back the results to the RAM 1214. Also, the CPU 1212 may search for information in files, databases, etc. within the recording medium. For example, when a plurality of entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored in the recording medium, the CPU 1212 searches for an entry that matches the condition where the attribute value of the first attribute is specified among the plurality of entries, reads the attribute value of the second attribute stored in the entry, and thereby may obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0076] The program or software module according to the above description may be stored on a computer - readable storage medium on or near the computer 1200. Also, a recording medium such as a hard disk or RAM provided within a server system connected to a dedicated communication network or the Internet can be used as a computer - readable storage medium, whereby the program is provided to the computer 1200 via the network.

[0077] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0078] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "earlier" or "preceding" etc. in particular, and it should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if explanations are made using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0079] 10... analysis device, 12... input section, 14... charge amount analysis section, 16... capacitance calculation section, 18... output section, 100... semiconductor device, 101... first main terminal, 102... second main terminal, 103... control terminal, 104... gate insulating film, 105... gate structure section, 110... interlayer insulating film, 111... semiconductor substrate, 112... emitter region, 113... upper surface, 114... base region, 115... lower surface, 116... drift region, 117... depletion layer, 118... buffer region, 120... collector region, 134... power supply, 135... power supply, 300... circuit, 401... small signal source, 402... ammeter, 405... measurement circuit, 420... circuit, 1200... computer, 1201... DVD-ROM, 1210... host controller, 1212... CPU, 1214... RAM, 1216... graphic controller, 1218... display device, 1220... input / output controller, 1222... communication interface, 1224... hard disk drive, 1226... DVD-ROM drive, 1230... ROM, 1240... input / output chip, 1242... keyboard

Claims

1. An analysis device for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, comprising: a charge amount analysis unit that analyzes a change in the charge amount at any one of the terminals when the power supply voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than the initial voltage after the current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage, by a device simulator that simulates a transient change in the charge in the semiconductor device; a capacitance calculation unit that calculates any one of the terminal capacitances based on the change in the charge amount analyzed by the charge amount analysis unit; and comprising: The charge amount analysis unit sets the voltage at the lower limit of the fluctuation range of the power supply voltage according to the saturation voltage at which the terminal capacitance saturates. Analysis device.

2. An analysis device for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, comprising: a charge amount analysis unit that analyzes a change in the charge amount at any one of the terminals when the power supply voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than the initial voltage after the current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage, by a device simulator that simulates a transient change in the charge in the semiconductor device; a capacitance calculation unit that calculates any one of the terminal capacitances based on the change in the charge amount analyzed by the charge amount analysis unit; and comprising: The charge amount analysis unit sets the displacement voltage of the power supply voltage according to the saturation voltage at which the terminal capacitance saturates. Analysis device.

3. The charge amount analysis unit calculates the saturation voltage by analyzing the C-V characteristics of the semiconductor device in the off state. The analysis device according to claim 1 or 2.

4. An analysis device for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, comprising: A charge quantity analysis unit that analyzes, by means of a device simulator that simulates a transient change in charge within the semiconductor device, a change in the charge quantity at any of the terminals when, with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to an initial voltage, the current flowing between the first main terminal and the second main terminal has been stabilized and then the power supply voltage is changed by a displacement voltage smaller than the initial voltage; A capacitance calculation unit that calculates any of the terminal capacitances based on the change in the charge quantity analyzed by the charge quantity analysis unit; Comprising; The semiconductor device has a p-type or n-type contact region that contacts the first main terminal or the second main terminal on the semiconductor substrate; The charge quantity analysis unit calculates the charge density in the contact region based on the displacement voltage; Analysis device.

5. The charge quantity analysis unit changes the power supply voltage from the initial voltage and analyzes, for each changed power supply voltage, the change in the charge quantity when the power supply voltage is changed by the displacement voltage; The capacitance calculation unit calculates the terminal capacitance for each power supply voltage based on the change in the charge quantity analyzed for each power supply voltage; The analysis device according to any one of claims 1 to 4.

6. The semiconductor device has a drift region disposed below the contact region on the semiconductor substrate; The charge quantity analysis unit further calculates the charge density in at least a part of the drift region based on the displacement voltage; The analysis device according to claim 4.

7. The charge quantity analysis unit sets the magnitude of the displacement voltage according to the magnitude of the power supply voltage; The analysis device according to any one of claims 3 to 6.

8. The charge quantity analysis unit sets the magnitude of the displacement voltage to a constant value regardless of the magnitude of the power supply voltage; The analysis device according to any one of claims 3 to 6.

9. The capacitance calculation unit calculates the terminal capacitance for a voltage obtained by changing the power supply voltage by only the displacement voltage; The analysis device according to any one of claims 1 to 8.

10. The charge quantity analysis unit analyzes a first change in the charge quantity when a first displacement voltage is added to a first power supply voltage and a second change in the charge quantity when a second displacement voltage is subtracted from a second power supply voltage; The analysis device according to any one of claims 1 to 9.

11. The voltage obtained by adding the first displacement voltage to the first power supply voltage is equal to the voltage obtained by subtracting the second displacement voltage from the second power supply voltage The analysis device according to claim 10

12. The first power supply voltage is equal to the second power supply voltage The analysis device according to claim 10

13. An analysis device for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, A charge amount analysis unit that analyzes, using a device simulator that simulates a transient change in charge within the semiconductor device, the change in the charge amount at any terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage after stabilizing the current flowing between the first main terminal and the second main terminal with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage; A capacitance calculation unit that calculates any one of the terminal capacitances based on the change in the charge amount analyzed by the charge amount analysis unit Comprising The device simulator has a convergence determination function for determining whether or not the process of analyzing the change in the charge amount converges The charge amount analysis unit sets the smallest displacement voltage within the range where it is determined that the process of analyzing the change in the charge amount converges Analysis device

14. An analysis method for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, A charge amount analysis stage that analyzes, using a device simulator that simulates a transient change in charge within the semiconductor device, the change in the charge amount at any terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage after stabilizing the current flowing between the first main terminal and the second main terminal with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage; A capacitance calculation stage that calculates any one of the terminal capacitances based on the change in the charge amount analyzed in the charge amount analysis stage Comprising In the charge amount analysis stage, the voltage at the lower limit of the fluctuation range of the power supply voltage is set according to the saturation voltage at which the terminal capacitance saturates Analysis method

15. An analysis method for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, a charge amount analysis step of analyzing, by a device simulator that simulates a transient change in charge in the semiconductor device, a change in the charge amount at any terminal when the power supply voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than the initial voltage after the current flowing between the first main terminal and the second main terminal has been stabilized with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage; a capacitance calculation step of calculating any one of the terminal capacitances based on the change in the charge amount analyzed in the charge amount analysis step; comprising; in the charge amount analysis step, setting the displacement voltage of the power supply voltage according to a saturation voltage at which the terminal capacitance saturates; analysis method.

16. An analysis method for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, a charge amount analysis step of analyzing, by a device simulator that simulates a transient change in charge in the semiconductor device, a change in the charge amount at any terminal when the power supply voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than the initial voltage after the current flowing between the first main terminal and the second main terminal has been stabilized with the semiconductor device set to the on state and the power supply voltage applied between the first main terminal and the second main terminal set to the initial voltage; a capacitance calculation step of calculating any one of the terminal capacitances based on the change in the charge amount analyzed in the charge amount analysis step; comprising; the semiconductor device has a p-type or n-type contact region in the semiconductor substrate that contacts the first main terminal or the second main terminal; in the charge amount analysis step, calculating a charge density in the contact region based on the displacement voltage; analysis method.

17. An analysis method for analyzing the terminal capacitance of a semiconductor device having a control terminal, a first main terminal, and a second main terminal, wherein the current flowing between the first main terminal and the second main terminal is controlled by a voltage applied to the control terminal, A charge quantity analysis step of analyzing, by a device simulator that simulates a transient change in charges in the semiconductor device, a change in the charge quantity at any one of the terminals when the power supply voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than the initial voltage after stabilizing the current flowing between the first main terminal and the second main terminal with the semiconductor device set to an on state and the power supply voltage applied between the first main terminal and the second main terminal set to an initial voltage; A capacitance calculation step of calculating any one of the terminal capacitances based on the change in the charge quantity analyzed in the charge quantity analysis step; Comprising; The device simulator has a convergence determination function for determining whether or not the process of analyzing the change in the charge quantity converges; In the charge quantity analysis step, the smallest displacement voltage is set within a range in which it is determined that the process of analyzing the change in the charge quantity converges; Analysis method.

18. A program for causing a computer to execute the analysis method according to any one of claims 14 to 17.

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