Semiconductor device and power conversion device

Abstract

To provide a semiconductor device which can be downsized, and a power conversion device.SOLUTION: A plurality of main terminals 3 is drawn from a second side face 1b of a sealing resin 1. The plurality of main terminals 3 comprises: bonding units 9HU, 9HV and 9HW which are wired with one of a plurality of semiconductor chips 5HU, 5HV and 5HW inside of the sealing resin 1; heat transfer units 6HU, 6HV and 6HW adjacent to the bonding units 9HU, 9HV and 9HW; and mounting units 8HU, 8HV and 8HW in which one of the plurality of semiconductor chips 5LU, 5LV and 5LW is mounted. A recess 10 is provided on the second side face 1b between adjacent main terminals 3. Side faces of the heat transfer units 6HU, 6HV and 6HW are opposed to the recess 10, and side faces of the bonding units 9HU, 9HV and 9HW are not opposed to the recess 10.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] The sealing resin of the semiconductor device has a first side surface and a second side surface facing each other. A plurality of control terminals, such as signal terminals to which a small voltage is applied, are drawn out from the first side surface, and a plurality of main terminals, such as output terminals to which a high voltage is applied, are drawn out from the second side surface (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-114640 Summary of the Invention [Problem to be solved by the invention]

[0004] By providing a recess on the second side surface of the sealing resin between adjacent main terminals, it is possible to ensure a creepage distance between adjacent main terminals. However, the bonding portion of the main terminal that is wire-bonded to the semiconductor chip is located inside the sealing resin so as to face the second side surface between the adjacent main terminals. Because the bonding portion for wire bonding cannot be made small, it was not possible to secure space for providing a recess in the area between the terminals.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a semiconductor device and a power conversion device that can be miniaturized. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a plurality of semiconductor chips, a plurality of control terminals connected to the plurality of semiconductor chips, a plurality of main terminals connected to the plurality of semiconductor chips and having a width thicker than that of the control terminals, and a plurality of semiconductor chips, a part of the plurality of control terminals, and a part of the plurality of main terminals. The encapsulating resin that encapsulates the plurality of main terminals, the encapsulating resin is rectangular in plan view and has a first side surface and a second side surface facing each other, the plurality of control terminals are drawn out from the first side surface of the encapsulating resin, and the plurality of main terminals are drawn out from the second side surface of the encapsulating resin. Each of the plurality of main terminals has, inside the encapsulating resin, a bonding portion wire-connected to one of the plurality of semiconductor chips, a heat transfer portion adjacent to the bonding portion, and a mounting portion on which another one of the plurality of semiconductor chips is mounted. The heat transfer part is provided between the mounting part and the bonding part. A recess is provided on the second side surface between the adjacent main terminals, the side surface of the heat transfer portion faces the recess, and the side surface of the bonding portion does not face the recess.

Advantages of the Invention

[0007] In the present disclosure, the heat transfer portion is arranged in a region facing the second side surface between adjacent main terminals, and the bonding portion is not arranged. Since the width of the heat transfer portion that is not wire-bonded can be made narrow, a space for providing a recess between adjacent main terminals can be secured. Even if the distance between adjacent main terminals is narrowed by the depth of the recess on the second surface, the creepage distance can be ensured. Therefore, the product can be miniaturized with a narrow pitch.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0009] The semiconductor device and the power conversion device according to the embodiments will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repeated descriptions may be omitted.

[0010] Embodiment 1. FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1. This semiconductor device is a three-phase inverter. The encapsulating resin 1 is rectangular in plan view and has a first side surface 1a and a second side surface 1b facing each other. A plurality of control terminals 2 are drawn out from the first side surface 1a of the encapsulating resin 1. A plurality of main terminals 3 are drawn out from the second side surface 1b of the encapsulating resin 1. The main terminal 3 has a wider width than the control terminal 2. Specifically, at the root portion protruding from the encapsulating resin 1, it is desirable that the width of the control terminal 2 is 0.65 ± 0.2 mm and the width of the main terminal 3 is 2 ± 0.2 mm.

[0011] The plurality of control terminals 2 include a plurality of high-side control terminals 2 H and a plurality of low-side control terminals 2 L . A higher potential is applied to the high-side control terminal 2 H than to the low-side control terminal 2 L . The plurality of main terminals 3 include P main terminals 3 P , three high-side main terminals 3 HU , 3 HV , 3 HW , and three low-side main terminals 3 LU , 3 LV , 3 LW . A higher potential is applied to the high-side main terminal 3 HU , 3 HV , 3 HW than to the low-side main terminal 3 LU , 3 LV , 3 LWA higher potential is applied to P main terminal 3. P , high side main terminal 3 HU ,3 HV ,3 HW , low side main terminal 3 LU ,3 LV ,3 LW are arranged in order on the second side surface 1b.

[0012] High side main terminal 3 HU ,3 HV ,3 HW correspond to the U, V, and W phases of the three-phase inverter. LU ,3 LV ,3 LW correspond to the U phase, V phase, and W phase, respectively. The order of the terminals for these three phases can be any order, for example, UVW phase, UWV phase, or WVU phase. HU ,3 HV ,3 HW and low side main terminal 3 LU ,3 LV ,3 LW It is desirable to arrange them in the same order, but they do not necessarily have to be arranged in the same order.

[0013] 2 is a plan view showing the inside of the semiconductor device according to the first embodiment. H Multiple high-side control terminals 2 H The semiconductor chip 5 is connected by wire. HU ,5 HV ,5 HW The gate electrodes of the control chip 4 H Wired to Control Chip 4 H is high side control terminal 2 H In response to the signal input from the semiconductor chip 5 HU ,5 HV ,5 HW Control chip 4 L Multiple low-side control terminals 2 L The semiconductor chip 5 is connected by wire. LU ,5 LV ,5LW The gate electrodes are respectively connected to the control chip 4 L . The control chip 4 L is configured to control the semiconductor chips 5 L in response to the signals input from the low-side control terminal 2 LU , 5 LV , 5 LW . Note that the control chips 4 H , 4 L can also be configured as one control chip. The control chips 4 H , 4 L may be joined to the mounting portion of a lead frame formed integrally with a plurality of control terminals 2

[0014] The encapsulating resin 1 encapsulates the control chips 4 H , 4 L , the semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW , a part of the plurality of control terminals 2, and a part of the plurality of main terminals 3. The P main terminal 3 P has, inside the encapsulating resin 1, a heat transfer portion 6 P and a mounting portion 8 P connected to the heat transfer portion 6 P through a connection portion 7 P .

[0015] The high-side main terminal 3 HU has, inside the encapsulating resin 1, a bonding portion 9 HU , a heat transfer portion 6 HU adjacent to the bonding portion 9 HU , and a mounting portion 8 HU connected to the heat transfer portion 6 HU through a connection portion 7 HU . The portion of the high-side main terminal 3 HU drawn out to the outside of the encapsulating resin 1, the bonding portion 9 HU , the heat transfer portion 6 HU , the connection portion 7 HU , and the mounting portion 8 HUIt is composed of wirings called an integrated lead frame. These form a path for passing the main current. The lead frame is made of, for example, copper material.

[0016] Similarly, the high-side main terminal 3 HV inside the encapsulating resin 1 has a bonding part 9 HV , a heat transfer part 6 HV adjacent to the bonding part 9 HV , and a mounting part 8 HV connected to the heat transfer part 6 HV via a connection part 7. The high-side main terminal 3 HV inside the encapsulating resin 1 has a bonding part 9 HW , a heat transfer part 6 HW adjacent to the bonding part 9 HW , and a mounting part 8 HW connected to the heat transfer part 6 HW via a connection part 7. HW HW

[0017] The lower electrodes of the semiconductor chips 5 HU , 5 HV , 5 HW are joined to the mounting part 8 P of the P main terminal 3 P by solder or the like. The lower electrodes of the semiconductor chips 5 LU , 5 LV , 5 LW are respectively joined to the mounting parts 8 HU , 8 HV , 8 HW of the high-side main terminals 3 HU , 3 HV , 3 HW by solder or the like. The upper electrodes of the semiconductor chips 5 HU , 5 HV , 5 HW are respectively wire-connected to the bonding parts 9 HU , 9 HV , 9 HW of the high-side main terminals 3 HU , 3 HV , 3 HW . The semiconductor chips 5 LU , 5 LV , 5LW The upper electrodes are each wire-connected to the low-side main terminals 3 LU , 3 LV , 3 LW .

[0018] At least four recesses 10 are provided in the second side surface 1b of the encapsulating resin 1 between adjacent main terminals 3. Specifically, one recess 10 is provided between an adjacent P main terminal 3 P and a high-side main terminal 3 HU , two recesses 10 are provided between adjacent high-side main terminals 3 HU , 3 HV , 3 HW , and one recess 10 is provided between an adjacent high-side main terminal 3 HW and a low-side main terminal 3 LU . Note that since the creepage distance required between low-side main terminals 3 LU , 3 LV , 3 LW to which no high voltage is applied is small, no recess 10 is provided between low-side main terminals 3 LU , 3 LV , 3 LW .

[0019] The side surfaces of the heat transfer portions 6 P , 6 HU , 6 HV , 6 HW face the bottom surfaces of the recesses 10. That is, the heat transfer portions 6 P , 6 HU , 6 HV , 6 HW are adjacent to the recesses 10 of the encapsulating resin 1. The heat generated by the semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW is transferred to the heat transfer portions 6 P , 8 HU , 8 HV , 8 HW and the connection portions 7 P , 7 HU , 7 HV , 7 HW via the mounting portions 8 P , 6 HU , 6HV ,6 HW is transmitted to. Since the heat transfer area is increased by the concave portion 10, the heat transfer part 6 P ,6 HU ,6 HV ,6 HW the heat transmitted to can be released from the concave portion 10 to the outside by air cooling. Therefore, the heat dissipation performance is improved. Note that the connection part 7 HU ,7 HV ,7 HW does not face the concave portion 10 on its side surface.

[0020] The bonding part 9 HU ,9 HV ,9 HW is respectively arranged on an extension line where the high-side main terminal 3 HU ,3 HV ,3 HW extends from the outside to the inside of the sealing resin 1. The side surface of the bonding part 9 HU ,9 HV ,9 HW does not face the concave portion 10. The bonding part 9 HU and the heat transfer part 6 HU are connected in an L shape and are basically integrated. In the direction perpendicular to the second side surface 1b, the width of the bonding part 9 HU is wider than the width of the heat transfer part 6 HU . Thus, even when the wire from the semiconductor chip 5 HU is connected to the bonding part 9 HU substantially vertically, wire bonding can be sufficiently performed. The bonding part 9 HV ,9 HW and the heat transfer part 6 HV ,6 HW are the same.

[0021] Subsequently, the effects of the present embodiment will be described in comparison with a comparative example. FIG. 3 is a plan view showing the inside of a semiconductor device according to the comparative example. In the comparative example, the bonding part 9 HU ,9 HV ,9 HW is provided so as to face the second side surface 1b between adjacent main terminals 3. The bonding part 9 HU ,9 HV,9 HW Since it cannot be made smaller, it is impossible to secure a space for providing the recess 10 in the region between the adjacent main terminals 3. Therefore, the creepage distance between the adjacent main terminals 3 cannot be secured, and it is necessary to widen the interval between the adjacent main terminals 3, resulting in an increase in the size of the device.

[0022] In contrast, in the present embodiment, a bonding portion 9 is not disposed in the region facing the second side surface 1b between the adjacent main terminals 3 HU ,9 HV ,9 HW but a heat transfer portion 6 P ,6 HU ,6 HV ,6 HW is disposed. Since the width of the heat transfer portion 6 P ,6 HU ,6 HV ,6 HW where wire bonding is not performed can be made narrow, a space for providing the recess 10 in the region between the adjacent main terminals 3 can be secured. Even if the interval between the adjacent main terminals 3 is narrowed by the depth of the recess 10 on the second side surface 1b, the creepage distance can be secured. Therefore, the product can be miniaturized with a narrow pitch. Also, by narrowing the width of the heat transfer portion 6 P ,6 HU ,6 HV ,6 HW not only the long side but also the short side of the encapsulating resin 1 can be miniaturized.

[0023] In FIG. 1, the interval D1 between the adjacent P main terminal 3 P and the high-side main terminal 3 HU is 4 ± 0.2 mm. The interval D2 between the adjacent high-side main terminals 3 HU ,3 HV ,3 HW is 6.1 ± 0.2 mm. The interval D3 between the adjacent high-side main terminal 3 HW and the low-side main terminal 3 LU is 6.1 ± 0.2 mm. The interval D4 between the adjacent low-side main terminals 3 LU ,3 LV ,3 LW is 3.5 ± 0.2 mm. The P main terminal 3 Pand high-side main terminal 3 HU , 3 HV , 3 HW Since a high potential difference is generated between adjacent terminals, the intervals D1, D2, D3 on the high-side are made wider than the interval D4 on the low-side. Here, the interval between adjacent terminals refers to the interval between the center lines of the adjacent terminals in a plan view.

[0024] As shown in FIG. 1, on the second side surface 1b, the P main terminal 3 P , the high-side main terminal 3 HU , 3 HV , 3 HW , the low-side main terminal 3 LU , 3 LV , 3 LW are arranged in this order. Not limited to this, on the second side surface 1b, the P main terminal 3 P , the low-side main terminal 3 LU , 3 LV , 3 LW , the high-side main terminal 3 HU , 3 HV , 3 HW may be arranged in this order. In this case, one recess 10 is provided between the adjacent P main terminal 3 P and the low-side main terminal 3 LU , two are provided between the adjacent high-side main terminals 3 HU , 3 HV , 3 HW to each other, and one is provided between the adjacent low-side main terminal 3 LW and the high-side main terminal 3 HU . However, since the low-potential low-side main terminal 3 P is arranged next to the high-potential P main terminal 3 LU , 3 LV , 3 LW , insulation becomes slightly more difficult than when the main terminals are arranged in the order of FIG. 1.

[0025] When the operating voltage of the semiconductor device is 560 to 630 V, it is necessary to ensure a creepage distance of 4 mm or more between the adjacent high-side main terminals HU , 3 HV , 3 HW to each other. Therefore, a recess 10 with a depth of 0.5 mm or more is provided in the high-side main terminal 3 HU,3 HV ,3 HW By providing it in between, the distance between adjacent high-side main terminals 3 HU ,3 HV ,3 HW can be made less than 4 mm. As a result, the miniaturization of the semiconductor device can be sufficiently achieved.

[0026] The higher the voltage applied to the terminals, the wider the distance between the terminals and the larger the terminal width need to be. When the applied voltage is the same, the wider the terminal width, the wider the distance. Specifically, for adjacent low-side control terminals 2 L the distance D5 between them is LU ,3 LV ,3 L narrower than the distance D4 between adjacent low-side main terminals 3 H The distance D6 between adjacent high-side control terminals 2 P is HU narrower than the distance D1 between the adjacent P main terminal 3 HU ,3 HV ,3 HW and the high-side main terminal 3 LU ,3 LV ,3 L and wider than the distance D4 between adjacent low-side main terminals 3

[0027] The distance between adjacent P main terminals 3 P and the high-side main terminal 3 HU is greater than or equal to the distances between other adjacent main terminals 3 and the distances between adjacent control terminals 2. By making the distance between adjacent P main terminals 3 P and the high-side main terminal 3 HU the widest, the insulation distance can be ensured even if the P main terminal 3 P is made thicker. That is, since the P main terminal 3 P can be made thicker, the design freedom is increased.

[0028] Figure 4 is an enlarged view of the P terminal. The P main terminal 3 PThere may be a case where 1.4 times the current flows compared to the other main terminals 3. Therefore, for the P main terminal 3 P the width of the P main terminal 3 P is made wider than the width of the main terminals 3 other than the P main terminal 3 and the width of the control terminal 2. It is desirable that the width of the P main terminal 3 P is 1.3 times or more the width w of the other main terminals 3. Since there is no heat transfer through the wire for the P main terminal 3 P this width has a sufficient temperature reduction effect. Specifically, at the root portion protruding from the encapsulating resin 1, the width of the P main terminal 3 P is 2.6 ± 0.2 mm, the width of the main terminals 3 other than the P main terminal 3 is 2 ± 0.2 mm, and the width of the control terminal 2 is 0.65 ± 0.2 mm. Thereby, the self-heating of the P main terminal 3 through which the most energizing current flows P is suppressed, and further reduction of the terminal temperature rise becomes possible. P

[0029] Embodiment 2. FIG. 5 is a plan view showing the inside of a semiconductor device according to Embodiment 2. In Embodiment 1, the recess 10 was provided in the second side surface 1b between adjacent main terminals 3, but in this embodiment, a convex portion 11 is provided instead of the recess 10. Even if the interval between adjacent main terminals 3 corresponding to the height of the convex portion 11 is narrowed on the second side surface 1b, the creepage distance can be ensured. Therefore, the product can be miniaturized with a narrow pitch.

[0030] The wide bonding portion 9 HU ,9 HV ,9 HW can be arranged between adjacent main terminals 3 without any problem in forming the convex portion 11. Therefore, the heat transfer portion 6 HU ,6 HV ,6 HW can be omitted, and the bonding portion 9 HU ,9 HV ,9 HW can be made adjacent to the convex portion 11. The heat generated in the semiconductor chip 5 LU ,5 LV ,5 LW by energization is transferred to the mounting portion 8 HU ,8 HV ,8 HW and the connection portion 7 HU ,7​HV ,7 HW Bonding part 9 via HU ,9 HV ,9 HW is transmitted. Since the heat transfer area is increased by the convex part 11, the heat transmitted to the bonding part 9 HU ,9 HV ,9 HW can be released to the outside from the convex part 11 by air cooling. Note that, like in Embodiment 1, the heat transfer part 6 HU ,6 HV ,6 HW is provided, and the heat transfer part 6 HU ,6 HV ,6 HW may be adjacent to the convex part 11.

[0031] When the operating voltage of the semiconductor device is 560 to 630 V, the creepage distance between adjacent high-side main terminals 3 HU ,3 HV ,3 HW needs to be ensured to be 4 mm or more. Therefore, by providing the convex part 11 with a protrusion height of 0.5 mm or more between the high-side main terminals 3 HU ,3 HV ,3 HW , the distance between adjacent high-side main terminals 3 HU ,3 HV ,3 HW can be made less than 4 mm. As a result, the semiconductor device can be sufficiently miniaturized. Other configurations and effects are the same as those in Embodiment 1.

[0032] Note that, in Embodiment 1 or 2, a concave or convex part may be provided on the first side surface 1a between adjacent control terminals 2. Also, although the semiconductor chip 5 HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LW is mounted on the lead frame, the semiconductor chip 5 HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LWThe insulating substrate has a structure in which metal plates are attached to both sides of an insulating layer. HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LW The wiring is extended from the heat transfer part in the same way as the lead frame, and the wiring is joined to the metal plate by soldering or ultrasonic vibration.

[0033] Semiconductor chip 5 HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LW is an RC-IGBT in which an IGBT and a diode are integrated on a single chip. This allows the semiconductor device to be made smaller than when the IGBT and the diode are mounted separately. The IGBT and the diode may also be mounted separately. In this case, the P main terminal 3 P Implementation part 8 P Three IGBTs and three diodes are mounted on the high-side main terminal 3 HU ,3 HV ,3 HW Implementation part 8 HU ,8 HV ,8 HW One IGBT and one diode are mounted on the

[0034] In addition, semiconductor chip 5 HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LWThe semiconductor chip is not limited to those formed from silicon, but may be formed from a wide bandgap semiconductor having a wider bandgap than silicon. Wide bandgap semiconductors include, for example, silicon carbide, gallium nitride-based materials, or diamond. Semiconductor chips formed from such wide bandgap semiconductors have high voltage resistance and allowable current density, allowing for miniaturization. By using this miniaturized semiconductor chip, semiconductor devices incorporating this semiconductor chip can also be miniaturized and highly integrated. Furthermore, since the semiconductor chip has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized, and the water-cooled part can be replaced with air-cooled, thereby further miniaturizing the semiconductor device. Furthermore, since the semiconductor chip has low power loss and high efficiency, the efficiency of the semiconductor device can be increased.

[0035] Embodiment 3 In this embodiment, the semiconductor device according to the first or second embodiment is applied to a power conversion device. The power conversion device is, for example, an inverter device, a converter device, a servo amplifier, a power supply unit, etc. Although the present disclosure is not limited to a specific power conversion device, the following describes a case where the present disclosure is applied to a three-phase inverter.

[0036] 6 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a third embodiment is applied. This power conversion system includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from various sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. Furthermore, the power supply 100 may be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0037] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, which converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. The power conversion device 200 includes a main conversion circuit 201 that converts and outputs DC power into AC power, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0038] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application, but is a motor mounted on various electrical devices, and is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

[0039] Hereinafter, the power conversion device 200 will be described in detail. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown), and by switching the switching elements, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit, and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements. Each switching element and each freewheeling diode of the main conversion circuit 201 are constituted by a semiconductor device 202 corresponding to any one of the above-described Embodiments 1 to 4. The six switching elements are connected in series in pairs of two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0040] Further, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built into the semiconductor device 202, or may be configured to include a drive circuit separate from the semiconductor device 202. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element. When maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0041] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired amount of power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control in which the on time of the switching element is modulated according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit included in the main conversion circuit 201 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state at each point in time. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with this control signal.

[0042] In the power conversion device according to the present embodiment, since the semiconductor device 202 according to Embodiment 1 or 2 is applied, the power conversion device can be miniaturized.

[0043] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described. However, the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure may be applied to a single-phase inverter. Further, when supplying power to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0044] Moreover, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is a motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power feeding system. Furthermore, it can also be used as a power conditioner for a solar power generation system or a power storage system.

Description of Reference Numerals

[0045] 1 Sealing resin, 1a First side surface, 1b Second side surface, 2 Control terminal, 2 H High-side control terminal, 2 L Low-side control terminal, 3 Main terminal, 3 HU ,3 HV ,3 HW High-side main terminal, 3 LU ,3 LV ,3 LW Low-side main terminal, 3 P P main terminal, 4 H ,4 L Control chip, 5 HU ,5 HV ,5 HW ,5 LU ,5 LV ,5 LW Semiconductor chip, 6 P ,6 HU ,6 HV ,6 HW Heat transfer part, 7 P ,7 HU ,7 HV ,7 HW Connection part, 8 P ,8 HU ,8HV , 8 HW Implementation part, 9 HU , 9 HV , 9 HW Bonding part, 10 recessed part, 11 protruding part, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit

Claims

1. A plurality of semiconductor chips, a plurality of control terminals connected to the plurality of semiconductor chips, a plurality of main terminals connected to the plurality of semiconductor chips and having a width thicker than that of the control terminals, a sealing resin that seals the plurality of semiconductor chips, a part of the plurality of control terminals, and a part of the plurality of main terminals, the sealing resin is rectangular in plan view and has a first side surface and a second side surface facing each other, the plurality of control terminals are drawn out from the first side surface of the sealing resin, the plurality of main terminals are drawn out from the second side surface of the sealing resin, each of the plurality of main terminals has a bonding portion wire-connected to one of the plurality of semiconductor chips inside the sealing resin, a heat transfer portion adjacent to the bonding portion, and a mounting portion on which another one of the plurality of semiconductor chips is mounted, the heat transfer portion is provided between the mounting portion and the bonding portion, a recess is provided on the second side surface between adjacent main terminals, a semiconductor device, wherein a side surface of the heat transfer portion faces the recess, and a side surface of the bonding portion does not face the recess.

2. The semiconductor device according to claim 1, wherein wire bonding is not performed on the heat transfer portion.

3. The semiconductor device according to claim 1 or 2, wherein in a direction perpendicular to the second side surface, the width of the bonding portion is wider than the width of the heat transfer portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the bonding portion is arranged on an extension line where the main terminal extends from the outside to the inside of the sealing resin.

5. the plurality of main terminals include a P main terminal, a plurality of high-side main terminals, and a plurality of low-side main terminals, the distance between adjacent P main terminals and high-side main terminals and the distance between adjacent high-side main terminals are wider than the distance between adjacent low-side main terminals, The semiconductor device according to any one of claims 1 to 4, wherein the recess is provided between adjacent P main terminals and high-side main terminals and between adjacent high-side main terminals.

6. the operating voltage of the semiconductor device is 560 to 630 V, the depth of the recess is 0.5 mm or more, The semiconductor device according to claim 5, wherein the distance between adjacent high-side main terminals is less than 4 mm.

7. The plurality of control terminals include a plurality of high-side control terminals and a plurality of low-side control terminals, the distance between adjacent low-side control terminals is narrower than the distance between adjacent low-side main terminals, the semiconductor device according to claim 5 or 6, wherein the distance between adjacent high-side control terminals is narrower than the distance between an adjacent P main terminal and the high-side main terminal and the distance between adjacent high-side main terminals, and wider than the distance between adjacent low-side main terminals.

8. the distance between an adjacent P main terminal and the high-side main terminal is equal to or greater than the distance between other adjacent main terminals and the distance between adjacent control terminals, the semiconductor device according to claim 5 or 6, wherein the width of the P main terminal is thicker than the width of the main terminals other than the P main terminal and the width of the control terminals.

9. the semiconductor device according to claim 8, wherein the width of the P main terminal is 1.3 times or more the width of the other main terminals.

10. In the second side surface, the semiconductor device according to any one of claims 5, 6, 8, and 9, wherein the P main terminal, the plurality of high-side main terminals, and the plurality of low-side main terminals are arranged in this order.

11. the semiconductor device according to any one of claims 1 to 10, wherein the semiconductor chip is an RC-IGBT in which an IGBT and a diode are integrated on one chip.

12. the semiconductor device according to any one of claims 1 to 11, wherein the semiconductor chip is formed of a wide bandgap semiconductor.

13. A power conversion device, comprising: a main conversion circuit that has the semiconductor device according to any one of claims 1 to 12 and converts and outputs input power; and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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