Quantum circuit design program, quantum circuit design method, and quantum circuit design device

Abstract

The present invention enhances the accuracy of quantum calculations.　A quantum circuit design device (10) detects, from a quantum circuit (1) indicating gate operations with respect to a plurality of qubits (8a, 8b...) included in a quantum device, a first quantum gate at which the gate operations cannot be executed by the quantum device. Next, the quantum circuit design device (10) determines, on the basis of a relaxation time of the qubits to be operated by the detected first quantum gate, equivalent circuits to be implemented from among a plurality of equivalent circuits that realize the same gate operation as the first quantum gate by a second quantum gate at which the gate operations can be executed by the quantum device. Then, the quantum circuit design device (10) converts the first quantum gate in the quantum circuit (1) to the determined equivalent circuits (7a, 7b).

Description

Technical Field

[0001] The present invention relates to a quantum circuit design program, a quantum circuit design method, and a quantum circuit design apparatus.

Background Art

[0002] Currently, available quantum computers are of a type called NISQ (Noisy Intermediate-Scale Quantum Computer) using superconducting or ion trap qubits. In these quantum devices, the error rate is about 1% and the number of qubits is about 10 - 1000. Such small-scale quantum computers cannot completely correct errors. Therefore, when performing quantum calculations on a quantum computer, it is important to perform quantum calculations using a quantum circuit for reducing errors as much as possible.

[0003] In addition, in a quantum computer, a single-qubit gate and a two-qubit gate are implemented as quantum gates for operating qubits. These quantum gates are called native gates. Which two-qubit gates are supported as native gates depends on the type of quantum device adopted in the quantum computer.

[0004] On the other hand, a quantum circuit created corresponding to a problem to be solved may include quantum gates other than native gates. Therefore, quantum gates other than native gates are implemented in a qubit control device that performs gate operations on qubits after being converted into an equivalent circuit combining native gates. For example, a three-qubit gate such as a CCX (Toffoli) gate is implemented using a plurality of two-qubit gates. A CnX gate or a CnZ gate (n is an integer of 3 or more) having three or more control bits is converted into a plurality of CCX gates and then further converted into native gates.

[0005] As a technology related to improving the processing executed by a quantum computer, for example, a constant folding method in the compilation of a quantum algorithm has been proposed. Also, a method for designing a quantum computing circuit specific to an application or algorithm for a specific application or algorithm has been proposed. Furthermore, for a quantum algorithm, when using logical qubits for only a short time, a technique for reusing one physical qubit by an active reset operation has been proposed if the usage times do not overlap.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] When converting a quantum gate not supported by a quantum device of a quantum computer into an equivalent circuit composed of native gates, there may be a plurality of equivalent circuits that can be the conversion destination. In this case, it is desirable to convert to an equivalent circuit with a smaller error rate in quantum computing among the plurality of equivalent circuits.

[0008] The error rate of an equivalent circuit depends on the characteristics of the quantum bits used in that equivalent circuit. However, conventionally, conversion to an equivalent circuit has not been performed taking into account the characteristics of the quantum bits. As a result, the quantum gate to be converted is mechanically converted to an equivalent circuit that is pre-associated with that quantum gate, which can increase the error rate of quantum computing. An increase in the error rate of quantum computing leads to a decrease in calculation accuracy.

[0009] In one aspect, the present invention aims to improve the accuracy of quantum computing. [Means for solving the problem]

[0010] In one proposal, a quantum circuit design program is provided that causes a computer to perform the following processes: The computer detects a first quantum gate that cannot perform the gate operation in the quantum device from a quantum circuit that indicates gate operations on multiple quantum bits included in the quantum device.The computer determines an equivalent circuit to be implemented from among multiple equivalent circuits that realize the same gate operation as the first quantum gate using a second quantum gate that can perform the gate operation in the quantum device, based on the relaxation time of the quantum bit to be operated by the detected first quantum gate.The computer then converts the first quantum gate in the quantum circuit into the determined equivalent circuit. [Effects of the Invention]

[0011] According to one aspect, the accuracy of quantum computing can be improved. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention. [Brief explanation of the drawings]

[0012]

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Embodiments for Carrying Out the Invention

[0013] <^ Hereinafter, the present embodiment will be described with reference to the drawings. Note that a plurality of embodiments can be combined and implemented within a non - conflicting range. 〔First Embodiment〕 The first embodiment is a quantum circuit design method for converting a quantum gate not supported by the quantum device of a quantum computer into an equivalent circuit that can reduce the error rate by considering the characteristics of the qubits used when converting it into a native gate.

[0014] FIG. 1 is a diagram showing an example of the quantum circuit design method according to the first embodiment. FIG. 1 shows a quantum computer having a quantum circuit design apparatus 10 and a qubit control apparatus 8. The quantum circuit design apparatus 10 can implement the quantum circuit design method according to the first embodiment by executing a quantum circuit design program.

[0015] The quantum circuit design apparatus 10 is connected to the qubit control apparatus 8. The qubit control apparatus 8 has a plurality of qubits 8a, 8b, ··· and executes quantum calculation using the qubits 8a, 8b, ···. The quantum circuit design apparatus 10 can design an appropriate quantum circuit 7 according to the characteristics of the qubits 8a, 8b, ··· of the qubit control apparatus 8.

[0016] The quantum circuit design apparatus 10 has a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device of the quantum circuit design apparatus 10. The processing unit 12 is, for example, a processor or an arithmetic circuit of the quantum circuit design apparatus 10.

[0017] The memory unit 11 stores the quantum circuit 1 and the qubit characteristic information 2. The quantum circuit 1 is information indicating the operation procedure of qubits for obtaining the number of turns of the problem to be solved by quantum calculation. In the quantum circuit 1, the gate operation on the qubits is represented by quantum gates. The quantum gates used in the quantum circuit 1 are not limited to the quantum gates that are hardware-supported by the quantum devices of the quantum computer. Therefore, the quantum circuit 1 also includes quantum gates that operate on three or more qubits. For example, the quantum circuit 1 includes a CCX gate 1a (also called a Toffoli gate) or a CCZ gate 1b.

[0018] The qubit characteristic information 2 stores information regarding the characteristics of each of the qubits 8a, 8b,... that the qubit control device 8 has. For example, the qubit characteristic information 2 includes the relaxation time indicating the period during which the qubit 8a, 8b,... can hold the information of the quantum state. Also, the qubit characteristic information 2 can include the fidelity for each of the qubits 8a, 8b,.... The fidelity is an index indicating how close the state of the qubit is to the ideal quantum state.

[0019] The processing unit 12 converts the quantum circuit 1 stored in the memory unit 11 into a quantum circuit 7 that can be implemented in the qubit control device 8. For example, the processing unit 12 converts a quantum gate that operates on three or more qubits in the quantum circuit 1 into an equivalent circuit combined with one-qubit gates or two-qubit gates. Also, when the quantum device of the qubit control device 8 can perform the gate operation of the CZ gate but cannot perform the gate operation of the CX gate (CNOT gate), the processing unit 12 converts the CX gate into an equivalent circuit using the CZ gate. Specifically, the processing unit 12 performs the following processing.

[0020] The processing unit 12 detects a first quantum gate from a quantum circuit 1 that represents gate operations on a plurality of qubits 8a, 8b, ··· included in the quantum bit control device 8 in the quantum computer, which cannot be executed by the quantum device of the quantum computer. The first quantum gate is, for example, a CCX gate 1a or a CCZ gate 1b.

[0021] Next, the processing unit 12 determines an equivalent circuit to be implemented from among a plurality of equivalent circuits that realize the same gate operation as the first quantum gate, based on the relaxation time of the qubits to be operated on by the first quantum gate. The plurality of equivalent circuits are quantum circuits using second quantum gates that can execute gate operations on the quantum device of the quantum computer. For example, the processing unit 12 determines the equivalent circuit to be implemented based on the ratio of the gate operation time of a two-qubit gate in the quantum computer to the relaxation time of the qubits to be operated on. In this case, the processing unit 12 obtains the minimum value among the relaxation times of the plurality of qubits to be operated on. Then, the processing unit 12 compares the value of the ratio of the gate operation time to the minimum value of the relaxation time (gate operation time / relaxation time) with a predetermined threshold. If "gate operation time / relaxation time" is less than the threshold, the processing unit 12 determines to convert to an equivalent circuit using an iSWAP gate. Also, if "gate operation time / relaxation time" is greater than or equal to the threshold, the processing unit 12 determines to convert to an equivalent circuit using a CZ gate.

[0022] When the equivalent circuit to be implemented is determined, the processing unit 12 converts the first quantum gate in the quantum circuit 1 into the determined equivalent circuit. For example, when the detected first quantum gate is the CCX gate 1a, the processing unit 12 first converts the CCX gate 1a into an equivalent circuit 3 that performs the same gate operation as the CCX gate 1a. The equivalent circuit 3 includes a CCZ gate 3a.

[0023] Next, the processing unit 12 converts the CCZ gate 3a included in the equivalent circuit 3 into an equivalent circuit 4 that performs the same gate operation as the CCZ gate 3a. The equivalent circuit 4 includes a CX gate 4a. Also, when the detected first quantum gate is the CCZ gate 1b, the processing unit 12 converts the CCZ gate 1b into the equivalent circuit 4.

[0024] Furthermore, the processing unit 12 converts the CX gate 4a in the equivalent circuit 4 into either of two equivalent circuits 5 and 6 that perform the same gate operation as the CX gate 4a. The equivalent circuit 5 includes iSWAP gates 5a and 5b. The equivalent circuit 6 includes a CZ gate 6a. For example, when it is determined that the processing unit 12 converts to an equivalent circuit using the iSWAP gate, the CX gate 4a in the equivalent circuit 4 is converted into the equivalent circuit 5. When it is determined that the processing unit 12 converts to an equivalent circuit using the CZ gate, the CX gate 4a in the equivalent circuit 4 is converted into the equivalent circuit 6.

[0025] Then, the processing unit 12 instructs the quantum bit control device 8 to perform quantum computing according to the quantum circuit 7 generated by converting the first quantum gate of the quantum circuit 1 into an equivalent circuit. The quantum circuit 7 includes, for example, equivalent circuits 7a and 7b instead of the CCX gate 1a and the CCZ gate 1b of the quantum circuit 1. The quantum circuit 7 is composed only of quantum gates that the quantum bit control device 8 natively supports by the quantum device. The quantum bit control device 8 executes gate operations on the quantum bits 8a, 8b, ··· by the quantum gates shown in the quantum circuit 7, and measures the states of the quantum bits 8a, 8b, ··· after executing the gate operations according to the quantum circuit 7.

[0026] In this way, the processing unit 12 can convert the CCX gate 1a or the CCZ gate 1b into equivalent circuits 7a and 7b with a reduced error rate based on the relaxation times of the quantum bits 8a, 8b, ···. As a result, the error rate of the quantum computing by the quantum bit control device 8 is reduced, and high-precision computing becomes possible.

[0027] Further, the processing unit 12 determines an equivalent circuit to be implemented based on the ratio between the gate operation time of a two-qubit gate and the relaxation time of the qubit to be operated on. As a result, it is possible to correctly evaluate the influence of noise according to the relaxation time, and to appropriately determine the equivalent circuit of the conversion destination.

[0028] Further, the processing unit 12 calculates a value of the ratio between the gate operation time and the relaxation time using the minimum value among the relaxation times of the plurality of quantum gates operated by the first quantum gate to be converted, and compares it with a threshold value. In this way, the equivalent circuit of the conversion destination is determined using the minimum value of the relaxation time of each quantum gate. As a result, the equivalent circuit of the conversion destination is determined according to the characteristics of the quantum gate with poor quality. Since the error of the gate operation on the qubit accumulates for each gate operation, if there is a quantum gate with a high error rate, the error rate of the quantum circuit operating on that quantum gate also becomes high. Therefore, by determining the equivalent circuit of the conversion destination according to the characteristics of the quantum gate with poor quality, it is possible to correctly evaluate the quality of each of the plurality of equivalent circuits and then determine the equivalent circuit of the conversion destination.

[0029] Note that the relaxation times of the qubits 8a, 8b,... change due to various influences. Therefore, the processing unit 12 may measure the relaxation time of each of the qubits 8a, 8b,... regularly (for example, every day) and update the qubit characteristic information 2. As a result, when converting the quantum circuit 1, it is possible to determine the equivalent circuit of the conversion destination using the latest relaxation time of each of the qubits 8a, 8b,....

[0030] In addition, by using high-quality qubits as the qubits to be operated on in the quantum circuit 7, the accuracy of quantum computing can also be improved. Therefore, the processing unit 12 determines the qubits to be operated on in the quantum circuit based on the fidelity of the plurality of qubits 8a, 8b, ··· included in the quantum computer. For example, the processing unit 12 determines, as the qubit group to be operated on in the quantum circuit 7, the qubit group with the highest average fidelity among consecutive qubit groups corresponding to the number of qubits used in the quantum circuit 7. Here, the consecutive qubit group refers to a plurality of qubits in which adjacent qubits are in a connection relationship when these qubits are arranged in a column. By using qubits with high fidelity, high-precision quantum computing becomes possible.

[0031] 〔Second Embodiment〕 Next, the second embodiment will be described. The second embodiment is a system that allocates optimal qubits to a quantum circuit in consideration of the fidelity of the qubits and executes quantum computing with a quantum circuit optimized according to the relaxation time of the qubits.

[0032] FIG. 2 is a diagram showing an example of the system configuration of the second embodiment. The quantum computer 300 is a gate-based quantum computer. The quantum computer 300 includes a control computer 100 and a qubit control device 200. Terminal devices 401, 402, ··· are connected to the control computer 100 via the network 20. The terminal devices 401, 402, ··· are computers used by users who request quantum computing by the quantum computer 300. The control computer 100 receives a quantum circuit from the terminal devices 401, 402, ···. The quantum circuit indicates the order of operations on the qubits by the arrangement of elements such as gates. A qubit is a bit capable of expressing a superposition state of the "0" state and the "1" state.

[0033] The control computer 100 gives instructions to the qubit control device 200 to control the qubits according to the quantum circuits received from the terminal devices 401, 402, ···. Also, the control computer 100 acquires the measurement results of each qubit from the qubit control device 200.

[0034] The qubit control device 200 has a plurality of qubits and devices for operating each of the plurality of qubits. The plurality of qubits included in the qubit control device 200 may be, for example, of the superconducting type or the ion trap type. Also, the plurality of qubits may be of the diamond spin type. When the qubits are of the superconducting type, the qubit control device 200 may have a refrigerator for cooling the qubits.

[0035] The qubit control device 200 irradiates the qubits with microwaves, for example, in response to an instruction from the control computer 100. Also, the devices for operating each of the plurality of qubits measure the states of each of the plurality of qubits and transmit them to the control computer 100.

[0036] FIG. 3 is a diagram showing a configuration example of the hardware of the control computer. The control computer 100 is controlled as a whole by a CPU (Central Processing Unit) 101. The CPU 101 is a processor that executes program instructions. Note that the CPU 101 may include a plurality of processor cores. Also, the CPU 101 may be a plurality of processors, or may be an MPU (Micro Processing Unit), a DSP (Digital Signal Processor), or the like. Also, at least a part of the functions realized by the CPU 101 executing a program may be realized by an electronic circuit such as an ASIC (Application Specific Integrated Circuit) or a PLD (Programmable Logic Device). A RAM (Random Access Memory) 102 and a plurality of peripheral devices are connected to the CPU 101 via a bus 100a.

[0037] The RAM 102 is the main memory device of the control computer 100. At least a part of the OS (Operating System) program and application programs to be executed by the CPU 101 are temporarily stored in the RAM 102. Also, various data used for the processing by the CPU 101 are stored in the RAM 102. Note that the control computer 100 may include memory of types other than the RAM, or may include a plurality of memories.

[0038] Peripheral devices connected to the bus 100a include an HDD (Hard Disk Drive) 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, device connection interfaces 107, 108, and a network interface 109.

[0039] The HDD 103 is an auxiliary storage device of the control computer 100. The HDD 103 magnetically writes and reads data to and from the built-in magnetic disk. The OS program, application programs, and various data are stored in the HDD 103. Note that the control computer 100 may include other types of auxiliary storage devices such as flash memory or SSD (Solid State Drive), or may include a plurality of auxiliary storage devices.

[0040] A monitor 21 is connected to the GPU 104. The GPU 104 displays an image on the screen of the monitor 21 according to an instruction from the CPU 101. Examples of the monitor 21 include a display device using organic EL (Electro Luminescence) and a liquid crystal display device.

[0041] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 or the mouse 23 to the CPU 101. Note that the mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, a trackball, etc.

[0042] The optical drive device 106 reads data recorded on the optical disk 24 using laser light or the like. The optical disk 24 is a portable recording medium on which data is recorded so that it can be read by reflection of light. Examples of the optical disk 24 include a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), etc.

[0043] The device connection interface 107 is a communication interface for connecting peripheral devices to the control computer 100. For example, a memory device 25 and a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a communication function with the device connection interface 107. The memory reader / writer 26 is a device that writes data to or reads data from the memory card 27. The memory card 27 is a card-type recording medium.

[0044] The device connection interface 108 is a communication interface for connecting the quantum bit control device 200 to the control computer 100. The control computer 100 transmits an instruction for controlling quantum bits to the quantum bit control device 200 via the device connection interface 108.

[0045] Network interface 109 is connected to network 20. Network interface 109 transmits and receives data to and from other computers or communication devices via network 20.

[0046] With the above hardware configuration, control computer 100 can implement the processing functions of the second embodiment. Note that quantum circuit design device 10 shown in the first embodiment can also be implemented with the same hardware as control computer 100 shown in FIG. 3. Further, CPU 101 is an example of processing unit 12 shown in the first embodiment.

[0047] Control computer 100 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. Programs describing the processing content to be executed by control computer 100 can be recorded on various recording media. For example, a program to be executed by control computer 100 can be stored in HDD 103. CPU 101 loads at least a part of the program in HDD 103 into RAM 102 and executes the program. Further, a program to be executed by control computer 100 can also be recorded on portable recording media such as optical disk 24, memory device 25, memory card 27, etc. The program stored on the portable recording medium becomes executable after being installed in HDD 103 under the control of, for example, CPU 101. Further, CPU 101 can also directly read and execute the program from the portable recording medium.

[0048] In the system as described above, the control computer 100 acquires a quantum circuit in which the procedure of the gate operation of qubits for quantum computing is described from the terminal devices 401, 402, ···. The quantum circuits acquired from the terminal devices 401, 402, ··· include gate operations of three-qubit gates or more. On the other hand, the gate operations in the qubit control device 200 are limited to gate operations of one-qubit gates or two-qubit gates. Therefore, the control computer 100 converts the quantum gates of three-qubit gates or more included in the acquired quantum circuit into an equivalent circuit using one-qubit gates or two-qubit gates.

[0049] As an example, with reference to FIGS. 4 to 7, a method for converting a CCX (Toffoli) gate into an equivalent circuit will be described. The quantum circuits used in the following description have horizontal lines corresponding to each qubit on which a gate operation is performed. On the horizontal lines, quantum gates indicating the gate operations to be performed on the corresponding qubits are arranged. In the quantum circuit, the quantum gates indicating the operations performed earlier are arranged further to the left.

[0050] FIG. 4 is a diagram showing an example of an equivalent circuit of a CCX gate. The CCX gate 30 indicates that when two control bits (q0, q1) are “1”, an X gate is applied (the bit is inverted) to one target bit (q2). In the quantum circuit, a symbol combining a circle and a + is arranged on the line corresponding to the qubit that becomes the target bit of the CCX gate 30, and a point connected by a line to the symbol is arranged on each line corresponding to the qubits that become the two control bits. Such a CCX gate 30 can be converted into an equivalent circuit 31 combining an H gate (Hadamard gate) and a CCZ gate 31a.

[0051] The equivalent circuit 31 is a quantum circuit that performs a gate operation equivalent to that of the CCX gate 30. In the equivalent circuit 31, in the quantum bit of the target bit, two H gates (rectangles marked as "H" in FIG. 4) are arranged sandwiching the CCZ gate 31a. The CCZ gate 31a indicates that when the two control bits (q0, q1) are "1", a Z gate is applied (phase is inverted) to one target bit (q2).

[0052] The CCZ gate 31a included in the equivalent circuit 31 can be converted into an equivalent circuit combining a one-qubit gate and a two-qubit gate. FIG. 5 is a diagram showing an example of an equivalent circuit of the CCZ gate. The equivalent circuit 33 is equivalent to the CCZ gate 32 for the quantum bits q0, q1, q2 and is a quantum circuit combining a one-qubit gate and a two-qubit gate. The blocks marked as T arranged on the horizontal lines corresponding to the quantum bits q0, q1, q2 of the equivalent circuit 33 indicate T gates. The T gate indicates an operation of shifting the phase by a predetermined value. Also, the blocks marked as T † arranged on the horizontal lines corresponding to the quantum bits q0, q1, q2 of the equivalent circuit 33 indicate T † gates. The T † gate indicates an operation of shifting the phase by a predetermined value in the direction opposite to that of the T gate.

[0053] The symbol combining a circle and a + arranged on the horizontal lines corresponding to the quantum bits q0, q1, q2 of the equivalent circuit 33, and the dot arranged on the line connected to the symbol and corresponding to each of the quantum bits q0, q1, q2 indicate a CX gate. Note that the symbol combining a circle and a + is arranged on the line corresponding to the quantum bit that becomes the target bit of the CX gate, and the dot is arranged on the line corresponding to the quantum bit that becomes the control bit of the CX gate. The CX gate indicates that when the control bit is "1", the bit of the target bit is inverted.

[0054] In this way, the CCZ gate 32 can be converted into an equivalent circuit 33 that combines a one-qubit gate and a two-qubit gate. However, the equivalent circuit 33 includes CX gates 33a and 33b for the qubit q0 and the qubit q2. In a quantum computer, a two-qubit gate operation can only be executed between two connected qubits. When assigning actual qubits in the quantum computer 300 to the qubits shown in the quantum circuit, the connected qubits among the actual qubits are assigned to the qubits adjacent on the quantum circuit. However, for qubits that are not adjacent on the quantum circuit, unconnected qubits among the actual qubits may be assigned. In that case, the equivalent circuit 33 is converted into an equivalent circuit 34 using a SWAP gate 34a.

[0055] In the equivalent circuit 34, a SWAP gate 34a is inserted in front of the CX gates 33a and 33b in the equivalent circuit 33. The SWAP gate 34a represents a gate operation that exchanges the states of two qubits. By inserting the SWAP gate 34a, the CX gates 33a and 33b are replaced with CX gates 34b and 34c for the qubit q0 and the qubit q1. Also, the last T gate 33c of the qubit q2 in the equivalent circuit 33 is replaced with the last T gate 34d of the qubit q1 in the equivalent circuit 34.

[0056] Note that in the equivalent circuit 34, the assignment of the actual qubits in the qubit control device 200 to the qubits that are the targets of quantum calculation in the quantum algorithm is different before and after the execution of the equivalent circuit 34. Therefore, there are differences in the quantum states measured at each of the qubits q0, q1, and q2 after execution between the equivalent circuit 33 and the equivalent circuit 34.

[0057] For example, let the qubits to be quantum-computed on the quantum algorithm be x0, x1, and x2. When executing the equivalent circuit 33, assume that the actual qubit q0 in the qubit control device 200 is assigned to the qubit x0. Also, assume that the actual qubit q1 in the qubit control device 200 is assigned to the qubit x1. And assume that the actual qubit q2 in the qubit control device 200 is assigned to the qubit x2. If the equivalent circuit 33 is executable, the quantum state of the qubit x0 can be obtained by measuring the qubit q0, the quantum state of the qubit x1 can be obtained by measuring the qubit q1, and the quantum state of the qubit x2 can be obtained by measuring the qubit q2.

[0058] Note that if the qubit q0 and the qubit q1 are not connected in the quantum computer 300, the equivalent circuit 33 cannot be executed. In that case, the equivalent circuit 34 is executed. Since the equivalent circuit 34 includes the SWAP gate 34a, for the qubits x1 and x2 whose states are exchanged by the SWAP gate 34a, the actual qubits to be assigned are changed.

[0059] For example, for the qubit x1 on the quantum algorithm, the qubit q1 is assigned at the start of the execution of the equivalent circuit 34, but the qubit q2 is assigned at the end of the execution of the equivalent circuit 34. Also, for the qubit x2 on the quantum algorithm, the qubit q2 is assigned at the start of the execution of the equivalent circuit 34, but the qubit q1 is assigned at the end of the execution of the equivalent circuit 34. In this case, after executing the equivalent circuit 34, the quantum state of the qubit x0 can be obtained by measuring the qubit q0, the quantum state of the qubit x2 can be obtained by measuring the qubit q1, and the quantum state of the qubit x1 can be obtained by measuring the qubit q2.

[0060] When causing the quantum control device 200 to execute the quantum circuit including the equivalent circuit 34, the SWAP gate 34a in the equivalent circuit 34 is converted into a combination of CX gates. Also, the equivalent circuit 34 is optimized.

[0061] FIG. 6 is a diagram showing an example of an equivalent circuit of an optimized CCZ gate. In the example of FIG. 6, for the equivalent circuit 34, the circuit is converted into the circuits shown in three conversion patterns, resulting in the equivalent circuit 35.

[0062] The first conversion pattern (conversion pattern 1) shows the conversion from a SWAP gate to three CX gates. The second conversion pattern (conversion pattern 2) shows that two consecutive CX gates with a common control bit and target bit are the same as when no gate operation is performed, and these CX gates can be deleted. The third conversion pattern (conversion pattern 3) shows that when there is a T gate before or after the control bit of a CX gate, the positions of the control bit of the CX gate and the T gate may be swapped.

[0063] For example, the SWAP gate 34a of the equivalent circuit 34 is converted into three CX gates according to the "conversion pattern 1", with qubit q10 of the equivalent circuit 34 as qubit q2 and qubit q11 as qubit q1. In this case, for the first CX gate among the three converted CX gates, qubit q2 is the control bit and qubit q1 is the target bit.

[0064] Then, in the equivalent circuit 34, the first of the three CX gates converted from the SWAP gate 34a and the CX gate 34f immediately before the SWAP gate 34a have a common control bit and target bit. In that case, the "conversion pattern 2" can be applied. As a result, the first of the three CX gates converted from the SWAP gate 34a and the CX gate 34f immediately before the SWAP gate 34a are deleted. What remains in the converted equivalent circuit 35 are the second and third CX gates 35a among the three CX gates converted from the SWAP gate 34a.

[0065] Also, for the quantum bit q1 in the equivalent circuit 34, the control bit of the CX gate 34e is arranged before the last T gate 34d. In this case, by applying the "conversion pattern 3", the T gate 34d can be moved before the CX gate 34e. As a result, in the converted equivalent circuit 35, a T gate 35b corresponding to the T gate 34d is arranged before the last CX gate 35c for the quantum bit q1.

[0066] Here, compared with the gate operation time of a single-qubit gate, the gate operation time of a two-qubit gate is more than 10 times. Therefore, the number of two-qubit gates can be used as an index of the gate operation time for the converted equivalent circuit 35. The two-qubit gates included in the equivalent circuit 35 are 7 CX gates.

[0067] By replacing the CCZ gate 31a in the equivalent circuit 31 of the CCX gate 30 shown in FIG. 4 with the equivalent circuit 35 shown in FIG. 6, an equivalent circuit of the CCX gate can be obtained. Although the quantum computer 300 often supports the CZ gate, it does not support the CX gate. For example, in the case of the superconducting circuit method, gates such as the CZ gate and the iSWAP gate are supported as native gates, but the CX gate is not always supported. When the CX gate is not supported, by replacing the CX gates included in the equivalent circuit 35 with an equivalent circuit using the CZ gate, a quantum circuit that can be gate-operated by the quantum bit control device 200 is obtained.

[0068] FIG. 7 is a diagram showing an example of an implementable equivalent circuit of the CCZ gate. The CX gate can be converted into an equivalent circuit 41 using the CZ gate as shown in the "conversion pattern 4". In the equivalent circuit 41, the CX gate is replaced by a CZ gate, and two H gates are arranged sandwiching the CZ gate in the quantum bit of the target bit of the CX gate. By converting the 7 CX gates included in the equivalent circuit 35 into the equivalent circuit 41, an equivalent circuit 36 is obtained.

[0069] In addition to the CZ gate, the iSWAP gate is also a native gate of the quantum computer 300. The CX gate can also be replaced with an equivalent circuit using the iSWAP gate.

[0070] FIG. 8 is a diagram showing an example of an equivalent circuit of the CX gate using the iSWAP gate. The equivalent circuit 42 of the CX gate is composed of two iSWAP gates 42a and 42b and five rotation gates 42c to 42g. In the equivalent circuit 42, first, a rotation gate 42c that rotates by "-π / 2" around the Z axis is arranged on the control bit side of the CX gate. Also, on the target bit side of the CX gate, a rotation gate 42d that rotates by "π / 2" around the X axis and a rotation gate 42e that rotates by "π / 2" around the Z axis are arranged. Next to these rotation gates 42c to 42e, the first iSWAP gate 42a is arranged.

[0071] Next to the first iSWAP gate 42a, a rotation gate 42f that rotates by "π / 2" around the X axis is arranged on the control bit side of the CX gate. Next to this rotation gate 42f, the second iSWAP gate 42b is arranged. Then, next to the second iSWAP gate 42b, a rotation gate 42g that rotates by "π / 2" around the Z axis is arranged on the target bit side of the CX gate.

[0072] Here, the quantum computer 300 is NISQ. NISQ has a small number of qubits and cannot perform error correction. Errors occur due to the influence of noise, and the more gates included in the quantum circuit, the more the generated errors accumulate. Therefore, when converting the quantum gates included in the quantum circuit into native gates, an implementation considering noise is required. For example, when implementing the CCX gate, it is required to appropriately determine whether to implement it using an equivalent circuit using the CX gate or using the iSWAP gate.

[0073] The susceptibility of a qubit to noise effects is represented by the fidelity. The higher the fidelity, the less susceptible the qubit is to noise effects. The fidelity of a quantum gate is an indicator showing how close the quantum gate operation on a qubit is to an ideal operation. Also, a qubit can only hold information for a limited time without loss. Such a time is called the relaxation time. When the operation time in a quantum circuit exceeds the relaxation time, the information of the qubit is lost and an error occurs. Note that the relaxation time includes the average time to maintain the excited state (energy relaxation time) and the average time to maintain the superposition (phase relaxation time). Hereinafter, the energy relaxation time is referred to as "T1" and the phase relaxation time is referred to as "T2".

[0074] Indicators showing the susceptibility of errors to occur include the fidelity of qubits, the relaxation time of qubits, and the fidelity of quantum gates. The values of each indicator of the susceptibility of errors to occur vary for each qubit due to variations during the fabrication of the quantum device. Therefore, when the control computer 100 converts the acquired quantum circuit into an implementable quantum circuit, it is important to appropriately determine which native gate to implement on which qubit.

[0075] Here, when the control computer 100 attempts to execute a simulation to obtain an equivalent circuit with the lowest errors, all combinations need to be verified, resulting in an enormous computational time. Therefore, the control computer 100 determines the quantum circuit to be implemented based on the indicators of the susceptibility of errors to occur.

[0076] For example, the control computer 100 measures the fidelity and T1 of all qubits. The control computer 100 assigns qubits with high fidelity, which can be continuously arranged, to the quantum circuit to be executed, where the number of qubits used to execute the quantum algorithm is concerned. Then, the control computer 100 determines the native two-qubit gates to be used in the quantum circuit to be implemented based on a threshold value based on the qubit with the shortest T1 value among the three qubits performing the CCX gate or CCZ gate operation on the assigned qubits.

[0077] Next, the functions of the control computer 100 will be described in detail. FIG. 9 is a block diagram showing an example of the functions of the control computer. The control computer 100 includes a storage unit 110, a quantum calculation control unit 120, a qubit characteristic measurement unit 130, a qubit allocation unit 140, and a gate conversion unit 150.

[0078] The storage unit 110 stores conversion information 111, connection topology information 112, and qubit characteristic information 113. In the conversion information 111, the quantum gates to be converted and the equivalent circuits are registered in association with each other. In the connection topology information 112, connection topology information indicating the connection relationship between the qubits in the qubit control device 200 is registered. In the qubit characteristic information 113, the fidelity and T1 of each qubit in the qubit control device 200 are registered.

[0079] The quantum calculation control unit 120 controls quantum calculation. First, the quantum calculation control unit 120 acquires a quantum circuit. For example, the quantum calculation control unit 120 receives a request for quantum calculation by the quantum computer 300 and a quantum circuit from the terminal devices 401, 402, ···. Then, the quantum calculation control unit 120 controls the qubit control device 200 according to the quantum circuit converted by the gate conversion unit 150.

[0080] The qubit characteristic measurement unit 130 measures the fidelity and T1 of each qubit in the qubit control device 200 at a predetermined interval. For example, the qubit characteristic measurement unit 130 controls the qubit control device 200 about once a day to measure the fidelity and T1. Each time the qubit characteristic measurement unit 130 measures, it updates the qubit characteristic information 113.

[0081] The qubit allocation unit 140 allocates the qubits in the quantum bit control device 200 to the qubits used in the quantum circuit acquired by the quantum calculation control unit 120. For example, the qubit allocation unit 140 refers to the connection topology information 112 and allocates the qubits according to the condition that the qubits adjacent vertically in the quantum circuit are connected. When there are multiple qubit allocation patterns that satisfy the conditions, the qubit allocation unit 140 adopts the allocation pattern with the highest average fidelity of the included qubits.

[0082] The gate conversion unit 150 refers to the conversion information 111 and converts the quantum circuit acquired from the terminal devices 401, 402,... into a quantum circuit that can be implemented in the quantum bit control device 200. When converting the CX gate, the gate conversion unit 150 determines the equivalent circuit of the conversion destination based on the minimum value among the T1 values of each qubit allocated to the quantum circuit.

[0083] Note that the lines connecting the elements shown in FIG. 9 indicate a part of the communication path, and communication paths other than the illustrated communication path can also be set. Further, the functions of the elements shown in FIG. 9 can be realized, for example, by causing a computer to execute a program module corresponding to the element.

[0084] Next, the conversion information 111, the connection topology information 112, and the qubit characteristic information 113 stored in the storage unit 110 will be described in detail. FIG. 10 is a diagram showing an example of conversion information. In the conversion information 111, columns for a detection gate and an equivalent circuit are provided. In the column for the detection gate, the gate to be detected as the conversion target is set. In the column for the equivalent circuit, the equivalent circuit of the detection gate is set. For example, in the conversion information 111, an equivalent circuit 31 using a CCZ gate is registered in association with the CCX gate. Also, in the conversion information 111, an equivalent circuit 35 combining a single-qubit gate and two qubits is registered in association with the CCZ gate. Furthermore, in the conversion information 111, an equivalent circuit 41 using a CZ gate and an equivalent circuit 42 using an iSWAP gate are registered in association with the CX gate.

[0085] FIG. 11 is a diagram showing an example of connection topology information. In the connection topology information 112, a plurality of connection qubit pairs indicating two qubits in a connection relationship are registered. For any two qubits shown in the connection qubit pair, an operation of a two-qubit gate operating on them can be executed by the qubit control device 200.

[0086] FIG. 12 is a diagram showing an example of qubit characteristic information. In the qubit characteristic information 113, the fidelity and T1 of the corresponding qubit are set in association with each identifier of the qubits that the qubit control device 200 has. The fidelity and T1 of the qubit are periodically updated by the qubit characteristic measurement unit 130.

[0087] FIG. 13 is a flowchart showing an example of the procedure for the qubit characteristic information update process. Hereinafter, the process shown in FIG. 13 will be described according to the step numbers. [Step S101] The qubit characteristic measurement unit 130 determines whether or not a preset measurement time (for example, a specific time every day) has arrived. If the measurement time has arrived, the qubit characteristic measurement unit 130 proceeds to step S102. If the measurement time has not arrived, the qubit characteristic measurement unit 130 repeats step S101 and waits for the measurement time to arrive.

[0088] [Step S102] The qubit property measurement unit 130 controls the qubit control device 200 to measure the fidelity and T1 of each qubit. [Step S103] The qubit property measurement unit 130 updates the values of the fidelity and T1 of each qubit in the qubit property information 113 to the latest measured values. Then, the qubit property measurement unit 130 advances the process to Step S101.

[0089] Next, a method for determining the equivalent circuit to be converted when converting the CX gate into an equivalent circuit will be described in detail. When the T1 (average time to maintain the excited state) and T2 (average time to maintain superposition) of the qubits affected by relaxation time noise are known, the error occurring in each qubit for each gate operation on the qubit is represented by the Choi matrix shown in Equation (1).

[0090]

Equation

[0091] t is the gate execution time. p is a probability vector. When there is no noise, p = 0. From Equation (1), it can be seen that the influence of noise depends on the ratio of the gate execution time t to the relaxation time (T1 or T2). Specifically, the larger the value of the ratio of the gate execution time t to the relaxation time (gate execution time / relaxation time), the more susceptible it is to the influence of noise. That is, it is not possible to correctly judge the degree of influence of noise only by the relaxation time.

[0092] The gate execution time t of a single-qubit gate is a time determined in advance in the quantum computer 300 and does not depend on the type of single-qubit gate. Similarly, the gate execution time of a two-qubit gate also does not depend on the type of two-qubit gate.

[0093] The operation of a two-qubit gate takes time, and the gate execution time of a two-qubit gate is set to a very long value compared to the gate execution time of a single-qubit gate. Therefore, in a quantum circuit, the number of two-qubit gates is used as an index of the ease of error occurrence. The number of two-qubit gates in a quantum circuit is called the circuit length. A quantum circuit with a shorter circuit length is less likely to generate errors.

[0094] Also, the iSWAP gate is less affected by coherent noise than the CZ gate. On the other hand, when comparing the two equivalent circuits 41 and 42 of the CX gate, only one two-qubit gate is required for the equivalent circuit 41 using the CZ gate, while two two-qubit gates are required for the equivalent circuit 42 using the iSWAP gate. That is, the circuit length of the equivalent circuit 42 is twice that of the equivalent circuit 41. The greater the circuit length, the greater the influence of decoherence noise. Decoherence noise varies depending on the ratio of the relaxation time to the gate operation time, and the relaxation time differs for each qubit.

[0095] When the relaxation time is sufficiently long compared to the gate execution time and the value of the ratio of the gate execution time to the relaxation time is small, the influence of coherent noise becomes greater than the influence of noise related to the relaxation time. When the influence of coherent noise is greater, even if the circuit length is doubled, the iSWAP gate, which is less affected by coherent noise, may have a smaller overall influence of noise. Therefore, when the gate conversion unit 150 converts the CX gate into either of the equivalent circuits 41 and 42, it determines the destination equivalent circuit based on the value of the ratio of the gate execution time to the relaxation time for the two-qubit gate.

[0096] FIG. 14 is a diagram showing an example of the conversion process of a CCX gate. The gate conversion unit 150 converts the CCX gate 30 into an equivalent circuit 31 using a CCZ gate 31a. Next, the gate conversion unit 150 converts the CCZ gate 31a in the equivalent circuit 31 into an equivalent circuit 35 composed of one qubit and two qubits. The equivalent circuit 35 includes seven CX gates. Therefore, the gate conversion unit 150 converts each of the seven CX gates into either the equivalent circuit 41 or 42 according to whether the value of the ratio (t / T1) of the gate execution time t of the two-qubit gate to T1 is less than a threshold value.

[0097] Specifically, if t / T1 is greater than or equal to the threshold value, the gate conversion unit 150 converts each CX gate into an equivalent circuit 41 using a CZ gate. In this case, the converted quantum circuit includes seven CZ gates. Also, if t / T1 is less than the threshold value, the gate conversion unit 150 converts each CX gate into an equivalent circuit 42 using an iSWAP gate. In this case, the converted quantum circuit includes 14 iSWAP gates.

[0098] FIG. 15 is a flowchart showing an example of the procedure of the quantum circuit conversion process. Hereinafter, the process shown in FIG. 15 will be described according to the step numbers. [Step S201] The quantum calculation control unit 120 acquires a quantum circuit. For example, the quantum calculation control unit 120 receives a request for quantum calculation and a quantum circuit from the terminal devices 401, 402,... by the quantum computer 300.

[0099] [Step S202] The qubit allocation unit 140 generates a candidate qubit group that can be continuously arranged based on the connection topology information 112. Being continuously arrangeable means satisfying the condition that the qubits connected to the qubit control device 200 can be allocated to the qubits that are vertically adjacent in the quantum circuit.

[0100] [Step S203] The qubit allocation unit 140 refers to the qubit characteristic information 113 and calculates the average value of the fidelity of the qubits belonging to each of the generated candidate qubit groups.

[0101] [Step S204] The qubit allocation unit 140 determines the candidate qubit group with the highest average fidelity as the allocation destination of the qubits of the quantum circuit. [Step S205] The gate conversion unit 150 detects three qubits that are the target of the CCX gate or CCZ gate operation from the acquired quantum circuit.

[0102] [Step S206] The gate conversion unit 150 determines whether the corresponding three qubits have been detected. If the gate conversion unit 150 determines that the corresponding three qubits have been detected, the process proceeds to Step S207. Also, if the gate conversion unit 150 determines that the corresponding three qubits have not been detected, the process proceeds to Step S211.

[0103] [Step S207] The gate conversion unit 150 acquires the minimum value among the T1 values of each of the detected three qubits from the qubit characteristic information 113. [Step S208] The gate conversion unit 150 determines whether the value of the ratio (t / T1) of the gate execution time t to the acquired T1 is less than the threshold value. If the value of the ratio is less than the threshold value, the gate conversion unit 150 proceeds to Step S209. Also, if the value of the ratio is greater than or equal to the threshold value, the gate conversion unit 150 proceeds to Step S210.

[0104] [Step S209] The gate conversion unit 150 converts all of the CCX gates or CCZ gates executed on the detected three qubits into an equivalent circuit using iSWAP gates. Then, the gate conversion unit 150 proceeds to Step S205.

[0105] [Step S210] The gate conversion unit 150 converts all of the CCX gates or CCZ gates executed on the detected three qubits into an equivalent circuit using CZ gates. Then, the gate conversion unit 150 proceeds to Step S205.

[0106] [Step S211] The quantum calculation control unit 120 controls the quantum bit control device 200 according to the converted quantum circuit. In this way, the CCX gate or the CCZ gate can be converted into an equivalent circuit with less influence of noise. The threshold used for determining the equivalent circuit can be determined, for example, by evaluating the influence of noise between the equivalent circuit using the iSWAP gate and the equivalent circuit using the CZ gate.

[0107] As an evaluation index of the influence from noise, for example, there is the Total Variation Distance (TVD). TVD is based on the sum of the ideal probability without noise and the probability with noise. TVD is represented by the following formula (2).

[0108] [Number]

[0109] p ideal (x) is the occurrence probability in the ideal situation (the situation without noise) of the sequence of quantum bit values (bit sequence x). p(x) is the occurrence probability of the bit sequence x measured by actual measurement or simulation. In formula (2), for each bit sequence x belonging to the set X of possible bit sequences, the difference between the probability with noise and the probability without noise is calculated. And 1 / 2 of the sum of those differences becomes the TVD. The smaller the value of the TVD, the less the influence of noise.

[0110] FIG. 16 is a diagram showing an example of the change in TVD for each equivalent circuit according to noise. In the example of FIG. 16, the characteristics of the qubit are "T1 = 33 μsec, T2 = 16 μsec". The value of TVD according to noise differs for each oracle to be calculated. In graphs 51 to 56, the TVD according to noise is obtained for all oracles, and the change in the average value of TVD according to the increase in noise is shown for each of a plurality of equivalent circuits of the CCX gate. The horizontal axis of graphs 51 to 56 indicates the magnitude of noise, and the vertical axis indicates TVD. The noise is, for example, over-rotation noise.

[0111] Graphs 51 to 56 each have a different value of t / T1. In graphs 51 to 56, the change in the average value of TVD of the equivalent circuit using the iSWAP gate is shown by a thin broken line, and the change in the average value of TVD of the equivalent circuit using the CZ gate is shown by a thick broken line.

[0112] Graph 51 is an example when "t / T1 = 10 -5 ". In this case, the equivalent circuit using the iSWAP gate always has a smaller TVD value than the equivalent circuit using the CZ gate. Graph 52 is an example when "t / T1 = 5×10 -5 ". In this case, when the noise is smaller than "0.02", the equivalent circuit using the CZ gate has a smaller TVD value than the equivalent circuit using the iSWAP gate. When the noise becomes larger than "0.02", the equivalent circuit using the iSWAP gate has a smaller TVD value than the equivalent circuit using the CZ gate.

[0113] Graph 53 is an example when "t / T1 = 10 -4 ". In this case, when the noise is smaller than "0.04", the equivalent circuit using the CZ gate has a smaller TVD value than the equivalent circuit using the iSWAP gate. When the noise becomes larger than "0.04", the equivalent circuit using the iSWAP gate has a smaller TVD value than the equivalent circuit using the CZ gate.

[0114] Graph 54 is an example for the case of "t / T1 = 5×10 -4 ". In this case, the equivalent circuit using the CZ gate always has a smaller TVD value than the equivalent circuit using the iSWAP gate.

[0115] Graph 55 is an example for the case of "t / T1 = 10 -3 ". In this case, the equivalent circuit using the CZ gate always has a smaller TVD value than the equivalent circuit using the iSWAP gate. The difference in the TVD values between the equivalent circuit using the CZ gate and the equivalent circuit using the iSWAP gate is wider than that in the case of "t / T1 = 5×10 -4 ".

[0116] Graph 56 is an example for the case of "t / T1 = 5×10 -3 ". In this case, the equivalent circuit using the CZ gate always has a smaller TVD value than the equivalent circuit using the iSWAP gate. The difference in the TVD values between the equivalent circuit using the CZ gate and the equivalent circuit using the iSWAP gate is wider than that in the case of "t / T1 = 10 -3 ".

[0117] Thus, when the value of "t / T1" exceeds "10 -4 ", the equivalent circuit using the CZ gate is less affected by noise. On the contrary, when the value of "t / T1" is "10 -4 " or less, there are cases where the equivalent circuit using the iSWAP gate is less affected by noise. When the value of "t / T1" is "10 -4 " or less, if the noise is small, the equivalent circuit using the CZ gate is less affected by noise, but the difference in TVD from the equivalent circuit using the iSWAP gate is tiny. Therefore, it is appropriate to set the threshold value of "t / T1" for determining the equivalent circuit to "10 -4 ". That is, if "t / T1 < 10 -4 ", the gate conversion unit 150 converts the CCX or CCZ gate into an equivalent circuit using the iSWAP gate. Also, if "t / T1 ≥ 10 -4 ", the gate conversion unit 150 converts the CCX or CCZ gate into an equivalent circuit using the CZ gate.

[0118] By setting the threshold value of t / T1 to an appropriate value, the quantum circuit to be calculated can be optimized into a quantum circuit with reduced noise effects and implemented in the quantum bit control device 200. For example, a method of implementation when performing quantum calculation with the Grover's algorithm of three quantum bits will be described with reference to FIGS. 17 to 19.

[0119] FIG. 17 is a diagram showing an example of a quantum circuit of the Grover's algorithm of three quantum bits. The quantum circuit 60 shows the order of operations for each of the quantum bits q0, q1, and q2 when executing the Grover's algorithm once with three quantum bits.

[0120] For each of the quantum bits q0, q1, and q2, an operation of the H gate is performed as an initialization process. Thereby, a superposition state of all states is generated. Next, an oracle operation is performed on the quantum bits q0, q1, and q2. In the oracle, after performing an operation of the X gate on each of the quantum bits q0, q1, and q2, a CCZ gate operation of three quantum bits is performed. Then, again, an operation of the X gate is performed on each of the quantum bits q0, q1, and q2.

[0121] After the oracle operation, an amplification operation is performed. In the amplification operation, an operation of the H gate and an operation of the X gate are performed on each of the quantum bits q0, q1, and q2. Then, a CCZ gate operation of three quantum bits is performed. And an operation of the X gate and an operation of the H gate are performed on each of the quantum bits q0, q1, and q2.

[0122] After the amplification operation, measurements of each of the quantum bits q0, q1, and q2 are performed. By the measurement, the quantum bits q0, q1, and q2 are each determined to be in the state of "0" or "1". The result when the inversion amplification process of the Grover's algorithm is performed once is output by the observation shown in the quantum circuit 60.

[0123] Note that the quantum computer 300 has a device for performing gate operations on two or fewer qubits and does not have a device capable of performing gate operations on three or more qubits. Therefore, a gate for three qubits, such as the CCZ gate, is converted into an equivalent circuit that combines gates for two qubits or one qubit. The quantum circuit 60 includes two three-qubit CCZ gates, and these CCZ gates are first converted into an equivalent circuit 35 (see FIG. 10).

[0124] FIG. 18 is a diagram showing an example of an equivalent circuit of a quantum circuit of Grover's algorithm. By converting the CCZ gates of the quantum circuit 60 into the equivalent circuit 35, a quantum circuit 61 composed of one-qubit gates and two-qubit gates is generated. The quantum circuit 61 includes 14 CX gates.

[0125] When converting the CCZ gate into the equivalent circuit 35, operations of SWAP gates are performed on the qubits q1 and q2 as shown in FIGS. 5 and 6. Therefore, due to the conversion of the CCZ gate into the equivalent circuit 35, the assignment of the actual qubits to the qubits x0, x1, and x2 that are the targets of quantum calculation in the quantum algorithm changes. However, in the quantum circuit 61, since the conversion of the CCZ gate into the equivalent circuit 35 is performed twice, the assignment of the actual qubits to the qubits x0, x1, and x2 that are the targets of quantum calculation in the quantum algorithm returns to the original assignment at the time of measurement.

[0126] The quantum circuit 61 includes 14 CX gates. All 14 CX gates are converted into an equivalent circuit using iSWAP gates or all are converted into an equivalent circuit using CZ gates. The threshold value of t / T1 for determining which equivalent circuit to convert is determined based on the change in TVD according to the noise in Grover's algorithm.

[0127] FIG. 19 is a diagram showing an example of the change in TVD for each equivalent circuit according to noise in Grover's algorithm. In the example of FIG. 19, the characteristics of the quantum bit are "T1 = 33 μsec, T2 = 16 μsec". In graphs 71 to 76, the TVD according to noise is obtained for all oracles, and the change in the average value of the TVD according to the increase in noise is shown for each of a plurality of equivalent circuits of the CCX gate. The horizontal axis of graphs 71 to 76 indicates the magnitude of the noise, and the vertical axis indicates the TVD.

[0128] In graphs 71 to 76, the change in the average value of the TVD of the equivalent circuit using the iSWAP gate is shown by a thin broken line, and the change in the average value of the TVD of the equivalent circuit using the CZ gate is shown by a thick broken line.

[0129] Graph 71 is an example in the case of "t / T1 = 10 -5 ". In this case, the equivalent circuit using the iSWAP gate always has a smaller TVD value than the equivalent circuit using the CZ gate. Graph 72 is an example in the case of "t / T1 = 5×10 -5 ". Also in this case, as in the case of "t / T1 = 10 -5 ", the equivalent circuit using the iSWAP gate always has a smaller TVD value than the equivalent circuit using the CZ gate.

[0130] Graph 73 is an example in the case of "t / T1 = 10 -4 ". Also in this case, as in the case of "t / T1 = 5×10 -5 ", the equivalent circuit using the iSWAP gate always has a smaller TVD value than the equivalent circuit using the CZ gate.

[0131] Graph 74 is an example in the case of "t / T1 = 5×10 -4 ". When the noise is 0.01 or less, the equivalent circuit using the CZ gate has a smaller TVD value than the equivalent circuit using the iSWAP gate. When the noise becomes 0.02 or more, the equivalent circuit using the iSWAP gate has a smaller TVD value than the equivalent circuit using the CZ gate.

[0132] Graph 75 is an example for the case of "t / T1 = 10 -3 ". Until the noise reaches "0.03", the equivalent circuit using the CZ gate has a smaller TVD value than the equivalent circuit using the iSWAP gate. When the noise is "0.03" or more, the equivalent circuit using the iSWAP gate has a smaller TVD value than the equivalent circuit using the CZ gate.

[0133] Graph 76 is an example for the case of "t / T1 = 5×10 -3 ". In this case, the equivalent circuit using the CZ gate always has a smaller TVD value than the equivalent circuit using the iSWAP gate.

[0134] Thus, when the value of "t / T1" exceeds "10 -4 ", the equivalent circuit using the CZ gate may be less affected by noise. On the contrary, if the value of "t / T1" is "10 -4 " or less, the equivalent circuit using the iSWAP gate can be less affected by noise. In this case, for example, the threshold of "t / T1" when determining the equivalent circuit is set to "10 -4 ". That is, if "t / T1 < 10 -4 ", the gate conversion unit 150 converts the CCX or CCZ gate into an equivalent circuit using the iSWAP gate. Also, if "t / T1 ≥ 10 -4 ", the gate conversion unit 150 converts the CCX or CCZ gate into an equivalent circuit using the CZ gate.

[0135] As described above, the control computer 100 converts the CCX gate or CCZ gate into an equivalent circuit with less noise influence among the equivalent circuit using the iSWAP gate or the equivalent circuit using the CZ gate, and implements the quantum circuit on the quantum bit control device 200. Thereby, the influence of noise can be reduced and the accuracy of quantum calculation can be improved.

[0136] Moreover, by using a group of qubits with the lowest average fidelity as the qubits used in the quantum circuit, the accuracy of quantum computing can be further improved. Note that the fidelity and T1 of each qubit are measured periodically. As a result, based on the fidelity and T1 in the latest state when performing quantum computing, it is possible to determine the qubits to be used and implement the quantum circuit, and it becomes possible to stably perform high-precision quantum computing. That is, the fidelity or T1 of the qubit is not constant and changes depending on the environment in which the quantum computer 300 is placed and the passage of time. Therefore, by periodically measuring the fidelity or T1, the accuracy of the fidelity or T1 at the time of performing quantum computing is improved.

[0137] Furthermore, by using the value of t / T1 as an index for determining the influence of noise for each equivalent circuit, it is possible to correctly determine an equivalent circuit with less influence of noise. As a result, quantum computing can be performed with less noise, and the accuracy of quantum computing is improved.

[0138] 〔Other Embodiments〕 The control computer 100 can convert the quantum gate into an appropriate equivalent circuit based on the relaxation time as long as the quantum gate can be converted into an equivalent circuit using a CX gate, not limited to the CCX gate and the CCZ gate. In addition, the control computer 100 can also convert the CX gates included in the quantum circuit acquired from the terminal devices 401, 402,... into an equivalent circuit using an iSWAP gate or an equivalent circuit using a CZ gate based on the relaxation time.

[0139] The above merely shows the principle of the present invention. Further, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and application examples shown and described above, and all corresponding modifications and equivalents are considered to be within the scope of the present invention by the appended claims and their equivalents.

Explanation of Reference Numerals

[0140] 1, 7 Quantum circuit 1a CCX Gate 1b, 3a CCZ Gate 2. Quantum bit characteristics information 3~6, 7a, 7b Equivalent circuit 4a CX Gate 5a, 5b iSWAP Gate 6a CZ Gate 8 qubit controller 8a, 8b,... qubit 10 Quantum circuit design equipment 11 Storage section 12 Processing section

Claims

1. Detect a first quantum gate that cannot perform a gate operation in the quantum device from a quantum circuit showing gate operations on a plurality of qubits included in the quantum device, Based on the relaxation time of the qubit to be operated on by the detected first quantum gate, determine an equivalent circuit to be implemented from a plurality of equivalent circuits that realize the same gate operation as the first quantum gate by a second quantum gate capable of performing a gate operation in the quantum device, Convert the first quantum gate in the quantum circuit into the determined equivalent circuit, A quantum circuit design program that causes a computer to execute the process.

2. In the process of determining the equivalent circuit, determine the equivalent circuit to be implemented based on the ratio of the gate operation time of the two-qubit gate in the quantum device to the relaxation time. The quantum circuit design program according to Claim 1.

3. In the process of determining the equivalent circuit, determine the equivalent circuit to be implemented based on the ratio of the gate operation time to the minimum value of the relaxation times of two or more qubits to be operated on by the first quantum gate. The quantum circuit design program according to Claim 2.

4. In the process of determining the equivalent circuit, if the value of the ratio is equal to or greater than a predetermined threshold, determine the equivalent circuit to be implemented as a first equivalent circuit using a CZ gate, and if the value of the ratio is less than the threshold, determine the equivalent circuit to be implemented as a second equivalent circuit using an iSWAP gate. The quantum circuit design program according to Claim 3.

5. The first quantum gate is a CCX gate or a CCZ gate. The quantum circuit design program according to Claim 1.

6. Periodically measure the relaxation time of each of the plurality of qubits included in the quantum device. The quantum circuit design program according to any one of Claims 1 to 5, which further causes the computer to execute the process.

7. Based on the fidelity of the plurality of qubits included in the quantum device, determine the qubits to be operated on in the quantum circuit. The quantum circuit design program according to any one of Claims 1 to 5, which further causes the computer to execute the process.

8. Detect a first quantum gate that cannot perform a gate operation in the quantum device from a quantum circuit showing gate operations on a plurality of qubits included in the quantum device, Based on the relaxation time of the quantum bit to be operated on by the detected first quantum gate, determine an equivalent circuit to be implemented from a plurality of equivalent circuits that realize the same gate operation as the first quantum gate by a second quantum gate capable of performing a gate operation in the quantum device, Convert the first quantum gate in the quantum circuit into the determined equivalent circuit, A quantum circuit design method executed by a computer.

9. A processing unit that detects a first quantum gate that cannot perform a gate operation in the quantum device from a quantum circuit indicating gate operations on a plurality of quantum bits included in the quantum device, and based on the relaxation time of the quantum bit to be operated on by the detected first quantum gate, determines an equivalent circuit to be implemented from a plurality of equivalent circuits that realize the same gate operation as the first quantum gate by a second quantum gate capable of performing a gate operation in the quantum device, and converts the first quantum gate in the quantum circuit into the determined equivalent circuit, A quantum circuit design apparatus having the same.

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