Light-emitting diode-type optoelectronic devices for color displays

Abstract

The present disclosure relates to an optoelectronic device (10) including first, second, and third three-dimensional light-emitting diodes having an axial configuration. Each light-emitting diode includes a semiconductor element (20, 22, 24) and an active region disposed on the semiconductor element. Each semiconductor element corresponds to a microwire, nanowire, pyramidal, or frustum-shaped element in the nanometer or micrometer range. The first, second, and third light-emitting diodes are configured to emit first, second, and third radiation at first, second, and third wavelengths, respectively. The semiconductor elements of the first, second, and third light-emitting diodes have first, second, and third diameters (D1, D2, D3), respectively. The first diameter (D1) is smaller than the second diameter (D2), which is smaller than the third diameter (D3), the first wavelength is larger than the third wavelength, and the second wavelength is larger than the first wavelength.

Description

Technical Field

[0001] The present invention generally relates to optoelectronic devices comprising nano-wire or micro-wire type three-dimensional semiconductor elements and methods for manufacturing the same, and more particularly to optoelectronic devices capable of displaying images, particularly display screens or image projection devices.

Background Art

[0002] Pixels of an image correspond to the unit elements of the image to be displayed or captured by an optoelectronic device. When displaying a color image, an optoelectronic device generally comprises at least three components, also called display sub-pixels, each of which emits light radiation of a substantially single color (e.g., red, green, blue), for displaying each pixel of the image. The superposition of the radiation emitted by the three display sub-pixels provides the observer with the sensation of the color corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for displaying a pixel of the image is called a display pixel of the optoelectronic device.

[0003] There are optoelectronic devices comprising III-V compound-based nano-wire or micro-wire type three-dimensional semiconductor elements, which can form so-called three-dimensional light-emitting diodes. The light-emitting diode comprises an active region, and most of the electromagnetic radiation supplied by the light-emitting diode is emitted from the active region of the light-emitting diode. The three-dimensional light-emitting diode may be formed in a so-called radial configuration, also called a core / shell configuration, in which the active region is formed at the outer peripheral portion of the three-dimensional semiconductor element. Further, the active region may be formed in a so-called axial configuration that does not cover the outer peripheral portion of the three-dimensional semiconductor element and basically extends along the longitudinal epitaxial growth axis.

[0004] The three-dimensional light-emitting diode in the axial configuration has a smaller light-emitting area than the light-emitting diode in the radial configuration, but is made of a semiconductor material with excellent crystallinity. Therefore, particularly because the stress at the interface between semiconductor layers is easily relaxed, it has the advantage of high internal quantum efficiency.

[0005] It is known to coat light-emitting diodes with photoluminescent materials that can convert the electromagnetic radiation emitted by the active region into electromagnetic radiation of a different wavelength, particularly higher wavelengths. However, such photoluminescent materials are expensive, have low conversion efficiency, and can degrade in performance over time.

[0006] It would therefore be desirable to be able to form an optoelectronic device comprising a light emitting diode configured to directly emit radiation of three different colors to obtain a color display without using a photoluminescent material.

[0007] Furthermore, industrial development of methods for manufacturing the active regions of axial-type three-dimensional light-emitting diodes based on III-V compounds has been a tedious task. While it is known to simultaneously fabricate light-emitting diodes emitting radiation of different colors using semiconductor elements of different diameters, the wavelength of the radiation emitted by the active region depends, inter alia, on the diameter of the semiconductor elements and the distance between them, and theoretically, the wavelength decreases with the diameter of the semiconductor elements. However, fabricating light-emitting diodes that emit blue light can be difficult, and light-emitting diodes correspond to semiconductor elements whose diameters are too small to be compatible with industrial-scale manufacturing methods. Summary of the Invention

[0008] It is therefore an object of embodiments to at least partially overcome the drawbacks of the above-mentioned optoelectronic devices comprising light-emitting diodes.

[0009] Another object of an embodiment is that the active region of each light emitting diode comprises a stack of layers of semiconductor materials based on III-V compounds.

[0010] Another object of an embodiment is for an optoelectronic device to comprise a light emitting diode configured to emit light radiation of three different colors without the use of photoluminescent materials.

[0011] It is another object of an embodiment that the optoelectronic device comprises light emitting diodes configured and fabricated simultaneously to emit light radiation of three different colors.

[0012] An embodiment provides an optoelectronic device comprising first, second, and third three-dimensional light emitting diodes having an axial configuration, each light emitting diode comprising a semiconductor element and an active region mounted on the semiconductor element, each semiconductor element corresponding to a microwire, a nanowire, a pyramidal element in the nanometer or micrometer range, or a frustum-shaped element in the nanometer or micrometer range, the first light emitting diode configured to emit first radiation at a first wavelength, the semiconductor element of the first light emitting diode having a first diameter, the second light emitting diode configured to emit second radiation at a second wavelength, the semiconductor element of the second light emitting diode having a second diameter, the third light emitting diode configured to emit third radiation at a third wavelength, the semiconductor element of the third light emitting diode having a third diameter, the first diameter being smaller than the second diameter and the second diameter being smaller than the third diameter, the first wavelength being larger than the third wavelength, and the second wavelength being larger than the first wavelength.

[0013] According to an embodiment, the first diameter varies in the range of 80 nm to 150 nm.

[0014] According to an embodiment, the second diameter varies in the range of 200 nm to 350 nm.

[0015] According to an embodiment, the third diameter varies in the range of 370 nm to 500 nm.

[0016] According to an embodiment, the first wavelength is in the range of 510 nm to 570 nm.

[0017] According to an embodiment, the second wavelength is in the range of 600 nm to 720 nm.

[0018] According to an embodiment, the third wavelength is in the range of 430 nm to 490 nm.

[0019] According to an embodiment, the device includes a first optoelectronic circuit bonded to a second electronic circuit, the second electronic circuit includes a conductive pad, the first optoelectronic circuit includes pixels, and for each pixel, - includes a first conductive layer; - for each of the first, second, and third light-emitting diodes, the semiconductor element extends perpendicular to the first conductive layer, contacts the first conductive layer, and has an active region placed at an end of the semiconductor element on the side opposite to the first conductive layer; - includes second, third, fourth, and fifth conductive layers electrically coupled to the conductive pad, the second conductive layer is coupled to the active region of the first light-emitting diode, the third conductive layer is coupled to the active region of the second light-emitting diode, the fourth conductive layer is coupled to the active region of the third light-emitting diode, and the fifth conductive layer is coupled to the first conductive layer.

[0020] According to an embodiment, each active region includes a single quantum well or a plurality of quantum wells.

[0021] According to an embodiment, the semiconductor element and the active region are made of a group III-V compound.

[0022] According to an embodiment, the semiconductor elements of the first, second, and third light-emitting diodes are formed by MOCVD.

[0023] According to an embodiment, the active regions of the first, second, and third light-emitting diodes are formed by MBE.

[0024] According to an embodiment, the semiconductor elements of the first, second, and third light-emitting diodes are placed on a substrate and are in contact with a material compatible with the epitaxial growth of the semiconductor elements of the first, second, and third light-emitting diodes.

[0025] According to an embodiment, the first, second, and third light-emitting diodes form a monolithic structure.

[0026] Also, an embodiment provides a method of manufacturing an optoelectronic device as defined above. The method includes the following consecutive steps: - Simultaneously forming semiconductor elements of the first, second, and third light-emitting diodes; and - Simultaneously forming active regions of the first, second, and third light-emitting diodes on the semiconductor elements of the first, second, and third light-emitting diodes. It includes.

[0027] According to an embodiment, the method includes the following consecutive steps: - While forming semiconductor elements of the first, second, and third light-emitting diodes on a support, simultaneously forming active regions of the first, second, and third light-emitting diodes on the semiconductor elements of the first, second, and third light-emitting diodes; - Forming an electrically insulating layer between the three-dimensional semiconductor elements of the first, second, and third light-emitting diodes; and - Removing the support. It includes.

Brief Description of Drawings

[0028] The above and other features and advantages are described in detail in the following specific embodiments given as non-limiting examples of the invention with reference to the accompanying drawings.

[0029] [Figure 1] It is a partial schematic cross-sectional view showing an embodiment of an optoelectronic device including micro-wires or nano-wires. [Figure 2] It is a detailed view of a part of FIG. 1. [Figure 3] It is a diagram showing a curve of the change of the central wavelength of the radiation emitted by an axial light-emitting diode according to the diameter of the light-emitting diode obtained by testing. [Figure 4] It is a chromaticity diagram showing the color region that can be obtained with the optoelectronic device of FIG. 1. [Figure 5] It is a diagram showing the curve of the change in light intensity according to the wavelength of the radiation emitted by the three light-emitting diodes of the optoelectronic device in FIG. 1 obtained by the test. [Figure 6] It is a partial schematic cross-sectional view explaining the operation of the optoelectronic device in FIG. 1. [Figure 7A] It is a diagram showing the steps of an embodiment of the manufacturing method of the optoelectronic device shown in FIG. 1. [Figure 7B] It is a diagram showing another step of this method. [Figure 7C] It is a diagram showing another step of this method. [Figure 7D] It is a diagram showing another step of this method. [Figure 7E] It is a diagram showing another step of this method. [Figure 7F] It is a diagram showing another step of this method. [Figure 7G] It is a diagram showing another step of this method. [Figure 7H] It is a diagram showing another step of this method. [Figure 7I] It is a diagram showing another step of this method. [Figure 7J] It is a diagram showing another step of this method. [Figure 7K] It is a diagram showing another step of this method. [Figure 7L] It is a diagram showing another step of this method. [Figure 7M] It is a diagram showing another step of this method. [Figure 7N] It is a diagram showing another step of this method.

Embodiments for Carrying Out the Invention

[0030] Like features are designated by like reference numerals in the various drawings. In particular, structural and / or functional features that are common among the various embodiments may have the same reference numeral and may have the same structural, dimensional, and material characteristics. For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, means for controlling the light-emitting diodes of optoelectronic devices are well known and will not be described.

[0031] In the following description, when referring to terms that modify absolute positions such as "front", "rear", "upper", "lower", "left", "right", etc., or terms that modify relative positions such as "above", "below", "upward", "downward", etc., or terms that modify directions such as "horizontal", "vertical", etc., it refers to the orientation of the drawing or the optoelectronic device used in the normal position.

[0032] Unless otherwise specified, when referring to two elements being connected, it means directly connected without intermediate elements other than conductors, and when referring to two elements being coupled, it means that these two elements may be connected or may be coupled via one or more other elements.

[0033] Unless otherwise specified, the terms "approximately," "about," "substantially," and "on the order of" mean within 10%, preferably within 5%. Furthermore, unless otherwise specified, the term "insulating" means "electrically insulating," and the term "conductive" means "electrically conductive." In the following description, the internal transmittance of a layer corresponds to the ratio of the intensity of radiation exiting the layer to the intensity of radiation entering the layer. The absorption of a layer is equal to the difference between 1 and the internal transmittance. In the following description, a layer is said to be transparent to radiation if the absorption of radiation passing through the layer is less than 60%. In the following description, a layer is said to be absorbing to radiation if the absorption of radiation in the layer is greater than 60%. When radiation exhibits a spectrum that is generally "bell"-shaped, e.g., Gaussian, and has a maximum, the wavelength of the radiation, or the central or dominant wavelength of the radiation, refers to the wavelength at which the spectrum reaches its maximum. In the following description, the refractive index of a material corresponds to the refractive index of the material for the wavelength range of radiation emitted by the optoelectronic device. Unless otherwise specified, the refractive index is considered to be substantially constant over the wavelength range of useful radiation, e.g., equal to the average of the refractive index over the wavelength range of radiation emitted by an optoelectronic device.

[0034] The present application particularly relates to optoelectronic devices comprising three-dimensional elements, for example, light-emitting diodes comprising microwires, nanowires, pyramidal elements in the nanometer or micrometer range, or frustum-shaped elements in the nanometer or micrometer range. In particular, the pyramidal or frustum-shaped elements may be conical or frustum-shaped elements, or may be pyramidal or frustum-shaped elements. In the following description, embodiments are described in particular for electronic devices comprising microwires or nanowires. However, such embodiments can also be implemented for three-dimensional elements other than microwires or nanowires, for example, pyramidal or frustum-shaped three-dimensional elements.

[0035] The terms "microwire," "nanowire," "pyramidal element," or "frustum-shaped element" refer to a three-dimensional structure having an elongated shape along a preferred direction, the three-dimensional structure having at least two dimensions, called minor dimensions, in the range of 5 nm to 2.5 μm, preferably 50 nm to 1 μm, more preferably 30 nm to 300 nm, and a third dimension, called major dimension, that is at least 1 time, preferably at least 5 times, the largest minor dimension, e.g., in the range of 1 μm to 5 μm.

[0036] In the following description, the term "wire" is used to refer to a "microwire" or a "nanowire". Preferably, in a plane perpendicular to the preferred direction of the wire, the median line of the wire passing through the centroid of the cross section is substantially straight and is hereinafter referred to as the "axis" of the wire. The diameter of a wire is defined here as a quantity related to the circumference of the wire at the level of the cross section. It may also be the diameter of a disk having the same plane as the cross section of the wire. The local diameter, hereinafter also referred to as diameter, is the diameter of the wire at a given height level along the axis of the wire. The mean diameter is the average, e.g., arithmetic mean, of the local diameters along the wire or a part thereof.

[0037] According to an embodiment, each axial light-emitting diode comprises a wire and an active region above the wire, as described above. The active region is the region from which most of the radiation provided by the light-emitting diode is emitted. The active region may comprise a confinement means. The active region may comprise a quantum well, two quantum wells, or multiple quantum wells, each quantum well being sandwiched between two barrier layers, with the quantum well having a bandgap energy smaller than the bandgap energy of the barrier layer. The active region may comprise one or more quantum wells made of a ternary compound comprising the group III and group V elements of the wire and an additional group III element. The length of the radiation emitted by the active region depends on the proportion of the additional group III element incorporated. For example, the wire may be made of GaN, and the quantum well(s) may be made of InGaN. Accordingly, the length of the radiation emitted by the active region depends on the proportion of In incorporated.

[0038] It is known that the proportion of the additional group III element varies with the diameter of the wire, but previous literature that addresses this variation describes an increase in the proportion of the additional group III element with the diameter of the wire, resulting in an increase in the wavelength of radiation emitted by an axial light emitting diode comprising such a wire.

[0039] The inventors have determined that first, second and third successive diameter ranges can be observed, and that as the diameter of the wire increases through the first diameter range, the wavelength of the radiation emitted by the light-emitting diode increases, as the diameter of the wire increases through the second diameter range, the wavelength of the radiation emitted by the light-emitting diode decreases, and as the diameter of the wire increases through the third diameter range, the wavelength of the radiation emitted by the light-emitting diode stagnates.

[0040] This result is advantageously achieved using wires formed by metalorganic chemical vapor deposition (MOCVD) and active regions formed by conventional molecular beam epitaxy (MBE).

[0041] The above-described method may be implemented to fabricate optoelectronic devices capable of displaying images, particularly display screens or image projection devices. In particular, the above-described method may be implemented to fabricate wires of different average diameters, such as a first wire having a small average diameter, a second wire having a medium average diameter, and a third wire having a large average diameter. The active regions formed in the first, second, and third wires emit radiation of different wavelengths. In particular, the first wire having a small average diameter emits radiation at a first central wavelength, the second wire having a medium average diameter emits radiation at a second central wavelength, and the third wire having a large average diameter emits radiation at a third central wavelength, the second wavelength being greater than the first wavelength and the third wavelength being smaller than the first wavelength. A color display screen can then be fabricated.

[0042] The formation of wires by MOCVD has the advantage of enabling the production of wires with fewer defects, and in particular, defect-free wires, compared to wires obtained by MBE. The formation of wires by MOCVD has the advantage of enabling the wires to be grown rapidly. Furthermore, wires with diameters that comply with the diameter-wavelength curves implemented in accordance with the present invention can be easily obtained. The MBE method has the advantage of enabling the incorporation of a larger proportion of additional group III elements into the quantum wells, compared to MOCVD.

[0043] Furthermore, the fact that the active region is formed only on top of the wires, and not on the sides of the wires, has the advantage of allowing the active region to be grown only on the c-plane or semipolar planes, rather than on the m-plane, which allows for a greater proportion of group III elements to be incorporated into the quantum wells compared to when the active region is grown on the m-plane.

[0044] FIG. 1 is a partial schematic cross-sectional view of a optoelectronic device 10 formed from a wire as described above and capable of emitting electromagnetic radiation. According to an embodiment, there is provided an optoelectronic device 10 comprising at least two integrated circuits 12 and 14, also called chips. The first integrated circuit 12 comprises a light-emitting diode. The second integrated circuit 14 comprises electronic components, particularly transistors, used for controlling the light-emitting diode of the first integrated circuit 12. The first integrated circuit 12 is bonded to the second integrated circuit, for example, by molecular bonding or by a "flip-chip" type of bonding, particularly the "flip-chip" method of balls or microtubes. The first integrated circuit 12 is referred to as an optoelectronic circuit or optoelectronic chip in the following description, and the second integrated circuit 14 is referred to as a control circuit or control chip in the following description.

[0045] Preferably, the optoelectronic chip 12 comprises only light-emitting diodes and connection elements for these light-emitting diodes, and the control chip 14 comprises all the electronic components necessary for controlling the light-emitting diodes of the optoelectronic chip. As a variant, the optoelectronic chip 12 may comprise other electronic components in addition to the light-emitting diodes.

[0046] In FIG. 1, in its left portion, elements of the optoelectronic chip 12 for a display pixel are shown, the structure of which is repeated for each display pixel, and in its right portion, elements adjacent to the display pixel and common to a plurality of display pixels are shown.

[0047] The optoelectronic chip 12 comprises the following elements from bottom to top in FIG. 1. - An electrical insulating layer 16: at least partially transparent to the electromagnetic radiation emitted by the light-emitting diode and defining a surface 17; - A conductive layer 18: at least partially transparent to the electromagnetic radiation emitted by the light-emitting diode; - first wires 20 (three first wires are shown) of diameter D1, second wires 22 (three second wires are shown) of diameter D2, and third wires 24 (three third wires are shown) of diameter D3: the first, second, and third wires 20, 22, 24 have axes parallel to each other and perpendicular to the surface 17, extend from and are in contact with the conductive layer 18, and the diameter D1 is smaller than the diameter D2, which is smaller than the diameter D3; first, second and third heads 26, 28, 30: a first head 26 is provided at the end of each first wire 20 opposite the conductive layer 18, a second head 28 is provided at the end of each second wire 22 opposite the conductive layer 18, and a third head 30 is provided at the end of each third wire 24 opposite the conductive layer 18; an electrical insulating layer 32 made of a first electrically insulating material between the wires 20, 22, 24, having a thickness substantially equal to the sum of the heights H of the wires 20, 22, 24 and the associated heads 26, 28, 30, measured along the axis of the wires; an electrically insulating layer 34 of a second electrically insulating material, which may be different from the first insulating material or identical to the first insulating material: it extends around the first insulating layer 32 and has the same thickness as the insulating layer 32; - opening 36: extending through the insulating layer 34 over the entire thickness of the insulating layer 34; - conductive layer 38: extending into opening 36 and in contact with conductive layer 18; - separate conductive layers 42, 44, 46, 48: conductive layer 42 contacts the first head 26, conductive layer 44 contacts the second head 28, conductive layer 46 contacts the third head 30, and conductive layer 48 contacts the conductive layer 38; an electrically insulating layer 50 covering the conductive layers 42, 44, 46, and 48 and extending between the conductive layers 42, 44, 46, and 48, and defining a surface 51 that is preferably substantially planar; and Conductive pads 52, 54, 56, 58: may have a multi-layer structure, extending through insulating layer 50 and flush with surface 51, with conductive pad 52 in contact with conductive layer 42, conductive pad 54 in contact with conductive layer 44, conductive pad 56 in contact with conductive layer 46, and conductive pad 58 in contact with conductive layer 48.

[0048] The control chip 14 particularly comprises, on one side of the optoelectronic chip 12, an electrically insulating layer 60 defining a preferably substantially planar surface 61, and a conductive pad 62 flush with the surface 61, the conductive pad 62 being electrically coupled to the conductive pads 52, 54, 56, 58. If the control chip 14 is bonded to the optoelectronic chip 12 by molecular bonding, the conductive pad 62 may be in contact with the conductive pads 52, 54, 56, 58. If the control chip 14 is bonded to the optoelectronic chip 12 by "flip-chip" type bonding, solder balls or microtubes may be interposed between the conductive pad 62 and the conductive pads 52, 54, 56, 58.

[0049] The assembly formed by each wire 20, 22, 24 and the associated head 26, 28, 30 forms an elementary light-emitting diode in the form of a wire in an axial configuration.

[0050] 2 is a partial schematic cross-sectional view showing a more detailed embodiment of light-emitting diode head 26. Heads 28 and 30 may have a similar structure.

[0051] The head 26 comprises, from bottom to top in FIG. a semiconductor layer 70 (possibly referred to as a semiconductor cap), made of the same material as the wire 20, doped with a first conductivity type, for example N-type, covering the upper end 72 of the wire 20 and having an upper surface 74; an active region 76 covering the surface 74 of the semiconductor layer 70; and Semiconductor stack 78 : covering the active area 76 and comprising at least one semiconductor layer 80 of opposite conductivity type to the wires 20 .

[0052] Each wire 20, 22, 24 and each semiconductor layer 70, 80 is at least partially formed from at least one semiconductor material. According to an embodiment, the semiconductor material is selected from the group consisting of III-V compounds, e.g., III-N compounds. Examples of III elements include gallium (Ga), indium (In), or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN, or AlInGaN. Other group V elements can also be used, such as phosphorus or arsenic. Generally, elements included in III-V compounds can be combined in different mole fractions. The semiconductor material of the wires 20, 22, 24 and / or the semiconductor layers 70, 80 may include a dopant, e.g., silicon to ensure N-type doping of the III-N compound, or magnesium to ensure P-type doping of the III-N compound.

[0053] The stack 78 may further include an electron blocking layer 82 between the active region 76 and the semiconductor layer 80, and a bonding layer 84 covering the semiconductor layer 80 on the side opposite the active region 76, the bonding layer 84 being covered by the conductive layer 42. The bonding layer 84 may be made of the same semiconductor material and may be of the same conductivity type as the semiconductor layer 80, but with a greater dopant concentration. The bonding layer 84 allows for an ohmic contact to be formed between the semiconductor layer 80 and the conductive layer 42.

[0054] The active region 76 is the region where most of the radiation supplied from the light-emitting diode is emitted. According to one example, the active region 76 may include confinement means. The active region 76 may include at least one quantum well including a layer of additional semiconductor material having a bandgap energy smaller than the bandgap energies of the semiconductor layer 70 and the semiconductor layer 80, preferably intervening between two barrier layers, thus improving the confinement of charge carriers. The additional semiconductor material may include III-V compounds of the doped semiconductor layers 70, 80, in which at least one additional element is incorporated. As an example, in the case of the wires 20, 22, 24 made of GaN, the additional material forming the quantum well is preferably InGaN. The active region 76 may be made of a single quantum well or multiple quantum wells.

[0055] According to a preferred embodiment, each wire 20, 22, 24 is made of GaN. The semiconductor layer 70 is made of GaN and may be doped with a first conductivity type, for example, N-type, particularly silicon. The height of the semiconductor layer 70 measured along the axis C may be in the range of 10 nm to 1 μm, for example, in the range of 20 nm to 200 nm. The active region 76 may include one or more quantum wells made of, for example, InGaN. The active region 76 may include a single quantum well extending between the semiconductor layers 70, 80. As a variant, the active region 76 may include a plurality of quantum wells. For example, a quantum well 86 made of InGaN and a barrier layer 88 made of, for example, GaN are alternately formed along the axis C. Three GaN layers 88 and two InGaN layers 86 are shown as an example in FIG. 2. The GaN layer 88 may be doped with, for example, N-type or P-type, or may be undoped. The thickness of the active region 76 measured along the axis C may be in the range of 2 nm to 100 nm. The semiconductor layer 80 is made of GaN and may be doped with a second conductivity type opposite to the first conductivity type, for example, P-type, particularly magnesium. The thickness of the semiconductor layer 80 may be in the range of 20 nm to 100 nm. When the electron blocking layer 82 is present, it may be made of GaN or a ternary III-N compound, such as AlGaN or AlInN, and is preferably doped with P-type. Thereby, the radiative recombination rate in the active region 76 can be improved. The thickness of the electron blocking layer 82 may be in the range of 10 nm to 50 nm. The electron blocking layer 82 may correspond to a superlattice of layers of InAlGaN or AlGaN and GaN, and each layer has a thickness of, for example, 2 nm.

[0056] Tests were conducted. In the tests, the wire 20 was made of GaN. The active region 76 includes seven quantum wells made of InGaN separated by GaN layers, respectively. The wire 20 was formed by MCVD, and the active region 76 was formed by MBE. The wavelength of the radiation emitted by the active region 76 and the diameter of the wire 20 were measured.

[0057] Figure 3 compiles the results of these tests. The vertical axis represents the central wavelength λ of the radiation emitted by the active region 76 in nanometers, and the horizontal axis represents the diameter D of the wire 20 in nanometers. The results of the first series of tests are shown in Figure 3 by open circles, and the results of the second series of tests are shown in Figure 3 by filled circles. The curve CT is the curve of variation of the wavelength λ as a function of the diameter D, obtained by cubic spline regression from the values obtained in the first and second tests. The horizontal lines R, G, and B correspond to the colors red, green, and blue, respectively.

[0058] For comparison, the black diamonds represent the results published in Kishino et al.'s paper, "Monolithic integration of four-color InGaN-based nanocolumn LEDs" (Elec Letters, May 28, 2015, Vol. 51, pages 852-854), and the hexagons containing crosses represent the results published in Mi et al.'s paper, "Tunable, Full-Color Nanowire Light-Emitting Diode Arrays Monolithically Integrated on Si and Sapphire" (Proc. of SPIE Vol. 9748+, 2016). The comparative results were obtained with GaN wires and active regions with a single InGaN quantum well. Furthermore, in both Mi et al.'s and Kishino et al.'s papers, the wires and active regions were formed by molecular beam epitaxy (MBE). It is observed that the wavelength of the emitted radiation increases as the wire diameter increases. It is known that increasing the indium fraction in the quantum well increases the wavelength of the radiation emitted by the active region. Therefore, this comparison suggests that the fraction of indium in a single quantum well increases as the wire diameter increases.

[0059] Formation of wires by MOCVD allows for the formation of wires with larger diameters than those achieved by conventional MBE, and therefore, after formation of the active region by MBE, it was unexpectedly observed that the change curve CT successively comprises a first rising portion C1, a second falling portion C2, and a third substantially constant portion C3, wherein in the first rising portion C1, the wavelength of the emitted radiation increases with the diameter of the wire, in the second falling portion C2, the wavelength of the emitted radiation decreases with the diameter of the wire, and in the third substantially constant portion C3, the wavelength of the emitted radiation varies little with the diameter of the wire.

[0060] According to an embodiment, the first increasing portion C1 is obtained for wire diameters varying in a first range P1 of about 50 nm to about 300 nm. The wavelength of the radiation emitted over the first increasing portion increases from about 510 nm to about 675 nm. According to an embodiment, the second decreasing portion C2 is obtained for wire diameters varying in a second range P2 of about 300 nm to about 375 nm. The wavelength of the radiation emitted over the second decreasing portion decreases from about 675 nm to about 475 nm. According to an embodiment, the third constant portion C3 is obtained for wire diameters in a third range P3 of about 375 nm to about 550 nm. The wavelength of the radiation emitted over the third constant portion varies between about 460 nm and 490 nm. As shown in FIG. 3 , blue-emitting light-emitting diodes may be formed with diameters in the third range P3, while green-emitting light-emitting diodes and red-emitting light-emitting diodes may be formed with diameters in the first range P1. Green light emitting diodes may be formed with diameters in the second range P2, but in practice the resulting wavelength variation depending on the diameter may be too large for industrial scale applications.

[0061] A display pixel is formed by forming a first light emitting diode with a wire 20 of small diameter D1, a second light emitting diode with a wire 22 of medium diameter D2, and a third light emitting diode with a wire 24 of large diameter D3.

[0062] Figure 4 is an XY chromaticity diagram showing the results of the first and second tests as black circles. By selecting light-emitting diodes corresponding to the circles DR, DG, and DB where the radiation is closest to the "vertices" of the chromaticity diagram to form display sub-pixels, it is possible to display, as an image pixel, the color obtained by the combination of the colors corresponding to the circles DR, DG, and DB. The circle DR has a diameter equal to about 200 nm to 250 nm. The circle DG has a diameter equal to about 100 nm to 150 nm. The circle DB has a diameter of about 370 nm or more. It can be seen that most of the chromaticity diagram can be reached.

[0063] Figure 5 shows curves C R , C G , and C B of the light intensity I (expressed in arbitrary units (a.u.)) according to the wavelength λ (expressed in nanometers (nm)) of the radiation emitted by each of the light-emitting diodes corresponding to the circles DR, DG, and DB in Figure 4. As shown in Figure 5, the spectra of the radiation of these light-emitting diodes are relatively narrow.

[0064] FIG. 6 illustrates a possible interpretation of the change in the curve CT of FIG. 3. FIG. 6 highly schematically illustrates three wires 20, 22, and 24 without showing the associated active region 76, semiconductor stack 78, and conductive layers 42, 44, and 46. The top of each wire 20, 22, and 24 may comprise a c-plane (surface 90 perpendicular to axis C) and / or a semi-polar plane (surface 92 tilted relative to axis C). The active region 76 is considered to overlie the c-plane and / or a semi-polar plane. The optical properties of the portion of the active region 76 overlie the c-plane are not the same as the optical properties of the portion of the active region 76 overlie the semi-polar plane. In particular, the maximum incorporation rate of the additional element into the portion of the active region 76 overlie the c-plane is greater than the maximum incorporation rate of the additional element into the portion of the active region 76 overlie the semi-polar plane. The interpretation of the change in the curve CT of FIG. 3 is as follows. That is, in the first diameter range P1, the contribution of the portion of the active region 76 mounted on the c-plane to the general radiation emitted by the active region 76 dominates over the portion of the active region 76 mounted on the semipolar plane. As a result, an increase in the wavelength of the general radiation with wire diameter can be observed. In the second diameter range P2, the importance of the contribution of the portion of the active region 76 mounted on the c-plane to the general radiation of the active region 76 reverses, and the central wavelength of the general radiation decreases as indium incorporation into the portion of the active region 76 mounted on the semipolar plane decreases. In the third diameter range P3, the contribution of the portion of the active region 76 mounted on the semipolar plane to the general radiation emitted by the active region 76 dominates over the portion of the active region 76 mounted on the c-plane, resulting in a plateau in the central wavelength of the emitted radiation.

[0065] Referring again to FIG. 1, according to an embodiment, each display pixel of the optoelectronic device 10 comprises at least three types of light-emitting diodes. According to an embodiment, a first type of light-emitting diode, e.g., comprising wire 20 and head 26, is adapted to emit a first radiation at a first center wavelength. A second type of light-emitting diode, e.g., comprising wire 22 and head 28, is adapted to emit a second radiation at a second center wavelength. A third type of light-emitting diode, e.g., comprising wire 24 and head 30, is adapted to emit a third radiation at a third center wavelength. The first, second, and third center wavelengths are different.

[0066] According to an embodiment, the first wavelength corresponds to green light and is in the range of 510 nm to 550 nm. According to an embodiment, the first diameter D1 varies in the range of 80 nm to 150 nm. According to an embodiment, the second wavelength corresponds to red light and is in the range of 600 nm to 720 nm. According to an embodiment, the second diameter D2 varies in the range of 200 nm to 350 nm. According to an embodiment, the third wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to an embodiment, the third diameter D3 varies in the range of 370 nm to 500 nm. As can be seen from FIG. 3, above a diameter equal to approximately 400 nm, the wavelength of the radiation emitted by the active region 76 is advantageously hardly affected by the diameter of the wire.

[0067] According to an embodiment, each display pixel Pix comprises a fourth type of light-emitting diode adapted to emit a fourth radiation at a fourth wavelength. The first, second, third, and fourth wavelengths may be different. According to an embodiment, the fourth wavelength corresponds to yellow light and lies in the range of 570 nm to 600 nm, or to cyan and lies in the range of 490 nm to 510 nm, or generally to any color other than the first, second, and third radiation.

[0068] According to an embodiment, for each display pixel, a basic light-emitting diode having wires of the same diameter has a common electrode, and when a voltage is applied between the conductive layer 18 and the conductive layer 42, 44, or 46, light emission is emitted by the active regions of these basic light-emitting diodes.

[0069] In this embodiment, the electromagnetic radiation emitted by each light-emitting diode escapes from the optoelectronic device 10 through the surface 17. Preferably, each of the conductive layers 42, 44, 46 is reflective, and has the advantage that it can increase the proportion of the radiation emitted by the light-emitting diode that escapes from the optoelectronic device 10 through the surface 17.

[0070] By laminating the optoelectronic chip 12 and the control chip 14, the lateral profile of the optoelectronic device 10 is reduced. According to an embodiment, the lateral dimension of the display pixel measured perpendicular to the axis of the wire is less than 5 μm, preferably less than 4 μm, for example, equal to about 3 μm. Further, the optoelectronic chip 12 may have the same dimensions as the control chip 14. Thereby, there is an advantage that the compactness of the optoelectronic device 10 can be improved.

[0071] The conductive layer 18 biases the active regions of the heads 26, 28, 30 and enables the passage of the electromagnetic radiation emitted by the light-emitting diode. The material forming the conductive layer 18 may be graphene or a transparent conductive oxide (TCO), particularly indium tin oxide (ITO), zinc oxide (doped or undoped with aluminum, gallium, or boron), or a transparent conductive material such as silver nanowires. As an example, the conductive layer 18 has a thickness in the range of 20 nm to 500 nm, preferably in the range of 20 nm to 100 nm.

[0072] The conductive layers 38, 42, 44, 46, 48, and conductive pads 52, 54, 56, 58 may be made of a metal (e.g., aluminum, silver, platinum, nickel, copper, gold, or ruthenium) or an alloy containing at least two of these compounds (e.g., a PdAgNiAu alloy or a PtAgNiAu alloy). The conductive layer 38 may have a thickness in the range of 100 nm to 3 μm. The conductive portions 42, 44, 46, 48 may have a thickness in the range of 100 nm to 2 μm. The smallest lateral dimension in a plane perpendicular to the surface 17 is in the range of 150 nm to 1 μm, e.g., about 0.25 μm. The conductive pads 52, 54, 56, 58 may have a thickness in the range of 0.5 μm to 2 μm.

[0073] Each of the insulating layers 16, 32, 34, 50 is made of a material selected from the group consisting of silicon oxide (SiO), silicon nitride (SixNy, where x is equal to about 3 and y is equal to about 4, e.g., Si3N4), silicon oxynitride (particularly of the general formula SiOxNy, e.g., Si2ON2), hafnium oxide (HfO2), titanium oxide (TiO2), or aluminum oxide (Al2O3). Layer 34 and / or layer 32 may further be made of an organic insulating material, for example, made of parylene or benzocyclobutene (BCB). Insulating layer 16 may have a maximum thickness in the range of 100 nm to 5 μm. Insulating layers 32 and 34 may have a maximum thickness in the range of 0.5 μm to 2 μm. Insulating layer 50 may have a maximum thickness in the range of 0.5 μm to 2 μm.

[0074] Each wire 20, 22, 24 may have an elongated semiconductor structure along an axis substantially perpendicular to the surface 17. Each wire 20, 22, 24 may have a generally cylindrical shape, and its cross section may have a different shape, such as an ellipse, a circle, or a polygon (especially a triangle, a rectangle, a square, or a hexagon). The axes of two adjacent wires 20, 22, 24 may be separated by 100 nm to 3 μm, preferably 200 nm to 1.5 μm. The height of each wire 20, 22, 24 may be in the range of 150 nm to 10 μm, preferably 200 nm to 1 μm, and more preferably 250 nm to 750 nm. The average diameter of each wire 20, 22, 24 may be in the range of 50 nm to 10 μm, preferably 100 nm to 2 μm, and more preferably 120 nm to 1 μm.

[0075] According to an embodiment, the wires 20, 22, and 24 are simultaneously formed by MOCVD from a seed layer. Growth conditions in the reactor are adapted to favor preferential growth of each wire 20, 22, and 24 along its axis C. This means that the growth rate of the wire along axis C is much greater, preferably at least an order of magnitude greater, than the growth rate of the wire along a direction perpendicular to axis C. In one example, the method may include injecting a precursor of a group III element and a precursor of a group V element into the reactor. Examples of precursors of group III elements include trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn), or trimethylaluminum (TMAl). Examples of precursors of group V elements include ammonia (NH), tributylphosphate (TBP), arsine (AsH), or dimethylhydrazine (UDMH). Some of the precursor gases may be generated using a water mixture and a carrier gas.

[0076] According to the embodiment, the temperature in the reactor is in the range of 900 °C to 1,065 °C, preferably in the range of 1,000 °C to 1,065 °C, and particularly 1,050 °C. According to the embodiment, the pressure in the reactor is in the range of 50 Torr (about 6.7 kPa) to 200 Torr (about 26.7 kPa), and particularly 100 Torr (about 13.3 kPa). According to the embodiment, the flow rate of the group III element precursor, for example TEGa, is in the range of 500 sccm to 2,500 sccm, and particularly 1,155 sccm. According to the embodiment, the flow rate of the group V element precursor, for example NH3, is in the range of 65 sccm to 260 sccm, and particularly 130 sccm. According to the embodiment, the ratio of the flow rate of the group V element precursor gas injected into the reactor to the flow rate of the group III element precursor gas injected into the reactor (referred to as the V / III ratio) is in the range of 5 to 15. The carrier gas may contain N2 and H2. According to the embodiment, the proportion of hydrogen injected into the reactor is in the range of 3 wt% to 15 wt% with respect to the total mass of the carrier gas, and particularly 5 wt%. The growth rate of the obtained wire 34 is in the range of 1 μm / h to 15 μm / h, and may particularly be 5 μm / h.

[0077] A dopant precursor may be injected into the reactor. For example, when the dopant is Si, the precursor may be silane (SiH4). The flow rate of the precursor may be selected so as to target an average dopant concentration in the range of 5×10 18 to 5×10 19 atoms / cm 3 and particularly 10 19 atoms / cm 3 .

[0078] In another embodiment, the semiconductor layer 70, if present, is grown on each wire by MBE. According to the embodiment, for the MBE growth of the semiconductor layer 70, the temperature in the reactor is in the range of 800 °C to 900 °C. According to the embodiment, the pressure in the reactor is 3×10 -8 Torr (about 4×10 -3 mPa) to 5×10 -5Torr (approximately 6.7 mPa). According to an embodiment, the plasma is created with an RF power between 300 W and 600 W, for example 360 W. According to an embodiment, the temperature of the solid source of the group III element, for example Ga, is in the range of 800° C. to 1000° C., in particular 850° C. According to an embodiment, the flow rate of the precursor gas of the group V element, for example N2, is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm.

[0079] A precursor of the dopant may be injected into the reactor. For example, if the dopant is Si, the precursor may be silane (SiH4). The flow rate of the precursor is 5×10 18 From 2 x 10 19 atoms / cm 3 range, especially 10 19 atoms / cm 3 may be selected to target an average dopant concentration of

[0080] According to an embodiment, each layer of the active region 76 is grown by MBE. In an embodiment, the MOCVD and MBE steps are performed in different reactors. In an embodiment, the method may use solid / gas source precursors for the group III and group V elements for MBE. According to an embodiment, a solid source may be used when the group III element is Ga, and a gas or plasma precursor may be used when the group V element is N. According to an embodiment, a beam of activated nitrogen is provided by a DC plasma source. In this source, excited neutral nitrogen molecules are formed in a field-free region and accelerated toward the substrate by the pressure gradient of the vacuum chamber.

[0081] Formation of particular layers of the active region 76, particularly the quantum wells 86, may involve injecting solid / gas precursors of the additional elements into the reactor. According to embodiments, when the additional group III element is In, Ga, or Al, a solid source may be used. The incorporation rate of the additional elements into the active region 76 depends, among other things, on the lateral dimensions of the active region 76, the distance between the wires 20, 22, 24, and the height of the active region 76 relative to the support (with the wires 20, 22, 24 extending therefrom).

[0082] The dopant may be injected into the reactor. For example, if the dopant is made of Si, a solid source may be used. According to an embodiment, the temperature of the solid source of the dopant element is in the range of 1,000° C. to 1,200° C.

[0083] According to an embodiment, for the MBE growth of each barrier layer 88, the temperature in the reactor is in the range of 570° C. to 640° C., and in particular 620° C. According to an embodiment, the pressure in the reactor is 3×10 -8 Torr (approx. 4 × 10 -3 mPa) to 5 × 10 -5 Torr (approximately 6.7 mPa). According to an embodiment, the plasma is created with an RF power between 300 W and 600 W, for example 360 W. According to an embodiment, the temperature of the solid source of the group III element, for example Ga, is in the range of 850° C. to 950° C., in particular 895° C. According to an embodiment, the flow rate of the precursor gas of the group V element, for example N2, is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm.

[0084] According to an embodiment, for the MBE growth of each quantum well 86, the temperature in the reactor is in the range of 570° C. to 640° C., and in particular 620° C. According to an embodiment, the pressure in the reactor is 3×10 -8 Torr (approx. 4 × 10 -3 mPa) to 5 × 10 -5Torr (approximately 6.7 mPa). According to an embodiment, the plasma is created with an RF power between 300 W and 600 W, for example 360 W. According to an embodiment, the temperature of the solid source of the group III element, for example Ga, is in the range of 850°C to 950°C, in particular 895°C. According to an embodiment, the temperature of the solid source of the additional element, for example In, is in the range of 750°C to 900°C, in particular 790°C. According to an embodiment, the flow rate of the precursor gas of the group V element, for example N2, is in the range of 0.5 sccm to 5 sccm, in particular 1.5 sccm.

[0085] According to an embodiment, each layer of the semiconductor stack 78 is grown by MBE. According to an embodiment, the semiconductor layer 80 is grown with a substantially c-plane orientation. According to an embodiment, for the MBE growth of the electron blocking layer 82, the temperature in the reactor is in the range of 700° C. to 900° C., and in particular, 800° C. According to an embodiment, the pressure in the reactor is 3×10 -8 Torr (approx. 4 × 10 -3 mPa) to 5 × 10 -5 Torr (approximately 6.7 mPa). According to an embodiment, the plasma is generated with an RF power between 300 W and 600 W, for example, 360 W. According to an embodiment, the temperature of the solid source of the group III element, for example, Ga, is in the range of 850°C to 950°C, particularly 905°C. According to an embodiment, the temperature of the solid source of the additional element, for example, Al, is in the range of 1,000°C to 1,100°C, particularly 1,010°C. According to an embodiment, the flow rate of the precursor gas of the group V element, for example, N2, is in the range of 0.5 sccm to 5 sccm, particularly 1.5 sccm. A dopant may be injected into the reactor. For example, if the dopant is Mg, a solid source may be used. According to an embodiment, the temperature of the solid source of the dopant element is in the range of 150°C to 350°C, particularly 190°C.

[0086] 7A-7N are partial schematic cross-sectional views of structures obtained in successive steps of another embodiment of a method for manufacturing the optoelectronic device 10 shown in FIG.

[0087] FIG. 7A shows the structure obtained after the following steps: forming a support 100, which corresponds to a stack of, from bottom to top in FIG. 7A, a substrate 101, at least one nucleation layer, also called seed layer (two nucleation layers 102 and 103 are shown by way of example in FIG. 7A), an electrical insulating layer 104 and an electrical insulating layer 106 on the insulating layer 104, the insulating layers 104, 106 being made of different materials; - forming a first opening 108 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location of the first wire 20, the diameter of the first opening 108 substantially corresponding to the diameter of the first wire 20, forming a second opening 110 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location of the second wire 22, the diameter of the second opening 110 substantially corresponding to the diameter of the second wire 22, and forming a third opening 112 in the insulating layers 104 and 106 to expose a portion of the nucleation layer 103 at a desired location of the third wire 24, the diameter of the third opening 112 substantially corresponding to the diameter of the third wire 24; - simultaneously growing wires 20, 22, 24 by MOCVD from the nucleation layer 103 in the openings 108, 110, 112; The heads 26, 28, 30 are simultaneously grown by MBE on the wires 20, 22, 24, each head 26, 28, 30 comprising an active region 76 and a semiconductor layer stack 78.

[0088] Alternatively, the insulating layers 104, 106 may be replaced by a single insulating layer.

[0089] The substrate 101 may correspond to a monoblock structure or to a layer covering a support made of another material. The substrate 101 is preferably a semiconductor substrate (e.g., a substrate made of silicon, germanium, silicon carbide, III-V compounds such as GaN or GaAs), a ZnO substrate, or a conductive substrate (e.g., a substrate made of metal or metal alloy, in particular copper, titanium, molybdenum, nickel-based alloys, and steel). Preferably, the substrate 101 is a monocrystalline silicon substrate. Preferably, the semiconductor substrate is compatible with manufacturing methods practiced in microelectronics. The substrate 101 may also correspond to a multilayer structure of the silicon-on-insulator type, also called SOI. The substrate 101 may be heavily doped, lightly doped, or undoped.

[0090] The nucleation layers 102, 103 are made of a material that favors the growth of the wires 20, 22, 24. The material forming each nucleation layer 102, 103 may be a metal, a metal oxide, a nitride, carbide or boride of a transition metal from column IV, V or VI of the periodic table of the elements, or a combination of these compounds, and preferably is a nitride of a transition metal from column IV, V or VI of the periodic table of the elements, or a combination of these compounds. By way of example, each seed layer 102, 103 may be made of aluminum nitride (AlN), aluminum oxide (Al2O3), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), tantalum carbonitride (TaCN), magnesium nitride of the MgxNy type (where x is approximately equal to 3 and y is approximately equal to 2, e.g., magnesium nitride of the Mg3N2 type). Each nucleation layer 102, 103 has a thickness, for example, in the range of 1 nm to 100 nm, preferably in the range of 10 nm to 30 nm.

[0091] Each of the insulating layers 104 and 106 is made of a material selected from the group consisting of silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example, Si3N4), silicon oxynitride (especially the general formula SiOxNy, for example, Si2ON2), hafnium oxide (HfO2) or aluminum oxide (Al2O3). According to an embodiment, the insulating layer 104 is made of silicon oxide and the insulating layer 106 is made of silicon nitride. The thickness of each of the insulating layers 104 and 106 is in the range of 10 nm to 100 nm, preferably in the range of 20 nm to 60 nm, and particularly equal to about 40 nm.

[0092] The growth method of the wires 20, 22, 24 is the MOCVD method as described above. The height of each of the wires 20, 22, 24 at the end of the growth step may be in the range of 250 nm to 15 μm, preferably in the range of 500 nm to 5 μm, and more preferably in the range of 1 μm to 3 μm. The height of the first wire 20 is different from the height of the second wire 22 and the height of the third wire 24. The height of the wires 20, 22, 24 depends particularly on the diameter of the wires and the distance between the wires. According to an embodiment, the height of the first wire 20 is greater than the height of the second wire 22, and the height of the second wire 22 is greater than the height of the third wire 24.

[0093] Each of the seed layers 102, 103 and each of the insulating layers 104, 106 may be deposited, for example, by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0094] FIG. 7B shows a structure obtained after depositing a dielectric layer 113 on top of all the wires 20, 22, 24 and on top of the insulating layer 106 between the wires 20, 22, 24.

[0095] The dielectric layer 113 may be made of the same material as the insulating layer 106. According to an embodiment, the minimum thickness of layer 113 is greater than the sum of the heights of the smallest wires 20, 22, 24 and the heights of the associated heads 26, 28, 30. Preferably, the minimum thickness of layer 113 is greater than the sum of the heights of the largest wires 20, 22, 24 and the heights of the associated heads 26, 28, 30.

[0096] As an example, the thickness of the dielectric layer 113 is in the range from 250 nm to 15 μm, preferably in the range from 300 nm to 5 μm, and is, for example, equal to about 2 μm. The insulating layer 113 may be formed by the same method used to form the insulating layers 104, 106.

[0097] FIG. 7C shows a structure obtained after thinning and planarizing a part of the insulating layer 113 and the heads 26, 28, 30 to define a flat surface 114 at the height of the insulating layer 106 in the range, for example, from 150 nm to 10 μm. The etching is, for example, CMP (Chemical-Mechanical Planarization). The presence of the insulating layer 113 between the wires 20, 22, 24 enables the implementation of a CMP-type etching method, which is difficult or even impossible to implement when only the wires are present. After this step, all wire-head assemblies 20-26, 22-28, 24-30 have the same height. The etching of a part of the insulating layer 113 and the wires 20, 22, 24 may be carried out in a plurality of steps. As a variant, when the wire-head assemblies 20-26, 22-28, 24-30 have substantially the same height, the step of thinning and planarizing a part of the insulating layer 113 and the heads 26, 28, 30 may not be necessary.

[0098] 7D shows the resulting structure after the dielectric layer 113 has been completely removed to expose the insulating layer 106 and the wirehead assemblies 20-26, 22-28, 24-30. The insulating layer 106 can then act as an etch stop layer during etching of the dielectric layer 113. Removal of the dielectric layer 113 may be performed by wet etching. Alternatively, the dielectric layer 113 may only be partially etched, leaving a residual layer on the insulating layer 106.

[0099] FIG. 7E shows the structure obtained after the following steps: forming an insulating layer 32; forming the insulating layer 34; and The insulating layer 34 is etched or thinned over a portion of its thickness to define a substantially planar surface 116 .

[0100] The insulating layer 32 may be formed by conformal deposition, for example, by LPCVD. The method for forming the insulating layer 32 is preferably performed at a temperature below 700°C to avoid damaging the active region of the light-emitting diode. Furthermore, the LPCVD method can provide good filling between the wires 20, 22, and 24. The deposited thickness of the insulating layer 32 may be in the range of 100 nm to 1 μm, for example, approximately 500 nm. The insulating layer 34 may be formed by conformal deposition, for example, by PECVD. The deposited thickness of the insulating layer 34 may be 2 μm or more. Partial etching of the insulating layer 34 may be performed by CMP. The etching stop may be performed on the insulating layer 34 or the insulating layer 32, as shown in FIG. 7E, but in either case, it is performed before exposing the heads 26, 28, and 30.

[0101] FIG. 7F shows the resulting structure after etching the insulating layers 32 and 34 to expose the top surfaces of the heads 26, 28, and 30. The etching is, for example, reactive ion etching (RIE) or inductively coupled plasma etching (ICP). Since the heads 26, 28, and 30 may have different dimensions, some heads 26, 28, and 30 may be more exposed than others. The heads 26, 28, and 30 are not etched in this step. The etching is preferably anisotropic. Portions of layer 32 (not shown) may be retained on the sidewalls of the heads 26, 28, and 30. The layer located on top of the heads 26, 28, and 30 serves as an etch stop layer. According to an embodiment, an additional layer is added to the top of the heads 26, 28, and 30 during the formation of the heads 26, 28, and 30 to serve as an etch stop layer. This layer may be an AlN layer.

[0102] FIG. 7G shows the structure obtained after the following steps: - removing the etch stop layer, if present, on the heads 26, 28, 30; - depositing a metal layer, for example by cathode sputtering, having a thickness of for example 0.5 μm on the structure shown in FIG. 7E; and The metal layer is etched to define the conductive layers 42, 44, 46, 48.

[0103] If the etch stop layer on the heads 26, 28, 30 is made of AlN, it may be removed by etching with tetramethylammonium hydroxide (TMAH). Before forming the conductive layers 42, 44, 46, 48, isolated metal portions may be formed over the entire structure. This may be done by depositing a metal layer, for example nickel or platinum, with a thickness of 1 nm, followed by a thermal annealing step at a temperature of, for example, 550° C., resulting in the formation of isolated portions.

[0104] FIG. 7H shows the structure obtained after the following steps: depositing an insulating layer 50 on the structure shown in FIG. 7G; and -Form conductive pads 52, 54, 56, 58 made of, for example, copper.

[0105] FIG. 7I shows the structure obtained after bonding the control chip 14 to the optoelectronic chip 12. The bonding of the control chip 14 to the optoelectronic chip 12 may be performed by using an insert such as a connection microball not shown. As a modification, the bonding of the control chip 14 to the optoelectronic chip may be performed by direct bonding without using an insert. The direct bonding may include direct metal-to-metal bonding of the metal regions of the control chip 14, particularly the conductive pads 62, and the metal regions of the optoelectronic chip 12, particularly the conductive pads 52, 54, 56, 58, and dielectric-to-dielectric bonding of the dielectric regions of the control chip 14, particularly the insulating layer 50, and the dielectric regions of the optoelectronic chip 12, particularly the insulating layer 50. The bonding between the control chip 14 and the optoelectronic chip 12 may be performed by a thermocompression bonding method in which the optoelectronic chip 12 is pressed against the control chip 14 while applying pressure and heat.

[0106] FIG. 7J shows the structure obtained after the following steps: -Remove the substrate 101; -Remove the seed layers 102, 103; -Remove the insulating layers 104, 106; -Partially etch the insulating layer 32, the insulating layer 34, and the wires 20, 22, 24 to define a substantially planar surface 118.

[0107] The removal of the substrate 101 may be performed by grinding and / or wet etching. The removal of the seed layers 102, 103, the insulating layer 32, the insulating layer 34, and the wires 20, 22, 24 may be performed by wet etching, dry etching, or CMP. The insulating layer 104 or 106 can serve as an etch stop layer during the etching of the seed layer 103.

[0108] FIG. 7K shows a structure obtained after depositing a TCO layer having a thickness of, for example, 50 nm over the entire surface 118 and etching this layer by photolithography techniques to leave only the TCO layer 18, thereby forming the conductive layer 18 on the surface 118.

[0109] FIG. 7L shows a structure obtained after etching the opening 36 of the insulating layer 34 through the entire thickness of the insulating layer 34 to expose the conductive layer 48. This may be carried out by photolithography techniques.

[0110] FIG. 7M shows a structure obtained after forming a conductive layer 38 that contacts the conductive layer 18 within the opening 36 and on the surface 118. This may be performed, for example, by depositing a laminate of a conductive layer of the Ti / TiN / AlCu type over the entire structure on the surface 118 side and etching this laminate by photolithography techniques to leave only the conductive layer 38.

[0111] FIG. 7N shows a structure obtained after forming an insulating layer 16 that defines the surface 17 on the conductive layer 18. For example, it is a SiON layer deposited with a thickness of 1 μm by PECVD.

[0112] To increase the light extraction, an additional step of forming raised regions on the surface 17, also called a texturing step, may be provided.

[0113] The reduction in the height of the wire from the back surface may be carried out by a CMP type method as described above, or any other dry etching or wet etching method. In particular, the resulting height of the wire made of GaN may be selected to increase the light extraction from the base of the wire due to the optical interaction within the wire itself. Further, this height may be selected to be advantageous for the optical coupling between different wires and thus increase the collective emission of the wire assembly.

[0114] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and that other variations will occur to those skilled in the art. In particular, while in the above-described embodiments the optoelectronic device comprises two chips bonded together, it will be apparent that the optoelectronic device may comprise a single chip, with the electronic light-emitting diode control circuitry integrally formed with the light-emitting diode. Finally, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art based on the functional representations provided herein.

[0115] This patent application claims priority from French Patent Application No. 20 / 09895, which is incorporated herein by reference.

Claims

1. A optoelectronic device (10) comprising: first, second and third three-dimensional light-emitting diodes in an axial configuration, each light-emitting diode comprising a semiconductor element (20, 22, 24) and an active region (76) disposed on the semiconductor element, each semiconductor element corresponding to a microwire, nanowire, conical element in the nanometer or micrometer range, or frustoconical element in the nanometer or micrometer range, wherein the first light-emitting diode is configured to emit first radiation at a first wavelength, the semiconductor element of the first light-emitting diode having a first diameter (D1), the second light-emitting diode being configured to emit second radiation at a second wavelength, the semiconductor element of the second light-emitting diode having a second diameter (D2), the third light-emitting diode being configured to emit third radiation at a third wavelength, the semiconductor element of the third light-emitting diode having a third diameter (D3), the first diameter (D1) being smaller than the second diameter (D2), the second diameter (D2) being smaller than the third diameter (D3), the first wavelength being larger than the third wavelength, and the second wavelength being larger than the first wavelength.

2. The optoelectronic device according to claim 1, wherein the first diameter (D1) varies in the range of 80 nm to 150 nm.

3. The optoelectronic device according to claim 1 or 2, wherein the second diameter (D2) varies in the range of 200 nm to 350 nm.

4. The optoelectronic device according to any one of claims 1 to 3, wherein the third diameter (D3) varies in the range of 370 nm to 500 nm.

5. The optoelectronic device according to any one of claims 1 to 4, wherein the first wavelength is in the range of 510 nm to 570 nm.

6. The optoelectronic device according to any one of claims 1 to 5, wherein the second wavelength is in the range of 600 nm to 720 nm.

7. The optoelectronic device according to any one of claims 1 to 6, wherein the third wavelength is in the range of 430 nm to 490 nm.

8. Comprising a first optoelectronic circuit (12) bonded to a second electronic circuit (14), the second electronic circuit (14) comprising conductive pads (62), the first optoelectronic circuit comprising pixels, and for each pixel, - comprising a first conductive layer (18), - For each of the first, second, and third light-emitting diodes, the semiconductor elements (20, 22, 24) extend perpendicular to the first conductive layer and are in contact with the first conductive layer, and an active region (76) is placed at an end of the semiconductor element on the side opposite to the first conductive layer. - Comprising second, third, fourth, and fifth conductive layers (42, 44, 46, 48) electrically coupled to the conductive pad (62), wherein the second conductive layer (42) is coupled to the active region (76) of the first light-emitting diode, the third conductive layer (44) is coupled to the active region (76) of the second light-emitting diode, the fourth conductive layer (46) is coupled to the active region (76) of the third light-emitting diode, and the fifth conductive layer (48) is coupled to the first conductive layer. The optoelectronic device according to any one of claims 1 to 7.

9. The optoelectronic device according to any one of claims 1 to 8, wherein each active region (76) comprises a single quantum well or a plurality of quantum wells.

10. The optoelectronic device according to any one of claims 1 to 9, wherein the semiconductor elements (20, 22, 24) and the active region are made of III-V compounds.

11. The semiconductor elements (20, 22, 24) of the first, second, and third light-emitting diodes are placed on a substrate (100) and are in contact with a material suitable for epitaxial growth of the semiconductor elements (20, 22, 24) of the first, second, and third light-emitting diodes. The optoelectronic device according to any one of claims 1 to 10.

12. The optoelectronic device according to any one of claims 1 to 11, wherein the first, second, and third light-emitting diodes form a monolithic structure.

13. A method for manufacturing the optoelectronic device (10) according to any one of claims 1 to 12, comprising: The following consecutive steps: - Simultaneously forming the semiconductor elements (22, 24, 26) of the first, second, and third light-emitting diodes; - Simultaneously forming the active regions (76) of the first, second, and third light-emitting diodes on the semiconductor elements (22, 24, 26) of the first, second, and third light-emitting diodes. A method comprising the above steps.

14. The method according to claim 13, wherein the semiconductor elements (22, 24, 26) of the first, second, and third light-emitting diodes are formed by MOCVD.

15. The method according to claim 13 or 14, wherein the active regions (76) of the first, second and third light-emitting diodes are formed by MBE.

16. The following successive steps: - Forming the semiconductor elements (22, 24, 26) of the first, second and third light-emitting diodes on a support (110), and simultaneously forming the active regions (76) of the first, second and third light-emitting diodes on the semiconductor elements (22, 24, 26) of the first, second and third light-emitting diodes; - Forming an electrically insulating layer (32) between the three-dimensional semiconductor elements (20, 22, 24) of the first, second and third light-emitting diodes; - Removing the support The method according to any one of claims 13 to 15, comprising:

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