Semiconductor device and inverter equipped with the semiconductor device

Abstract

To provide a semiconductor device that achieves both of a low inductance and an equivalent inductance and an inverter having the semiconductor device.SOLUTION: In a semiconductor device and an inverter having the semiconductor device, an upper arm semiconductor element on a positive electrode wiring board and an AC wiring board are connected by a first wiring member, and a lower arm semiconductor element on the AC wiring board and a negative electrode wiring board are connected by a second wiring member. The AC wiring board includes: a first region where the first wiring member is connected; a second region where the lower arm semiconductor element is provided; and a connection region that connects the two regions. The connection region is positioned at a position opposite to positive electrode and negative electrode terminals with the region where the first and second wiring members are used intervening therebetween, and the positive electrode wiring board, the negative electrode wiring board, the first region, and the second region are arranged in this order.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an inverter including the semiconductor device.

Background Art

[0002] In order to improve the efficiency of an EV (Electric Vehicle) power train, an inverter using SiC (Silicon Carbide) that operates with lower loss than Si (Silicon) has been required.

[0003] Due to two characteristics of SiC, namely, high-speed switching and a small chip size, it is required to drive by mounting a large number of chips connected in parallel. At this time, since the wiring length becomes long by connecting many chips in parallel, there arises a problem that the drain / source peripheral inductance of the SiC chips increases and the loss increases. Furthermore, since current concentration also occurs due to variations in inductance, the structure of the inverter needs to have a low inductance in order to suppress the surge voltage during switching. Furthermore, in order to suppress current concentration during switching, equal inductance among a plurality of SiC chips is also required. In particular, in a single-sided direct-cooled type power module including a semiconductor device, wiring is performed using wire bonding and a pattern of a ceramic substrate, and it is necessary to use these to form an equal inductance structure for each SiC chip.

[0004] As the background art of the present invention, Patent Document 1 below discloses a configuration of an inverter in which inductance is reduced by laminating patterns of a positive electrode and a negative electrode in a three-phase inverter.

Prior Art Document

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the configuration of the prior art, the consideration of arranging a plurality of semiconductor chips in parallel with one arm is not taken into account. When the number of parallel chips is large (for example, 4 or more in parallel), the mounting area of the chips becomes large, resulting in a long wiring length. As a result, the wiring inductance increases, making it impossible to improve the switching speed and causing a problem of increased loss. Furthermore, since the wiring length for each chip is also different, there is a problem that it becomes difficult to achieve both low inductance and equal inductance.

[0007] Based on this, an object of the present invention is to provide a semiconductor device that achieves both low inductance and equal inductance, and an inverter equipped with the semiconductor device.

Means for Solving the Problems

[0008] A semiconductor device and an inverter including the semiconductor device include a positive wiring board provided with a positive terminal, a negative wiring board provided with a negative terminal, and an AC wiring board provided with an AC terminal on an insulating layer of a substrate included in the semiconductor device. The positive wiring board has a plurality of upper arm semiconductor elements electrically connected in parallel. The AC wiring board has a plurality of lower arm semiconductor elements electrically connected in parallel. The plurality of upper arm semiconductor elements and the AC wiring board are electrically connected to each other by a first wiring member. The plurality of lower arm semiconductor elements and the negative wiring board are electrically connected to each other by a second wiring member. The AC wiring board has a first region to which the first wiring member is connected, a second region in which the plurality of lower arm semiconductor elements are provided, and a connection region connecting the first region and the second region. The connection region has, between a region where the first wiring member connects the positive wiring board and the first region and a region where the second wiring member connects the negative wiring board and the second region, the positive terminal and the negative terminal provided at opposite positions. The positive wiring board, the negative wiring board, the first region, and the second region are arranged in the order of the positive wiring board, the negative wiring board, the first region, and the second region on the insulating layer.

Advantages of the Invention

[0009] Based on this, the present invention can provide a semiconductor device that achieves both low inductance and equal inductance, and an inverter including the semiconductor device.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and for the sake of clarity of explanation, appropriate omissions and simplifications have been made. The present invention can be implemented in various other forms. Unless otherwise particularly limited, each component may be singular or plural.

[0012] In the drawings, the positions, sizes, shapes, ranges, etc. of each component shown may not represent the actual positions, sizes, shapes, ranges, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.

[0013] (Overall configuration diagram of an embodiment of the present invention) (Figure 1) The basic configuration of the semiconductor device 104 will be described. The semiconductor device 104 has a positive electrode wiring board 1, a negative electrode wiring board 2, and an alternating current wiring board 3. The positive electrode wiring board 1, the negative electrode wiring board 2, and the alternating current wiring board 3 are arranged on an insulating layer 20 (Figure 1(b)) on a ceramic substrate included in the semiconductor device 104. On the substrate of this semiconductor device 104, a conductor layer 21 (Figure 1(b)) is integrally arranged so as to cover the positive electrode wiring board 1, the negative electrode wiring board 2, and the alternating current wiring board 3 with the insulating layer 20 in between. However, eddy currents flow through the conductor layer 21 so as to cancel out the magnetic flux generated by the currents flowing through the positive electrode wiring board 1, the negative electrode wiring board 2, and the alternating current wiring board 3 (the first region 3a and the second region 3b described later), thereby reducing the inductance of the positive electrode wiring board 1, the negative electrode wiring board 2, and the alternating current wiring board 3.

[0014] The positive electrode wiring board 1 has a positive electrode terminal 4 and a plurality of semiconductor elements 7a which are semiconductor chips. A plurality of semiconductor elements 7a are arranged in a row along the longitudinal direction on the positive electrode wiring board 1, thereby constituting the upper arm semiconductor element 23a of the semiconductor device 104. The negative electrode wiring board 2 has a negative electrode terminal 5. The AC wiring board 3 has a first region 3a, a second region 3b, and a connection region 6. The second region 3b has a plurality of semiconductor elements 7b which are semiconductor chips. A plurality of semiconductor elements 7b are arranged in a row in the longitudinal direction on the second region 3b of the AC wiring board 3, thereby constituting the semiconductor element 23b of the lower arm of the semiconductor device 104. An AC terminal 9 is arranged at the connection portion between the second region 3b and the connection region 6.

[0015] The first region 3a and the second region 3b are connected by the connection region 6. Thus, since the first region 3a and the second region 3b divide the AC wiring pattern by the connection region 6, the difference in inductance between the semiconductor elements 7a and 7b can be reduced.

[0016] A first wiring member 8a is wire-bonded to each of the semiconductor elements 7a. Each first wiring member 8a connects the positive electrode wiring board 1 and the first region 3a. A second wiring member 8b is wire-bonded to each of the semiconductor elements 7b. Each second wiring member 8b connects the negative electrode wiring board 2 and the second region 3b. Thereby, a plurality of semiconductor elements 7a and a plurality of semiconductor elements 7b are electrically connected in parallel, respectively.

[0017] Since the currents flowing through the first wiring member 8a and the second wiring member 8b which are source wirings are in opposite directions to each other, similar to the currents flowing through the positive electrode wiring board 1, the negative electrode wiring board 2, the first region 3a, and the second region 3b, the inductances of the first wiring member 8a and the second wiring member 8b can be reduced by canceling out the magnetic fluxes with each other. Also, the first wiring member 8a and the second wiring member 8b are arranged in an alternating parallel arrangement. The more the wires 8a and 8b cross the wiring board alternately in this way, the greater the canceling effect of the respective magnetic fluxes and the greater the effect of reducing the inductance.

[0018] (Figure 2) Current 10 flows to the right in positive wiring plate 1 and first region 3a, and current 10 flows to the left in negative wiring plate 2 and second region 3b. By alternately flowing current 10 on the wiring plate in this way, magnetic fluxes generated by adjacent currents can be canceled out, reducing mutual inductance (loop inductance) between the wiring plates. Furthermore, reducing inductance has the effect of reducing losses during switching, improving reliability.

[0019] (Figure 3) 1, the present invention is further described with reference to the configuration in which the lengths of wires 8a and 8b are not uniform but are varied. For example, the length of wire 8a is made longer the closer it is to AC terminal 9, which is the terminal on the emitter side (source side in the case of a MOS-FET) of semiconductor element 7a (the further it is from AC terminal 9, the shorter it is).

[0020] This is because the magnitude of the emitter (source) inductance of each semiconductor element 7a in the semiconductor device 104 is the sum of the inductance between the connected wire 8a and the first region 3a and the inductance between the second region 3b and the semiconductor element 7b. That is, since the inductance of the first region 3a increases as each semiconductor element 7a is closer to the positive terminal 4, the wires 8a are made shorter as they get closer to the positive terminal 4, thereby reducing the inductance of the wires 8a, and the sum of these inductances is equalized between each semiconductor element 7a.

[0021] Similarly, for the emitter (source) inductance of the semiconductor element 7b on the second region 3b, the length of the wire bonding 8b is made longer the closer it is to the negative terminal 5, which is the terminal on the emitter (source) side of the semiconductor element 7b (the further it is from the negative terminal 5, the shorter it is).

[0022] By doing so, the source inductance can be adjusted, and the difference in source inductance between each semiconductor element can be reduced. As a result, the current variation between each semiconductor element during switching becomes smaller, and inductance matching with the source pattern on the substrate can be achieved. Furthermore, current concentration can be suppressed, and low inductance due to the current flow in the substrate pattern can be achieved.

[0023] The AC wiring board 3 has a first region 3a and a second region 3b, and further has a connection region 6. This connection region 6 is provided at positions opposite to each other between the positive terminal 4 and the negative terminal 5 with the region where the wires 8a and 8b connect the wiring boards in between. Also, on the substrate of the semiconductor device 104, the positive wiring board 1, the negative wiring board 2, and the AC wiring board 3 are arranged side by side in this order. Thereby, the mutual inductance between the wiring boards is reduced, and the inductance of the wiring boards is reduced.

[0024] (Fig. 4) The three-phase semiconductor devices 104 are arranged in parallel along the short side direction (the left-right direction in Fig. 4) of each semiconductor device 104. Also, the DC voltage input terminal 109 (the high-voltage side input wiring 106 and the low-voltage side input wiring 107) and the semiconductor device 104 are connected via a smoothing capacitor 102 composed of film capacitors 111 arranged in parallel along the direction in which the three-phase semiconductor devices 104 are arranged. Also, the semiconductor device 104 is connected to the motor output terminal 110.

[0025] (Fig. 5) The three-phase inverter circuit 101 included in the inverter 300 is connected in parallel with the battery 100 and the smoothing capacitor 102, and DC power is supplied from the battery 100. The DC power is smoothed by the smoothing capacitor 102 connected in parallel. The smoothed DC power is converted into AC power by the semiconductor device 104 and output to the motor 200.

[0026] The three-phase inverter circuit 101 has a three-phase one-leg inverter 108 that combines the semiconductor device 104 and the control circuit 103, and outputs three-phase alternating current to the motor 200 by switching the ON / OFF of the switching respectively. Note that only one phase is shown in Fig. 5, and the illustration of the other two phases is omitted.

[0027] The currents flowing through the upper arm element 23a and the lower arm element 23b of the semiconductor device 104 are switched between ON and OFF of the aforementioned switching by the control signal output from the control circuit 103. The control signals output from the control circuit 103 are respectively input to the upper arm element 23a and the lower arm element 23b via the gate resistor 105 through the signal wiring.

[0028] The three-phase semiconductor devices 104 are respectively connected in parallel to the high-voltage side input wiring 106 and the low-voltage side input wiring 107. Also, the three-phase inverter circuit 101 is connected to the three-phase stator windings 200a of the motor 200 at the intermediate points respectively connected in series with the upper arm semiconductor element 23a and the lower arm semiconductor element 23b.

[0029] The three-phase semiconductor devices 104 are connected in parallel to the high-voltage side input wiring 106 and the low-voltage side input wiring 107, and further, by including the signal wiring of the semiconductor device 104, a signal wiring board (not shown), and the control circuit 103, each of the upper arm semiconductor element 23a and the lower arm semiconductor element 23b is controlled by the signal input from the control circuit 103 via the signal wiring, and functions as a three-phase inverter circuit 101 which is an electric circuit device. Furthermore, the motor output terminal 110 (Fig. 4) is connected to the three-phase stator windings 200a of the motor 200, smoothing capacitors 102 are connected to the high-voltage side input wiring 106 and the low-voltage side input wiring 107, and a battery 100 is connected to the DC voltage input terminal 109 (Fig. 4), whereby an inverter that converts DC power into AC power functions.

[0030] (Fig. 6) The inverter 300 is housed in the inverter case 201 together with a motor control board, an EMC filter, and a gate drive board (not shown respectively). The battery 100 (Fig. 5) outside the inverter 300 and the inverter power connector 202 are connected by a harness, so that the battery is connected to the DC voltage input terminal 109 and DC power is input to the inverter 300.

[0031] Also, a cable for transmitting signals for information exchange between the inverter 300 and the vehicle equipped with the motor 200 and for controlling the inverter 300 is connected to the inverter signal connector 203 to control the inverter 300 and exchange information with the vehicle. The inverter case 201 is connected to the motor case 204, and the motor output terminal of the inverter 300 and the three-phase AC wiring of the motor 200 are connected by an AC wiring cable (not shown). Although not shown, the present invention assumes a single-sided cooled inverter.

[0032] As described above, by using the low-inductance three-phase inverter circuit 101 to which the present invention is applied, the magnitude of the surge voltage generated during switching is suppressed, the switching speed is improved, and thereby the switching loss is reduced, so that the system efficiency of the inverter 300 is improved and the reliability is improved. Also, not only can the lengths of the wires 8a and 8b be changed so that they are closer to the connection region 6 or the negative terminal 5, but also by arranging them to alternately connect the wiring boards, both low inductance and equal inductance can be achieved.

[0033] According to one embodiment of the present invention described above, the following operational effects are obtained.

[0034] (1) The semiconductor device 104 is provided in the inverter 300, and includes a positive wiring board 1 provided with a positive electrode terminal 4, a negative wiring board 2 provided with a negative electrode terminal 5, and an AC wiring board 3 provided with an AC terminal 9 on an insulating layer 20 of a substrate included in the semiconductor device 104. The positive wiring board 1 has a plurality of upper arm semiconductor elements 7a connected electrically in parallel, and the AC wiring board 3 has a plurality of lower arm semiconductor elements 7b connected electrically in parallel. The plurality of upper arm semiconductor elements 7a and the AC wiring board 3 are electrically connected to each other by a first wiring member 8a, and the plurality of lower arm semiconductor elements 7b and the negative wiring board 2 are electrically connected to each other by a second wiring member 8b. The AC wiring board 3 has a first region 3a to which the first wiring member 8a is connected, a second region 3b in which the plurality of lower arm semiconductor elements 7b are provided, and a connection region 6 connecting the first region 3a and the second region 3b. The connection region 6 is provided at a position opposite to the positive electrode terminal 4 and the negative electrode terminal 5 with a region where the first wiring member 8a connects the positive wiring board 1 and the first region 3a and a region where the second wiring member 8b connects the negative wiring board 2 and the second region 3b in between. The positive wiring board 1, the negative wiring board 2, the first region 3a, and the second region 3b are arranged in the order of the positive wiring board 1, the negative wiring board 2, the first region 3a, and the second region 3b in the arrangement order on the insulating layer 20. By doing so, a semiconductor device 104 that achieves both low inductance and equal inductance can be provided.

[0035] (2) The first wiring member 8a and the second wiring member 8b are arranged alternately. By doing so, the effect of reducing the inductance of the semiconductor device 104 is enhanced.

[0036] (3) The first wiring member 8a is longer the closer it is to the connection region 6, and the second wiring member 8b is longer the closer it is to the negative electrode terminal 5. By doing so, the total inductance is equalized among the semiconductor elements 7a and 7b.

[0037] (4) The inverter 300 includes semiconductor devices 104, which are arranged parallel to the short dimension direction of the semiconductor devices 104 and connected to the DC voltage input terminal 109 via the smoothing capacitor elements 102. This configuration suppresses the magnitude of surge voltages generated during switching, improves the switching speed, and thereby reduces switching losses, improving the system efficiency and reliability of the inverter 300.

[0038] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0039] 1 Positive wiring board 2 Negative wiring board 3 AC wiring board 3a 1st area 3b 2nd area 4 Positive terminal 5 Negative terminal 6 Connection Area 7a Semiconductor element (upper arm) 7b Semiconductor element (lower arm) 8a Wire (first wiring member) 8b Wire (second wiring member) 9 AC terminal 10 Current (direction) 20 insulating layer 21 Conductor layer 23a Upper arm semiconductor element 23b Lower arm semiconductor element 101 Three-phase inverter circuit 102 smoothing capacitor 103 Control circuit 104 Semiconductor devices 105 Gate Resistor 106 High voltage input wiring 107 Low voltage side input wiring 108 1-leg Inverter 109 DC Voltage Input Terminal 110 Motor Output Terminal 111 Film Capacitor 200 Motor 201 Inverter Case 202 Inverter Power Connector 203 Inverter Signal Connector 204 Motor Case 300 Inverter

Claims

1. A semiconductor device provided in an inverter, on an insulating layer of a substrate included in the semiconductor device, a positive wiring board provided with a positive terminal, a negative wiring board provided with a negative terminal, and an AC wiring board provided with an AC terminal, the positive wiring board having a plurality of upper arm semiconductor elements electrically connected in parallel, the AC wiring board having a plurality of lower arm semiconductor elements electrically connected in parallel, the plurality of upper arm semiconductor elements and the AC wiring board being electrically connected to each other by a first wiring member, the plurality of lower arm semiconductor elements and the negative wiring board being electrically connected to each other by a second wiring member, the AC wiring board having a first region to which the first wiring member is connected, a second region in which the plurality of lower arm semiconductor elements are provided, and a connection region connecting the first region and the second region, the connection region having, between a region where the first wiring member connects the positive wiring board and the first region and a region where the second wiring member connects the negative wiring board and the second region, the positive terminal and the negative terminal provided at opposite positions, the positive wiring board, the negative wiring board, the first region, and the second region being arranged in the order of the positive wiring board, the negative wiring board, the first region, and the second region in the arrangement order on the insulating layer semiconductor device.

2. The semiconductor device according to claim 1, wherein the first wiring member and the second wiring member are arranged alternately semiconductor device.

3. The semiconductor device according to claim 1, wherein the first wiring member is longer the closer it is to the connection region, and the second wiring member is longer the closer it is to the negative terminal semiconductor device.

4. An inverter comprising the semiconductor device according to any one of claims 1 to 3, wherein the semiconductor devices are arranged side by side in parallel with respect to the short side dimension direction of the semiconductor device and are connected to a DC voltage input terminal via smoothing capacitor elements inverter.

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