Data transfer technology for multiple devices on a shared bus

Abstract

To provide a method for improving efficiency of a memory controller and efficiency of data transfer between different memories, a memory system, and a non-temporal computer-readable medium.SOLUTION: In a method, a first memory device receives a chip select signal which validates a first memory device among a plurality of memory devices coupled to SPI through a serial peripheral interface (SPI), and the first memory device receives a command including a first address for instructing read-out operation executed by the first memory device through the SPI, on the basis of the chip select signal. The method also writes data from a first address in the first memory device into the SPI, and writes the data into a second memory device among the plurality of memory devices from the SPI, on the basis of at least the partially read-out operation.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] [Cross-reference] This patent application claims priority to U.S. Patent Application No. 14 / 928,988 (Zhang et al., invention title "Data Transfer Technology for Multiple Devices on a Shared Bus", filing date October 30, 2015). The U.S. Patent Application has been assigned to the assignee of this application and is hereby incorporated by reference in its entirety.

[0002] [Technical Field] The following generally relates to data transfer between devices, and more particularly to data transfer technology for multiple devices on a shared bus.

Background Art

[0003] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices have two states representing logic "1" or logic "0". In other systems, more than two states may be stored. To access the stored information, an electronic device can read or detect the stored state of the memory device. To store information, an electronic device can write or program a state to the memory device. In other systems, more than two states may be stored. To access the stored information, an electronic device can read or detect the stored state of the memory device. To store information, an electronic device can write or program a state to the memory device.

[0004] There are many types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, or others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as flash memory, can store data over a long period without an external power source. Volatile memory devices, such as DRAM, may lose their stored state over time if not periodically refreshed by an external power source. Certain aspects of volatile memory may offer performance advantages such as faster read or write speeds, while certain aspects of non-volatile memory may have advantages such as the ability to store data without periodic refreshing.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] When transferring data between devices, a memory controller may read data from a source device into a data storage section within the memory controller and then write that data from the data storage section within the memory controller to a target device. Further, in many cases, the memory controller may have different types of interfaces for each different storage device such as volatile and non-volatile memory. With such a design, the memory controller may be involved in all of them in order to facilitate data transfer. Therefore, it may be beneficial to provide a technology that enables improvement in the efficiency of the memory controller and the efficiency of data transfer between different electronic devices.

MEANS FOR SOLVING THE PROBLEMS

[0006] A method according to one aspect of the present invention includes setting an address in a target memory for storing data received in the target memory, and transmitting, to both a source memory and the target memory, a single command sequence for storing the data from the source memory in the target memory, at least partially based on setting the address in the target memory, the single command sequence instructing a first operation in the source memory and a second operation in the target memory.

[0007] An apparatus according to one aspect of the present invention includes a target address register, a memory array, and an operation instruction decoder that decodes a received instruction as a command for storing data available on a bus in the memory array, the data being stored in the memory array from an address indicated by the target address register, the received instruction including a read instruction for a second device and a source address in the second device for a read operation associated with the read instruction, the received instruction instructing a write operation to be executed in the apparatus according to the address in the target address register simultaneously with the read operation in the second device.

Brief Description of the Drawings

[0008] Embodiments of the present disclosure will be described with reference to the following figures.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0009] [DETAILED DESCRIPTION] Various embodiments of the present disclosure provide for direct data transfer between devices sharing a single bus with reduced involvement from a controller. In some embodiments, a controller such as a memory controller, a source memory device, and a target memory device may be coupled to a shared bus. In some embodiments, the shared bus may be a Serial Peripheral Interface (SPI) bus, although other types of buses may be used as well. In some examples, the controller may include a processor (e.g., a microprocessor) or may operate under the control of a processor. The controller is capable of identifying a source address in the source memory device for data to be transferred to the target memory device. The controller can identify a target address in the target memory device and initiate a direct data transfer from the source memory device to the target memory device via the bus. The controller may send a command for reading data to a first memory device, and this command may also be received by a second memory device. In response to the command, the source memory device may read data onto the bus, and the target memory device may read data from the bus and store this data from the target address (starting with the target address) without further commands from the controller. In some embodiments, the command for reading data from the first memory device may be a read command for the first memory device according to a protocol set or a command set, or may be a special program command for the second memory device for storing the data provided by the first memory device in the second memory device.

[0010] In one embodiment, the controller may provide an enable signal to the target memory device and write the target address to a target address register within the target memory device. The controller may then provide an enable signal to both the source memory device and the target memory device and, along with that, transmit a read command. The controller may provide a clock to the source memory device and the target memory device, and as long as this clock is provided, the source memory device may read data to the bus and the target memory device may read data from the bus. In this way, the controller, and / or the processor managing the controller, can reduce its involvement in data transfer simply by providing the source and target addresses, the read command, the enable, and the clock signals. This can improve system operation by freeing up resources for other processing tasks, and can also reduce the amount of internal memory, such as cache memory and buffer memory, required by the controller according to the technique where the controller actually receives the data transferred between the memory devices. Furthermore, this technique can reduce system power and processing time compared to other techniques for data transfer.

[0011] Regarding the embodiments of the present disclosure described above, with respect to an electronic system involving different devices that may have data transferred between the devices, the following will be further described. A specific example of a memory system that employs direct data transfer with reduced involvement of the memory controller will be described. These or other embodiments of the present disclosure will be further described with reference to device diagrams, system diagrams, and flowcharts regarding direct data transfer between devices using a shared bus, and will be further described with reference to those diagrams.

[0012] FIG. 1 shows a diagram of a system 100 that supports direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. System 100 includes a device 105, which can be or include a printed circuit board for connecting or physically supporting various components. Device 105 can include a processor 110, a BIOS component 115, peripheral components 120, an input / output control component 125, and a memory system 150. The components of device 105 can communicate electronically with each other via a device bus 130. In the exemplary system 100 of FIG. 1, the memory system 150 includes a memory controller 155, volatile memory 160, and non-volatile memory 165, and memories 160 and 165 can be coupled to the memory controller 155 by a shared bus 170.

[0013] Processor 110 can be configured to interface with the memory system 150 via the memory controller 155. In some cases, processor 110 may execute the functions of the memory controller 155, and in other cases, the memory controller 155 may be integrated into the processor 110. Processor 110 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of components of these types, and processor 110 can perform various functions described herein, including direct data transfer between devices using a shared bus. Processor 110 can be configured to execute computer-readable instructions stored in the memory system 150, for example, to cause device 105 to perform various functions or tasks.

[0014] The BIOS component 115 is a software component that includes a Basic Input / Output System (BIOS) operating as firmware, and can activate and operate various hardware components of the system 100. The BIOS component 115 can also manage the data flow between the processor 110 and various components (e.g., the peripheral component 120, the input / output controller 125, etc.). The BIOS component 115 may include a program or software stored in a read-only memory (ROM), a flash memory, or any other non-volatile memory.

[0015] The peripheral component 120 can be any input or output device integrated into the device 105, or an interface for such a device. An example thereof may include a disk controller, a sound controller, a graphic controller, an Ethernet controller, a modem, a USB controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) slot or an Accelerated Graphics Port (AGP) slot.

[0016] The input / output controller 125 can manage data communication between the processor 110 and the peripheral component 120, the input device 135, or the output device 140. The input / output controller 125 may manage peripheral devices not integrated into the device 105. In some cases, the input / output controller 125 can be a physical connection or port to an external peripheral device.

[0017] The input 135 can be a device or signal external to the device 105 that provides an input to the device 105 or its components. This may include a user interface or an interface between other devices or between other devices. In some cases, the input 135 can be a peripheral device that interfaces with the device 105 via the peripheral component 120, or can be managed by the input / output controller 125.

[0018] The output device 140 can be a device or signal external to the device 105 configured to receive output from either the device 105 or its components. An example of the output device 140 can include a display, an audio speaker, a printing device, another processor, or a printed circuit board, etc. In some cases, the output 140 may be a peripheral device that interfaces with the device 105 via the peripheral component 120, or may be managed by the input / output controller 125.

[0019] As described above, the memory system 150 may include a memory controller 155, a volatile memory 160, and a non-volatile memory 165, and these memories can be connected to the memory controller 155 by a shared bus 170. In one example, the shared bus 170 may be an SPI bus, and the memory controller 155 may use one SPI interface for accessing both the volatile memory 160 and the non-volatile memory 165. Various existing designs for the memory controller can use separate interfaces for the volatile memory and the non-volatile memory, and using the shared bus 170 with one interface can provide a more effective and less complex design.

[0020] The SPI buses of various examples may use a protocol that includes commands, addresses, and data all in one command sequence. Such a command sequence may be initiated by providing a chip enable signal or a chip select signal to a specific component (e.g., volatile memory 160 and / or non-volatile memory 165), and may be terminated by deselecting the chip enable signal or the chip secret signal described above. The commands of the SPI protocol may define the operations to be performed (e.g., memory read), and the addresses may identify the location where the data associated with the commands is to be placed or written. For example, the command may be a read command, and the address may be a source address indicating the starting memory location of the data read from volatile memory 160 or non-volatile memory 165. In various examples, following the commands of the SPI protocol, a dummy cycle may be provided between the provision of the address and the output of the data to enable a memory or other device to detect the data (e.g., detect the data stored at a specific location within a memory array) before the data is output. The techniques provided herein are described for systems using an SPI shared bus for several examples. However, the techniques may also be used in systems using other types of shared buses that may have a similar command sequence that may include all of the commands, addresses, and data as one identical chip select event.

[0021] Now, referring to FIG. 2, a more specific example of a system 200 that supports direct data transfer between devices using a shared bus according to various embodiments of the present disclosure will be described. System 200 may include a memory system 150-a, which is an example of the memory system 150 of FIG. 1. Memory system 150-a may include a memory controller 155-a, which is an example of the memory controller 155 of FIG. 1, coupled to a shared bus 170-a, which is an example of the shared bus 170 of FIG. 1. Also coupled to the shared bus 170-a are a volatile memory 160-a and a non-volatile memory 165-a, which are examples of the volatile memory 160 and the non-volatile memory 165 of FIG. 1, respectively.

[0022] The volatile memory 160-a may include a first operation instruction decoder 205, a first target address register 210, a volatile memory array 215, and a first chip enable 220. The volatile memory 160-a may be, for example, one integrated circuit or chip included in the memory system 150-a. In one example, the volatile memory 160-a may be a memory module consisting of a larger integrated circuit including components as described above. In other examples, the first operation instruction decoder 205, the first target address register 210, and the volatile memory array 215 may be discrete components (e.g., components mounted on a printed circuit board) included in one memory module, and the first chip enable 220 may be used to enable the above (and other) components of the memory module.

[0023] The first operation instruction decoder 205 may decode an instruction received via the shared bus 170-a and operate according to the decoded instruction. The first target address register 210 may be a register for the memory controller 155-a to provide a target address for data transferred to the volatile memory 160-a. The volatile memory array 215 may include an array of memory cells (e.g., a DRAM array or an SRAM array). The first target address register 210 is shown separately from the volatile memory array 215, but in one example, the first target address register 210 may be part of the volatile memory array 215. The first chip enable 220 may be an enable line that causes the volatile memory 160-a to execute an instruction and communicate with other components via the shared bus 170-a.

[0024] Similarly, the non-volatile memory 165-a may include a second operation instruction decoder 225, a second target address register 230, a non-volatile memory array 235, and a second chip enable 240. The non-volatile memory 165-a may be, for example, one integrated circuit or chip included in the memory system 150-a. In one example, the non-volatile memory 165-a may be a memory module consisting of a larger integrated circuit including components as described above. In other examples, the second operation instruction decoder 225, the second target address register 230, and the non-volatile memory array 235 may be discrete components (e.g., components mounted on a printed circuit board) included in one memory module, and the second chip enable 240 may be used to enable the above (and other) components of the memory module.

[0025] The second operation instruction decoder 225 can decode the instructions received via the shared bus 170-a and operate according to the decoded instructions. The second target address register 230 can be a register for the memory controller 155-a to provide the target address for the data transferred to the non-volatile memory 165-a. The non-volatile memory array 235 may include an array of non-volatile memory cells (e.g., an EEPROM array or a flash memory array). Although the second target address register 230 is shown separately from the non-volatile memory array 235, in some examples, the second target address register 230 may be part of the non-volatile memory array 235. The second chip enable 240 may be an enable line that causes the non-volatile memory 165-a to execute instructions and communicate with other components via the shared bus 170-a. Note that the example in FIG. 2 is for illustration and explanation purposes, and other examples may include other or additional components. For example, in this example, it is also possible to exchange the volatile memory 160-a and the non-volatile memory 165 with each other, or it is also possible to couple additional memory or interfaces that enable further communication between different devices on the shared bus 170-a to the shared bus 170-a.

[0026] In this example, the memory controller 155-a may include a memory manager 245 and a chip enable (CE) manager 255. The memory manager 245 may provide instructions, such as a command sequence according to the SPI protocol, to the volatile memory 160-a and the non-volatile memory 165-a. The memory controller 155-a may be coupled to other external components to provide data from the memory system 150-a to other components or to receive data stored in the memory system 150-a from other components. The CE manager 255 may be coupled to the first chip enable 220 of the volatile memory 160-a via a first chip enable line 246, and may also be coupled to the second chip enable 240 of the non-volatile memory 165-a via a second chip enable line 250. The memory controller 155-a may provide a clock 260 to the volatile memory 160-a and the non-volatile memory 165-a.

[0027] As described above, the shared bus 170-a according to various examples can be an SPI bus. Various embodiments of the present disclosure use the serial protocol of the SPI bus and provide an improved technique for data transfer between the memory controller 155-a, the volatile memory 160-a, and the non-volatile memory 165-a. Both the volatile memory 160-a and the non-volatile memory 165-a are servants of the memory controller 155-a, and they have individual chip enables 220 and 240 that can be separately accessed by the memory controller 155-a. In one example, data such as program instructions executed by a processor external to the memory system, for example, can be loaded from the non-volatile memory 165-a to the volatile memory 160-a. A load data process for such a transfer can discretely move data from the non-volatile memory 165-a to the volatile memory 160-a while limiting the involvement from the memory controller 155-a. Similarly, certain data from the volatile memory 160-a may need to be written to the non-volatile memory 165-a by a write-back data process that can directly move data from the volatile memory 160-a to the non-volatile memory 165-a while limiting the involvement from the memory controller 155-a. For clarity of explanation, such load data processes and write-back data processes have been described separately, but in one example, these operations may be combined.

[0028] For the data load process, the memory controller 155-a may, in some examples, determine the source address in the non-volatile memory 165-a for the data to be loaded into the volatile memory 160-a. The memory controller may also determine the target address for storing the data in the volatile memory 160-a. The memory controller 155-a may start the data load process by setting the target address in the first target address register 210 (e.g., by enabling the first chip enable 220, writing the target address to the first target address register 210, and then disabling the first chip enable 220). The memory controller 155-a may then transmit the command sequence received in both the volatile memory 160-a and the non-volatile memory 165-a via the shared bus 170-a. Such a command may, in some examples, be a read command established according to the SPI protocol and may also include a read command and a source address. As described above, existing techniques for moving data from the non-volatile memory 165-a to the volatile memory 160-a may include a read command that moves data starting from the source address to the data cache within the memory controller 155-a. However, according to the techniques described herein, both the non-volatile memory 165-a and the volatile memory 160-a receive the read command, verify the command sequence, and transfer the data directly without storing the data in the memory controller 155-a, i.e., without involving the memory controller 155-a in the actual data transfer.

[0029] In one example, the memory manager 245 provides chip enable signals to both the first chip enable 220 and the second chip enable 240 via the CE manager 255, enabling both the non-volatile memory 165-a and the volatile memory 160-a to acknowledge read commands. As described above, following the read command, a source address that may be ignored by the volatile memory may follow, and the memory controller 155-a may provide a clock to each of the non-volatile memory 165-a and the volatile memory 160-a. The non-volatile memory 165-a outputs data starting from the source address from the non-volatile memory array 235 according to the read command decoded by the second operation instruction decoder 225, and may continue to output data at consecutive memory locations from the source address as long as the clock 260 is continuously provided by the memory controller 155-a. The first operation instruction decoder 205 of the volatile memory 160-a receives and decodes the read command, ignores the source address, and may store the data provided to the shared bus 170-a by the non-volatile memory 165-a at the target address location in the volatile memory array 215. The reading of data and the corresponding storing of data continue during the duration (time duration) that the clock 260 is provided to the volatile memory 160-a and the non-volatile memory 165-a. In such a manner, the memory controller 155-a can directly move data from the non-volatile memory 165-a to the volatile memory 160-a while limiting the involvement of the memory controller 155-a and without storing the data in the cache or buffer of the memory controller 155-a. A similar operation may be used for the write-back operation from the non-volatile memory 165-a to the volatile memory 160-a, in which case the target address for the write-back data is stored in the second target address register 230, and a read command for reading data from the volatile memory 160-a to the shared bus 170-a is issued.

[0030] As described above, the techniques described for the various embodiments of the present disclosure include both the first operation instruction decoder 205 and the second operation instruction decoder 225 receiving commands from the memory controller 155-a. In the data load process, the non-volatile memory 165-a treats the instruction as a read operation, while the volatile memory 160-a may treat the same instruction as a write operation. Similarly, in the write-back process, the volatile memory 160-a treats the instruction as a read operation, while the non-volatile memory 165-a may treat the same instruction as a write operation. These instructions may be defined to match the timing requirements for both the volatile memory 160-a and the non-volatile memory 165-a. These instructions may also utilize existing non-volatile and volatile memory read commands defined in the SPI protocol, as long as such instructions are unique for each part. For example, if the "0Bh" instruction (an existing FAST read command in the SPI flash non-volatile memory) is not used for any SPI operation on the volatile memory side, this command may be defined as a write command on the volatile memory side. The first instruction decoder 205 can then understand the FAST read command, convert the command sequence into a write sequence using knowledge of the data output expected by the non-volatile memory 165-a, and latch the data provided on the shared bus 170-a at the correct clock and timing.

[0031] Furthermore, as described above, each of the volatile memory 160-a and the non-volatile memory 165-a may have a target address register. Since the source address is provided in the command sequence but the target address is not, such an address register can be used. For example, in the load data process, the command sequence includes the address that the non-volatile memory 165-a needs to send out, but it may not be the target address that the memory controller 155-a needs for the volatile memory 160-a. Therefore, before the automatic operation, the memory controller 155-a provides the volatile memory 160-a with the target address where the data from the non-volatile memory 165-a is to be loaded. Similarly, in the write-back process, the memory controller 155-a sets a second target address register 230 in the non-volatile memory 165-a so that the data from the volatile memory 160-a can be written back to the correct position. In some examples, a new command sequence including both the source address and the target address may be defined. However, by using the target address register, the modification to the existing protocol can be reduced, and improved flexibility can be provided. The operation for the data shadowing operation from the non-volatile memory 165-a to the volatile memory 160-a can be similarly described.

[0032] Figure 3 shows a timing diagram 300 of signals provided from a memory controller to a memory device that supports direct data transfer using a shared bus, according to various embodiments of the present disclosure. The signals of the timing diagram 300 can be provided, for example, by the memory controller 155 described above with respect to FIGS. 1 and 2. In the example of FIG. 3, a non-volatile memory chip enable signal 305 (CE#_NVM) can be provided to a non-volatile memory such as the non-volatile memory 165-a of FIGS. 1 or 2. A volatile memory chip enable signal 310 (CE#_RAM) can be provided to a volatile memory such as the volatile memory 160-a of FIGS. 1 or 2. A data signal 315 (DQ[x:0]) can be provided to a shared bus such as the shared bus 170 of FIGS. 1 or 2. A clock 320 can also be provided. The example of FIG. 3 shows operations for a write-back operation from a volatile memory to a non-volatile memory.

[0033] First, at time 325, the controller provides a low-level chip enable signal 305 to the non-volatile memory, thereby enabling the non-volatile memory to latch data from the data signal 315. In this example, the data signal 315 may provide an instruction for setting a target address along with the target address during a first period 335. Further, during this first period 335, the chip enable 310 is high, thereby keeping the volatile memory disabled and thus preventing it from receiving the above instruction. Following the above instruction, the chip enable signal 305 is deasserted high, and then, at time 330, both the chip enable signals 305 and 310 are set low, enabling both the non-volatile memory and the volatile memory. During a duration (time duration) 345, the clock 320 is similarly provided to both memories, whereupon the controller provides a read instruction for the data signal 315 on the shared bus, and this read instruction is received by both the non-volatile memory and the volatile memory. The non-volatile memory decodes the above instruction, recognizes the above instruction as a write-back instruction, ignores the source address provided in the above instruction, and then detects the data output to the bus from the volatile memory on the shared bus. The non-volatile memory stores the detected data from the location specified by the target address. The volatile memory also decodes the read instruction for the data signal 315 on the shared bus, decodes the source address from this instruction, starts detecting the data stored from the location of this source address, and outputs this data to the shared bus. As described above, the command sequence from the memory controller may include several dummy cycles that enable the volatile memory to detect its stored data, and both the volatile memory and the non-volatile memory are made to know the number of dummy cycles in order to provide the correct timing for data transfer. These operations continue during the duration 345. When the duration 345 ends at time 340, the memory controller may deselect both the chip enable signals 305 and 310 and stop providing the clock 320.

[0034] The above example described different memory components that can be coupled to a shared bus, but the techniques described herein may be used for direct data transfer between such devices by other devices provided in addition to the memory device. For example, such techniques may be used in embedded systems that may include, by way of several examples, sensors, secure digital cards, and liquid crystal displays. Such electronic devices may use techniques for data transfer as described herein with restricted involvement from a controller.

[0035] FIG. 4 shows a system 400 that supports direct data transfer between different types of devices using a shared bus, according to various embodiments of the present disclosure. System 400 may include a device 405, which may be or include a printed circuit board for connecting or physically supporting various components. Device 405 may include a controller 420, a first electronic device 425, a second electronic device 430, an input / output control component 435, and optionally one or more other components 440. These components of device 405 may communicate electronically with each other via a shared bus 445, which may be an example of the shared bus 170 of FIG. 1 or FIG. 2. In the exemplary system 400 of FIG. 4, the first electronic device 425 may include a first data storage area 450 and a chip enable / clock input 455. Similarly, the second electronic device 430 may include a second data storage area 460 and an associated chip enable / clock input 465.

[0036] The controller 420 may be configured to interface with the first electronic device 425, the second electronic device 430, the input / output control component 435, and / or other components 440 via a shared bus 445. The controller may, in some examples, initiate direct data transfer between devices in the manner described above. In some cases, the controller 420 may perform the functions of the memory controller 155 described previously with respect to FIGS. 1-3. The controller 420 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The controller 420 may perform various functions described herein, including direct data transfer between devices using the shared bus 445. The controller 420 may be configured to execute computer-readable instructions, for example, to cause the device 405 to perform various functions or tasks.

[0037] The input / output control component 435 manages data communication between the controller 420 and external components and can serve as a physical connection or port to the external components. The input 410 can be a device or signal external to the device 405 that provides an input to the device 405 or its components. This may include a user interface or an interface with or between other devices. In some cases, the input 410 may be a peripheral device that interfaces with the device 405 or may be managed by the input / output control component 435. The output device 415 can be a device or signal external to the device 405 that is configured to receive an output from either the device 405 or its components. Examples of the output device 415 can include a display, an audio speaker, a printing device, another processor, or a printed circuit board, etc. In some cases, the output 415 may be a peripheral device that interfaces with the device 405.

[0038] As described above, the controller 420 can cause one or more components of the device 405 to transfer data directly to one or more other components of the device 405. In one example, the controller 420 can provide a chip enable signal and a clock signal to a device that transfers data by the CE / clock component 460. In the example of FIG. 4, the first electronic device 425 can be a source device and the second electronic device 430 can be a target device. Thus, the data stored in the first data storage area 450 can be transferred via the shared bus 445 to the second data storage area 460 of the second electronic device. In this example, the first electronic device 425 includes a chip enable / clock input 455, and the second electronic device 430 can also include a chip enable / clock input 465. The controller can use the CE / Clock component 460 to select the first electronic device 425 and the second electronic device 430 to transmit a clock, and can also provide commands and addresses for starting and ending direct data transfer between the first electronic device 425 and the second electronic device 430 to the shared bus 445 in a manner similar to that discussed above with respect to FIGS. 1-3.

[0039] FIG. 5 shows an example of a flowchart 500 for direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. The flowchart 500 can illustrate an embodiment of direct data transfer between devices using a shared bus, and can be implemented in the device 105, the memory system 150, or the device 405 described above with respect to FIGS. 1-4.

[0040] In one example, a device such as memory controller 155 or controller 420 can identify a source address in source memory for data to be transferred to target memory, as shown in block 505. Such identification may be made by a memory manager such as memory manager 245, or as previously described with respect to FIGS. 1-4, may identify a starting address for data stored in a source device. For example, the source memory device may include program code for execution by a processor stored in non-volatile memory of the source device. The processor may identify the program code to be executed on this processor and provide this information to the memory manager. Subsequently, the memory manager may identify the source address to move the identified data from non-volatile memory to volatile memory, i.e., target memory, and in so doing, the processor can more easily access the source address for execution of the program code. In one example, the controller, source memory, and target memory may be coupled to the shared bus that can be used to transfer commands and data among devices on the shared bus.

[0041] At block 510, as previously described with respect to FIGS. 1-4, the device may send a target address to the target memory to initiate a direct data transfer from the source memory to the target memory. The device may identify, for example, the target address as the address where data from the source memory is to be stored in the target memory. For example, a memory controller may specify a region of volatile memory for storing program code executed by a processor, and use the starting address of this specified region as the target address. In one example, the controller may select chip enable in the target memory, provide a clock to the target memory, output a command to the shared bus to set the target address in the target address register of the target memory, and send the target address to the target memory by outputting the target address. The target memory may decode the command, latch data from the shared bus, and store this data in the target address register of the target memory. In one example, the source memory is non-volatile memory and the target memory is volatile memory, but many other examples may provide source and target memories that are data storage components of other types of memory or other types of devices (e.g., displays, sensors, cards, etc.).

[0042] At block 515, as previously described with respect to FIGS. 1-4, the device may send a read command to the source memory to read data from the source memory. This read command may include an instruction that data is to be read from the source memory, and may also include the starting address for the data to be read. In one example, the controller may send the read command by selecting chip enables in the source memory and the target memory, providing clocks to the source memory and the target memory, outputting a data output command to the shared bus, and outputting the source address. The source memory may decode the command (e.g., with an operation instruction decoder), latch data from the shared bus, and start transferring data starting from the source address to the shared bus. Further, when chip enables and clocks are provided to the source memory simultaneously with the provision of chip enables and clocks to the target memory, the target memory may decode the read command, recognize this read command as the start of data transfer, ignore the source address in the read command, and also start storing the data provided to the shared bus by the source memory.

[0043] At block 520, as previously described with respect to FIGS. 1-4, the source memory may transfer data directly from the source memory to the target memory. The source memory performs the transfer by providing data to the shared bus, and this data may be read from the shared bus by the target memory. The data may be stored in the target memory starting from a target address previously provided to the target memory (with the target address as the start). Such a transfer may continue, according to one example, as long as clocks are provided to the source memory and the target memory. Thus, a device such as a memory controller may determine the duration (time duration) of clock provision based on the amount of data read from the source memory and the speed at which data is read from the source memory or can be written to the target memory.

[0044] FIG. 6 shows an example of a flowchart for direct data transfer between devices using a shared bus according to various embodiments of the present disclosure. Flowchart 600 shows an embodiment of direct data transfer between devices using a shared bus, and as described above with reference to FIGS. 1-4, it may be implemented in device 105, memory system 150, or device 405.

[0045] In one example, a device such as memory controller 155 or controller 420 may provide chip enable and clock to the target device, as shown in block 605. Chip enable, i.e., chip select, and clock may prompt the target device to start reading one or more commands and / or data from the shared bus, as described above with respect to FIGS. 1-4. In one example, the shared bus may be an SPI bus as described above, or another type of bus having an associated protocol that provides commands within a command sequence and subsequent data.

[0046] At block 610, the device may set the address register in the target device, as described above with respect to FIGS. 1-4. The device may, for example, identify the target address as the address at which data from a source device (e.g., a source memory device) memory is to be stored in the target device (e.g., a target memory device), and set this target address in the address register. For example, a memory controller may specify a region of volatile memory for storing program code executed by a processor, and use the starting address of the specified region as the target address.

[0047] In block 615, the device can disable chip enable and clock to the target device, as described above with respect to FIGS. 1 - 4. For example, after providing a target address for storage in a target address register, the device can end the command sequence provided to the target device to set the address register by deselecting the target device (e.g., a target memory device).

[0048] In block 620, the device can provide chip enable and clock to the source device and the target device, as described above with respect to FIGS. 1 - 4. As described above, by providing chip enable and clock to each of the source device and the target device, both the source device and the target device will attempt to decode the command provided on the shared bus and any data following this command, and a new command sequence will be started for each of these devices.

[0049] In block 625, the device can send a read command to the source device, and this read command can also be received by the target device, as described above with respect to FIGS. 1 - 4. Since both the source device and the target device are enabled and clock is sent to both, the read command can be received by each device. In one example, the operation instruction decoder of each device may decode the read command, thereby indicating to the device that data is to be transferred between the source device and the target device.

[0050] At block 630, the device may provide chip enable and clock to the source device and the target device for a duration (time duration) corresponding to the amount of data to be transferred, similar to what was described above with respect to FIGS. 1 - 4. The source device and the target device thus perform a direct transfer of data, where the source device provides data to the shared bus and this data can be read from the shared bus by the target device. The data may be stored in the target device from the address provided to the address register at block 610. The duration (time duration) for providing clock and chip enable by the device (e.g., memory controller 155 or controller 420) may be based on the amount of data read from the source device and the rate at which data is read from the source device or the rate at which data can be written to the target device.

[0051] At block 635, the device may disable the chip enable and clock to the source device and the target device after the end of the duration, similar to what was described above with respect to FIGS. 1 - 4. After the above - mentioned duration, the device (memory controller 155 or controller 420) may determine that all data has been transferred and may deselect the first memory device and the second memory device.

[0052] FIG. 7 shows an example of a flowchart 700 for direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. Flowchart 700 shows an embodiment of direct data transfer between devices using a shared bus, and as described above with reference to FIGS. 1 - 4, it may be implemented in device 105, memory system 150, or device 405.

[0053] In one example, as shown in block 705 and as previously described with respect to FIGS. 1 - 4, a target device (e.g., non - volatile memory 165, volatile memory 160, or second electronic device 430) may receive a target address from a controller (e.g., memory controller 155 or controller 420). The controller, in one example, selects a chip enable associated with the device, provides a clock to the device, outputs a command for setting the target address in the target address register of the target device to the shared bus, and may send the target address by outputting the target address. According to various examples, the target device may decode the command, latch data from the shared bus, and store this data in the target address register.

[0054] At block 710, the target device may decode a read command sent from the controller to the source device, as previously described with respect to FIGS. 1 - 4. This read command may include an indication that data is to be read from the source device and may also include a starting address for the data to be read. The target device may decode this command (e.g., with an operation instruction decoder), latch data from the shared bus, and store this data starting from the target address.

[0055] At block 715, the target device may ignore the source address included in the command, as previously described with respect to FIGS. 1-4. As described above, the target device may cause its target address to be stored in the target address register, which may be different from the source address where data is stored in the source device. Thus, if the command includes a source address, the target device may simply ignore the information as being irrelevant to the target device. As described above, in other examples, the command sequence may include both a source address and a target address, in which case the operations of blocks 710 and 715 may be combined, and each of the source device and the target device may ignore the address related to the other device. For example, the command sequence may be in the form of <CMDcode|Add1|Add2>, where Add1 is the source address and Add2 is the target address. In such an example, the source device and the target device may be enabled by chip enable, and by decoding CMDcode, it may be possible to specify which device is the source device and which device is the target device (or such a specification may be made in advance).

[0056] At block 720, the target device may identify data from the source device available on the bus, as previously described with respect to FIGS. 1-4. The data available on the bus may be data transferred from the source device to the shared bus (by the controller sending a read command to the source device). In one example, the target device may wait for a predetermined number of clock cycles associated with providing the source address to the shared bus and a predetermined number of dummy cycles to provide sufficient time for the source device to detect the data stored at the source address, and then identify the subsequent information on the shared bus as data transferred from the source device.

[0057] At block 725, the target device can store data transferred from the source device to the bus from the target address (starting with the target address), in the same manner as previously described with respect to FIGS. 1-4. According to one example, such a transfer can then continue as long as a clock is provided to the source device and the target device. Thus, a device such as a memory controller may determine the duration (time duration) for which the clock is provided based on the amount of data read from the source device and the rate at which data is read from the source device or written to the target device.

[0058] Accordingly, methods 500, 600, and 700 can provide direct data transfer using a shared bus. Note that methods 500, 600, and 700 describe possible implementations, and the above operations and steps may be rearranged or modified to allow other implementations. In one example, aspects from two or more of methods 500, 600, and 700 may be combined.

[0059] A method will be described. In one example, the method may include, at a memory controller, identifying a source address in a source memory for data to be transferred to a target memory, where each of the memory controller, the source memory, and the target memory is coupled to one bus. In one example, the method may include, by the memory controller, sending a target address to the target memory to initiate a direct transfer of the data from the source memory to the target memory via the bus. In one example, the method may include sending a read command to the source memory to read data from the source memory to the bus.

[0060] In one example, this method may include transferring, by the source memory, data starting from the source address to the bus. In one example, the read command may be sent to the source memory via the bus. In one example, this method may include receiving, by the target memory via the bus, the read command. In one example, this method may include storing, in the target memory from the target address, subsequent data provided from the source memory to the bus.

[0061] In one example, the read command may include a data output instruction and the source address. In one example, this method may include recognizing the read command as the start of the transfer of the data. In one example, this method may include ignoring the source address. In one example, this method may include providing a chip enable signal to each of the source memory and the target memory. In one example, this method may include providing a clock to the source memory and the target memory during a time duration.

[0062] In one example, the time duration corresponds to the amount of data transferred from the source memory to the target memory. In one example, the bus may include a Serial Peripheral Interface (SPI) bus. In one example, the source memory may include one of a non-volatile memory or a volatile memory, and the target memory may include one of a non-volatile memory or a volatile memory.

[0063] A method will be described. In one example, this method may include setting a target address for storing data received in the target memory in the target memory via a bus coupled to the target memory and a source memory. In one example, this method may include transmitting, to each of the source memory and the target memory, a command for reading data from the source memory to the bus and storing the data from the bus in the target memory. In one example, setting the target address may include providing the target address to a target address register of the target memory. In one example, this method may include receiving the command in an operation instruction decoder of the target memory. In one example, this method may include, in the target memory, starting storage of the data from the bus from the target address following the command.

[0064] In one example, this method may include transferring, by the source memory, data starting from a source address to the bus. In one example, this method may include storing, by the target memory, the data from the bus. In one example, the command may include one command sequence received in each of the source memory and the target memory. In one example, this method may include providing a chip enable signal to each of the source memory and the target memory. In one example, this method may include providing a clock to the source memory and the target memory during a time duration.

[0065] In one example, the time duration corresponds to the amount of data transferred from the source memory to the target memory. In one example, the bus may include a Serial Peripheral Interface (SPI) bus. In one example, the source memory includes one of a non-volatile memory or a volatile memory, and the target memory may include one of a non-volatile memory or a volatile memory.

[0066] The apparatus will be described. In one example, the apparatus may include a first electronic device coupled to a bus, the first electronic device comprising a first data storage area. In one example, the apparatus may include a second electronic device coupled to the bus, the second electronic device comprising a second data storage area. In one example, the apparatus includes a controller coupled to the bus and in electronic communication with the first electronic device and the second electronic device, the controller may support means for identifying a source address in the first data area for data transferred from the first data storage area to the second data storage area. In one example, the controller may support means for identifying a target address in the second data storage area. In one example, the controller may support means for directly initiating the transfer of the data from the first electronic device to the second electronic device via the bus.

[0067] In one example, the second electronic device includes a target address register, and the controller may further support means for setting the target address for storage of the transferred data in the target address register. In one example, the second electronic device may include an operation instruction decoder operable to receive a read command from the controller to initiate the transfer of the data. In one example, the controller may include a single interface with the bus for accessing each of the first electronic device and the second electronic device.

[0068] In one example, the controller may support means for providing a chip enable signal to each of the first electronic device and the second electronic device. In one example, the controller may support means for providing a clock to each of the first electronic device and the second electronic device for a time duration corresponding to the amount of data transferred from the first data storage area to the second data storage area. In one example, the first electronic device may include one of a non-volatile memory or a volatile memory, and the second electronic device may include one of a non-volatile memory or a volatile memory.

[0069] An apparatus will be described. In one example, the apparatus may include a source memory module coupled to a bus. In one example, the apparatus may include a target memory module coupled to the bus. In one example, the apparatus includes a controller coupled to the bus and in electronic communication with the source memory module and the target memory module, the controller may support means for setting a target address in the target memory module for storage of data received at the target memory module via the bus. In one example, the controller may support means for transmitting a read command to the source memory module to read data from the source memory module to the bus. In one example, the target memory module is operable to receive directly via the bus the data read from the source memory module.

[0070] In one example, the target memory module includes a target address register, and the controller may support means for setting the target address for storage of the transferred data in the target address register. In one example, the target memory module may include an operation instruction decoder operable to receive the read command from the controller. In one example, the controller may support means for providing a chip enable signal to each of the source memory module and the target memory module. In one example, the controller may support means for providing a clock to each of the source memory module and the target memory module for a time duration corresponding to the amount of data transferred from the source memory module to the target memory module. In one example, the bus may include a Serial Peripheral Interface (SPI) bus.

[0071] What has been described herein provides an example and does not limit the scope, applicability, or examples described in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the above-described components may be changed. Various examples may appropriately omit, substitute, or add various procedures or components. Also, the features described with respect to one example may be combined in other examples.

[0072] What has been described in connection with the accompanying drawings herein describes exemplary configurations and does not show all examples that are implementable or within the scope of the claims. The terms "example" and "exemplary" as used herein mean "serving as an example or an embodiment" and do not mean "preferred" or "advantageous over other examples". The detailed description includes detailed specific examples to provide an understanding of the technology described herein. However, the technology of the present disclosure may be implemented without those detailed specific examples. In one example, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0073] In the accompanying drawings, like components or features may have the same reference numerals. Further, various components of the same type may be distinguished by attaching a dash and a second numeral to distinguish between like components after the reference numeral. When a first reference numeral is used in this specification, this description may apply to any of the like components having the same first reference numeral, regardless of the second reference numeral.

[0074] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, referred to throughout the previous description, may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Although a figure may show a signal as one signal, one of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus has various bit widths.

[0075] The term "electronic communication" represents a relationship between components that supports the flow of electrons between the components. This includes direct connections between components, or may include intermediate components between them. Components in electronic communication may (e.g., within an energized circuit) dynamically exchange electrons or signals, or may not (e.g., within a non-energized circuit), but are configured or operable to exchange electrons or signals in response to the circuit being energized. As an example, two components physically connected via a switch (e.g., a transistor) are in electronic communication regardless of the state of the switch (i.e., open or closed).

[0076] The devices discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or may be an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a partial region thereof can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0077] The various exemplary blocks, components, and modules described in connection with the disclosure herein can be implemented or executed using a general-purpose processor, DSP P, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but in lieu thereof, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors operating in conjunction with a DSP core, or any other similar configuration).

[0078] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein including in the claims, the "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list. For example, the list of at least one of A, B, or C means A, or B, or C, or A and B, or A and C, or B and C, or A and B and C (i.e., A and B and C).

[0079] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium including any medium that can transfer a computer program from one place to another. The non-transitory storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, the non-transitory computer-readable medium may include, but is not limited to, RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0080] Also, some connections are properly called computer-readable media. For example, when software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, high frequency, microwave, etc., the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, high frequency, microwave, etc. are included in the definition of the above media. As used herein, disk (disk and disc) includes CD, laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, and these disks usually reproduce data magnetically or optically with a laser. Combinations thereof may also be included within the scope of computer-readable media.

[0081] What is described herein is provided to enable a person of ordinary skill in the art to make or use the present disclosure. Various modifications to the present disclosure may be readily made by a person of ordinary skill in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Accordingly, the present disclosure should not be limited to the examples and designs described herein, but the broadest scope consistent with the principles described herein and novel features that do not conflict therewith should be recognized for the present disclosure.

Explanation of Reference Numerals

[0082] 100 System 105 Device 110 Processor 115 BIOS Component 120 Peripheral Component 125 Input / Output Control Component 135 Input 140 Output 150, 150-a Memory System 155, 155-a Memory Controller 160, 160-a Volatile Memory 165, 165-a Non-Volatile Memory 170, 170-a Shared Bus 200 System 205 First Operation Instruction Decoder 210 First Target Address Register 215 Volatile Memory Array 220 First Chip Enable 225 Second Operation Instruction Decoder 230 Second Target Address Register 235 Non-Volatile Memory Array 240 Second Chip Enable 245 Memory Manager 246 First Chip Enable Line 250 Second Chip Enable Line 255 CE Manager 260 Clock 400 System 405 Device 410 Input 415 Output 420 Controller 425 First Electronic Device 430 Second Electronic Device 435 Input / Output Control Component 440 Other Components 450 First Data Storage Area 455 Chip Enable / Clock Input 460 Second Data Storage Area 465 Chip Enable / Clock Input

Claims

**Claim 1** Receiving, at a first memory device, a first chip select signal that enables the first memory device, wherein the first memory device is one of a plurality of memory devices coupled to a Serial Peripheral Interface (SPI) bus; receiving, at a second memory device of the plurality of memory devices coupled to the SPI bus, a second chip select signal that enables the second memory device; receiving, at the first memory device via the SPI bus, a command that includes a first address based at least in part on the first chip select signal, wherein the command instructs a read operation to be performed at the first memory device and a write operation to be performed at the second memory device; writing data from the first address within the first memory device to the SPI bus based at least in part on the read operation; writing the data to the second memory device from the SPI bus based at least in part on the write operation and the second chip select signal; A method comprising the above steps. **Claim 2** The method of claim 1, further comprising receiving, at the second memory device via the SPI bus, a second command that includes a second address associated with writing the data. **Claim 3** The method of claim 1, further comprising operating in accordance with a clock provided to the first memory device and the second memory device based at least in part on the first chip select signal. **Claim 4** Receiving an indication of a change in the first chip select signal; Stopping operation in accordance with the clock based at least in part on the change in the first chip select signal; The method of claim 3, further comprising the above steps. **Claim 5** A memory system comprising a Serial Peripheral Interface (SPI) bus; A plurality of memory devices coupled to the SPI bus; Wherein a first memory device of the plurality of memory devices is configured to: Receive a first chip select signal that enables the first memory device; And perform the operations as described above. Receiving, via the SPI bus, a command including a first address based at least in part on the first chip select signal, the command instructing a read operation to be performed at the first memory device and a write operation to be performed at a second memory device among the plurality of memory devices; Writing data from the first address in the first memory device to the SPI bus based at least in part on the read operation; Writing the data from the SPI bus to the second memory device based at least in part on the write operation and a second chip select signal associated with the second memory device; A memory system operable to perform the above. **Claim 6** The second memory device Receiving the second chip select signal enabling the second memory device, and writing the data being based at least in part on the second chip select signal; The memory system according to claim 5, further operable to perform the above. **Claim 7** The second memory device Receiving, via the SPI bus, a second command including a second address associated with writing the data; The memory system according to claim 5, further operable to perform the above. **Claim 8** The first memory device Operating according to a clock provided to the first memory device and the second memory device based at least in part on the first chip select signal; The memory system according to claim 5, further operable to perform the above. **Claim 9** The first memory device Receiving an indication of a change in the first chip select signal; Stopping operating according to the clock based at least in part on the change in the first chip select signal; The memory system according to claim 8, further operable to perform the above. **Claim 10** A non-transitory computer-readable medium storing code, the code being executable by one or more processors In a first memory device, receiving a first chip select signal that enables the first memory device, where the first memory device is one of a plurality of memory devices coupled to a Serial Peripheral Interface (SPI) bus, In a second memory device of the plurality of memory devices coupled to the SPI bus, receiving a second chip select signal that enables the second memory device, In the first memory device via the SPI bus, receiving a command that includes a first address, at least partially based on the first chip select signal, where the command instructs a read operation to be performed by the first memory device and a write operation to be performed by the second memory device, Based at least partially on the read operation, writing data from the first address within the first memory device to the SPI bus, Based at least partially on the write operation and the second chip select signal, writing the data from the SPI bus to the second memory device, A non-transitory computer-readable medium including instructions executable to perform the above.

11. The instructions are by the one or more processors, Receiving, via the SPI bus in the second memory device, a second command that includes a second address associated with writing the data, The non-transitory computer-readable medium according to claim 10, which is further executable to perform the above.

12. The instructions are by the one or more processors, Operating in accordance with a clock provided to the first memory device and the second memory device, at least partially based on the first chip select signal, The non-transitory computer-readable medium according to claim 10, which is further executable to perform the above.

13. The instructions are by the one or more processors, Receiving an indication of a change in the first chip select signal, Stopping operating in accordance with the clock, at least partially based on the change in the first chip select signal, The non-transitory computer-readable medium according to claim 12, which is further executable to perform the above.

Images