Configuration of Cache Policy of Cache Based on Composite Cache Policy Test

Abstract

The electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of a plurality of test areas in the cache memory, with different configuration values ​​of the two or more cache policies being used in each test area. The cache policy manager selects a configuration value for at least one of the two or more cache policies based on a performance metric of the cache operations while using the different configuration values ​​of the two or more cache policies in the test areas. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main area of ​​the cache memory.

Description

Background Art

[0001] (Related Art) Many of the latest electronic devices include a processor (e.g., a central processing unit, a graphics processing unit, etc.) that executes instructions within a program code (e.g., an application, an operating system, etc.) for causing the electronic device to perform operations related thereto. In many of these electronic devices, in order to execute instructions, the processor needs to retrieve instructions and data from a non-volatile storage device such as a hard disk or a large-capacity non-volatile semiconductor memory. Since it takes a relatively long time to retrieve instructions and data from the non-volatile storage device, the electronic device generally also includes a volatile memory, which may be referred to as a “main memory,” into which copies of instructions and data are loaded (e.g., in 4 kB pages, etc.) to enable the processor to retrieve instructions and data more quickly. Retrieving instructions and data from the volatile memory can be significantly faster than retrieving them from the non-volatile memory, but it still takes a sufficiently long time to retrieve instructions and data from the volatile memory, and the processor must periodically wait for the requested instructions and data to be returned from the memory. Thus, electronic devices often include a high-speed access cache memory (more simply, a “cache”) that is used to store a limited number of copies of instructions and / or data for the processor. For example, some electronic devices include a cache hierarchy that includes a 64 kB level 1 (L1) cache as the highest and fastest for accessing caches within the hierarchy, a 512 kB level 2 (L2) cache intermediate within the hierarchy for accessing caches within the hierarchy, and a 2 MB level 3 (L3) cache as the lowest and slowest. Since instructions and / or data can be retrieved from the cache for a portion of the time required to retrieve instructions and / or data from the volatile memory, the cache can significantly improve the performance of the processor.

[0002] Since a cache stores only a limited number of copies of instructions and / or data, it is common for the cache to become full (filled) with copies of instructions and / or data during operation. When the cache becomes full with copies of instructions and / or data, in order to store any further copies of instructions and / or data in the cache, existing copies of instructions and / or data stored in the cache must be evicted (or simply overwritten). The decision of whether to store (or not store) a copy of instructions and / or data in the cache and which copy of instructions and / or data to evict depends on the cache's performance, so processors that rely on caches are generally managed according to one or more cache policies. A cache policy is a rule, guideline, specification, and / or control, or includes such, regarding when, which, how, and / or where copies of instructions and / or data are stored, accessed, evicted / replaced, and / or otherwise interacted with the cache and / or caches within the cache hierarchy. For example, a cache policy can indicate which copy of instructions and / or data should be stored in a given cache at any time, which copy of instructions and / or data should be written back to a lower-level cache at any time, and which copy of instructions and / or data should be evicted at any time to create space for incoming copies of instructions and / or data, etc.

[0003] In some electronic devices, a cache controller (or other functional block) determines which cache policy should be used and / or how the cache policy should be configured for one or more caches. To determine the cache policy to be used and / or its configuration, some cache controllers test the performance of individual cache policies within the cache. For example, when testing a given cache policy, the cache controller can execute cache operations (e.g., storing copies of data and / or instructions, accessing copies of data and / or instructions, etc.) within the cache using the given cache policy and / or its configuration. While executing the cache operations, the cache controller records information such as cache access misses (or hits), eviction rates, latencies of operations, etc. The cache controller then uses the recorded information to determine whether the given cache policy should be used and / or how the cache policy should be configured for subsequent cache operations within the cache.

[0004] Testing the cache policy and / or its configuration can help determine the cache policy and / or its configuration used within the cache, but in some cases, the test may not accurately represent the cache performance considering the use of the cache policy and / or its configuration. For example, combinations of two or more cache policies (e.g., replacement via policy and write-back / write-through, etc.) and / or their configurations may be used simultaneously within the cache. In such situations, the above-described testing of individual cache policies and / or their configurations can characterize cache performance that does not represent the actual cache performance due to the interaction of the combination of two or more cache policies and / or their configurations. BRIEF DESCRIPTION OF THE DRAWINGS

[0005]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

[0006] Throughout the drawings and the description, like reference numerals refer to like elements.

[0007] The following description is presented to enable any person skilled in the art to make and use the described embodiments and is provided in the context of a particular application and its requirements. Various changes to the described embodiments will be readily apparent to those skilled in the art, and the general principles described herein may be applied to other embodiments and applications. Accordingly, the described embodiments are not limited to the embodiments shown, and the broadest scope consistent with the principles and features described herein should be given.

[0008] (Term) In the following description, various terms are used to describe the embodiments. The following is a simplified general description of some of the terms. Note that this term may have important additional aspects not described herein for the sake of clarity and conciseness, and thus the description is not intended to limit this term.

[0009] Functional block: A functional block refers to a set of interrelated circuit configurations such as integrated circuit configurations, discrete circuit configurations, etc. The circuit configurations are "interrelated" in that the circuit elements within the circuit configuration share at least one characteristic. For example, the circuit may be included in, manufactured on, or otherwise coupled to a particular integrated circuit chip, substrate, circuit board, or a part thereof, and may be involved in the execution of a particular operation (e.g., a computational operation, a control operation, a memory operation, etc.), and may be controlled by a common control element and / or a common clock. The circuits of a functional block can have any number of circuit elements, from a single circuit element (e.g., a single integrated circuit logic gate or a discrete circuit element) to millions or billions of circuit elements (e.g., an integrated circuit memory). In some embodiments, the functional block performs "hardware" operations using circuits that perform operations without executing program code.

[0010] (Cache policy) In the described embodiments, a cache policy is used to control the operation of one or more caches (e.g., the L1 instruction cache 202, the L1 data cache 204, the L2 cache 206, and / or the L3 cache portions 120 - 126 of FIG. 1) within an electronic device (e.g., the electronic device 100 of FIG. 1). Generally, a cache policy can be or can include rules, guidelines, specifications, and / or controls regarding when, which, how, where, how a copy of an instruction and / or data is stored, accessed, evicted / replaced, and / or otherwise interacted within a cache and / or within a cache hierarchy. For example, in some embodiments, a cache policy controls when (or when not) a copy of an instruction and / or data is stored in a particular cache within a cache or cache hierarchy. For example, whether a copy of a specified instruction and / or data (e.g., prefetched, requested fetched, from a particular source, from a specified address range, of a particular type, etc.) is stored in a particular cache within a cache or cache hierarchy. As another example, in some embodiments, a cache policy controls the eviction / replacement of a copy of an instruction and / or data with an incoming copy of the instruction and / or data. For example, a cache policy can instruct that the least recently used (i.e., accessed) copy of a specified set or group of copies of instructions and / or data within a cache is evicted / replaced first. As yet another example, in some embodiments, a cache policy controls replacing a copy of an instruction and / or data with an incoming copy of the instruction and / or data based on a prediction as to which future copies of instructions and / or data will be accessed. In some of these embodiments, an access record (e.g., a counter or other value) associated with a copy of an instruction and / or data within a cache is maintained and used to predict which copies of instructions and / or data are likely to be accessed later (i.e., not accessed for the longest time).As yet another example, in some embodiments, the cache policy controls when a modified copy of data is written back to a lower level cache and / or memory, using, for example, a write-through or write-back cache policy. As yet another example, in some embodiments, the cache policy controls where a copy of an instruction and / or data is stored in the cache, by, for example, an algorithm, table, hash function, or other means used to determine a set in a given way, or to configure where the copy of the instruction and / or data is stored (e.g., due to skewed associativity, etc.).

[0011] In the described embodiments, some or all of the cache policy used within the cache can be configured. Generally, configuring a cache policy includes setting configuration values (e.g., enable / disable values, timers, counters, thresholds, etc.) used to control the storage and / or access of copies of instructions and / or data according to the cache policy. For example, in some embodiments, one or more configuration values control which copies of instructions and / or data are stored (or not stored) in the cache or a particular cache in the cache hierarchy according to the cache policy. As another example, in some embodiments, one or more configuration values control which replacement cache policy is used for some or all of the cache. As yet another example, in some embodiments, the configuration values are or include a counter or timer used in a predictive replacement cache policy, or a threshold of a counter or timer. In some embodiments, "configuring" a cache policy includes disabling or otherwise preventing the cache policy from being used, or, in contrast, enabling the cache policy.

[0012] A cache policy is used by a cache controller within a cache (and optionally other functional blocks) to determine when, which, how, where, a copy of an instruction and / or data is stored, accessed, evicted / replaced, and / or interacted within the cache and / or within a hierarchy of caches. For example, in some embodiments, the cache controller includes circuitry for implementing (i.e., enabling / disabling, using, etc.) each or one or more cache policies, circuitry for holding configuration values for configuring the cache policy, and the like.

[0013] (Overview) In the described embodiments, an electronic device includes a processor (e.g., a central processing unit, a graphics processing unit, etc.) having processing circuitry (e.g., cores, instruction execution pipelines, computing units, etc.) that executes program code instructions and performs other operations. The processor includes a cache memory, or more simply, a "cache" that stores copies of instructions and / or data for quick retrieval for use in instruction execution or other operations in the processor. For example, in some embodiments, the cache is an instruction cache for storing copies of instructions, a data cache for storing copies of data (e.g., input data for instructions, results of previous instruction executions, constant values, etc.), or a unified cache for storing copies of instructions and data. In some embodiments, the cache is a cache within a hierarchy of two or more caches, such as a level 2 (L2) cache within a hierarchy of caches that includes an L2 cache and one or more level 1 (L1) caches.

[0014] In the described embodiments, the electronic device includes a cache policy manager that performs operations to configure a cache policy used in the cache. As described above, each cache policy includes one or more rules, guidelines, specifications, etc. used by a cache controller in the cache to control various aspects such as storage and access of copies of instructions and / or data in the cache. The cache policy manager configures the cache policy in use in the cache by causing the cache controller to use a predetermined cache policy and / or setting configuration values of the predetermined cache policy. For example, in some embodiments, the cache policy manager causes the cache controller to use a storage cache policy that indicates which types of data should be stored in the cache (e.g., prefetch, demand fetch, etc.) and / or configures the storage cache policy so that the specified types of data are (or are not) stored in the cache.

[0015] In the described embodiment, the cache policy manager performs operations to test combinations of two or more cache policies to determine the configuration of the cache policy to be used within the cache. Generally, to test combinations of two or more cache policies, the cache policy manager causes the cache controller to perform cache operations (e.g., storing copies of instructions and / or data in the cache, replacing copies of instructions and / or data within the cache, etc.) using different configurations of the combination of two or more cache policies being tested. While the cache controller performs cache operations using each of the configurations of the combination of two or more cache policies, the cache policy manager monitors performance metrics related to the cache operations. The cache policy manager then selects the configuration of the combination of two or more cache policies to be used within the cache based on the performance metrics. For example, the cache policy manager can select the configuration of the two or more cache policies to be used for subsequent cache operations within the cache that best meets a performance metric threshold (e.g., minimum misses, etc.) based on performance metrics such as misses that occurred within the cache for each of the tested configurations of the two or more cache policies. In this way, the cache policy manager tests separate configurations of combinations of two or more cache policies that reflect the interaction and impact on each other of the component cache policies to find the configuration of the combination of two or more cache policies that best meets the performance goals, and as a result, can use the "most desirable" configuration of the combination of two or more cache policies within the cache.

[0016] In some embodiments, the test regions within the cache are used for the above-described tests of combinations of cache policies. Generally, a test region includes a block, portion, or section of the memory circuitry within the cache that is used to execute cache operations using a given configuration of a combination of two or more cache policies being tested. In some embodiments, tests of two or more configurations of a combination of two or more cache policies are performed simultaneously in separate test regions within the cache, and in some cases, separate test regions are used for each available configuration of the combination of two or more cache policies. For example, assuming that each of cache policies A and B (e.g., write-through policy and replacement policy, etc.) can be used in a first configuration (0) or a second configuration (1), four separate test regions can be used to test the following configurations of the combination of cache policies A and B: 00, 01, 10, 11.

[0017] In some embodiments, the cache is divided into a number of test regions and a "main" region, and the test regions are, for example, one order of magnitude or more smaller than the main region. For example, the four test regions above may be 50 kB within a 2 MB cache, such that the main region is 1.8 MB. In these embodiments, each configuration of a combination of two or more cache policies is tested via cache operations in a relatively small region of the cache, and the "most desirable" configuration of the combination of two or more cache policies (i.e., the configuration of the combination of two or more cache policies that best meets the performance metric goals) is selected to be used in the larger main region of the cache.

[0018] In some embodiments, the test area is only used temporarily to test the configuration of a combination of two or more cache policies before being returned to the main area. In other words, the test area is identified / selected, used to test the configuration of two or more cache policies, and then returned to the main area for use in typical cache operations (and thus is no longer used for testing, at least temporarily). The test area can thus be established, used, and returned multiple times to test the configuration of two or more cache policies, such as every N seconds, periodically, when an event occurs, etc. However, in some embodiments, the testing is performed substantially continuously in the test area to enable the cache policy manager to react to changing cache operation characteristics. In other words, in these embodiments, the test area persists beyond the initial selection of the configuration of a combination of two or more cache policies and can be used multiple times to test the configuration of a combination of two or more cache policies.

[0019] In some embodiments, to use the above test regions, the cache policy manager causes the cache controller in the cache to use different configurations of a combination of two or more cache policies (i.e., commands, requests, etc.) to perform cache operations in each of the multiple test regions in the cache. Continuing with the example of the above A and B cache policies, for this operation, in some embodiments, the cache policy manager causes the cache controller to simultaneously use the 00, 01, 10, 11 configurations of cache policies A and B in four separate test regions. The cache policy manager then selects a selected configuration value of at least one of the two or more cache policies based on the performance metric of the cache operation while using different configuration values of the two or more cache policies within the test region. Continuing with the example of cache policies A and B again, assuming that the number of cache misses (or other performance metric) is closest to the performance metric threshold (e.g., 0) for the performance metrics of the 10 configurations of cache policies A and B, the cache policy manager can select the selected configuration value from among the configuration values of 1 configuration of cache policy A and / or 0 configurations of cache policy B. The cache policy manager then causes the cache controller to use the selected configuration value when using at least one cache policy for cache operations in the main region of the cache. Continuing with the example of cache policies A and B, the cache policy manager causes the cache controller to set the configuration values of cache policies A and / or B in the main region to the selected configuration value from among the configuration values of 1 configuration of cache policy A and / or 0 configurations of cache policy B (i.e., commands, requests, etc.). This operation may include causing the cache controller to start using cache policy A and / or B if cache policy A and / or B has not yet been used in the main region.

[0020] In some embodiments, the cache policy manager uses the test area described above to perform a per-configuration value or hierarchical test of combinations of two or more cache policies. In these embodiments, combinations of two or more cache policies are used to perform cache operations in each of a plurality of test areas within the cache, and different configuration values are used for the combinations of two or more cache policies within each test area. The cache policy manager divides the test areas into conflict groups of test areas based on the configuration values used in each test area, and collects performance metrics representing the relative performance of each conflict group of test areas and groups of test areas only within each test area. The cache policy manager then uses the performance metrics of a hierarchical test scheme in which only some "levels" (i.e., sets, etc.) of the test areas and conflict groups of test areas are used to determine a "winning" test area that best meets the performance metric target (e.g., the target number of misses, etc.). The cache policy manager then selects the configured value selected for at least one of the two or more cache policies based on the configured value used in the winning test area, and causes the cache controller to use the selected configured value when using two or more cache policies for cache operations in the main area of the cache.

[0021] In some embodiments, the cache policy manager uses the test area described above to perform a one-to-many test of the configurations of combinations of two or more cache policies. In these embodiments, combinations of two or more cache policies are used to perform cache operations in each of a plurality of test areas within the cache, and different configuration values are used for the combinations of two or more cache policies within each test area. The cache policy manager divides the test areas into competing groups of test areas such that each competing group of test areas has one test area for every other test area, and each test area has the configuration of each of the combinations of two or more cache policies. The cache policy manager collects performance metrics for the competing groups of test areas and uses the collected performance metrics to determine the competing group of "winning" test areas that best meets the group performance metric goal. The cache policy manager then selects the configuration values selected for at least one of the two or more cache policies based on the configuration values used for the individual test areas within the winning competing group of test areas, and causes the cache controller to use the selected configuration values when using two or more cache policies for cache operations in the main area of the cache.

[0022] In some embodiments, the cache policy manager uses the above test area to perform a per-area test of the configuration of a combination of two or more cache policies. In these embodiments, a combination of two or more cache policies is used to perform cache operations in each of a plurality of test areas within the cache, and different configuration values are used for the combination of two or more cache policies within each test area. The cache policy manager separately collects performance metrics for each test area and uses the collected performance metrics to determine a "winning" test area from among the test areas that best meet the group performance metric goal. The cache policy manager then selects the configured value selected for at least one of the two or more cache policies based on the configured values used in the winning test area, and causes the cache controller to use the selected configured value when using two or more cache policies for cache operations in the main area of the cache.

[0023] By performing the above test of the configuration of a combination of two or more cache policies, the described embodiments reveal the impact of the mutual cache policies during cache operation. In contrast to existing systems where cache policies are tested individually, the described embodiments can better identify combinations of cache policies that result in more efficient cache operation (e.g., reduction of misses in the cache, better retention of useful copies of instructions and / or data, etc.). Since storing and accessing copies of instructions and / or data in memory is a significant performance bottleneck for a processor within an electronic device, improving the operation of the cache (avoiding the need to store and access copies of instructions and / or data in memory) can potentially lead to an improvement in the performance of the processor. As the performance of the processor improves, the performance of the electronic device improves, and user satisfaction improves.

[0024] (Electronic device) FIG. 1 is a block diagram showing an electronic device 100 according to some embodiments. As seen in FIG. 1, the electronic device 100 includes processors 102 and 104, a memory 106, and a fabric 108. All of the processors 102 and 104, the memory 106, and the fabric 108 are “hardware,” i.e., implemented using corresponding circuits. For example, in some embodiments, the processors 102 and 104, the memory 106, and the fabric 108 are entirely fabricated from one or more semiconductor chips, in some cases integrated circuits on one or more individual semiconductor chips, or formed from semiconductor chips in combination with individual circuits, or fabricated from individual circuits only. Also, the electronic device 100 includes a storage device 110, which is a functional block, device, and / or element that includes a larger-capacity non-volatile memory for storing instructions and data used by other functional blocks within the electronic device 100. For example, the storage device 110 may be, or include, a hard disk, an optical disk, a magnetic tape, a non-volatile semiconductor memory, etc. Each of these functional blocks and / or devices may include relevant firmware and / or software, as will be understood by those skilled in the art.

[0025] Processors 102 and 104 are functional blocks that perform calculations, memory access, and other operations (e.g., control operations, configuration operations, etc.) in the electronic device 100. For example, processors 102 and 104 may be one or more central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or other processing mechanisms, or may include them. Processors 102 and 104 each include cores 112-114 and 116-118, which are functional blocks such as CPU cores, GPU cores, ASICs, FPGAs, etc. that perform calculations, memory access, and other operations within each processor. Also, processors 102-104 each include level 3 (L3) cache portions (L3 portions) 120-122 and 124-126, which are cache memory functional blocks that each include a memory circuit such as a static random access memory (SRAM) memory circuit for storing copies of instructions and data, and a control circuit for storing copies of instructions and data in the memory circuit and accessing the stored copies of instructions and data.

[0026] In some embodiments, L3 cache portions 120-126 are shared among cores 112-118. Thus, each memory circuit of L3 cache portions 120-126 can be used to store copies of instructions and data from any of cores 112-118 (although in some cases it may be preferable to store copies of instructions and data in a "local" L3 cache portion such as L3 cache portion 120 of core 112), and / or the instructions and data stored in L3 cache portions 120-126 can be accessed by any of cores 112-118. In these embodiments, L3 cache portions 120-126 can be considered as a group that forms a shared L3 cache within the electronic device 100.

[0027] Memory 106 is a functional block that performs operations on the memory (e.g., the "main" memory) within the electronic device 100. Memory 106 includes a fourth-generation double data rate synchronous DRAM (DDR4 SDRAM) memory circuit for storing copies of instructions and data used by other functional blocks within the electronic device 100, as well as a volatile memory circuit such as a control circuit for storing, accessing, etc., copies of instructions and data within the memory circuit and performing other control or configuration operations. In some embodiments, copies of instructions and data are retrieved from the storage device 110 (e.g., in 4 kB blocks or "pages") and stored in the memory 106 for use by various functional blocks within the electronic device 100.

[0028] Fabric 108 is a functional block that includes communication paths used to communicate instructions, data, control signals, and / or other information between functional blocks (e.g., the processor 102, the memory 106, etc.) within the electronic device 100. Fabric 108 includes one or more serial or parallel buses (e.g., wires, guides, etc.) and circuits (e.g., transmitters, receivers, buffers, repeaters, optical elements, etc.) used to communicate instructions, data, etc., between functional blocks. In some embodiments, the communication traffic (e.g., packets, signals, messages, etc.) communicated between functional blocks using the fabric 108 is arranged, formatted, and processed according to one or more protocols or standards such as the Infinity Fabric standard of Advanced Micro Devices, Inc. of Santa Clara, California.

[0029] The electronic device 100 is simplified for illustrative purposes. However, in some embodiments, the electronic device 100 includes additional or different functional blocks, subsystems, and / or elements. For example, the electronic device 100 may include a display subsystem, a power subsystem, an input / output (I / O) subsystem, etc. Further, although the electronic device 100 is shown with certain functional blocks and elements, in some embodiments, the electronic device 100 includes different functional blocks or elements. For example, in some embodiments, the electronic device 100 includes a different number of processors, from one processor to many processors (as indicated using the ellipsis in FIG. 1). As another example, although L3 cache portions 120 - 126 are shown in FIG. 1, in some embodiments, there is no L3 cache, or the L3 cache is differently configured (e.g., not divided into parts). As yet another example, in some embodiments, the electronic device 100 has and is arranged with multiple memory portions (instead of the one memory 106 as shown in FIG. 1), such as memory portions associated with individual processors like a non-uniform memory access (NUMA) arrangement. Generally, in the described embodiments, the electronic device 100 includes functional blocks and elements sufficient to perform the operations described herein.

[0030] The electronic device 100 may be or may be included in any device that performs the operations described herein. For example, the electronic device 100 may be or may be included in a desktop computer, a laptop computer, a wearable computing device, a tablet computer, a virtual or augmented reality device, a smartphone, an artificial intelligence (AI) or machine learning device, a server, a network device, a toy, an audiovisual device, a household appliance, a vehicle, etc., and / or combinations thereof.

[0031] (Processor) As described above, the processors 102 to 104 each include cores 112 to 114 and 116 to 118. FIG. 2 is a block diagram showing a core 200 according to some embodiments. In some embodiments, some or all of the cores 112 to 114 and 116 to 118 include functional blocks similar to those shown in the core 200, that is, they are arranged internally in the same manner as the core 200.

[0032] As shown in FIG. 2, the core 200 includes a level 1 (L1) instruction cache 202, an L1 data cache 204, and a level 2 (L2) cache 206. Each of the L1 instruction cache 202, the L1 data cache 204, and the L2 cache 206 is a cache memory functional block including a memory circuit (e.g., an SRAM memory circuit, etc.) for storing a copy of instructions and / or data for use by the front-end subsystem 208 and / or the back-end subsystem 210, and a control circuit for controlling the storage of the copy of instructions and / or data in the memory circuit and accessing the stored copy of the instructions and data stored in the memory circuit. In some embodiments, the L1 instruction cache 202 is exclusively used to store a copy of instructions fetcheable for execution by the front-end subsystem 208, and the L1 data cache 204 is exclusively used to store a copy of data (e.g., input data of instructions, results of previous instruction executions, constant values, etc.) that can be obtained from the L1 data cache 204 or stored in the data cache 204 by the back-end subsystem 210. In some embodiments, the L2 cache 206 can store copies of both instructions and data.

[0033] In some embodiments, the L1 instruction cache 202, the L1 data cache 204, and the L2 cache 206 are part of a "hierarchy" of cache memories within the core 200. The L1 caches 202 and 204 are at the first level "Level 1" of the hierarchy, and are the fastest to access by the circuits of the front-end subsystem 208 or the back-end subsystem 210 respectively, but have a smaller capacity than the L2 cache 206. The L2 cache 206 is at the second level within the hierarchy, and is slower to access by the circuits within the front-end subsystem 208 or the back-end subsystem 210, but has a larger capacity than the L1 instruction cache 202 and the L1 data cache 204. For example, in some embodiments, the L1 instruction cache 202 and the L1 data cache 204 are 32 kB, and the L2 cache 206 is 512 kB. In some embodiments, the L3 cache (e.g., some or all of the L3 cache portions 120 - 126) is included in the hierarchy as the maximum capacity cache, e.g., 16 MB, but has the slowest access. Within the cache memory hierarchy, the L1 caches (i.e., the L1 instruction cache 202 and the L1 data cache 204) are considered to be at the "highest" level of the hierarchy, the L2 cache 206 is considered to be at a level "lower" by only one level of the hierarchy than the L1 caches, and the L3 cache is at the "lowest" level of the hierarchy.

[0034] The front-end subsystem 208 includes functional blocks that obtain instructions from the L1 instruction cache 202 (or, optionally, the L2 cache 206, the L3 cache, the memory 106, or the storage device 110) and perform operations to generate micro-operations from the instructions to be sent to the execution units within the back-end subsystem 210 for execution. For example, in some embodiments, the front-end subsystem 208 includes some or all of an instruction fetch / decode functional block, a program counter calculation functional block, a branch prediction functional block, a micro-operation cache functional block, a micro-operation dispatch functional block, and the like. The back-end subsystem 210 includes functional blocks that perform operations to execute the micro-operations received from the front-end subsystem 208. For example, in some embodiments, the back-end subsystem 210 includes some or all of an integer execution functional block, a floating point functional block, an address calculation functional block, an instruction retirement functional block, and the like.

[0035] In some embodiments, the L1 instruction cache 202, the L1 data cache 204, the L2 cache 206, the front-end subsystem 208, and the back-end subsystem 210 (and their constituent functional blocks) are implemented "in hardware", i.e., using corresponding circuitry. For example, in some embodiments, the L1 instruction cache 202, the L1 data cache 204, the L2 cache 206, the front-end subsystem 208, and the back-end subsystem 210 (and their constituent functional blocks) are fabricated entirely on one or more semiconductor chips, possibly within an integrated circuit on one or more individual semiconductor chips, or formed from semiconductor chips in combination with individual circuits, or fabricated from individual circuits only.

[0036] Although a particular arrangement, connectivity, and number of elements are shown in the core 200 of FIG. 2, in some embodiments, different arrangements, connectivity, and / or numbers of elements exist in the core 200. Generally, the core 200 includes sufficient elements to perform the operations described herein.

[0037] (Cache Policy Manager) In the described embodiment, the cache policy manager performs operations to configure the cache policy used in one or more caches (e.g., L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126) within an electronic device (e.g., electronic device 100). FIG. 3 is a block diagram showing a cache 300 and a cache policy manager 302 according to some embodiments. As can be seen from FIG. 3, the cache 300 includes a cache memory 304 and a cache controller 306. The cache memory 304 is a functional block including a memory circuit (e.g., SRAM memory circuit, etc.) used to store and access (e.g., read, evict, modify, etc.) copies of instructions and / or data within a cache block. As used herein, a "cache block" is a portion of the memory circuit within the cache memory 304, such as an N-byte cache line or a portion or combination thereof, where N = 64, 128, or another number. To store a copy of an instruction or data in the cache memory 304, a block, portion, or chunk (e.g., 10 bytes, 64 bytes, etc.) of the copy of the instruction or data is obtained from a core (e.g., core 112, core 114, etc.), a lower-level cache memory, a memory (e.g., memory 106), a storage device (e.g., storage device 110), or another source and stored in a cache block within the cache memory 304. To access a copy of an instruction or data within the cache memory 304, a block, portion, or chunk (e.g., 10 bytes, 64 bytes, etc.) of the copy of the instruction or data is accessed (e.g., read from a cache block within the cache memory 304, etc.) within the cache block within the cache memory 304.

[0038] In some embodiments, the cache memory 304 is configured to be able to use cache blocks to store copies of instructions and / or data from different ranges of memory addresses. In other words, cache blocks are not reserved to store copies of instructions and / or data from specific individual addresses in memory. Instead, they can be used to store copies of instructions and / or data from multiple addresses in memory. For example, in some embodiments, the cache memory is direct mapped or associative, such as set associative, skewed associative, etc. Depending on the mapping or associativity in use, the memory circuits within the cache memory 304 can be divided into a number of sets, ways, and / or other partitions that are used to store copies of instructions and / or data from corresponding addresses in memory. For example, in some embodiments, the cache memory 304 is set associative, and the memory circuits within the cache memory 304 are divided into a number of sets and ways that are used to store copies of instructions and / or data from a specified range of addresses in the address space used by the electronic device 100.

[0039] The cache controller 306 is a functional block that performs operations for managing the operation of the cache 300. Among the operations performed by the cache controller 306 are operations for storing a copy of an instruction and / or data in a cache block in the cache memory 304, operations for searching the cache memory 304 (or another functional block such as a tag array (not shown)) to determine whether a copy of an instruction and / or data exists in a cache block in the cache memory 304, operations for accessing a copy of an instruction and / or data in a cache block in the cache memory 304, operations for maintaining a copy of an instruction and / or data in the cache memory 304 (e.g., via periodic memory circuit refresh or other operations), and the like. In the described embodiment, the cache controller 306 controls the storage and / or access of a copy of an instruction and / or data in the cache memory 304 based on or in accordance with the cache policy described herein. For example, the cache controller 306 can replace / evict a copy of an instruction and / or data according to a replacement cache policy, and store (or not store) a particular type of copy of an instruction and / or data (e.g., prefetch, demand fetch, etc.) in the cache memory 304 according to a storage cache policy.

[0040] The cache policy manager 302 is a functional block that performs operations to set the cache policy used by the cache controller 306. Generally, to configure the cache policy, the cache policy manager 302 sets the configuration values of the cache policy used in the cache 300. In other words, the cache policy manager 302 sets the configuration values for enabling, disabling, or (via timer values, threshold values, counters, etc.) controlling the cache policy in use in the cache 300. For example, in some embodiments, the cache policy manager 302 configures the cache controller 306 to use (or not use) a specified predictive replacement policy, or sets the threshold, counter value, etc. of the predictive replacement policy. Then, the cache controller 306 processes (e.g., stores, accesses, etc.) the copies of instructions and / or data stored in the cache memory 304 according to the configuration of the cache policy. Also, the cache policy manager 302 executes operations to test the configuration of combinations of multiple cache policies to determine how the cache policy is configured within the cache 300. Generally, the cache policy manager 302 executes tests to find a specific configuration of a combination of two or more cache policies that best meets the performance metric goals. Based on the configuration of the combination of two or more cache policies that best meets the performance metric goals, the cache policy manager 302 causes the cache controller 306 to use a specific configuration of the combination of two or more cache policies for cache operations in the cache memory 304.

[0041] As shown in FIG. 3, the cache policy manager 302 includes a controller 308 and a performance (PERF) metric 310. The controller 308 is a functional block including a circuit for performing operations of the cache policy manager 302, including configuring the cache policy of the cache 300, testing the configuration of a combination of two or more cache policies, recording a performance metric for testing the configuration of a combination of two or more cache policies, and the like. The performance metric 310 is a functional block including a circuit for recording / storing the performance metric of the controller 308 for testing the configuration of a combination of cache policies within the cache 300. For example, the performance metric 310 may store or be associated with a counter and / or other value of a performance metric such as a hit or miss on a copy of an instruction and / or data in the cache memory 304.

[0042] In some embodiments, for the above-described tests of combinations of two or more cache policies, the controller 308 uses a test area of the cache memory 304 to test different configurations of combinations of two or more cache policies. The test area is a section or portion of the cache memory 304 where different configurations of combinations of two or more cache policies are tested separately. Performance metrics collected from or based on the cache operations executed in each test area during testing function as an example or representation of how the configuration of the combination of two or more cache policies is likely to perform if subsequently used in the "main" area of the cache memory 304. FIG. 4 is a block diagram showing test areas 400-406 and a main area 408 within the cache memory 304 according to some embodiments. As seen in FIG. 4, each of the test areas 400-406 includes a part of the memory circuitry within the cache memory 304. For example, the test area can include a specified number of cache blocks (e.g., N-byte cache lines or portions thereof or combinations thereof), a predetermined percentage of the cache blocks within the cache memory 304 (e.g., 5%, 10% or another ratio), etc. In some embodiments, each test area includes a relatively small portion of the memory circuitry within the cache memory 304 compared to the main area. For example, in some embodiments, each of the test areas 400-406 is at least one order of magnitude smaller than the main area 408, such as a 250 kB test area within a 4 MB cache memory 304.

[0043] In some embodiments, test regions 400-406 are used continuously, i.e., substantially permanently, to test the configuration of a combination of two or more cache policies. In these embodiments, each of the configurations of the two or more cache policies has an individual test region assigned or allocated from among test regions 400-406, and the cache operations are continuously executed in each of the test regions using each of the configurations of the two or more cache policies. Based on the performance metrics collected by cache policy manager 302 while the cache operations are being executed in test regions 400-406, cache policy manager 302 configures the cache policy for main region 408. For example, in some embodiments, cache policy manager 302 substantially continuously collects performance metrics based on the cache operations in test regions 400-406 (e.g., collects performance metrics at predetermined time intervals), and uses the collected performance metrics to configure and in some cases reconfigure the cache policy for main region 408 every N seconds, when a specified event occurs, such as at software application or context switch time.

[0044] In some embodiments, the cache policy manager 302 temporarily establishes and uses test regions 400-406 during the "test" phase, and then returns the test regions 400-406 to the main region 408 for operation during the "normal operation" phase. In other words, in some embodiments, during a given test phase, the cache policy manager 302 selects the test regions 400-406 and then causes the cache controller 306 to perform cache operations in each of the test regions 400-406 using the configuration of each of the two or more cache policies. When the test is complete (e.g., when sufficient performance metrics have been collected), the cache policy manager 302 causes the cache controller 306 to return the test regions 400-406 to the main region 408 before proceeding with cache operations in the main region 408. Thus, the test regions 400-406 are temporarily reconfigured with each cache policy for testing before being restored to the configuration of the two or more cache policies being used in the main region 408. In some of these embodiments, the cache policy manager 302 can enter the test phase one or more times and can enter the test phase repeatedly or periodically. For example, the cache policy manager 302 can start the test phase every N seconds, when a specified event occurs, such as during a software application or context switch.

[0045] Figure 4 shows test regions 400 - 406 with a specific number and arrangement. However, in some embodiments, different numbers or arrangements of test regions can be used (as indicated by the ellipsis in Figure 4). For example, in some embodiments, the number of test regions used depends on the number of cache policies being tested. For example, if three cache policies A, B, and C with configurations 0 (e.g., invalidation, use of a first threshold, etc.) and 1 (e.g., validation, use of a second threshold, etc.) are being tested, eight test regions can be used to separately test the configurations 000, 001, 010, 011, 100, 101, 110, 111 of cache policies A, B, and C. As another example, in some embodiments, only a single test region is used, and each configuration of the combination of cache policies being tested is separately tested in order in the single test region ( "testing" includes running cache operations in the test region until sufficient performance metrics are collected to enable a determination regarding the configuration of the cache policy used in the main region of the cache). In other words, the test for a given configuration of a combination of two or more cache policies is completed in the test region, and then the test for the next configuration of the combination of two or more cache policies is started until all configurations of the combination of two or more cache policies are tested.

[0046] Test regions 400 - 406 are shown as being relatively small compared to main region 408. However, in some embodiments, the test regions are larger. For example, in some embodiments, the test regions are evenly divided among the available memory circuits within cache memory 304 and there is no main region. In these embodiments, the test regions may be used temporarily for testing during the test phase, and then the memory circuits may be restored to main region 408.

[0047] In some embodiments, some or all of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126 include functional blocks similar to those shown in cache 300, i.e., are internally configured and arranged in the same manner as cache 300. Further, in some embodiments, one or more of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126 are coupled to their respective cache policy managers with a configuration similar to that shown in FIG. 3. In other words, each of one or more of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126 is coupled to its own individual single-cache cache policy manager. In these embodiments, the cache policy manager configures the cache policy only for each respective cache. In some embodiments, two or more single-cache cache policy managers communicate and interact to configure the cache policy within each respective cache. However, in some embodiments, two or more of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126 are coupled to a single cache policy manager. In these embodiments, one cache policy manager configures the cache policy used for some or all of two or more of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126. For example, in some embodiments, a single cache policy manager configures the cache policy for the entire cache hierarchy within the electronic device 100, i.e., for all of the L1 instruction cache 202, L1 data cache 204, L2 cache 206, and / or L3 cache portions 120-126.

[0048] (Process for configuring the cache policy of the cache) In the described embodiments, a cache policy manager (e.g., cache policy manager 302) executes operations to configure a cache policy used by a cache controller in a cache (e.g., cache controller 306 in cache 300) to handle storage and access of copies of instructions and / or data in a cache memory (e.g., cache memory 304). FIG. 5 is a flowchart illustrating a process for configuring a cache policy of a cache according to some embodiments. Note that the operations shown in FIG. 5 are presented as general examples of operations executed by some embodiments. Operations executed by other embodiments may include different operations, operations executed in a different order, and / or operations executed by different entities or functional blocks.

[0049] The operation of FIG. 5 starts when the cache policy manager causes the cache controller to use two or more cache policies for different configuration values for two or more cache policies used in each test area in a cache memory (e.g., test areas 400 to 406) having different configuration values (step 500). For this operation, the cache policy manager causes the cache controller to use all of two or more cache policies for cache operations (i.e., storing copies of instructions and / or data, accessing copies of instructions and / or data, etc.) within each test area, but the combinations of the two or more cache policies are configured differently within each test area. FIG. 6 is a block diagram showing two cache policies (A and B) used in a test area within a cache memory 606 (which may be similar to the cache memory 304) according to some embodiments. In the example of FIG. 6, cache policy A is a first cache policy (e.g., a replacement policy, etc.), cache policy B is a second cache policy (e.g., a write-through or write-back policy, etc.), and cache policies A and B can be configured in first and second configurations (e.g., operating states, etc.) as indicated by the configuration 602 of 0 and 1 in the key of FIG. 6. For example, cache policy A can be made invalid (0) or valid (1) and can be set to use a first value (e.g., a counter, a threshold value, etc.) (0) or a second value (1), etc. Each of the four test areas (only one of which is labeled for clarity) is used to perform cache operations using a combination of cache policies A and B, and test area 600 is used for the first configuration / operating state of cache policies A and B, which is shown as 00 in FIG. 6 to represent cache policies A and B having configuration values, settings, etc. that arrange both cache policies A and B in their respective first configurations.The remaining test area is used to perform cache operations using combinations of cache policies A and B, each having different configurations of cache policies A and B, shown as 01, 10, and 11 in Figure 6.

[0050] Returning to FIG. 5, the cache policy manager then selects the selected configuration value of at least one of the two or more cache policies based on the performance metric for the cache operation while using different configuration values of the two or more cache policies within the test area (step 502). For this operation, the cache policy manager tracks the performance metric while the cache operation is being executed in each test area (i.e., for each of the configurations of the two or more cache policies). For example, the cache policy manager can track the count of cache misses, the ratio of cache access requests to misses, the count of requests to the lower-level cache memory for copies of data and / or instructions, the count of evictions of copies of instructions and / or data, and / or another metric indicating the performance of the configurations of the two or more cache policies in the test area. The cache policy manager then uses the performance metric to determine the "winning" test area, which is the test area having the configuration of each of the two or more cache policies indicated by the corresponding performance metric, and which is the best-performing configuration of the two or more cache policies within the test area. For this operation, the cache policy compares the performance metric to one or more performance metric thresholds to determine which configuration of the two or more cache policies best meets the performance metric goal (e.g., using the test operation described with respect to FIG. 7 or FIG. 9). The cache policy manager then selects the configuration value used in the winning test area as the selected configuration value of at least one cache policy. Continuing with the above examples of cache policies A and B, the cache policy manager can compare the performance metrics of the 00, 01, 10, 11 configurations of cache policies A and B in the test area (i.e., test area 600, etc.) and / or its group, and select as the "winning" test area the test area whose performance metric best meets the performance metric goal.In this example, it is assumed that configuration 10 best meets the performance metric goals (e.g., least number of misses, etc.), and thus the cache policy manager selects, as the selected configuration value for at least one cache policy, the configuration value used in the winning test region, i.e., the configuration value (or underlying settings, thresholds, etc.) 1 of cache policy A and / or the configuration 0 of cache policy B.

[0051] Next, in step 504, the cache policy manager causes the cache controller to use the selected configuration value when using at least one cache policy within the main region of the cache memory. For this operation, the cache policy manager causes the cache controller to use the configuration value 1 of cache policy A (i.e., respective settings, thresholds, etc.) and / or the configuration 0 of cache policy B (i.e., commands, requests, etc.), while causing cache policies A and B to be used for cache operations in the main region. In this way, the cache policy manager uses the test region to compare each of the configurations of two or more cache policies and determine the configurations of two or more cache policies that best meet the performance goals (e.g., having the least misses, least evictions, etc.), and uses that configuration for cache operations within the main region of the cache memory.

[0052] (Process of executing tests for each configuration value) In some embodiments, a cache policy manager (e.g., cache policy manager 302) executes tests for each configuration value of the configurations of two or more cache policies. FIG. 7 is a flowchart showing a process for executing tests for each configuration value of the configurations of two or more cache policies according to some embodiments. Note that the operations shown in FIG. 7 are presented as a general example of operations executed by some embodiments. Operations executed by other embodiments include different operations, operations executed in a different order, and / or operations executed by different entities or functional blocks. In some embodiments, the process shown in FIG. 7 is executed as part of step 502 of FIG. 5. In these embodiments, in other words, the configuration values selected for at least one cache policy are selected using the per-configuration-value tests shown in FIG. 7.

[0053] Generally, in the per-configuration-value test, combinations of two or more cache policies are used to execute cache operations in each of a plurality of test regions in the cache, and different configuration values are used for the combinations of two or more cache policies within each test region. The cache policy manager divides the test regions into conflict groups of test regions based on the configuration values used in each test region, and collects performance metrics representing the relative performance of each conflict group of test regions and the groups of test regions only in each test region. Then, the cache policy manager uses the performance metrics of a hierarchical test method in which only some "levels" (i.e., sets, etc.) of the test regions and the conflict groups of test regions are used to determine a "winning" test region that best meets a performance metric target (e.g., a target number of misses, etc.). Then, the cache policy manager selects, from among the configuration values of the winning test region, the configuration values to be used for subsequent cache operations in the main region of the cache.

[0054] In the process shown in FIG. 7, as an example of a combination of cache policies being tested, a combination of cache policies A and B (e.g., a replacement cache policy and a storage cache policy) is used. However, in some embodiments, three or more cache policies are tested, and the operations in FIG. 7 are adjusted accordingly. For example, in some of these embodiments, testing three or more cache policies involves including additional hierarchical test levels for each additional cache policy (and thus configuration value). Further, in the process shown in FIG. 7, the configuration values can only have two values (e.g., 0 / 1, on / off, etc.), and thus there are only two competing groups at each hierarchical level, i.e., it is assumed that the configuration can only be set in two ways or operating states. However, in some embodiments, some or all of the cache policies use at least some configuration values that have three or more values (can be set to three or more values, etc.), or use multiple configuration values, and the operations in FIG. 7 are adjusted accordingly. For example, three or more competing groups can be included in some or all of the hierarchical test levels.

[0055] The process shown in FIG. 7 begins with the cache controller performing cache operations on test areas within the cache memory (e.g., cache memory 304), where each test area has different configuration values for a combination of two cache policies being tested (step 700). For this operation, the cache controller is caused (e.g., caused by a request of the cache policy manager, caused by an instruction of the cache policy manager, etc.) by the cache policy manager (e.g., cache policy manager 302) and performs cache operations in each test area, such as storing a copy of the instruction and / or data, accessing the stored copy of the instruction and / or data, evicting / replacing the existing stored copy of the instruction and / or data with the incoming copy of the instruction and / or data. In each test area, the cache controller performs cache operations using a predetermined configuration out of two configurations for each of cache policies A and B. For example, using 0 and 1 to generally represent the first and second configurations of the cache policy, cache policies A and B can be configured in four test areas such as the cache policy configurations shown in FIG. 6. In other words, in the first test area, both cache policies A and B are set to the first configuration represented by 00, in the second test area, cache policy A is in the first configuration, cache policy B is in the second configuration represented by 01, in the third test area, cache policy A is in the second configuration, cache policy B is in the first configuration represented by 10, and so on.

[0056] The "0" and "1" used in the examples of FIG. 7 and elsewhere in this specification for cache policies A and B are used to identify or indicate the first and second configurations of cache policies A and B, but it should be noted that 0 and / or 1 are not necessarily the values actually used when configuring or testing the cache policy. In some embodiments, one or more settings, values, thresholds, counters, and / or other values can be actually set to configure cache policies A and B in the first and second configurations. For example, if cache policy A uses a timer, configuring cache policy A in the first configuration (i.e., as shown using 0 in the example) can mean setting the timer to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as shown using 1 in the example) can mean setting the timer to a predetermined second value. As another example, if cache policy A uses a data type specifier (e.g., for prefetched data, demand-fetched data, etc.), configuring cache policy A in the first configuration (i.e., as shown using 0 in the example) can mean setting the data type specifier to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as shown using 1 in the example) can mean setting the data type specifier to a predetermined second value.

[0057] The cache policy manager divides the test areas into competing groups of test areas and records the performance metrics of only the competing groups of test areas and the test areas while performing the cache operation (step 702). For this operation, the cache policy manager divides the test areas into competing groups of test areas based at least in part on the configuration values (or specific configurations) of cache policies A and B used in each test area. Generally, the cache policy manager divides the test areas into competing groups where the predetermined configuration values are the same for all of the test areas within each competing group of test areas. FIG. 8 is a block diagram showing test areas for testing by configuration value according to some embodiments. As seen in FIG. 8, four test areas are divided into two competing groups of test areas 800-802 at the hierarchical test level 804 for testing by configuration value. The competing groups of test areas are divided using cache policy A. As a result, in the competing group of test areas 800, cache policy A is in the first configuration for both test areas (i.e., test areas 00 and 01), and in the competing group of test areas 802, cache policy A is in the second configuration for both test areas.

[0058] To record the contention groups of test regions 800 - 802 and the performance metrics of only the test regions, the cache policy manager records performance metrics that identify the relative performance of the configurations of cache policies A and B in the contention groups of the test regions and in only the test regions. For example, in some embodiments, the cache policy manager uses a saturation push - pull counter to track misses (i.e., requests where a copy of an instruction and / or data was not found in the cache) in the contention groups of the test regions. In these embodiments, the cache policy manager starts the counter with an initial value, increments the counter (e.g., increment, double / shift, etc.) when a miss is encountered in contention group 800 of the test region, and decrements the counter (e.g., decrement, halve / shift, etc.) when a miss is encountered in contention group 802 of the test region. Thus, the counter is pushed / incremented for events occurring for one contention group of the test region and pulled / decremented for events occurring for another contention group of the test region (changing up to saturation values such as 16 or 0). As another example, the cache policy manager can use a simple counter to track misses occurring in the contention groups of the test regions and / or in only each test region. In some embodiments, the cache policy manager collects / records performance metrics for a specified amount of time (e.g., N seconds, where N is 0.5, 1, or another value) until a predetermined number of cache operations are executed and / or based on one or more other time values.

[0059] After collecting the performance metrics, the cache policy manager determines the winning group of test areas using the performance metrics in the hierarchical test scheme for the competing groups of the test area and the test area alone. For this operation, the cache policy manager determines whether the final competing group of the test area has been processed (step 704), i.e., whether there are remaining test levels to be executed. If the final competing group of the test area has not been processed (step 704), the cache policy manager determines a specific group of test areas within the current group of the test area that best meets the performance metric goal based on the performance metrics recorded for the current competing group of the test area (step 706). In other words, for the current test level, the cache policy manager compares the performance of the groups of test areas within a given competing group of the test area. For example, in some embodiments, the cache policy manager checks the push-pull counter described above to determine the competing group of test areas that best meets the performance metric goal, such as when a specific value of the push-pull counter indicating the number of misses, etc., is lower for one of the given competing groups of the test area. FIG. 8 shows an example of a hierarchical test level 804 and uses the performance metric(s) of the competing groups of test areas 800-802 to determine the winning group 806 that best meets the performance metric goal. In the example of FIG. 8, the winning group 806 is the competing group of test area 800, which means that the performance metrics of the competing groups of test areas 800-802 indicate that the competing group of test area 800 better meets the performance metric goal. The cache policy manager then sets a specific group of test areas as the current competing group of the test area (step 708). In this way, the test areas within the winning competing group of the test area are transferred to the next level of the hierarchical test. This is shown in FIG. 8 via an arrow (indicating the transfer of the winning group 806).

[0060] When the test is completed at a specified level, the cache policy manager returns to step 704 to determine whether the final conflict group in the test area has been processed. If the final conflict group in the test area has not been processed (step 704), the cache policy manager uses the current conflict group in the test area (set in step 708) at the next level of the hierarchical test. In other words, for the conflict groups in the test area within the current conflict group in the test area (recalling that the conflict groups in the test area were determined by the cache policy manager in step 702), the cache policy manager executes steps 706-708. The cache policy manager repeats the sequence of determining the winning group in the test area at each level of the hierarchy until it reaches the final level of the hierarchy where the conflict "group" in the test area is simply one individual test area versus another individual test area. An example of the final conflict group in the test area, and thus the final level of the test hierarchy, is shown in FIG. 8 as hierarchical test level 808, where the conflict groups of test areas 810-812 are tested to see which conflict group of test areas best meets the performance metric goals. As shown, the conflict group of test area 812 is the winning group of test area 814.

[0061] If the final conflict group in the test area has been processed (step 704), the cache policy manager selects the selected configuration of at least one of the two or more cache policies from the current group's configuration values in the test area (step 710). In other words, the cache policy manager uses the configuration value from the winning group in the test area at the final level of the test hierarchy as the configuration value to be used in the main area of the cache memory. The cache policy manager then causes the cache controller to use the selected configuration value when using at least one cache policy within the main area of the cache memory (e.g., as shown in step 504 of FIG. 5).

[0062] (Process for performing a one - to - many test) In some embodiments, a cache policy manager (e.g., cache policy manager 302) performs a one - to - many test of the configurations of two or more cache policies. FIG. 9 is a flowchart showing a process for performing a one - to - many test of the configurations of two or more cache policies according to some embodiments. Note that the operations shown in FIG. 9 are presented as general examples of operations performed by some embodiments. Operations performed by other embodiments may include different operations, operations performed in a different order, and / or operations performed by different entities or functional blocks. In some embodiments, the process shown in FIG. 9 is performed as part of step 502 of FIG. 5. In these embodiments, in other words, the configuration values selected for at least one cache policy are selected using the one - to - many test shown in FIG. 9.

[0063] Generally, in a one-to-many test, a combination of two or more cache policies is used to perform cache operations in each of a plurality of test regions within a cache, and different configuration values are used for the combination of two or more cache policies within each test region. The cache policy manager divides the test regions into competing groups of test regions such that each competing group of test regions has one individual test region for all of the other test regions. In other words, each competing group of test regions has a first set of test regions that includes only one of each of the test regions, and a second set of test regions that includes all of the other test regions of each of the test regions. The cache policy manager then collects performance metrics that represent the relative performance of the groups of test regions in each competing group of test regions. The cache policy manager then uses the performance metrics of the competing groups to determine the competing group of winning test regions for the test regions that best meets the performance metric goal (e.g., a goal for the number of misses, etc.). The selected configuration values used for subsequent cache operations within the main region of the cache are then selected from among the configuration values of the individual test regions within the winning competing group of test regions.

[0064] In the process shown in FIG. 9, as an example of a combination of cache policies being tested, a combination of cache policies A and B (e.g., a replacement cache policy and a storage cache policy) is used. However, in some embodiments, three or more cache policies are tested, and the operations in FIG. 9 are adjusted accordingly. For example, in some of these embodiments, testing three or more cache policies involves including additional conflict groups in the test area such that all configurations of two or more cache policies are alone within the conflict groups of the test area. Further, in the process shown in FIG. 9, it is assumed that the configuration values can only have two values (e.g., 0 / 1, on / off, etc.), that is, the configuration can only be set in two ways or operating states. However, in some embodiments, some or all of the cache policies use at least some configuration values having three or more values (such as being able to set three or more values) or multiple configuration values, and the operations in FIG. 9 are adjusted accordingly.

[0065] The process shown in FIG. 9 begins with the cache controller performing cache operations on test areas within the cache memory (e.g., cache memory 304), where each test area has different configuration values for a combination of two cache policies being tested (step 900). For this operation, the cache controller is caused (e.g., caused by a request of the cache policy manager, caused by an instruction of the cache policy manager, etc.) by the cache policy manager (e.g., cache policy manager 302) to perform cache operations in each test area, such as storing copies of instructions and / or data, accessing the stored copies of instructions and / or data, and evicting / replacing the existing stored copies of instructions and / or data with incoming copies of instructions and / or data. In each test area, the cache controller performs cache operations using a predetermined configuration out of two configurations for each of cache policies A and B. For example, using 0 and 1 to generally represent the first and second configurations of the cache policy, cache policies A and B can be configured in four test areas such as the cache policy configurations shown in FIG. 6. In other words, in the first test area, both cache policies A and B are set to the first configuration represented by 00, in the second test area, cache policy A is in the first configuration and cache policy B is in the second configuration represented by 01, in the third test area, cache policy A is in the second configuration and cache policy B is in the first configuration represented by 10, etc.

[0066] The "0" and "1" used in the examples of FIG. 9 and elsewhere in this specification for cache policies A and B are used to identify or indicate the first and second configurations of cache policies A and B, but it should be noted that 0 and / or 1 are not necessarily the values actually used when configuring or testing the cache policy. In some embodiments, one or more settings, values, thresholds, counters, and / or other values can be actually set to configure cache policies A and B in the first and second configurations. For example, if cache policy A uses a timer, configuring cache policy A in the first configuration (i.e., as indicated by using 0 in the example) can mean setting the timer to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as indicated by using 1 in the example) can mean setting the timer to a predetermined second value. As another example, if cache policy A uses a data type specifier (e.g., for prefetched data, demand-fetched data, etc.), configuring cache policy A in the first configuration (i.e., as indicated by using 0 in the example) can mean setting the data type specifier to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as indicated by using 1 in the example) can mean setting the data type specifier to a predetermined second value.

[0067] The cache policy manager divides the test regions into competing groups of test regions and records the performance metrics of the competing groups of test regions while performing cache operations (step 902). For this operation, the cache policy manager divides the test regions into competing groups of test regions such that each test region is included in each competing group of test regions alone with the remaining test regions. In other words, the cache policy manager divides the test regions into one-to-many competing groups such that each of the individual test regions competes separately against all the other test regions within each competing group of test regions. FIG. 10 is a block diagram showing test regions for one-to-many testing according to some embodiments. As seen in FIG. 10, four test regions are divided into four competing groups 1000-1006 of test regions, and each of the competing groups 1000-1006 of test regions includes a first set of test regions having only one of the test regions and a second set of test regions having the remaining test regions together. For example, the competing group 1000 of test regions includes a set 1008 of test regions having test regions where cache policies A and B are in a first configuration and a set 1010 of test regions having the remaining test regions.

[0068] To record the performance metrics of contention groups 1000 - 1006 in the test area, the cache policy manager records performance metrics that identify the relative performance of the configurations of cache policies A and B in the contention groups of the test area. For example, in some embodiments, the cache policy manager uses individual saturation push - pull counters to track misses (i.e., requests where a copy of an instruction and / or data was not found in the test area) for each contention group in the test area. In these embodiments, the cache policy manager starts the counter for each contention group in the test area with an initial value, and if a miss is encountered in the first set of test areas that includes a single test area (e.g., test area set 1008), the counter is incremented (e.g., increment, double / shift, etc.), and if a miss is encountered in the second set of test areas that includes the remaining test areas (e.g., test area set 1010), the counter is decremented (e.g., decrement, halve / shift, etc.). Thus, the counter for each contention group of test areas is pushed / incremented for events that occur for the first set of test areas within that contention group of test areas and pulled / decremented for events that occur for the second set of test areas within that contention group of test areas (changing up to a saturation value such as 16 or 0). In some embodiments, the cache policy manager collects / records performance metrics for a specified amount of time (e.g., N seconds, where N is 0.5, 1, or another value) until a predetermined number of cache operations are executed and / or based on one or more other time values.

[0069] In some embodiments, the amount by which the counter increases for the first set of test regions is greater than the amount by which the counter decreases for the second set of test regions. This can help balance the impact on the counters of events occurring in the first set of test regions and the second set of test regions due to differences in the sizes of the sets of test regions. In other words, as an example, using the misses in the contention group 1000 of test regions, if the misses are substantially equally distributed among the test regions (as can generally be expected), the number of misses encountered in the set 1008 of test regions should be 1 / 3 of the number of misses encountered in the set 1010 of test regions. Thus, in some embodiments, the counter maintained for a contention group of test regions increases three times more when a miss is encountered in the set 1010 of test regions than the amount by which the counter decreases when a miss is encountered in the set 1008 of test regions, in order to balance the effect on the counter.

[0070] Next, the cache policy manager determines a particular contention group of test regions that best meets the performance metric target value based on the recorded performance metrics (step 904). For this operation, the cache policy manager compares the performance metrics of the contention groups of test regions to each other to find the performance metric that best meets the performance metric target value. For example, in some embodiments, the cache policy manager checks the push-pull counters described above for the contention groups of test regions and determines the contention group of test regions that best meets the performance metric target, such as when a particular value of the push-pull counter indicating the number of misses, etc., is lower for one of the predetermined ones among the contention groups of test regions. As seen in FIG. 10, the winning contention group 1012 of test regions is the contention group of test regions that best meets the performance metric target.

[0071] The cache policy manager then selects the selected configuration of at least one of the two or more cache policies from the configuration values of the specified test area from among the specific conflict groups of the test area (step 906). In some embodiments, the specified test area is a single test area within a specific / winning group of test areas, such as 10 test areas within the winning group 1012 of the test area. Thus, for this operation, the cache policy manager then selects the selected configuration of at least one of the two or more cache policies from the configuration values of a single test area within a specific group of test areas. The cache policy manager then causes the cache controller to use the selected configuration value when using at least one cache policy within the main area of the cache memory (e.g., as shown in step 504 of FIG. 5).

[0072] (Process for Executing Tests for Each Area) In some embodiments, the cache policy manager (e.g., cache policy manager 302) performs per-area tests of the configurations of two or more cache policies. FIG. 11 is a flowchart showing a process for performing per-area tests of the configurations of two or more cache policies according to some embodiments. Note that the operations shown in FIG. 11 are presented as a general example of operations performed by some embodiments. Operations performed by other embodiments include different operations, operations performed in a different order, and / or operations performed by different entities or functional blocks. In some embodiments, the process shown in FIG. 11 is performed as part of step 502 of FIG. 5. In these embodiments, in other words, the configuration values for at least one cache policy are selected using the per-area tests shown in FIG. 11.

[0073] Generally, in per-region testing, combinations of two or more cache policies are used to perform cache operations in each of multiple test regions within the cache, and different configuration values are used for combinations of two or more cache policies within each test region. The cache policy manager collects performance metrics representing the performance of each test region. The cache policy manager then uses the performance metrics to determine a "winning" test region, where the "winning" test region best meets the goal of the performance metric (e.g., the goal of the number of misses, etc.). In other words, the test regions are pitted individually against each of the other test regions to find the winning test region among all the test regions. Subsequently, the configuration value used for subsequent cache operations in the main region of the cache is selected from among the configuration values of the winning test region.

[0074] In the process shown in FIG. 11, as an example of a combination of cache policies being tested, a combination of cache policies A and B (e.g., a replacement cache policy and a storage cache policy) is used. However, in some embodiments, three or more cache policies are tested with the operations of FIG. 11 adjusted accordingly. Further, in the process shown in FIG. 11, it is assumed that the configuration value can have only two values (e.g., 0 / 1, on / off, etc.), i.e., the configuration can be set only in two ways or operating states. However, in some embodiments, some or all of the cache policies have three or more values (can be set to three or more values, etc.), or use at least some of the configuration values that use multiple configuration values, and the operations of FIG. 11 are adjusted accordingly.

[0075] The process shown in FIG. 11 begins with the cache controller performing cache operations on test areas within the cache memory (e.g., cache memory 304), where each test area has different configuration values for a combination of two cache policies being tested (step 1100). For this operation, the cache controller is caused (e.g., caused by a request of the cache policy manager, caused by an instruction of the cache policy manager, etc.) by the cache policy manager (e.g., cache policy manager 302) and performs cache operations in each test area such as storing a copy of the instruction and / or data, accessing the stored copy of the instruction and / or data, evicting / replacing the existing stored copy of the instruction and / or data with the incoming copy of the instruction and / or data. In each test area, the cache controller performs cache operations using a predetermined configuration out of two configurations for each of cache policies A and B. For example, using 0 and 1 to generally represent the first and second configurations of the cache policy, cache policies A and B can be configured in four test areas such as the cache policy configurations shown in FIG. 6. In other words, in the first test area, both cache policies A and B are set to the first configuration represented by 00, in the second test area, cache policy A is in the first configuration, cache policy B is in the second configuration represented by 01, in the third test area, cache policy A is in the second configuration, cache policy B is in the first configuration represented by 10, etc.

[0076] The "0" and "1" used in the examples of FIG. 11 and elsewhere in this specification for cache policies A and B are used to identify or indicate the first and second configurations of cache policies A and B, but it should be noted that 0 and / or 1 are not necessarily the values actually used when configuring or testing the cache policy. In some embodiments, one or more settings, values, thresholds, counters, and / or other values can be actually set to configure cache policies A and B in the first and second configurations. For example, if cache policy A uses a timer, configuring cache policy A in the first configuration (i.e., as indicated by using 0 in the example) can mean setting the timer to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as indicated by using 1 in the example) can mean setting the timer to a predetermined second value. As another example, if cache policy A uses a data type specifier (e.g., for prefetched data, demand-fetched data, etc.), configuring cache policy A in the first configuration (i.e., as indicated by using 0 in the example) can mean setting the data type specifier to a predetermined first value, and configuring cache policy A in the second configuration (i.e., as indicated by using 1 in the example) can mean setting the data type specifier to a predetermined second value.

[0077] The cache policy manager records the performance metrics of the test areas while performing the cache operation (step 1102). For this operation, the cache policy manager records performance metrics that identify the relative performance of the configurations of cache policies A and B in each test area. For example, in some embodiments, the cache policy manager uses individual counters to track the misses of each test area (i.e., requests where a copy of an instruction and / or data was not found in the test area). In these embodiments, the cache policy manager starts the counter for each test area at 0 and, when a miss is encountered in a respective test area, increments (e.g., increments, doubles / shifts, etc.) the counter for that test area. When any counter in a test area increases and reaches the maximum value of the counter (e.g., the value of a 4-bit counter is 15), the cache policy manager decreases all counters in a specified manner (e.g., divides by half / shift, truncates, etc.) and then continues to increment the counters as described above. In some embodiments, the cache policy manager collects / records performance metrics for a specified amount of time (e.g., N seconds, where N is 0.5, 1, or another value) until a predetermined number of cache operations are performed and / or based on one or more other time values.

[0078] Next, the cache policy manager determines the specific test area that best meets the performance metric target value based on the recorded performance metrics (step 1104). For this operation, the cache policy manager compares the performance metrics of the test areas with each other to find the performance metric that best meets the performance metric target value. For example, in some embodiments, the cache policy manager checks the above counters of the test areas to determine the test area that best meets the performance metric target, such as when a specific value of each counter indicating the number of misses in that test area is lower.

[0079] The cache policy manager then selects the selected configuration of at least one of the two or more cache policies from the configuration values of the test regions that best meet the performance metric target values (step 1106). For this operation, the cache policy manager selects the selected configuration of at least one of the two or more cache policies from the configuration values of the winning test regions. The cache policy manager then causes the cache controller to use the selected configuration values when using at least one cache policy within the main area of the cache memory (e.g., as shown in step 504 of FIG. 5).

[0080] In some embodiments, at least one electronic device (e.g., electronic device 100) uses code and / or data stored in a non-transitory computer-readable storage medium to perform some or all of the operations described herein. More specifically, at least one electronic device reads code and / or data from the computer-readable storage medium and executes the code and / or uses the data when performing the described operations. The computer-readable storage medium may be any device, medium, or combination thereof that stores the code and / or data used by the electronic device. For example, the computer-readable storage medium can include, but is not limited to, flash memory, random access memory (e.g., eDRAM, RAM, SRAM, DRAM, DDR4 SDRAM, etc.), non-volatile RAM (e.g., phase change memory, ferroelectric random access memory, spin transfer random access memory, magnetic random access memory, etc.), read-only memory (ROM), and / or magnetic or optical storage media (e.g., disk drive, magnetic tape, CD, DVD, etc.).

[0081] In some embodiments, one or more hardware modules perform the operations described herein. For example, the hardware module can include, but is not limited to, one or more central processing units (CPUs) / CPU cores, graphics processing units (GPUs) / GPU cores, application specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), compressors or encoders, computing units, embedded processors, accelerated processing units (APUs), controllers, and / or other functional blocks. When the circuit configuration (e.g., integrated circuit elements, discrete circuit elements, etc.) within such a hardware module is activated, the circuit configuration performs some or all of the operations. In some embodiments, the hardware module includes a general-purpose circuit such as an execution pipeline that performs operations when executing instructions (e.g., program code, firmware, etc.), a computing or processing unit, etc. In some embodiments, the hardware module includes a special-purpose or dedicated circuit configuration that performs the operations, and in some cases, includes a circuit configuration that performs some or all of the operations "within the hardware" without executing instructions.

[0082] In some embodiments, a data structure representing some or all of the functional blocks and circuit elements described herein (e.g., electronic device 100, cache 300, cache policy manager 302, or some portions thereof) is stored in a persistent computer-readable storage medium that includes a database or other data structure that can be read by an electronic device and used directly or indirectly to manufacture hardware including the functional blocks and circuit elements. For example, the data structure can be an operational-level description or a register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool that can synthesize the description to generate a netlist including a list of transistors / circuit elements from a synthesis library representing the functionality of the hardware including the above functional blocks and circuit elements. The netlist can then be placed and routed to generate a data set describing the geometric shapes to be applied to a mask. The mask can then be used in various semiconductor processing steps to manufacture a semiconductor circuit or circuit (e.g., an integrated circuit) corresponding to the above functional blocks and circuit elements. Alternatively, a database on a computer-accessible storage medium can be, optionally, a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data.

[0083] In this description, variables or unspecified values (i.e., general descriptions of values that do not include specific examples of values) are represented by letters such as N, M, X, etc. As used herein, although similar letters may be used in different places in this description, the variables and unspecified values in each case are not necessarily the same, i.e., there may be variables and values intended for some or all of the general variables and unspecified values. In other words, specific examples of values of N, as well as any other letters used to represent variables and unspecified values in this description, are not necessarily related to each other.

[0084] As used herein, the expressions "etc." or "and the like" are intended to indicate one and / or case, i.e., the equivalent of "at least one of" the elements within the list to which the "etc." is associated. For example, in the description "an electronic device performs a first operation, a second operation, etc.", the electronic device performs at least one of the first operation, the second operation, and other operations. Additionally, the elements within a list associated with "etc." are merely examples from a set of examples, and some of the examples may not appear in some embodiments.

[0085] The above description of the embodiments is presented for purposes of illustration and explanation only. They are not intended to be exhaustive or to limit the embodiments to the disclosed form. Accordingly, many modifications and variations will be apparent to those skilled in the art. Further, the above disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. An electronic device, a cache including a cache controller and a cache memory, and a cache policy manager, wherein the cache policy manager causes the cache controller to use a combination of two or more cache policies for cache operations in each of a plurality of test areas in the cache memory, and different configuration values of the combination of the two or more cache policies are used in each test area, selects a configuration value of at least one cache policy among the combination of the two or more cache policies based on a performance metric of cache operations, and causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main area of the cache memory, is configured to perform the above, an electronic device.

2. In order to select the configuration value, the cache policy manager records a performance metric regarding a conflict group of test areas while the cache controller uses the combination of the two or more cache policies for cache operations in the plurality of test areas, and each of the conflict groups of test areas includes first and second groups of test areas where the same configuration value is used for all of the test areas, selects the configuration value from among the conflict groups of test areas that satisfy a corresponding group performance metric target, is further configured to perform the above, the electronic device according to Claim 1.

3. When recording the performance metric, the cache policy manager is configured to update a counter related to a conflict group of test areas, and the updating includes, for each conflict group of test areas, increasing a counter related to that conflict group of test areas when an event occurs for a first group of test areas in the conflict group of test areas, and decreasing a counter related to that conflict group of test areas when an event occurs for a second group of test areas in the conflict group of test areas, the electronic device according to Claim 2.

4. When selecting the configuration value, the cache policy manager for the current contention group in the test area, starting from the first contention group in the test area and reaching the final contention group in the test area determine a specific group of test areas in the current contention group of the test area that meets the performance metric target value among the first or second groups of test areas in the current contention group of the test area based on the counter associated with the current contention group of the test area; set the specific group of test areas as the current contention group of the test area; select the configuration value from among the configuration values of the final contention group of the test area; is configured to perform The electronic device according to claim 3.

5. To select the configuration value, the cache policy manager while the cache controller uses a combination of the two or more cache policies for cache operations in the plurality of test areas, record a performance metric for the contention groups in the test area, where each contention group in the test area has a first set of test areas including one test area and a second set of test areas including the remaining test areas; select the configuration value from among the contention groups of test areas that meet the group performance metric target; is configured to perform The electronic device according to claim 1.

6. When recording the performance metric, the cache policy manager is configured to update a counter associated with the contention group in the test area, wherein the updating for each contention group in the test area, increase the counter associated with that contention group in the test area when an event occurs for the one test area in the first set of test areas in the contention group in the test area; and decrease the counter associated with that contention group in the test area when an event occurs for any of the remaining test areas in the second set of test areas in the contention group in the test area, The electronic device according to claim 5.

7. When increasing the counter associated with a predetermined contention group in the test area, the cache policy manager configured to increase the counter in proportion to the ratio of the number of test regions in the first set of test regions and the second set of test regions in the predetermined conflict group of the test region The electronic device according to claim 6.

8. When selecting the configuration value, the cache policy manager determines a specific conflict group of test regions where the counter meets the performance metric target value based on the counter related to the conflict group of test regions selects the configuration value from among the configuration values used for the one test region in the first set of test regions in the specific conflict group of test regions is configured to perform The electronic device according to claim 6.

9. To select the configuration value, the cache policy manager records the performance metric for each test region while the cache controller uses a combination of the two or more cache policies for cache operations in the plurality of test regions selects the configuration value from test regions that meet the corresponding group performance metric target is configured to perform The electronic device according to claim 1.

10. When using a combination of the two or more cache policies for cache operations, the cache controller in accordance with each of the two individual cache policies stores data in cache blocks within the test region of the cache memory accesses the data of the cache blocks within the test region of the cache memory evicts the data of the cache blocks within the test region of the cache memory is configured to control at least one of The electronic device according to claim 1.

11. When using a combination of the two or more cache policies for cache operations, the cache controller a timing policy that indicates the period during which a specific type of data is held in a cache block within the cache memory a data copy policy that indicates whether a copy of a specific type of data is stored in a cache block within the cache memory A replacement policy that instructs conditions under which data is evicted from the cache memory to clear space for storing other data in the cache memory, A modified data write-back policy for data in cache blocks within the cache memory, is configured to use one or more of The electronic device according to claim 1.

12. The plurality of test areas in the cache memory have a first size in byte units, The main area of the cache memory has a second size in byte units, The second size is one digit or more larger than the first size, The electronic device according to claim 1.

13. A method for performing a cache operation in an electronic device including a cache including a cache memory, a cache controller, and a cache policy manager, The cache policy manager causes the cache controller to use a combination of two or more cache policies for cache operations in each of a plurality of test areas in the cache memory, wherein different configuration values of the combination of the two or more cache policies are used in each test area, The cache policy manager selects a configuration value of at least one cache policy among the combination of the two or more cache policies based on a performance metric of the cache operation, The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in the main area of the cache memory, Method.

14. Selecting the configuration value while the cache controller uses the combination of the two or more cache policies for cache operations in the plurality of test areas, the cache policy manager records a performance metric regarding a conflict group of test areas, each of the conflict groups of test areas includes a group of first and second test areas that match for a predetermined configuration value, the cache policy manager selects the configuration value from among the conflict groups of test areas that satisfy a corresponding group performance metric target, The method of claim 13.

15. Recording the performance metric includes the cache policy manager updating a counter associated with a contention group in the test area, wherein the updating increases the counter associated with the contention group in the test area when an event occurs for a first group of test areas in the contention group in the test area, and decreases the counter associated with the contention group in the test area when an event occurs for a second group of test areas in the contention group in the test area, The method of claim 14.

16. Selecting the configuration value for the current contention group in the test area, starting from the first contention group in the test area and reaching the final contention group in the test area, the cache policy manager determines a specific group of test areas that meets the performance metric target value among the first or second group of test areas in the current contention group in the test area based on the counter associated with the current contention group in the test area, the cache policy manager sets the specific group of test areas as the current contention group in the test area, and the cache policy manager selects the configuration value from among the configuration values of the final contention group in the test area, The method of claim 15.

17. Selecting the configuration value is for the cache policy manager to record a performance metric for a contention group in the test area while the cache controller uses a combination of the two or more cache policies for cache operations in the plurality of test areas, where each contention group in the test area has a first set of test areas including one test area and a second set of test areas including the remaining test areas, and the cache policy manager selects the configuration value from among the contention groups in the test area that meet the group performance metric target, The method of claim 13.

18. Recording the performance metric includes the cache policy manager updating a counter associated with the contention group in the test area, Said updating includes, for each conflict group of test regions, when an event occurs for said one test region of said first set of test regions in a conflict group of test regions, incrementing a counter associated with that conflict group of test regions; and when an event occurs for any of said remaining test regions of said second set of test regions in a conflict group of test regions, decrementing a counter associated with that conflict group of test regions, The method of claim 17.

19. Incrementing a counter associated with a given conflict group of test regions includes said cache policy manager incrementing said counter in proportion to a ratio of a number of test regions of said first set of test regions and a number of test regions of said second set of test regions in said given conflict group of test regions, The method of claim 18.

20. Said selecting the configuration value includes said cache policy manager determining a particular conflict group of test regions for which said counter meets a performance metric target value based on a counter associated with said conflict group of test regions; and said cache policy manager selecting said configuration value from among configuration values used for said one test region of said first set of test regions in said particular conflict group of test regions, The method of claim 18.

21. Said selecting the configuration value includes said cache policy manager recording a performance metric for each test region while said cache controller uses a combination of said two or more cache policies for cache operations in said plurality of test regions; and said cache policy manager selecting said configuration value from test regions that meet a corresponding group performance metric target, The method of claim 13.

22. Using a combination of said two or more cache policies for cache operations includes in accordance with each of two individual cache policies, storing data in cache blocks within said test region of said cache memory; accessing data in cache blocks within said test region of said cache memory; and evicting data in cache blocks within said test region of said cache memory, including controlling at least one of them The method of claim 13

23. A method of operating a processor, comprising: using a combination of two or more cache policies for cache operations in each of a plurality of test regions in a cache memory, wherein different configuration values of the combination of the two or more cache policies are used in each test region, and the combination of the two or more cache policies is configured to be different in each test region; selecting a configuration value of at least one cache policy of the combination of the two or more cache policies based on a performance metric of cache operations while using different configuration values of the combination of the two or more cache policies in the test region, wherein the configuration value is used in a predetermined test region among the test regions having a performance metric that meets a performance metric target; using the selected configuration value when using the at least one cache policy in a main region of the cache memory; and A method

24. The cache policy manager is configured to individually test different combinations of two or more cache policies in a plurality of different test regions using the different combinations. The electronic device of claim 1

Images