Speed detection device and speed detection method

Abstract

To provide a speed detection device that can perform high-resolution rotational speed detection calculations with little detection delay regardless of the type of encoder.SOLUTION: A speed detection device includes: a phase latch trigger selection processing unit 3 that selects a trigger signal according to the type of encoder 1 and outputs it as a phase detection trigger for speed detection; a phase information latch circuit 4 that uses the trigger to latch and hold phase information θenc obtained by performing phase detection processing on the output of the encoder 1; a phase detection buffer 5-1 to 5-n that stores information from multiple times before the phase information held in the latch circuit 4; and a rotation speed detection value calculation unit that calculates rotation speed detection value Nr (subtractor 8, multiplier 9) based on a difference θcal between the current phase information of the latch circuit 4 and the oldest phase information stored in the buffers 5-1 to 5-n and time information Tcal for rotation speed detection calculation, which is obtained by multiplying the rotation speed detection period Tsmp by a coefficient n corresponding to the number of buffers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a system having a detector that detects the phase and rotation speed of an electric motor (hereinafter sometimes referred to as a motor), and in particular to a technical field related to a mechanism for reducing the detection delay of the rotation speed and increasing the detection resolution, with the aim of detecting the rotation speed with high precision in order to control the rotation speed and torque of the motor with high precision. [Background technology]

[0002] Conventionally, a device for detecting the rotation speed of an electric motor has been proposed, for example, as described in Patent Document 1.

[0003] Patent Document 1 describes a rotation speed detection method for a pulse encoder. The method in Patent Document 1 aims to suppress offset errors in rotation speed detection that occur when there is jitter in the pulse output of the pulse encoder. To suppress this, the method is configured with a pulse phase buffer and a pulse generation time buffer, and calculates the rotation speed from the phase and time of several previous pulses. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-25391 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 only mentions pulse encoders. Therefore, the rotation speed detection configuration is for pulse encoders, and there is a problem that it cannot be applied as is to encoders that detect discrete values at regular intervals using encoder phase information communication methods or the like.

[0006] Furthermore, when controlling a motor, rotation speed information is used for various controls. For this reason, it is required to detect the rotation speed with high accuracy and without delay. To reduce the delay in the rotation speed, the detection cycle needs to be made faster, but it is well known that a faster cycle reduces the detection resolution. Furthermore, to increase the detection resolution, the detection cycle needs to be slowed down.

[0007] The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a speed detection device and a speed detection method that can perform rotation speed detection calculations with little detection delay and high resolution, regardless of the type of encoder. [Means for solving the problem]

[0008] In order to solve the above problem, the speed detection device according to claim 1 is A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the latch circuit; and a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between the current phase information held in the latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by multiplying the rotation speed detection period by a coefficient corresponding to the number of the phase detection buffers.

[0009] The speed detection device according to claim 2 is A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a phase information latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a time information latch circuit that latches phase time information obtained when encoder information is acquired by performing time processing synchronized with phase detection processing on the output of the encoder counter using the speed detection phase detection trigger, and holds the information as a rotation speed detection period; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the phase information latch circuit; a plurality of phase time buffers for storing information of a plurality of rotation speed detection periods earlier than the time information latch circuit; and a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between the current phase information held in the phase information latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by calculating the difference between the current rotation speed detection period held in the time information latch circuit and the oldest rotation speed detection period stored in the phase time buffer.

[0010] The speed detection device according to claim 3 is A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a phase information latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a time information latch circuit that latches phase time information obtained when encoder information is acquired by performing time processing synchronized with phase detection processing on the output of the encoder counter using the speed detection phase detection trigger, and holds the phase time information as a rotation speed detection period; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the phase information latch circuit; a plurality of phase time buffers for storing information of a plurality of rotation speed detection periods earlier than the time information latch circuit; a buffer selection processing unit that selects a phase detection buffer and a phase time buffer to be used for calculation based on the relationship between the rotation speed detection resolution of the encoder and the desired rotation speed detection resolution; and a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between the current phase information held in the phase information latch circuit and the phase information stored in the phase detection buffer selected by the buffer selection processing unit, and rotation speed detection calculation time information obtained by calculating the difference between the current rotation speed detection period held in the time information latch circuit and the rotation speed detection period stored in the phase time buffer selected by the buffer selection processing unit.

[0011] The speed detection device according to claim 4 is the device according to claim 3, The buffer selection processing unit is characterized in that it selects the number of buffers in which the relationship between the number of buffers, encoder resolution, rotation speed detection processing period, and desired rotation speed detection resolution satisfies the condition of equation (13), and determines the phase detection buffer and phase time buffer indicated by the number of buffers as the phase detection buffer and phase time buffer to be used for calculation.

[0012]

number

[0013] The speed detection method according to claim 5 comprises: A speed detection method using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing step in which a phase latch trigger selection processing unit selects a trigger signal corresponding to the type of the encoder from a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a latch step in which a latch circuit latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a storage step in which a phase detection buffer stores information of a plurality of previous times of the phase information held in the latch circuit; and a rotation speed detection value calculation step in which the rotation speed detection value calculation unit calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between the current phase information held in the latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by multiplying the rotation speed detection period by a coefficient corresponding to the number of the phase detection buffers. [Effects of the Invention]

[0014] (1) According to the inventions set forth in claims 1 to 5, it is possible to perform rotation speed detection calculations with little detection delay and high resolution, regardless of the type of encoder. (2) According to the invention described in claim 2, the phase time information when the encoder information is acquired is used, so that the rotation speed detection calculation can be performed taking into consideration the acquisition cycle of the encoder phase information. (3) According to the inventions set forth in claims 3 and 4, it is possible to perform rotation speed detection calculations with the required rotation speed detection resolution. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a diagram showing a speed detection configuration according to the first embodiment of the present invention. [Figure 2] 10 is an explanatory diagram showing the operation when an external interrupt signal trigger is applied as a phase detection trigger for speed detection of the present invention. FIG. [Figure 3] 10 is an explanatory diagram showing the operation when a communication interrupt signal trigger is applied as a phase detection trigger for speed detection of the present invention. FIG. [Figure 4]FIG. 10 is a diagram illustrating a speed detection configuration according to a second embodiment of the present invention. [Figure 5] 10 is a timing chart illustrating an operation taking into consideration an error in processing time in the second embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing a speed detection configuration according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. [Example]

[0017] Figure 1 is a speed detection configuration diagram for the proposed method, showing the configuration of a speed detection device according to Example 1. In Figure 1, reference numeral 1 denotes an encoder that detects the phase and rotation speed of a motor, and reference numeral 2 denotes a phase detection processing unit that performs phase detection processing according to the type of encoder on the output of encoder 1 and outputs the encoder-detected phase θenc (phase information).

[0018] 3 is a phase latch trigger selection processing unit 3 having a trigger selection switch 13 that selects one of multiple trigger signals depending on the type of encoder indicated by the input encoder selection flag (enc_flg) and outputs it as a phase detection trigger (Trig_Ndet) for speed detection.

[0019] In this embodiment, the phase latch trigger selection processing unit 3 sets an external interrupt signal trigger (Trig_eirq), a communication interrupt signal trigger (Trig_comrq), an internal interrupt signal trigger (Trig_iirq), etc. as multiple trigger signals, but other triggers may also be set.

[0020] Reference numeral 4 denotes a phase information latch circuit that latches the encoder detection phase θenc output from the phase detection processing unit 2 using the speed detection phase detection trigger Trig_Ndet output from the trigger selection switch 13 as an enable signal, and holds it as the encoder detection phase θdet for speed detection.

[0021] 5 -1 ~5 -n is a phase detection buffer that reads out the speed detection encoder detected phase θdet of the phase information latch circuit 4 and stores information from a number of detection periods ago (the previous value of θdet to the value n times ago).

[0022] 6 is a comparison of the current phase information (current speed detection encoder detected phase θdet) latched in the phase information latch circuit 4 and the oldest phase information stored in the phase detection buffer (phase detection buffer 5 -n and outputs rotation speed detection calculation phase information (rotation speed detection calculation phase θcal).

[0023] 7 is the rotation speed detection period Tsmp and the phase detection buffer 5 -1 ~5 -n The multiplier multiplies the number N of the input signals by a coefficient (gain) corresponding to the number N of the input signals and outputs time information for rotation speed detection calculation (time Tcal for rotation speed detection calculation).

[0024] Reference numeral 8 denotes a divider that divides the output of the subtractor 6 (phase θcal for rotation speed detection calculation) by the output of the multiplier 7 (time Tcal for rotation speed detection calculation), and 9 denotes a multiplier that multiplies the output of the divider 8 by 1 / 6, which is a coefficient calculated in advance from 60 [s] ÷ 360 [°], and outputs the rotation speed detection value Nr.

[0025] the phase detection buffer 5 -1 ~5 -n , subtractor 6 , multipliers 7 and 9 , and divider 8 constitute a speed detection processing unit 100 .

[0026] Here, rotation speed detection (speed detection) can be expressed by the following equation (1).

[0027]

number

[0028] Phase detection difference [°] = current phase detection value [°] - previous phase detection value [°] As can be seen from equation (1), shortening the rotation speed detection cycle reduces the resolution of the rotation speed detection value. However, slowing down the rotation speed detection cycle in an attempt to improve the resolution of the rotation speed detection value increases the detection delay. When the detection delay increases, it causes delays in responding to commands and load fluctuations, deteriorating control performance.

[0029] Next, the operation of the system shown in FIG. 1 will be described.

[0030] The phase detection value (encoder detected phase θenc) detected by the phase detection processing unit 2 from the encoder information (output of the encoder 1) is latched and held by the phase information latch circuit 4 using the trigger signal (Trig_Ndet) output from the phase latch trigger selection processing unit 3.

[0031] By holding the phase detection value with a trigger signal, the phase seen by the speed detection processing unit 100 becomes a signal held at the speed detection cycle regardless of the encoder used, and can be treated as the same phase information.

[0032] The phase latch trigger selection processing unit 3 selects a trigger signal according to the type of encoder. In this example, the operation will be explained using the external interrupt signal trigger (Trig_eirq), communication interrupt signal trigger (Trig_comrq), and internal interrupt signal trigger (Trig_iirq) as examples of trigger signals.

[0033] First, we will explain the operation when applying the external interrupt signal trigger (Trig_eirq) and the internal interrupt signal trigger (Trig_iirq). The external interrupt signal trigger and the internal interrupt signal trigger have similar operation. The external interrupt signal and the internal interrupt signal determine the signal to be used depending on whether the device that runs the rotation speed detection process uses an external timer or an internal timer as the basis for determining the rotation speed detection process period.

[0034] FIG. 2 shows an example of the external interrupt signal trigger generating timer (Trig_eirq generating timer), the external interrupt signal trigger Trig_eirq, the encoder detected phase θenc, and the speed detection encoder detected phase θdet when the trigger selection switch 13 selects the external interrupt signal trigger Trig_eirq.

[0035] At times t1, t2, and t3 when the external interrupt signal trigger Trig_eirq is input to the enable terminal EN of the phase information latch circuit 4, the value of the encoder detected phase θenc at each of those times is latched in the phase information latch circuit 4 and held as the encoder detected phase θdet for speed detection.

[0036] In the case of the internal interrupt signal trigger Trig_iirq, the Trig_eirq generation timer and Trig_eirq in FIG. 2 can be replaced with the Trig_iirq generation timer and Trig_iirq.

[0037] For example, in the case of a pulse encoder as in Patent Document 1, the phase detection period and the rotation speed detection period are not synchronized. In such a case, it is necessary to hold the phase information once at the rotation speed detection period. Since the rotation speed detection period Tsmp acts as an enable signal for the external interrupt signal trigger, the information on θenc is held once at the external interrupt signal trigger Trig_eirq and set as θdet. Therefore, it can be seen that θdet becomes a signal with a Tsmp period.

[0038] Next, an example of operation when the communication interrupt signal trigger Trig_comrq is applied is shown in Figure 3. Figure 3 shows an example of the phase determination signal (a signal that determines the phase, set in the system at a cycle faster than speed detection), the communication interrupt signal trigger Trig_comrq, the encoder detection phase θenc, and the speed detection encoder detection phase θdet when exchanging phase information with an encoder via communication.

[0039] When phase information is exchanged with an encoder via communication, the phase detection period and rotation speed detection period have the relationship shown in equation (2) below.

[0040]

number

[0041] If the condition of equation (2) is not satisfied, the detection cycle used for detecting the rotation speed will differ from the detection cycle for the phase detection difference information, and the rotation speed will not be detected accurately.

[0042] Furthermore, when exchanging phase information with an encoder via communication, a communication delay inevitably occurs, and it is necessary to store the phase information while taking this communication delay into consideration.

[0043] In FIG. 3, the phase determination signal is established at time tz, and then the encoder detected phase θenc is determined at time t1, which is delayed by the communication time Tx.

[0044] At this time, a communication interrupt signal trigger Trig_comrq is output, and the information on θenc is temporarily held by the phase information latch circuit 4 at the time of Trig_comrq, and is set as θdet.

[0045] Thereafter, at times t2 and t3 when the communication interrupt signal trigger Trig_comrq is input, the value of the encoder detected phase θenc at each of these times is latched by the phase information latch circuit 4 and held as the speed detection encoder detected phase θdet. Therefore, it can be seen that θdet becomes a signal with a Tsmp period.

[0046] Next, the operation of the rotation speed detection process will be described. The speed detection encoder detection phase θdet is input to the phase detection buffer 5 -1 ~5 -n The phase detection difference for calculating the rotation speed detection value is the current phase detection value and the phase detection value output from the buffer. -1 When the value of the phase detection buffer 5 is used, the rotation speed detection value is expressed by equation (3). -2 When the value of is used, the rotation speed detection value is given by equation (4).

[0047]

number

[0048]

number

[0049] The denominator value of equation (4) is larger than that of equation (3), and equation (4) has better resolution. Although the denominator times are different, equations (3) and (4) are updated at the same cycle, so the detection delay is the same.

[0050] Buffer 5 used for phase detection difference -1 ~5 -n If the number of times is n, the time in the denominator also needs to be n times the detection period, so the detection period (Tsmp) is multiplied by n in multiplier 7. The phase detection difference (output of subtractor 6) is divided by n times the detection period (output Tcal of multiplier 7) in divider 8, and then multiplied by 1 / 6 in multiplier 9 to calculate the rotation speed detection value Nr.

[0051] Here, the phase detection buffer 5 -1 ~5 -n The number of buffers may be set to a number that satisfies the required rotation speed detection value, and is the number of buffers shown in equation (5).

[0052]

number

[0053] As described above, according to the first embodiment, it is possible to perform rotation speed detection calculation with little detection delay and high resolution, regardless of the type of encoder. [Example]

[0054] Fig. 4 shows the configuration of velocity detection in Example 2. In Example 2, in order to accurately record the phase time, a process for holding the phase time in synchronization with the phase detection is added to the configuration of Fig. 1 (Example 1), and a buffer is also provided for the phase time.

[0055] 4, the same parts as those in Fig. 1 are designated by the same reference numerals, and the description of those parts will be omitted. 21 is a phase time measurement counter. 22 is a phase time processing unit that performs time processing on the output of the phase time measurement counter 21 in synchronization with the phase detection of the phase detection processing unit 2, and outputs phase time information Tθenc at the time of encoder information acquisition.

[0056] Reference numeral 24 denotes a time information latch circuit that latches the phase time information Tθenc output from the phase time processing unit 22 using the speed detection phase detection trigger Trig_Ndet output from the trigger selection switch 13 as an enable signal and holds it as the rotation speed detection period Tsmp.

[0057] twenty five -1 ~25 -n is a phase time buffer that reads out the rotation speed detection period Tsmp of the time information latch circuit 24 and stores information on the detection period several times before (the previous value of Tsmp to the value n times before).

[0058] 26 is a comparison of the current rotation detection period Tsmp latched in the time information latch circuit 24 and the oldest rotation detection period stored in the phase time buffer (phase time buffer 25 -n This is a subtractor that calculates the difference between the rotation speed detection period Tsmp[n] and the rotation speed detection period Tsmp[n], and outputs the time information (Tcal) for rotation speed detection calculation.

[0059] Reference numeral 8 denotes a divider that divides the output of subtractor 26 (rotation speed detection calculation time Tcal) from the output of subtractor 6 (rotation speed detection calculation phase θcal), and 9 denotes a multiplier that multiplies the output of divider 8 by 1 / 6, which is a coefficient calculated in advance from 60 [s] ÷ 360 [°], to output the rotation speed detection value Nr.

[0060] the phase detection buffer 5 -1 ~5 -n , Phase time buffer 25 -1 ~25 -n The subtractors 6 and 26, the divider 8, and the multiplier 9 constitute a speed detection processing unit 200.

[0061] Although the rotation speed detection process is performed at a constant cycle, the time at which phase information is acquired is not necessarily constant. For example, as in Patent Document 1, the phase of a pulse encoder is measured at the edge of a pulse, but the measurement cycle between pulses is not strictly the same as that of the rotation speed detection process.

[0062] Consider also the case where encoder information is obtained via communication. When the encoder information is obtained by sending a signal requesting encoder information from the CPU that performs the rotation speed detection process, the signal requesting encoder information from the CPU does not necessarily occur at a constant cycle. This is because the CPU has multiple processing cycles and priorities are set. Also, even within the same processing cycle, some processes may or may not be executed depending on conditions, and the processing volume within the same process may change depending on the process with higher priority or the conditions, so the cycle in which the speed detection process is actually processed is not necessarily constant.

[0063] A timing chart that takes processing time errors into consideration is shown in Figure 5. Like Figure 3, Figure 5 shows the operation when a communication interrupt signal trigger is applied, but the first and second rows from the top of Figure 5 show the phase determination signal, communication interrupt signal trigger Trig_comrq, in an ideal state, while the third and fourth rows from the top show the phase determination signal, communication interrupt signal trigger Trig_comrq, that takes processing time errors into consideration.

[0064] In FIG. 5, the phase determination signal is established at time tz, and then the encoder detected phase θenc is determined at time t1, which is delayed by the communication time Tx.

[0065] In an ideal state, the value of θenc at time t2 when the communication interrupt signal trigger Trig_comrq next rises is latched by the phase information latch circuit 4 and held as the speed detection encoder detected phase θdet, but when processing time error is taken into consideration, Trig_comrq rises at time t2', which is delayed from time t2 by the processing time error, so the value of θenc at time t2' is latched and held as θdet.

[0066] Therefore, during the period from time t1 to time t2', the first phase time buffer 25 -1 The rotation speed detection period is calculated by adding an error Terr1 (a value of the buffer in which the previous value of the rotation speed detection period is stored).

[0067] Furthermore, in an ideal state, the value of θenc at time t3 when the communication interrupt signal trigger Trig_comrq next rises is latched by the phase information latch circuit 4 and held as the speed detection encoder detected phase θdet, but when processing time error is taken into consideration, Trig_comrq rises at time t3', which is delayed from time t3 by the processing time error, so the value of θenc at time t3' is latched and held as θdet.

[0068] Therefore, during the period from time t2' to time t3', the rotation speed detection period Tsmp in the ideal state is equal to the second phase time buffer 25 -2 The rotation speed detection period is calculated by adding an error Terr2 (a value of the rotation speed detection period before last) to the period.

[0069] In this way, in an ideal state, the rotation speed detection cycle is constant, but errors in processing time cause deviations in the rotation speed detection cycle. In this case, a difference also occurs in the phase. Because a difference occurs in the phase, rotation speed detection cannot be performed accurately unless time is taken into consideration.

[0070] As described above, even if the speed processing cycle is fixed, the time at which phase information is acquired is not necessarily constant depending on the type of encoder, and if the phase is detected when there is a time lag, an error will occur in the phase difference, making it impossible to detect the rotation speed accurately.

[0071] Therefore, in this embodiment 2, in order to perform rotation speed detection with high accuracy, the error in the time at which phase information is acquired is taken into consideration and the Trig_Ndet output from the trigger selection switch 13 is held in the time information latch circuit 24 as an enabling signal regarding the phase time.

[0072] The stored value is then set as the rotation speed detection period (Tsmp) for the speed detection process. -1 ~25 -n The rotation speed detection calculation time (Tcal) for calculating the rotation speed detection value is the current rotation speed detection period and the rotation speed detection period output from the phase time buffer.

[0073] For example, the error from the ideal value of the rotation speed detection period when the number of phase time buffers is set to three will be explained below.

[0074] Error in the current value of rotation speed detection period and phase time acquisition: Terr0, Rotation speed detection period buffer 1 (phase time buffer 25 -1 ) and phase time acquisition error: Terr1, Rotation speed detection period buffer 2 (phase time buffer 25 -2 ) and phase time acquisition error: Terr2, Rotation speed detection period buffer 3 (phase time buffer 25 -3 ) and the error in phase and time acquisition: Terr3.

[0075] In this case, the rotation speed detection period calculation is expressed by equation (6), and the ideal rotation speed detection period calculation value is expressed by equation (7).The rotation speed detection value including error calculated by divider 8 and multiplier 9 is expressed by equation (8), and the ideal rotation speed detection value is expressed by equation (9).

[0076]

number

[0077]

number

[0078]

number

[0079]

number

[0080] As can be seen from these equations (6) to (9), the error that occurs when the rotation speed detection period is set to a fixed value can be compensated for in the second embodiment.

[0081] As described above, according to the second embodiment, in addition to the effects of the first embodiment, the phase time information at the time of acquiring the encoder information is used, so that the rotation speed detection calculation can be performed taking into account the acquisition period of the encoder phase information. [Example]

[0082] In addition to the configuration of the second embodiment, the third embodiment is configured to include a processing unit that selects which values to use in the phase detection buffer and the phase time buffer, and by selecting the optimal buffer depending on the encoder selection, it is possible to perform rotation speed detection calculation with the required rotation speed detection resolution.

[0083] Fig. 6 shows the configuration of speed detection in Example 3. In Fig. 6, the same parts as in Fig. 4 are designated by the same reference numerals, and the description of those parts will be omitted.

[0084] 30 selects the phase detection buffer 5 to be used for calculation based on the relationship between the rotation speed detection resolution of the encoder 1 and the required rotation speed detection resolution, based on the input encoder selection flag (enc_flg). -1 ~5 -n and phase time buffer 25 -1 ~25 -n The buffer selection processing unit generates and outputs a buffer selection signal.

[0085] 31 is a phase detection buffer (5 -1 ~5 -n The phase detection buffer selection switch 32 selects the phase time buffer (25) determined by the buffer selection signal. -1 ~25-n This is a phase time buffer selection switch that selects one of the buffers.

[0086] The buffer selection processing unit 30, phase detection buffer selection switch 31, and phase time buffer selection switch 32 select the number of buffers such that the relationship between the number of buffers, encoder resolution, rotation speed detection processing period, and desired rotation speed detection resolution satisfies the condition of equation (13) described below, and determine the phase detection buffer and phase time buffer indicated by the number of buffers as the phase detection buffer and phase time buffer to be used for calculation.

[0087] the phase detection buffer 5 -1 ~5 -n , Phase time buffer 25 -1 ~25 -n , subtractors 6 and 26 , divider 8 , multiplier 9 , buffer selection processing unit 30 , phase detection buffer selection switch 31 , and phase time buffer selection switch 32 constitute a speed detection processing unit 300 .

[0088] The buffer selection processing unit 30 sets the number of buffers to be used based on the required rotation speed detection resolution and the rotation speed detection resolution of the encoder to be used. The relationship between the required rotation speed detection resolution and the rotation speed detection resolution of the encoder is given by equation (10).

[0089]

number

[0090] Here, the encoder rotation speed detection resolution can be expressed by equation (11).

[0091]

number

[0092] Encoder resolution indicates the number of pulses per revolution for pulse encoders, and the number of bits for absolute encoders.

[0093] The rotation speed detection period is given by equation (12), and the number of buffers can be calculated from equation (13).

[0094]

number

[0095]

number

[0096] From equation (13), it can be seen that the minimum number of buffers differs depending on the encoder. The buffer selection processor 30 selects the number of buffers and determines which buffers to use depending on the encoder selection flag. By performing rotation speed detection processing using this selected buffer, it is possible to select the optimal number of buffers according to the encoder selection.

[0097] As described above, according to the third embodiment, in addition to the effects of the first and second embodiments, it is possible to perform rotation speed detection calculations with a required rotation speed detection resolution. [Explanation of symbols]

[0098] 1...Encoder 2...Phase detection processing section 3...Phase latch trigger selection processing section 4...Phase information latch circuit 5 -1 ~5 -n …phase detection buffer 6, 26...Subtractor 7, 9... multiplier 8...Divider 13...Trigger selection switch 21...Phase time measurement counter 22...Phase time processing section 24...Time information latch circuit twenty five -1 ~25 -n …Phase time buffer 30...Buffer selection processing unit 31...Phase detection buffer selection switch 32...Phase time buffer selection switch 100, 200, 300...Speed detection processing section

Claims

1. A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the latch circuit; and a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between current phase information held in the latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by multiplying the rotation speed detection period by a coefficient corresponding to the number of the phase detection buffers.

2. A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a phase information latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a time information latch circuit that latches phase time information obtained when encoder information is acquired by performing time processing synchronized with phase detection processing on the output of the encoder counter using the speed detection phase detection trigger, and holds the information as a rotation speed detection period; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the phase information latch circuit; a plurality of phase time buffers for storing information of a plurality of rotation speed detection periods earlier than the time information latch circuit; and a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between current phase information held in the phase information latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by calculating the difference between the current rotation speed detection period held in the time information latch circuit and the oldest rotation speed detection period stored in the phase time buffer.

3. A speed detection device using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing unit that selects a trigger signal corresponding to the type of the encoder from among a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a phase information latch circuit that latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a time information latch circuit that latches phase time information obtained when encoder information is acquired by performing time processing synchronized with phase detection processing on the output of the encoder counter using the speed detection phase detection trigger, and holds the information as a rotation speed detection period; a plurality of phase detection buffers for storing information of a plurality of previous phases of the phase information held in the phase information latch circuit; a plurality of phase time buffers for storing information of a plurality of rotation speed detection periods earlier than the time information latch circuit; a buffer selection processing unit that selects a phase detection buffer and a phase time buffer to be used for calculation based on the relationship between the rotation speed detection resolution of the encoder and the desired rotation speed detection resolution; a rotation speed detection value calculation unit that calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating the difference between the current phase information held in the phase information latch circuit and the phase information stored in the phase detection buffer selected by the buffer selection processing unit, and rotation speed detection calculation time information obtained by calculating the difference between the current rotation speed detection period held in the time information latch circuit and the rotation speed detection period stored in the phase time buffer selected by the buffer selection processing unit.

4. 4. The speed detection device according to claim 3, wherein the buffer selection processing unit selects the number of buffers in which the relationship between the number of buffers, the encoder resolution, the rotation speed detection processing period, and the required rotation speed detection resolution satisfies the condition of equation (13), and determines the phase detection buffer and the phase time buffer indicated by the selected number of buffers as the phase detection buffer and the phase time buffer to be used for calculation. [0013]

5. A speed detection method using an encoder that detects the phase and rotation speed of an electric motor, a phase latch trigger selection processing step in which a phase latch trigger selection processing unit selects a trigger signal corresponding to the type of the encoder from a plurality of trigger signals and outputs the selected trigger signal as a phase detection trigger for speed detection; a latch step in which a latch circuit latches and holds phase information obtained by performing phase detection processing on the output of the encoder using the phase detection trigger for speed detection; a storage step in which a phase detection buffer stores information of a plurality of previous times of the phase information held in the latch circuit; a rotation speed detection value calculation step in which a rotation speed detection value calculation unit calculates a rotation speed detection value based on rotation speed detection calculation phase information obtained by calculating a difference between current phase information held in the latch circuit and the oldest phase information stored in the phase detection buffer, and rotation speed detection calculation time information obtained by multiplying a rotation speed detection period by a coefficient corresponding to the number of phase detection buffers.

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