MEMORY CONTROLLER, METHOD FOR CONTROLLING MEMORY CONTROLLER, AND PROGRAM - Patent application

Abstract

To provide a technique for improving memory access efficiency.SOLUTION: A memory controller for controlling a DRAM, includes: a first storage unit which stores requests received by the memory controller and contains information on priority and an access type; a first control unit which selects requests from among the requests stored in the first storage unit; a second storage unit which stores the requests selected by the first control unit; and a second control unit which generates a DRAM command by rearranging the requests stored in the second storage unit, and issues the DRAM command to the DRAM. The second control unit generates a priority access type indicating which access type of the requests is to be issued in priority to the DRAM. The first control unit selects the request on the basis of the information on the priority of the requests and access type stored in the first storage unit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a memory controller, a control method for a memory controller, and a program. [Background technology]

[0002] Dynamic Random Access Memory (DRAM) is now widely used. However, as computer systems become more sophisticated and powerful, the performance demands on DRAM are increasing. Memory controllers that control DRAM are required to maximize the performance of accessing DRAM.

[0003] The factors that cause a decrease in performance when accessing DRAM are page misses that access a closed page and switching between read and write. When a page miss occurs, if there is an open page, a precharge must be executed to close the open page, and then an active command must be executed to open the required page, which affects access performance. Many methods have been proposed for memory controllers that control DRAM in order to suppress this performance decrease.

[0004] Among the proposed methods, the reordering method rearranges DRAM access requests (hereinafter referred to as requests) to minimize the penalty incurred when accessing DRAM (hereinafter referred to as DRAM access penalty). This rearrangement reduces the DRAM access penalty and suppresses the degradation of access performance.

[0005] Patent document 1 discloses a technology that has a request buffer for storing requests, determines the bank group to which a memory request is to be issued based on the number of banks that are not busy among the banks belonging to the memory bank group, and issues the memory request. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6237945 [Patent Document 2] Japanese Patent Publication No. 2022-168545 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the reordering technique, DRAM commands such as activate, precharge, read, or write are generated in parallel from the requests in the request buffer to determine the DRAM access penalty and rearrange the requests. Therefore, the reordering logic circuit that implements the reordering technique becomes complex. Therefore, the technology disclosed in Patent Document 1 has a problem in that the area of the DRAM command generation logic circuit increases exponentially as the number of request buffer stages increases.

[0008] In response to this, Patent Document 2 provides a technology that can reduce the area of the reorder logic circuit that rearranges requests. However, since Patent Document 2 only considers page misses, there are many switches between read and write, which reduces memory access efficiency.

[0009] The present invention has been made in view of the above-mentioned problems, and has an object to provide a technique for improving memory access efficiency. [Means for solving the problem]

[0010] To achieve the above object, one aspect of the present invention provides a memory controller comprising: A memory controller that controls a dynamic random access memory (DRAM), a first storage unit for storing requests including information on priority and access type received by the memory controller; a first control unit that selects a request from the requests stored in the first storage unit; a second storage unit that stores the request selected by the first control unit; a second control unit that rearranges the requests stored in the second storage unit to generate a DRAM command and issues the DRAM command to the DRAM; The second control unit Based on the priority and access type of the request stored in the second storage unit, generating a priority access type indicating which access type of request is to be issued to the DRAM with priority; The first control unit selects the request based on the priority and access type information of the request stored in the first storage unit and the priority access type. [Effects of the Invention]

[0011] According to the present invention, it is possible to improve memory access efficiency. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram showing the configuration of a memory controller according to the first embodiment. [Figure 2] 10 is a flowchart showing a procedure for selecting a request from a first storage unit according to the first embodiment. [Figure 3] FIG. 4 is a diagram showing state transitions of a first storage unit and a second storage unit according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing state transitions of a first storage unit and a second storage unit according to the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating the configuration of a memory controller according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing state transitions of a first storage unit and a second storage unit according to the third embodiment. [Figure 7] FIG. 10 is a diagram showing state transitions of a first storage unit and a second storage unit according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0014] DRAM is generally used as the main memory device for computer systems. DRAM has a larger memory capacity per chip than other memory devices, and is also cheaper than other memory devices when compared for the same capacity. Therefore, DRAM makes it possible to build large-capacity memory systems at low cost.

[0015] DRAM is internally configured with memory cells arranged two-dimensionally. Each row of memory cells arranged two-dimensionally is called a page. To access a memory cell, the page is first specified, and the information of all memory cells that make up that page is read internally. Next, the memory cell to be accessed is identified by specifying the column. The identified memory cell is then accessed. Furthermore, DRAM has multiple memory cells arranged two-dimensionally, and each of these two-dimensionally arranged memory cells is called a bank. A bank is specified using a bank address.

[0016] The state of a page that has been read internally is called the open state, and the state of a page that has not been read internally is called the closed state. To open a closed page, specify the page address and execute active. Conversely, to close an open page, execute precharge. If there is already an open page and you want to open a different page, execute precharge to close the open page, then execute active to open the desired page.

[0017] <Memory controller configuration> FIG. 1 is a diagram showing an example of the configuration of a memory controller 1 according to a first embodiment. The memory controller 1 controls a dynamic random access memory (DRAM). The memory controller 1 includes a first control unit 11, a second control unit 12, a first storage unit 13, and a second storage unit 14. The main functions and features of each functional unit constituting the memory controller 1 are listed below.

[0018] The first control unit 11 stores the received request 101 in the first storage unit 13. In addition, the first control unit 11 selects a request that satisfies the conditions from all the requests 104 in the first storage unit stored in the first storage unit 13, and sends the selected request 111 to the second control unit 12.

[0019] The second control unit 12 stores the received request 111 in the second storage unit 14. Furthermore, the second control unit 12 reorders the requests 105 in the second storage unit stored in the second storage unit 14 so as to reduce the penalty for DRAM access, and generates a DRAM command 102. Furthermore, if the DRAM command 102 is an RD command or a WR command, the second control unit 12 generates a priority access type 112 and sends it to the first control unit 11.

[0020] The first storage unit 13 stores the request 101 received by the first control unit 11. All entries in the first storage unit 13 can be read by the first control unit 11 in parallel.

[0021] The second storage unit 14 stores requests 111 received by the second control unit 12. The entry numbers of the requests 111 stored in the second storage unit 14 indicate the order in which the requests 111 were stored. In other words, a more recently stored request 111 is stored in an entry with a relatively larger entry number. All entries in the second storage unit 14 can be read in parallel by the second control unit 12.

[0022] Next, we will explain the operation of the first control unit 11. When the first control unit 11 receives a request 101, it stores the request 101 in the first storage unit 13. Here, in the first embodiment, the request 101 includes information on an access type and priority.

[0023] The above-mentioned access type indicates the type of request. In the first embodiment, there are two types of access types: RD and WR. An RD request performs an operation to read data from the DRAM. A WR request performs an operation to write data to the DRAM. The access type is not limited to the above two types, and may be set arbitrarily.

[0024] The priority indicates the priority of the request. The format of the priority may be arbitrary as long as it is possible to indicate the priority.

[0025] <Operation of the first control section> Next, a detailed description will be given of a procedure in which the first control unit 11 according to the first embodiment selects a request that satisfies a condition from the requests in the first storage unit 104 stored in the first storage unit 13. Conditions (1) to (2) under which the first control unit 11 selects a request from the requests in the first storage unit 104 will be shown below.

[0026] (1) A first intra-storage request 104 stored in the first storage unit 13, the priority of which is equal to or higher than a threshold value.

[0027] (2) A first intra-storage request 104 stored in the first storage 13, the access type of which matches the priority access type 112.

[0028] Next, the operation of the first control unit 11 to select a request from the requests in the first storage unit 104 will be explained in more detail using the flowchart of Fig. 2. Fig. 2 is a flowchart showing an example of a control method for the memory controller 1. In Fig. 2, steps S1 to S7 indicate the steps executed when selecting a request.

[0029] 2, steps S1 and S2 are steps of searching for requests that satisfy the above conditions (1) and (2) in the first storage unit 13. As shown in FIG. 2, in the first embodiment, the first control unit 11 executes the steps S1 and S2 in parallel to search for requests that satisfy the condition (1) or (2) in the first storage unit 13 in parallel.

[0030] First, the process of step S1 will be described. In step S1, the first control unit 11 selects and extracts a request that satisfies condition (1) from the first in-storage requests 104 stored in the first storage unit 13. According to the definition of condition (1) described above, a request that satisfies condition (1) is a request with a priority equal to or higher than a preset threshold. Here, the first control unit 11 may extract multiple requests that satisfy condition (1).

[0031] Next, the process of step S2 will be described. In step S2, the first control unit 11 selects and extracts a request that satisfies condition (2) from the first in-storage requests 104 stored in the first storage unit 13. According to the definition of condition (2) described above, a request that satisfies condition (2) is a request whose access type matches the priority access type 112 generated by the second control unit 12. Here, the first control unit 11 may extract multiple requests that satisfy condition (2).

[0032] In step S3, the first control unit 11 determines whether or not a request that satisfies condition (1) exists in the first storage unit 13. If a request that satisfies condition (1) exists in the first storage unit 13, the process proceeds to step S5. On the other hand, if a request that satisfies condition (1) does not exist in the first storage unit 13, the process proceeds to step S4.

[0033] In step S4, the first control unit 11 determines whether or not a request that satisfies the condition (2) exists in the first storage unit 13. If a request that satisfies the condition (2) exists in the first storage unit 13, the process proceeds to step S6. On the other hand, if a request that satisfies the condition (2) does not exist in the first storage unit 13, the process returns to the execution of steps S1 to S2.

[0034] In step S5, the first control unit 11 selects the request with the highest priority among the requests in the first storage unit 13 that satisfy the condition (1) as the request 111. If there are multiple requests with the highest priority among the requests in the first storage unit 13 that satisfy the condition (1), the first control unit 11 selects the oldest request as the request 111. Then, the process proceeds to step S7.

[0035] In step S6, the first control unit 11 selects the oldest request among the requests in the first storage unit 13 that satisfy the condition (2) as the request 111. After that, the process proceeds to step S7.

[0036] In step S7, if the request 111 selected in step S5 or S6 exists and there is an empty entry in the second storage unit 14, the first control unit 11 sends the selected request 111 to the second control unit 12 and returns to the processes of steps S1 to S2. The second control unit 12 stores the request 111 in an empty entry in the second storage unit 14. If there is no empty entry in the second storage unit 14, the first control unit 11 does not send the request 111 and returns to the processes of steps S1 to S2.

[0037] <Operation of the second control section> Next, we will explain the operation of the second control unit 12. When the second control unit 12 receives the selected request 111 sent by the first control unit 11, it stores the request 111 in the second storage unit .

[0038] Furthermore, the second control unit 12 performs reordering on the second storage unit requests 105 stored in the second storage unit 14 so as to reduce the DRAM access penalty, and generates a DRAM command 102. The second control unit 12 then issues the DRAM command 102 to the DRAM. The reordering rearranges the requests so as to minimize the DRAM access penalty. This rearrangement reduces the DRAM access penalty and prevents a decrease in access performance.

[0039] <Operation of the first storage unit> Next, we will explain the first storage unit 13. The first storage unit 13 stores the request 101 received by the first control unit 11. The first storage unit 13 may have a queue structure or a buffer structure, as long as request information can be read from any entry.

[0040] Furthermore, the elements constituting the first storage unit 13 may be any elements as long as they satisfy the required specifications for the memory controller 1, such as speed and power consumption. That is, the elements constituting the first storage unit 13 may be configured by applying either an SRAM or a flip-flop (F / F).

[0041] <Operation of the second storage unit> Next, we will explain the second storage unit 14. The second storage unit 14 stores the request 111 received by the second control unit 12. The second storage unit 14 may have a queue structure or a buffer structure as long as request information can be read from any entry.

[0042] The elements constituting the second storage unit 14 may be any elements as long as they satisfy the required specifications for the memory controller 1, such as speed and power consumption. That is, the elements constituting the second storage unit 14 may be configured by applying either an SRAM or a flip-flop (F / F).

[0043] <Processing> Next, the operation according to the first embodiment will be described with reference to Figures 3 and 4, focusing on the operations of the first control unit 12, the first storage unit 13, and the second storage unit 14. In the description, it is assumed that the number of entries in the first storage unit 13 is four, and the number of entries in the second storage unit 14 is six.

[0044] 3, the operation from the selection of a request that satisfies the condition (1) by the first control unit 11 to the storage of the selected request 111 by the second control unit 12 in the second storage unit 14 will be described. The explanation will be given assuming that the priority threshold of the condition (1) is 2.

[0045] 3 shows the states of the first storage unit 13 and the second storage unit 14 at a certain time T0 and the next time T1, and the priority access types generated by the second control unit 12. At T0, the first storage unit 13 stores requests in three of its four entries. The second storage unit 14 stores requests in three of its six entries.

[0046] In step S1 of extracting requests that satisfy condition (1) shown in Fig. 2, "(1) requests that are first storage unit requests 104 stored in the first storage unit 13 and whose priority is equal to or higher than a threshold" are extracted. In the example of Fig. 3, the first control unit 11 extracts requests with entry numbers 0 and 1 from the requests 104 in the first storage unit (for example, threshold = 2).

[0047] Next, in step S3, the first control unit 11 determines that a request that satisfies condition (1) exists, and proceeds to step S5. In step S5, the first control unit 11 selects the request with entry number 1 (priority=3), which is the request with the highest priority, from the two requests. Thereafter, in step S7, the first control unit 11 sends the selected request to the second control unit 12 if a free entry exists in the second storage unit 14.

[0048] When the second control unit 12 receives the request sent by the first control unit 11, the second control unit 12 stores the request in the second storage unit 14. The states of the first storage unit 13 and the second storage unit 14 after the series of operations are completed are shown at T1 in FIG. 3. The second storage unit 14 generates the DRAM command 102 from the request with entry number 3 (priority=3) in order to generate the DRAM command 102 from the request with the higher priority. Then, since the request with entry number 3 is WR, the priority access type is changed to WR. This allows the high-priority request to be stored in the second storage unit 14. Therefore, it is possible to process the real-time processing request quickly.

[0049] Next, the operation when the condition (2) is met will be explained using Fig. 4. The explanation will be given assuming that the priority threshold of the condition (1) is 2.

[0050] 4 shows the states of the first storage unit 13 and the second storage unit 14 at a certain time T0 and the next time T1, and the priority access type generated by the second control unit 12. At T0, the first storage unit 13 stores requests in three of its four entries. The second storage unit 14 stores requests in three of its six entries. Since the only request stored in the second storage unit 14 is RD, the priority access type is RD.

[0051] 2, in step S1 of extracting requests that satisfy condition (1), all priorities are below the threshold (=2), so the first control unit 11 does not extract any requests from the requests 104 in the first storage unit. In step S2 of extracting requests that satisfy condition (2), the first control unit 11 extracts "(2) requests 104 in the first storage unit that are stored in the first storage unit 13 and whose access type matches the priority access type 112."

[0052] In the example of FIG. 4, the first control unit 11 extracts the requests with entry numbers 1 and 2 corresponding to the access type that matches the priority access type (RD) from the requests 104 in the first storage unit.

[0053] Next, in step S3, the first control unit 11 determines that there is no request that satisfies condition (1), and proceeds to step S4. In step S4, the first control unit 11 determines that there is a request that satisfies condition (2), and proceeds to step S6. In step S6, the first control unit 11 selects the request with entry number 1, which is the oldest request, from the two requests. Thereafter, in step S7, the first control unit 11 sends the selected request to the second control unit 12 if there is a free entry in the second storage unit 14.

[0054] When the second control unit 12 receives the request sent by the first control unit 11, the second control unit 12 stores the request in the second storage unit 14. The states of the first storage unit 13 and the second storage unit 14 after the series of operations are completed are shown at T1 in FIG.

[0055] Since the second storage unit 14 generates a DRAM command 102 from a request with a higher priority, it generates a DRAM command 102 from the request with entry number 1. Since the request with entry number 1 is an RD, the priority access type remains RD. Since all requests in the second storage unit 14 are RD, no switching between read and write occurs. Therefore, it is possible to reduce the DRAM access penalty.

[0056] The second control unit 12 may set the access type of the DRAM command last issued to the DRAM as the priority access type. Furthermore, the second control unit 12 may change the priority access type when there are no requests in the second storage unit 14 whose access type matches the priority access type.

[0057] As described above, in this embodiment, the queue is divided into a first queue (first storage unit) and a second queue (second storage unit), and DRAM commands are generated for requests in the second queue. By limiting the generation of DRAM commands to the second queue, it is possible to maintain the reordering effect while suppressing an increase in the area of the reordering circuit. In addition, it is possible to quickly process high-priority requests while suppressing the occurrence of switching between read and write.

[0058] As described above, according to this embodiment, it is possible to quickly process high-priority requests while making it difficult for switching between read and write to occur, thereby improving memory access efficiency.

[0059] (Embodiment 2) A second embodiment will be described with reference to FIG. 5. FIG. 5 is a diagram showing an example of the configuration of a memory controller according to the second embodiment. As shown in FIG. 5, the memory controller 1 includes a first control unit 11, a second control unit 12, a first storage unit for read requests (read storage unit) 15, a first storage unit for write requests (write storage unit) 16, and a second storage unit 14. Of these components, the second control unit 12 and the second storage unit 14 are the same as the second control unit 12 and the second storage unit 14 described in the first embodiment. The first storage unit for read requests 15 and the first storage unit for write requests 16 are obtained by dividing the first storage unit 13 in FIG. 1. The first storage unit for read requests 15 is a storage unit for storing read requests. The first storage unit for write requests 16 is a storage unit for storing write requests.

[0060] When the first control unit 11 receives the request 101, it stores the read request 103 in the first storage unit 15 for read requests. On the other hand, the first control unit 11 stores the write request 103 in the first storage unit 16 for write requests.

[0061] The first control unit 11 selects a request that satisfies the conditions from the requests in the first storage unit 104 stored in the first storage unit 15 for read requests and the first storage unit 16 for write requests, and sends the selected request 111 to the second control unit 12. This operation is the same as that of the first control unit 11 described in the first embodiment.

[0062] All entries of both the first storage unit 15 for read requests and the first storage unit 16 for write requests can be read in parallel by the first control unit 11. The request in the first storage unit 104 collects requests read from both the first storage unit 15 for read requests and the first storage unit 16 for write requests.

[0063] As described above, in this embodiment, two first storage units are provided: the first storage unit 15 for read requests and the first storage unit 16 for write requests. The first control unit 11 The second control unit 12 selects requests out of order from the first storage unit 15 for read requests and the first storage unit 16 for write requests. "Out of order" means that commands are executed starting from the command for which all the data necessary for processing is available, regardless of the order of the commands written in the program. The second control unit 12 stores the requests received from the first control unit 11 in the first storage unit 14.

[0064] In this way, according to this embodiment, by storing read requests and write requests by type, it is possible to improve processing efficiency.

[0065] (Embodiment 3) Next, a memory controller 1 according to embodiment 3 will be described. Like the memory controller 1 according to embodiment 1, the memory controller 1 according to embodiment 3 includes a first control unit 11, a second control unit 12, a first storage unit 13, and a second storage unit 14. The following description will focus on functions according to embodiment 3, and descriptions of functions similar to those of embodiment 1 will be omitted. The number of entries in the second storage unit 14 is 6, and entry numbers 4 and 5 are entries dedicated to high-priority requests.

[0066] <Processing> 6, the operation from the selection of a request that satisfies the condition (1) by the first control unit 11 to the storage of the selected request 111 by the second control unit 12 in the second storage unit 14 will be described. The explanation will be given assuming that the priority threshold of the condition (1) is 2.

[0067] 6 shows the states of the first storage unit 13 and the second storage unit 14 at a certain time T0 and the next time T1, and the priority access type generated by the second control unit 12. At T0, the first storage unit 13 stores requests in two of its four entries. The second storage unit 14 stores requests in four of its six entries. Since the only request stored in the second storage unit 14 is RD, the priority access type is RD.

[0068] In step S1 of extracting a request that satisfies condition (1) in FIG. 2, the first control unit 11 extracts a request with entry number 1 whose priority is equal to or higher than a threshold value (=2) from the requests 104 in the first storage unit.

[0069] Next, in step S3, the first control unit 11 determines that a request that satisfies condition (1) exists, and proceeds to step S5. In step S5, the first control unit 11 selects the request with entry number 1. Thereafter, in step S7, if a free entry exists in the second storage unit 14, the first control unit 11 sends the selected request to the second control unit 12.

[0070] 7, a description will be given of an operation in a case where a request that satisfies the condition (2) is selected by the first control unit 11 but is not stored in the second storage unit 14. The description will be given assuming that the priority threshold of the condition (1) is 2.

[0071] In step S2 of extracting requests that satisfy condition (2) in Figure 2, the first control unit 11 extracts requests with entry numbers 0 and 1 that correspond to an access type that matches the priority access type (RD) from the requests 104 in the first storage unit.

[0072] Next, in step S3, the first control unit 11 determines that a request that satisfies condition (2) exists, and proceeds to step S6. In step S6, the first control unit 11 selects the request with the oldest entry number 0. Thereafter, in step S7, the first control unit 11 determines that there are free entries in the second storage unit 14, but entry numbers 4 and 5 are entries dedicated to high-priority requests. Since there are free entries only in the entries dedicated to high-priority requests, the first control unit 11 does not send the selected request to the second control unit 12. In other words, if there are no free entries dedicated to high-priority requests, requests with a priority below the threshold will not be stored in the second storage unit 14.

[0073] As described above, in this embodiment, an entry dedicated to high priority requests is provided in the second storage unit 14. This makes it possible to reserve an entry for high priority requests, thereby preventing a high priority request from being unable to be processed and resulting in a waiting period.

[0074] The disclosure of this specification includes the following memory controller, memory controller control method, and program.

[0075] (Item 1) A memory controller that controls a dynamic random access memory (DRAM), a first storage unit for storing requests including information on priority and access type received by the memory controller; a first control unit that selects a request from the requests stored in the first storage unit; a second storage unit that stores the request selected by the first control unit; a second control unit that rearranges the requests stored in the second storage unit to generate a DRAM command and issues the DRAM command to the DRAM; the second control unit generates a priority access type indicating which access type of request is to be issued to the DRAM with priority; The memory controller is characterized in that the first control unit selects the request based on the priority and access type information of the request stored in the first storage unit and the priority access type.

[0076] (Item 2) The memory controller according to item 1, characterized in that the first control unit selects, from among the requests stored in the first storage unit, a request whose priority is equal to or greater than a threshold value, or a request whose access type matches the priority access type.

[0077] (Item 3) 3. The memory controller according to item 2, wherein the first control unit selects the request with the highest priority when there are multiple requests in the first storage unit whose priority is equal to or higher than the threshold.

[0078] (Item 4) The memory controller according to item 2 or 3, characterized in that the first control unit selects a request whose access type matches the priority access type when there is no request in the first storage unit whose priority is equal to or higher than the threshold.

[0079] (Item 5) 5. The memory controller according to item 4, wherein the first control unit selects the oldest request when there are multiple requests whose access type matches the priority access type.

[0080] (Item 6) 6. The memory controller according to any one of items 1 to 5, wherein the access type indicates a read or write.

[0081] (Item 7) 7. The memory controller according to any one of items 1 to 6, wherein the second control unit sets the access type of the DRAM command last issued to the DRAM as the priority access type.

[0082] (Item 8) The memory controller described in any one of items 1 to 7, characterized in that the second control unit changes the priority access type when there are no requests in the second storage unit whose access type matches the priority access type.

[0083] (Item 9) The first storage unit is a read storage unit for storing requests whose access type is read; a write storage unit for storing requests whose access type is write; 9. The memory controller according to any one of items 1 to 8, comprising:

[0084] (Item 10) The memory controller described in item 9, characterized in that the first control unit selects a request out of order from the requests stored in the read storage unit and the requests stored in the write storage unit.

[0085] (Item 11) the second storage unit includes a first entry that can accept a request regardless of the priority, and a second entry that can accept a request whose priority is equal to or greater than a threshold; Item 11. The memory controller according to item 10, wherein the first control unit does not store a request whose priority is lower than the threshold in the second storage unit if there is no free space in the first entry.

[0086] (Item 12) A control method for a memory controller that controls a dynamic random access memory (DRAM), comprising: a generation step of generating a priority access type indicating which access type of request is to be issued to the DRAM with priority; a first control step of storing requests received by the memory controller, each including information on a priority and an access type, in a first storage unit, and selecting a request from the requests stored in the first storage unit based on the information on the priority and the access type and the preferential access type; a second control step of storing the requests selected by the first control step in a second storage unit, rearranging the requests stored in the second storage unit to generate a DRAM command, and issuing the DRAM command to the DRAM; 1. A method for controlling a memory controller, comprising:

[0087] (Item 13) A program for causing a computer to function as the memory controller according to any one of items 1 to 11.

[0088] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0089] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0090] 1: memory controller, 11: first control unit, 12: second control unit, 13: first storage unit, 14: second storage unit, 101: request received by first control unit, 102: DRAM command, 104: request in first storage unit, 105: request in second storage unit, 111: request received by second control unit, 112: priority access type

Claims

1. A memory controller for controlling a dynamic random access memory (DRAM), comprising: a first storage unit for storing requests including information on priority and access type received by the memory controller; a first control unit that selects a request from the requests stored in the first storage unit; a second storage unit that stores the request selected by the first control unit; a second control unit that rearranges the requests stored in the second storage unit to generate a DRAM command and issues the DRAM command to the DRAM; the second control unit generates a priority access type indicating which access type of request is to be issued to the DRAM with priority based on the priority and access type of the request stored in the second storage unit; The memory controller is characterized in that the first control unit selects the request based on the priority and access type information of the request stored in the first storage unit and the priority access type.

2. 2. The memory controller according to claim 1, wherein the first control unit selects, from among the requests stored in the first storage unit, a request whose priority is equal to or greater than a threshold value, or a request whose access type matches the priority access type.

3. 3. The memory controller according to claim 2, wherein the first control unit selects the request with the highest priority when there are multiple requests in the first storage unit whose priority is equal to or higher than the threshold.

4. 3. The memory controller according to claim 2, wherein the first control unit selects a request whose access type matches the priority access type when there is no request in the first storage unit whose priority is equal to or higher than the threshold.

5. 5. The memory controller according to claim 4, wherein, when there are a plurality of requests whose access type matches the priority access type, the first control unit selects the oldest request.

6. 2. The memory controller according to claim 1, wherein the access type indicates a read or write.

7. 2. The memory controller according to claim 1, wherein the second control unit sets the access type of the DRAM command issued last to the DRAM as the priority access type.

8. 2. The memory controller according to claim 1, wherein the second control unit changes the priority access type when a request whose access type matches the priority access type is no longer stored in the second storage unit.

9. The first storage unit is a read storage unit for storing requests whose access type is read; a write storage unit for storing requests whose access type is write; 10. The memory controller of claim 1, comprising:

10. 10. The memory controller according to claim 9, wherein the first control unit selects a request out of order from the requests stored in the read storage unit and the requests stored in the write storage unit.

11. the second storage unit includes a first entry that can accept a request regardless of the priority, and a second entry that can accept a request whose priority is equal to or greater than a threshold; 11. The memory controller according to claim 10, wherein the first control unit does not store a request whose priority is lower than the threshold in the second storage unit when there is no free space in the first entry.

12. A memory controller for controlling a dynamic random access memory (DRAM), comprising: a first storage unit for storing requests including information on priority and access type received by the memory controller; a first control unit that selects a request from the requests stored in the first storage unit; a second storage unit that stores the request selected by the first control unit; a second control unit that rearranges the requests stored in the second storage unit to generate a DRAM command and issues the DRAM command to the DRAM; the second control unit generates a priority access type indicating which access type of request is to be issued to the DRAM with priority; the first control unit selects the request based on information on the priority and access type of the request stored in the first storage unit and the priority access type; The memory controller is characterized in that the second control unit sets the access type of the DRAM command last issued to the DRAM as the priority access type.

13. A control method for a memory controller that controls a dynamic random access memory (DRAM), comprising: a first storing step of storing a request including information on priority and access type received by the memory controller in a first storing unit; a first control step of selecting a request from the requests stored in the first storage unit; a second storage step of storing the request selected by the first control step in a second storage unit; a second control step of generating a DRAM command by rearranging the requests stored in the second storage unit and issuing the DRAM command to the DRAM; a generating step of generating a priority access type indicating which access type of request is to be preferentially issued to the DRAM based on the priority and access type of the request stored in the second storage unit, A control method for a memory controller, characterized in that in the first control step, the request is selected based on the information on the priority and access type of the request stored in the first storage unit and the priority access type.

14. A method for controlling a memory controller that controls a dynamic random access memory (DRAM), comprising: a first storing step of storing a request including information on priority and access type received by the memory controller in a first storing unit; a first control step of selecting a request from the requests stored in the first storage unit; a second storage step of storing the request selected by the first control step in a second storage unit; a second control step of generating a DRAM command by rearranging the requests stored in the second storage unit and issuing the DRAM command to the DRAM; a generating step of generating a priority access type indicating which access type of request is to be issued to the DRAM with priority, In the first control step, the request is selected based on information on priority and access type of the request stored in the first storage unit and the priority access type; The memory controller control method according to claim 1, wherein the generating step sets the access type of the DRAM command last issued to the DRAM as the priority access type.

15. A program for causing a computer to function as the memory controller according to any one of claims 1 to 12.

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