Semiconductor integrated circuit, electronic device, and method for controlling semiconductor integrated circuit

Abstract

The present invention shortens a lock time for a circuit provided with a phase comparator.　According to the present invention, a phase comparator compares the phase of an inputted reference clock signal and the phase of a feedback clock signal and outputs the comparison results. A charge pump generates a control voltage for controlling the frequency of the feedback clock signal on the basis of the comparison results. A feedback unit generates the feedback clock signal in accordance with the control voltage. A stoppage detection unit detects whether the reference clock signal has stopped and initializes the comparison results when the reference clock signal has stopped.

Description

[Technical Field]

[0001] The present technology relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that compares the phases of clock signals, a solid-state imaging device, and a method for controlling the semiconductor integrated circuit. [Background technology]

[0002] Conventionally, in circuits on the receiving side of a communication interface, a delay locked loop (DLL) or a phase locked loop (PLL) has been used to generate a clock signal synchronized with a reference clock signal or a standard clock signal from the transmitting side. For example, a PLL has been proposed that includes a detection circuit that detects whether the reference clock signal has stopped and stops a voltage controlled oscillator when the reference clock signal has stopped, a phase comparator, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-50958 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned conventional technology aims to reduce power consumption by stopping the voltage-controlled oscillator when the reference clock signal is stopped. However, in the above-mentioned PLL, the phase comparator continues to output the comparison result while the reference clock is stopped, causing the loop filter to charge or discharge, and the control voltage input to the voltage-controlled oscillator to fluctuate. As a result, it takes time for the control voltage to return to the level it was at just before the stop after the stop period has elapsed. The longer the stop period, the longer the lock time until the PLL output resynchronizes (i.e., locks) with the reference clock signal.

[0005] This technology was developed in light of these circumstances, and aims to shorten the lock time in a circuit equipped with a phase comparator. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor integrated circuit including: a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs a comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback unit that generates the feedback clock signal in accordance with the control voltage; and a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result if the reference clock signal has stopped; and a control method thereof, which results in an effect of shortening lock time.

[0007] In this first aspect, the feedback section may include a delay section that delays the reference clock signal by a delay time corresponding to the control voltage and outputs the delayed reference clock signal as the feedback clock signal, thereby shortening the lock time in the DLL.

[0008] In addition, in this first aspect, the comparison result may include a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage, the phase comparator outputs one of the first and second control signals, the stop detection unit includes a front-stage flip-flop that holds one of the first and second control signals in synchronization with a clock signal having a delay time different from that of the feedback clock signal, and a reset signal generation circuit that generates a reset signal for initializing the comparison result based on the control signal held in the front-stage flip-flop and the reference clock signal, and the phase comparator initializes the comparison result in accordance with the reset signal, thereby producing an effect of generating a reset signal.

[0009] In this first aspect, the reset signal generation circuit may include a delay element that delays the control signal held in the first flip-flop, a second logic gate that generates a predetermined detection signal based on the held control signal and the delayed control signal, and a second flip-flop that acquires and holds a predetermined value in synchronization with the reference clock signal, outputs the held value as the reset signal, and initializes the held value in accordance with the detection signal, thereby producing an effect of generating a reset signal.

[0010] In addition, in this first aspect, the preceding flip-flop may output the held control signal as a detection signal, and the reset signal generation circuit may include a subsequent flip-flop that receives and holds the detection signal in synchronization with the reference clock signal, an inverter that inverts the signal held in the subsequent flip-flop and outputs it as an inverted signal, and a subsequent logic circuit that generates the reset signal based on the held detection signal and the inverted signal, thereby producing an effect of generating a reset signal.

[0011] In addition, in the first aspect, the power supply circuit may further include a front-stage logic gate that inputs either the first or second control signal to the front-stage flip-flop when a predetermined period has elapsed since the control voltage was at its initial value, thereby preventing erroneous detection at startup.

[0012] In this first aspect, the feedback section may further include a multiplexer that selects one of a plurality of clock signals having different delay times and supplies the selected clock signal to the preceding flip-flop, thereby providing an effect of selecting a clock signal having an appropriate delay time.

[0013] In addition, in this first aspect, the feedback section may include a voltage controlled oscillator that generates, as the feedback clock signal, a clock signal having a frequency corresponding to the control voltage, thereby providing an effect of shortening the lock time in the PLL.

[0014] In this first aspect, the feedback section may include a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal, and a frequency divider that divides the output clock signal and outputs the result as the feedback clock signal, thereby shortening the lock time in the PLL.

[0015] In addition, in this first aspect, the circuit may further include a voltage correction unit that holds the control voltage when the comparison result is initialized as a hold value and corrects the control voltage to the hold value when a stop period of the reference clock signal has elapsed, thereby achieving the effect of correcting the voltage to the voltage before the fluctuation even when the voltage fluctuates due to a leakage current.

[0016] In addition, in this first aspect, the clock signal generating circuit may further include a voltage compensating unit that compensates for the control voltage based on the amount of fluctuation in the control voltage during a period when the reference clock signal is stopped, thereby achieving the effect of returning the control voltage to the voltage before the fluctuation.

[0017] In addition, in this first aspect, the voltage compensator may include a replica circuit that generates a compensation amount according to the fluctuation amount during the suspension period, and a calculator that compensates the control voltage with the compensation amount when the suspension period has elapsed, thereby providing an effect of adding or subtracting the compensation amount.

[0018] In addition, in this first aspect, the computing unit may include an operational amplifier, first and second capacitive elements having one end commonly connected to an input terminal of the operational amplifier, a first switch for opening and closing a path between a control line for supplying the control voltage and the other end of the first capacitive element, a second switch for opening and closing a path between the replica circuit and the other end of the second capacitive element, a third switch for opening and closing a path between the other end of the first capacitive element and an output terminal of the operational amplifier, a fourth switch for opening and closing a path between the input terminal and the output terminal of the operational amplifier, a fifth switch for opening and closing a path between the other end of the second capacitive element and a predetermined reference potential, and a sixth switch for opening and closing a path between the control line and the output terminal of the operational amplifier, thereby providing an effect of adding or subtracting a compensation amount.

[0019] In addition, in this first aspect, the voltage compensator may include a replica circuit that generates a compensation amount according to the fluctuation amount during the suspension period, and a calculator that compensates the control voltage with the compensation amount when the suspension period has elapsed, thereby providing an effect of further shortening the lock time.

[0020] In addition, in this first aspect, the feedback section may include a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal, and a frequency divider that divides the output clock signal and outputs the result as the feedback clock signal, thereby providing an effect of compensating for voltage in the PLL.

[0021] A second aspect of the present technology is an electronic device including: a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs a comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback unit that generates the feedback clock signal in accordance with the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result if the reference clock signal has stopped; and a transmission circuit that supplies the reference clock signal, thereby providing an effect of shortening a lock time in the electronic device. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment of the present technology. [Figure 2] 1 is a circuit diagram showing a configuration example of a receiving circuit according to a first embodiment of the present technology. [Figure 3] 1 is a block diagram showing an example of the configuration of a DLL according to a first embodiment of the present technology; [Figure 4] 2 is a circuit diagram showing an example configuration of a phase comparator, a charge pump, a stop detection unit, and a delay unit according to the first embodiment of the present technology. FIG. [Figure 5] 4A to 4C are diagrams illustrating an example of an operation of a flip-flop according to the first embodiment of the present technology. [Figure 6] 3 is a circuit diagram showing a configuration example of a stop detection unit according to the first embodiment of the present technology. FIG. [Figure 7] FIG. 10 is a block diagram showing an example of the configuration of a DLL in a comparative example. [Figure 8] 10 is a timing chart showing an example of the operation of a DLL in a comparative example. [Figure 9] 4 is a timing chart showing an example of an operation of a DLL according to the first embodiment of the present technology. [Figure 10] FIG. 4 is a circuit diagram showing another example of the stop detection unit in the first embodiment of the present technology. [Figure 11]11 is a timing chart showing another example of the operation of the DLL provided with the stop detection unit of FIG. 10 according to the first embodiment of the present technology. [Figure 12] 1 is a block diagram showing an example of the configuration of an imaging device in which a DLL is arranged in a solid-state imaging element according to a first embodiment of the present technology. [Figure 13] FIG. 10 is a circuit diagram showing a configuration example of a stop detection unit according to a second embodiment of the present technology. [Figure 14] 10 is a timing chart showing an example of an operation of a DLL according to the second embodiment of the present technology. [Figure 15] FIG. 13 is a circuit diagram showing a configuration example of a stop detection section and a feedback section according to a third embodiment of the present technology. [Figure 16] 13 is a timing chart showing another example of the operation of the DLL according to the third embodiment of the present technology. [Figure 17] FIG. 10 is a block diagram showing an example configuration of a PLL according to a fourth embodiment of the present technology. [Figure 18] 13 is a timing chart showing an example of an operation of a PLL according to a fourth embodiment of the present technology. [Figure 19] FIG. 13 is a block diagram showing another example of a PLL according to the fourth embodiment of the present technology. [Figure 20] FIG. 13 is a block diagram showing an example of the configuration of a DLL according to a fifth embodiment of the present technology. [Figure 21] FIG. 13 is a block diagram showing an example configuration of a voltage correction unit according to a fifth embodiment of the present technology. [Figure 22] 13 is a timing chart showing an example of an operation of a DLL according to the fifth embodiment of the present technology. [Figure 23] FIG. 20 is a block diagram showing an example of the configuration of a DLL according to a sixth embodiment of the present technology. [Figure 24] FIG. 20 is a circuit diagram showing a configuration example of a phase comparison unit according to a sixth embodiment of the present technology. [Figure 25] FIG. 20 is a circuit diagram showing a configuration example of a charge pump and a voltage compensation unit according to a sixth embodiment of the present technology. [Figure 26] FIG. 20 is a circuit diagram showing a configuration example of a replica circuit and an adder according to a sixth embodiment of the present technology. [Figure 27] 22 is a timing chart showing an example of an operation of a DLL according to the sixth embodiment of the present technology. [Figure 28] FIG. 20 is a block diagram showing an example of the configuration of a DLL according to a seventh embodiment of the present technology. [Figure 29] FIG. 20 is a circuit diagram showing a configuration example of a voltage compensation section according to a seventh embodiment of the present technology. [Figure 30] 20 is a timing chart showing an example of an operation of a DLL according to the seventh embodiment of the present technology. [Figure 31] FIG. 20 is a block diagram showing an example of the configuration of a DLL according to an eighth embodiment of the present technology. [Figure 32] FIG. 20 is a circuit diagram showing a configuration example of a phase comparison unit according to an eighth embodiment of the present technology. [Figure 33] FIG. 23 is a diagram illustrating an example of an operation of a flip-flop according to the eighth embodiment of the present technology. [Figure 34] 22 is a timing chart showing an example of an operation of a DLL according to the eighth embodiment of the present technology. [Figure 35] FIG. 20 is a block diagram showing an example configuration of a PLL according to an eighth embodiment of the present technology. [Figure 36] 1 is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 37] FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described in the following order. 1. First embodiment (example of initializing control signals when reference clock signal stops) 2. Second embodiment (example of initializing control signals when the reference clock signal stops, except at startup) 3. Third embodiment (example of selecting the delay time of the feedback clock signal and initializing the control signal when the reference clock signal stops) 4. Fourth embodiment (example of initializing a control signal when a reference clock signal stops in a phase locked loop) 5. Fifth embodiment (example of initializing control signal and correcting voltage when reference clock signal is stopped) 6. Sixth embodiment (example of voltage compensation) 7. Seventh embodiment (example of voltage compensation when comparator output is inverted) 8. Eighth embodiment (example of voltage compensation using a digital circuit) 9. Ninth embodiment (example of voltage compensation in phase locked loop) 10. Mobile application examples

[0024] <1. First embodiment> [Configuration example of imaging device] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to an embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes a solid-state imaging element 110 and a receiving device 120.

[0025] The solid-state imaging element 110 generates image data by photoelectric conversion. The solid-state imaging element 110 includes a transmission circuit 111 that transmits the image data. The transmission circuit 111 supplies a clock signal CLK and a data signal DATA that constitutes the image data to the receiving device 120. For example, MIPI (Mobile Industry Processor Interface) is used as a communication interface standard for transmitting these signals. Note that standards other than MIPI can also be used.

[0026] The receiving device 120 receives image data and performs predetermined signal processing on the data. For example, a DSP (Digital Signal Processing) is used as the receiving device 120. The receiving device 120 includes a receiving circuit 130 that receives image data. The receiving circuit 130 receives a clock signal CLK and a data signal DATA.

[0027] [Example of receiving circuit configuration] 2 is a circuit diagram showing an example configuration of a receiving circuit 130 according to the first embodiment of the present technology. The receiving circuit 130 includes a plurality of receivers such as receivers 131 to 133, a control unit 134, a DLL 200, and a predetermined number of flip-flops such as flip-flops 135 and 136.

[0028] Receiver 131 receives clock signal CLK from transmitter circuit 111 and inputs it as reference clock signal REFCLK to DLL 200. Receiver 132 receives bit signal B0 in data signal DATA and inputs it to flip-flop 135. Receiver 133 receives bit signal B1 in data signal DATA and inputs it to flip-flop 136.

[0029] The control unit 134 uses a control signal RSTN to control the operation of the DLL 200. The details of the control performed by the control signal RSTN will be described later.

[0030] The DLL 200 synchronizes the output clock signal OUTCLK with the reference clock signal REFCLK and supplies the output clock signal OUTCLK to the clock terminals of the flip-flops.

[0031] The flip-flop 135 synchronizes with the output clock signal OUTCLK to receive and hold the bit signal B0 from the receiver 132. The flip-flop 136 synchronizes with the output clock signal OUTCLK to receive and hold the bit signal B1 from the receiver 133.

[0032] Although the DLL 200 is disposed within the image capture device 100, the DLL 200 may also be disposed in an electronic device other than the image capture device 100. The image capture device 100 is an example of an electronic device as defined in the claims.

[0033] [DLL configuration example] 3 is a block diagram showing an example configuration of a DLL 200 according to the first embodiment of the present technology. The DLL 200 includes a phase comparison unit 210, a charge pump 220, a filter 230, and a feedback unit 240. The DLL 200 is an example of a semiconductor integrated circuit as defined in the claims.

[0034] The phase comparison section 210 includes a phase comparator 310 and a stop detection section 320. The phase comparator 310 compares the phase of the input reference clock signal REFCLK with the phase of the feedback clock signal FBCLK. The phase comparator 310 supplies the comparison result, which includes the control signals UP and DOWN, to the charge pump 220.

[0035] The stop detection unit 320 detects whether the reference clock signal REFCLK has stopped, and initializes the comparison result (control signals UP and DOWN) if the reference clock signal REFCLK has stopped.

[0036] The charge pump 220 generates a control voltage VCTRL for controlling the frequency of the feedback clock signal FBCLK based on the control signals UP and DOWN. This control voltage VCTRL is supplied to the feedback section 240 via a filter 230. The filter 230 may be, for example, a loop filter.

[0037] The feedback section 240 generates a feedback clock signal FBCLK in accordance with the control voltage VCTRL. The feedback section 240 includes a delay section 250. The delay section 250 delays the reference clock signal REFCLK for a delay time corresponding to the control voltage VCTRL, and outputs the delayed reference clock signal REFCLK to the phase comparator 310 as a feedback clock signal FBCLK. The delay section 250 also supplies a feedback clock signal FBCLK_X, which has a delay time different from that of the feedback clock signal FBCLK, to the stop detection section 320. The feedback clock signal FBCLK is also output to the flip-flop 135 and the like as an output clock signal OUTCLK.

[0038] 4 is a circuit diagram showing an example configuration of the phase comparator 310, the charge pump 220, the stop detection unit 320, and the delay unit 250 according to the first embodiment of the present technology. The phase comparator 310 includes flip-flops 311 and 312, an AND (logical product) gate 313, and a NAND (negative logical product) gate 314.

[0039] The flip-flop 311 synchronizes with the reference clock signal REFCLK, captures and holds a high level, and supplies this as a control signal UP to the charge pump 220. The flip-flop 312 synchronizes with the feedback clock signal FBCLK, captures and holds a high level, and supplies this as a control signal DOWN to the charge pump 220 and the stop detection unit 320. The clear terminals of these flip-flops 311 and 312 are non-inverting input terminals, and the control signal PFDRSTN is input to these clear terminals.

[0040] The NAND gate 314 supplies the NAND of the control signals UP and DOWN to the AND gate 313. The AND gate 313 supplies the logical product of the signal from the NAND gate 314 and the reset signal PFDRST to the flip-flops 311 and 312 as a control signal PFDRSTN.

[0041] The circuit configuration shown in the figure generates the control signals UP and DOWN according to the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK. When a low-level reset signal PFDRST is input, the control signals UP and DOWN are initialized to low levels.

[0042] Charge pump 220 includes current sources 221 and 224 and nMOS (n-channel Metal Oxide Semiconductor) transistors 222 and 223. Current source 221 is connected to a power supply terminal, and current source 224 is connected to a ground terminal. nMOS transistors 222 and 223 are inserted in series between current source 221 and current source 224. A control signal UP is input to the gate of nMOS transistor 222, and a control signal DOWN is input to the gate of nMOS transistor 223. The voltage at the connection node between nMOS transistors 222 and 223 is supplied to filter 230 as control voltage VCTRL.

[0043] With the circuit configuration illustrated in the figure, when the control signal UP is at a high level and the control signal DOWN is at a low level, the filter 230 is charged and the control voltage VCTRL rises. On the other hand, when the control signal UP is at a low level and the control signal DOWN is at a high level, the filter 230 is discharged and the control voltage VCTRL drops.

[0044] The stop detection unit 320 includes a flip-flop 321 and a reset signal generation circuit 330. The flip-flop 321 receives and holds a control signal DOWN in synchronization with the feedback clock signal FBCLK_X. The flip-flop 321 supplies the held control signal DOWN to the reset signal generation circuit 330. The flip-flop 321 is an example of a front-stage flip-flop as defined in the claims.

[0045] The reset signal generation circuit 330 detects whether the reference clock signal REFCLK has stopped based on the control signal from the flip-flop 321 and the reference clock signal REFCLK, and generates a low-level reset signal PFDRST if the reference clock signal REFCLK has stopped.

[0046] Normally, when the reference clock signal REFCLK stops, the output clock signal OUTCLK (i.e., the feedback clock signal FBCLK) also stops, making it difficult to control the circuit after the stop. By providing the stop detection unit 320 described above, this difficulty can be resolved.

[0047] The delay unit 250 includes a predetermined number of delay elements 251 (in other words, delay lines) whose first stage receives the reference clock signal REFCLK. The delay time of each of these delay elements 251 becomes longer as the control voltage VCTRL decreases. For example, an inverter is used as the delay element 251. Furthermore, where K is a predetermined odd number, the delay element 251 in the Kth stage supplies a delayed signal to the phase comparator 310 as the feedback clock signal FBCLK. Furthermore, a delay element 251 in a position different from the Kth stage (e.g., the K+1th stage) supplies a signal to the stop detection unit 320 as the feedback clock signal FBCLK_X.

[0048] 5 is a diagram showing an example of the operation of the flip-flop 311 in the first embodiment of the present technology. This flip-flop 311 has a clear terminal CLR, a clock terminal clk, a data input terminal D, and an output terminal Q. In the diagram, "H" indicates a high level, and "L" indicates a low level. Also, "↑" indicates the rising edge of a signal.

[0049] When a low level is input to the clear terminal CLR of the inverting input, a low level is output from the output terminal Q regardless of the values of the clock terminal clk and the data input terminal D. When a high level is input to the clear terminal CLR and the state of the clock terminal clk is other than rising, the flip-flop 311 is in a holding state, and the held value is output from the output terminal Q. When a high level is input to the clear terminal CLR and the state of the clock terminal clk is rising, the flip-flop 311 is in a through state, and the value of the data input terminal D is output directly from the output terminal Q.

[0050] The circuit configurations of flip-flops other than the flip-flop 311 (such as the flip-flop 312) are the same as that of the flip-flop 311.

[0051] [Configuration example of stop detection unit] 6 is a circuit diagram showing an example of the configuration of the stop detection unit 320 according to the first embodiment of the present technology. The reset signal generation circuit 330 includes a delay element 331, logic gates 332 and 333, and a flip-flop 334.

[0052] The delay element 331 delays the control signal DOWN from the flip-flop 321. For example, an inverter is used as the delay element 331. The logic gate 332 outputs the logical product of the inverted value of the signal delayed by the delay element 331 and the control signal DOWN from the flip-flop 321 as the detection signal STOP. The logic gate 332 is an example of a subsequent-stage logic gate as defined in the claims.

[0053] The logic gate 333 outputs the logical product of the inverted value of the detection signal STOP and the control signal RSTN to the clear terminal of the inverted input of the flip-flop 334 .

[0054] The flip-flop 334 synchronizes with the reference clock signal CLK, captures and holds a high level, and outputs the held value as a reset signal PFDRST to the phase comparator 310. The flip-flop 334 is an example of a subsequent-stage flip-flop as defined in the claims.

[0055] With the circuit configuration illustrated in the figure, when the reference clock signal REFCLK stops, a high-level detection signal STOP is generated for a predetermined pulse period.

[0056] Furthermore, when the control signal RSTN is at a high level, the inverted value of the detection signal STOP is output from the logic gate 333, and a low-level reset signal PFDRST is output from the inverter 335 until the next rising edge of the reference clock signal REFCLK. On the other hand, when the control signal RSTN is at a low level, a low level is output from the logic gate 333 regardless of the detection signal STOP, and a high-level reset signal PFDRST is output from the inverter 335. In this way, the detection operation of the stop detection unit 320 can be enabled or disabled by the control signal RSTN.

[0057] If it is not necessary to control the detection operation of the stop detection unit 320 to be valid or invalid, it is possible to omit the logic gate 333. In this case, the detection signal STOP is output to the flip-flop 334 as is.

[0058] 7, a DLL without a stop detection unit 320 is considered as a comparative example. In this comparative example, a control signal RSTN is input to the phase comparator 310 instead of the reset signal PFDRST. Also, the feedback clock signal FBCLK_X is not output from the delay unit 250.

[0059] 8 is a timing chart showing an example of the operation of the DLL in the comparative example. Before timing T1, the feedback clock signal FBCLK and the reference clock signal REFCLK are synchronized with each other, with no phase difference between them. In this case, the control signals UP and DOWN are generated as short pulses synchronized with the clock signal. However, because these pulse widths are short and they occur simultaneously, the control voltage VCTRL does not fluctuate.

[0060] It is assumed that the transmission circuit 111 stops supplying the reference clock signal REFCLK during the stop period from timing T1 to T2. For example, in the HS-IDLE mode in MIPI, the reference clock signal REFCLK stops. After the reference clock signal REFCLK stops, the feedback clock signal FBCLK also stops with a delay of one clock.

[0061] At timing T11, which is the rising edge immediately before the feedback clock signal FBCLK stops, the phase comparator 210 outputs a high-level control signal DOWN in accordance with the phase difference between the feedback clock signal FBCLK and the reference clock signal REFCLK. In the comparative example, the phase comparator 210 is not initialized, and therefore the high-level control signal DOWN is continuously output over the period from timing T11 to timing T2.

[0062] With the control signal DOWN at a high level, the control voltage VCTRL continues to drop from timing T11 to timing T2. The level of the control voltage VCTRL at timing T11 is set to V1, and the level of the control voltage VCTRL at timing T2 is set to V2.

[0063] At timing T2, the transmission circuit 111 resumes transmission of the reference clock signal REFCLK, and the feedback clock signal FBCLK also resumes with a delay. In accordance with the phase difference between the feedback clock signal FBCLK and the reference clock signal REFCLK, the phase comparator 210 outputs a high-level control signal UP, and the control signal UP gradually increases the control voltage VCTRL.

[0064] At time T3, the control voltage VCTRL returns to V1, the voltage immediately before the shutdown, and the feedback clock signal FBCLK resynchronizes with the reference clock signal REFCLK. The time from time T2, when the shutdown period has elapsed, to time T3, when the feedback clock signal FBCLK synchronizes, is defined as the recovery time ΔT1. This recovery time ΔT1 is also called the lock time.

[0065] As shown in the figure, in the comparative example, the control voltage VCTRL continues to decrease until the stop period has elapsed. Therefore, the longer the stop period, the greater the fluctuation in the control voltage VCTRL becomes, and it takes time for the control voltage VCTRL to return to the level it was at immediately before the stop period has elapsed. In other words, the longer the stop period, the longer the recovery time ΔT1 (lock time) becomes.

[0066] [DLL operation example] 9 is a timing chart showing an example of the operation of the DLL 200 according to the first embodiment of the present technology. During the stop period, the stop detection unit 320 receives the control signal DOWN at timing T12, which is the rising edge of the feedback clock signal FBCLK_X, and internally generates a high-level detection signal STOP. Then, immediately thereafter, at timing T13, the stop detection unit 320 generates a low-level reset signal PFDRST.

[0067] In response to the low-level reset signal PFDRST, the phase comparator 310 in the phase comparison unit 210 sets the control signal PFDRSTN to low level at timing T14, and the stop detection unit 320 sets the detection signal STOP to low level. Immediately thereafter, at timing T15, the phase comparator 310 initializes the control signal DOWN to low level.

[0068] Because the control signal DOWN is initialized at timing T15 before the end of the suspension period, the drop in the control voltage VCTRL stops at that timing T15. The level V3 of the control voltage VCTRL at this timing T15 is higher than the level V2 at the end of the suspension period in the comparative example.

[0069] At timing T2, the transmission circuit 111 resumes transmitting the reference clock signal REFCLK, and the phase comparator 310 sets the control signal RFDRSTN to high level.

[0070] When the stop detection unit 320 is provided, the time from timing T2 to timing T4 when the feedback clock signal FBCLK is synchronized is defined as recovery time ΔT2. When the stop detection unit 320 is provided, the amount of fluctuation in the control voltage VCTRL is smaller than in the comparative example, as described above, so that the control voltage VCTRL rises to the level V1 just before the stop in a shorter time than in the comparative example, and recovery time ΔT2 (lock time) is shorter than recovery time ΔT1 in the comparative example.

[0071] Although the phase comparator 310 that outputs the control signal DOWN during the stop period is used, it is also possible to use a phase comparator 310 that outputs the control signal UP instead. In this case, the control signal UP is input to the stop detection unit 320 instead of the control signal DOWN.

[0072] 10, a flip-flop 336, an inverter 337, a NAND gate 338, and an AND gate 339 can also be arranged in the reset signal generation circuit 330. In this case, the flip-flop 321 outputs the held signal as the detection signal STOP.

[0073] The flip-flop 336 receives and holds the detection signal STOP from the flip-flop 321 in synchronization with the reference clock signal REFCLK. The flip-flop 336 outputs the held signal as an internal signal REL. The inverter 337 inverts the internal signal REL from the flip-flop 336 and outputs the inverted signal to the NAND gate 338. The NAND gate 338 outputs the NAND of the inverted signal and the detection signal STOP to the AND gate 339. The AND gate 339 outputs the logical product of the output signal of the NAND gate 338 and the control signal RSTN to the phase comparator 310 as a reset signal RFDRST.

[0074] The flip-flop 336 is an example of a subsequent flip-flop as defined in the claims. The circuit made up of the NAND gate 338 and the AND gate 339 is an example of a subsequent logic circuit as defined in the claims.

[0075] 11 is a timing chart showing another example of the operation of the DLL 200 including the stop detection unit 320 of FIG. 10 according to the first embodiment of the present technology. During the stop period, the stop detection unit 320 internally generates a high-level detection signal STOP at timing T12, which is the rising edge of the feedback clock signal FBCLK_X. However, at timing T14, the detection signal STOP does not go low but remains high.

[0076] At timing T2, the stop detection unit 320 generates a high-level internal signal REL. Then, at timing T21 when the feedback clock signal FBCLK_X rises, the stop detection unit 320 sets the detection signal STOP to low level, and immediately thereafter sets the internal signal REL to low level.

[0077] Furthermore, although the DLL 200 is disposed in the receiving device 120 outside the solid-state imaging device 110, the DLL 200 can also be disposed inside the solid-state imaging device 110.

[0078] 12 is a block diagram showing an example configuration of an imaging device 100 in which a DLL 200 according to the first embodiment of the present technology is arranged within a solid-state imaging element 110. In the figure, the imaging device 100 further includes a transmitting device 140 provided with a transmitting circuit 141. The solid-state imaging element 110 further includes a receiving circuit 112 and an internal circuit 113.

[0079] The receiving circuit 112 receives a clock signal CLK and a data signal DATA from the transmitting circuit 141. A DLL 200 is disposed within this receiving circuit 112. The receiving circuit 112 supplies the received data to the internal circuit 113. The internal circuit 113 performs predetermined processing based on the received data, generates image data, etc., and supplies the generated data to the transmitting circuit 111.

[0080] As described above, according to the first embodiment of the present technology, the stop detection unit 320 initializes the control signal DOWN when the reference clock signal REFCLK is stopped, so that the amount of fluctuation in the control voltage VCTRL during the stop period can be reduced, thereby shortening the recovery time (lock time) compared to when the stop detection unit 320 is not provided.

[0081] <2. Second embodiment> In the first embodiment described above, the stop detection unit 320 holds the control signal DOWN in the flip-flop 321 and detects the stop of the reference clock signal REFCLK based on that signal. However, because the control signal DOWN is generated even at startup, there is a risk that the stop detection unit 320 will erroneously detect the stop of the reference clock signal REFCLK even when the reference clock signal REFCLK has not stopped. The DLL 200 of this second embodiment differs from the first embodiment in that the control signal DOWN is input to the flip-flop 321 after a predetermined period has elapsed at startup.

[0082] 13 is a circuit diagram showing a configuration example of a stop detection unit 320 according to a second embodiment of the present technology. The stop detection unit 320 according to the second embodiment differs from the first embodiment in that it further includes an AND gate 322. The circuit configuration of the reset signal generation circuit 330 according to the second embodiment is the same as that of the first embodiment, and the circuit exemplified in FIG. 6 or FIG. 10 is used.

[0083] The AND gate 322 outputs the logical product of the control signal READY and the control signal DOWN from the control unit 134 to the input terminal of the flip-flop 321. The control signal READY is set to a low level over at least the startup period from when the control voltage VCTRL is at its initial value until the feedback clock signal FBCLK is synchronized, and after that period has elapsed, the control signal READY is set to a high level. The AND gate 322 inputs the control signal DOWN to the flip-flop 321 when the startup period has elapsed.

[0084] The AND gate 322 is an example of a front-stage logic gate as defined in the claims.

[0085] 14 is a timing chart showing an example of the operation of the DLL 200 according to the second embodiment of the present technology. The control voltage VCTRL is initially set to V0. This V0 is set to the highest voltage within the voltage range set for the control voltage VCTRL. Therefore, the DLL 200 starts operation from a state in which the delay time of the delay unit 250 is shortest.

[0086] During the period up to timing T0 immediately after the feedback clock signal FBCLK is synchronized, the phase comparator 310 generates a high-level control signal DOWN in accordance with the phase difference, and the control voltage VCTRL gradually decreases in response to the control signal DOWN. At timing T0, the control voltage VCTRL reaches a level V1, lower than its initial level V0. If the stop detector 320 erroneously detects a stop of the reference clock signal REFCLK during this startup period, the control signal DOWN is initialized, causing a disruption to the synchronization operation.

[0087] Therefore, the control unit 134 keeps the control signal READY at low level until timing T0, and then changes it to high level after timing T0. After timing T0, the logic gate 333 inputs the control signal DOWN to the flip-flop 321. This prevents erroneous detection of a shutdown during the startup period.

[0088] As described above, according to the second embodiment of the present technology, when the start-up period has elapsed, the AND gate 322 inputs the control signal DOWN to the flip-flop 321, thereby preventing erroneous detection of stoppage.

[0089] <3. Third Embodiment> In the second embodiment described above, the delay unit 250 supplies a signal with a delay time different from that of the feedback clock signal FBCLK as the feedback clock signal FBCLK_X to the stop detection unit 320. However, it is desirable to set the delay time of the feedback clock signal FBCLK_X according to the signal quality of the reference clock signal REFCLK. The DLL 200 of this third embodiment differs from the second embodiment in that the feedback unit 240 selects one of a plurality of clock signals with different delay times and outputs it as the feedback clock signal FBCLK_X.

[0090] 15 is a circuit diagram showing a configuration example of the stop detection unit 320 and the feedback unit 240 according to the third embodiment of the present technology. The stop detection unit 320 according to the third embodiment is the same as that according to the second embodiment. Note that the stop detection unit 320 according to the first embodiment can also be applied to the third embodiment.

[0091] The feedback section 240 of the third embodiment differs from that of the second embodiment in that it further includes a multiplexer 241. The delay section 250 of the third embodiment also differs from that of the second embodiment in that it further includes a predetermined number of delay elements 252. An inverter or the like is used as the delay elements 252.

[0092] A delay element 252 is provided for all or some of the odd-numbered delay elements 251. The odd-numbered delay elements 251 also output signals to the corresponding delay elements 252. The delay elements 252 invert the signals from the delay elements 251 and supply them to the multiplexer 241. In addition, all or some of the even-numbered delay elements 251 also output signals to the multiplexer 241.

[0093] The multiplexer 241 selects one of the multiple clock signals from the delay elements 251 and 252 in accordance with a selection signal SEL from the control unit 134. The multiplexer 241 supplies the selected signal as a feedback clock signal FBCLK_X to the flip-flop 321. The selection signal SEL is set in advance before the DLL 200 starts operating, and is held in a register or the like within the control unit 134.

[0094] As shown in the figure, the feedback clock signal FBCLK_X may be output from any delay element 251 as long as the delay time is different from that of the feedback clock signal FBCLK. The shorter the delay time, the shorter the duration of the control signal DOWN during the stop period. However, if the delay time is too short, the stop detection unit 320 may erroneously capture the control signal DOWN during normal operation outside the stop period, resulting in an erroneous detection of a stop.

[0095] For this reason, it is desirable to set an appropriate delay time according to the signal quality of the reference clock signal REFCLK. For example, the higher the signal quality and the smaller the jitter of the reference clock signal REFCLK, the shorter the delay time of the selected clock signal. This shortens the duration of the control signal DOWN during the stop period, thereby shortening the recovery time. On the other hand, the lower the signal quality and the larger the jitter of the reference clock signal REFCLK, the longer the delay time of the selected clock signal. This makes it possible to prevent erroneous detection even when the signal quality of the reference clock signal REFCLK is low.

[0096] 16 is a timing chart showing an example of the operation of the DLL 200 according to the second embodiment of the present technology. The delay time of the feedback clock signal FBCLK_X is shorter than that of the second embodiment. In this case, the feedback clock signal FBCLK_X rises at timing T12, immediately after timing T11, when the feedback clock signal FBCLK rises during the stop period. The control signal DOWN is reset to low level at timing T12.

[0097] As illustrated in the figure, since the delay time of the feedback clock signal FBCLK_X is short, the period during which the control signal DOWN remains high is shorter than in the second embodiment.

[0098] As described above, according to the third embodiment of the present technology, the feedback section 240 selects one of a plurality of clock signals having different delay times and outputs it as the feedback clock signal FBCLK_X. Therefore, it is possible to set an appropriate delay time according to the signal quality of the reference clock signal REFCLK.

[0099] <4. Fourth embodiment> In the second embodiment described above, the stop detection unit 320 is arranged in the DLL 200, but the stop detection unit 320 can also be applied to a PLL. This fourth embodiment differs from the second embodiment in that the stop detection unit 320 is applied to a PLL.

[0100] 17 is a block diagram showing an example configuration of a PLL 205 according to the fourth embodiment of the present technology. The PLL 205 is provided in the receiving circuit 130 or the like. The PLL 205 includes a phase comparison unit 210, a charge pump 220, a filter 230, and a feedback unit 240. The PLL 205 is an example of a semiconductor integrated circuit as defined in the claims.

[0101] The configurations of the phase comparison unit 210, charge pump 220, and filter 230 of the fourth embodiment are the same as those of the second embodiment, and a stop detection unit 320 is arranged in the phase comparison unit 210. A voltage controlled oscillator 260 is arranged in the feedback unit 240 of the fourth embodiment. Note that the stop detection unit 320 of the first embodiment can also be applied to the fourth embodiment.

[0102] The voltage controlled oscillator 260 generates a feedback clock signal FBCLK having a frequency corresponding to the control voltage VCTRL and supplies it to the phase comparison unit 210. The voltage controlled oscillator 260 also generates a feedback clock signal FBCLK_X having a different phase from the feedback clock signal FBCLK, together with the feedback clock signal FBCLK, and supplies it to the phase comparison unit 210. The feedback clock signal FBCLK is also output as an output clock signal OUTCLK to a subsequent circuit (such as the flip-flop 135).

[0103] 18 is a timing chart showing an example of the operation of the PLL 205 according to the fourth embodiment of the present technology. The feedback clock signal FBCLK_X rises at timing T12, immediately after timing T11, when the feedback clock signal FBCLK rises during the stop period. The control signal DOWN is reset to low level at that timing T12, and the drop in the control voltage VCTRL stops. The voltage-controlled oscillator 260 continues to supply the feedback clock signal FBCLK in accordance with the control voltage VCTRL at that time.

[0104] 19, a frequency divider 270 can also be disposed within the feedback section 240. In this case, the voltage-controlled oscillator 260 outputs the generated signal to a subsequent circuit as an output clock signal OUTCLK and also inputs the signal to the frequency divider 270. The frequency divider 270 divides the frequency of the clock signal to generate a feedback clock signal FBCLK and a feedback clock signal FBCLK_X, which are supplied to the phase comparison section 210.

[0105] Moreover, the third embodiment can also be applied to the fourth embodiment.

[0106] As described above, according to the fourth embodiment of the present technology, since the stop detection unit 320 is arranged in the PLL 205, the recovery time of the PLL 205 can be shortened.

[0107] <5. Fifth Embodiment> In the second embodiment described above, the control signal DOWN is initialized when the reference clock signal REFCLK is stopped. However, if the stop period is long, the control voltage VCTRL may fluctuate due to leakage current after initialization. The DLL 200 of this fifth embodiment differs from the second embodiment in that it corrects the fluctuating control voltage VCTRL after initialization.

[0108] 20 is a block diagram showing an example configuration of a DLL 200 according to a fifth embodiment of the present technology. The DLL 200 according to the fifth embodiment differs from the second embodiment in that it further includes a voltage correction unit 280. The voltage correction unit 280 is connected to a control line 239 between the filter 230 and the feedback unit 240. Note that the stop detection unit 320 according to the first embodiment can also be applied to the fifth embodiment.

[0109] The voltage corrector 280 holds the value of the control voltage VCTRL when the control signal DOWN is initialized as a hold value, and corrects the control voltage VCTRL to the hold value when the stop period has elapsed.

[0110] 21 is a block diagram showing an example configuration of a voltage correction unit 280 according to the fifth embodiment of the present technology. The voltage correction unit 280 includes a sample-and-hold circuit 281, an analog-to-digital converter 282, a logic circuit 283, a digital-to-analog converter 284, and a switch 285.

[0111] The sample-and-hold circuit 281 samples and holds the control voltage VCTRL on the control line 239 in synchronization with the detection signal STOP from the phase comparator 210. The analog-to-digital converter 282 converts the voltage held by the sample-and-hold circuit 281 into a digital signal Dout. The analog-to-digital converter 282 supplies the digital signal Dout to a logic circuit 283.

[0112] The logic circuit 283 performs control to correct the voltage when the suspension period has elapsed. When the digital signal Dout is output from the analog-to-digital converter 282, the logic circuit 283 stores the signal in a memory or the like. Then, at the timing when the reset signal PFDRST from the phase comparison unit 210 rises, the logic circuit 283 supplies the digital signal Dout to the digital-to-analog converter 284 and controls the switch 285 to a closed state.

[0113] The digital-to-analog converter 284 converts the digital signal Dout from the logic circuit 283 into a voltage and supplies it to the switch 285. The switch 285 opens and closes the path between the digital-to-analog converter 284 and the control line 239 under the control of the logic circuit 283.

[0114] 22 is a timing chart showing an example of the operation of the DLL 200 according to the fifth embodiment of the present technology. When the detection signal STOP rises at timing T12 during the stop period, the voltage correction unit 280 immediately thereafter converts the level V3 of the control voltage VCTRL at the time of initialization into a digital signal Dout and holds it. Here, it is assumed that the control voltage VCTRL fluctuates after initialization due to a leakage current and becomes a value lower than the level V3 at the time of initialization.

[0115] Then, when the reset signal PFDRST rises at timing T2 after the suspension period has elapsed, the voltage corrector 280 converts the held digital signal Dout to the level V3 before the leakage current fluctuation, and corrects the control voltage VCTRL to that level.

[0116] The third and fourth embodiments can also be applied to the fifth embodiment.

[0117] As described above, according to the fifth embodiment of the present technology, the voltage corrector 280 holds the control voltage VCTRL at the time of initialization, and corrects the control voltage VCTRL to the held value after the stop period has elapsed. This allows the control voltage VCTRL to be applied at the level before the fluctuation even if the control voltage VCTRL fluctuates after initialization due to leakage current.

[0118] 6. Sixth Embodiment In the first embodiment described above, the stop detector 320 detects the stop of the reference clock signal REFCLK and initializes the control signal DOWN. However, in this configuration, the control voltage VCTRL drops during the period leading up to initialization. The DLL 200 of this sixth embodiment differs from the first embodiment in that it compensates for the control voltage VCTRL based on the amount of this fluctuation. Here, "compensation" means that when the control voltage VCTRL fluctuates from V1 to V3 during the stop period, it is returned to V1, the voltage before the fluctuation.

[0119] 23 is a block diagram showing an example configuration of a DLL 200 according to a sixth embodiment of the present technology. The DLL 200 according to the sixth embodiment differs from the DLL 200 according to the first embodiment in that a voltage compensation unit 400 is further provided.

[0120] The voltage compensating section 400 compensates for the control voltage VCTRL based on the amount of fluctuation in the control voltage VCTRL during the period in which the reference clock signal REFCLK is stopped.

[0121] 24 is a circuit diagram showing an example configuration of a phase comparison unit 210 according to a sixth embodiment of the present technology. The phase comparison unit 210 according to the sixth embodiment differs from the first embodiment in that an inverter 315 is further provided in the phase comparator 310. The inverter 315 inverts the signal output from the flip-flop 311 and supplies the inverted signal to the charge pump 220 as a control signal UP.

[0122] Furthermore, the reset signal generating circuit 330 of the sixth embodiment supplies the detection signal STOP to the voltage compensation unit 400.

[0123] 25 is a circuit diagram showing a configuration example of a charge pump 220 and a voltage compensation unit 400 according to the sixth embodiment of the present technology. The charge pump 220 according to the sixth embodiment includes a pMOS (p-channel MOS) transistor 225 instead of the nMOS transistor 222.

[0124] The voltage compensation unit 400 includes an inverter 411, a replica circuit 420, capacitive elements 412 and 413, a logic circuit 414, and an adder 430. The replica circuit 420 includes a current source 421, a pMOS transistor 422, an nMOS transistor 423, and a current source 424.

[0125] The current source 421, pMOS transistor 422, nMOS transistor 423, and current source 424 are connected in series between a power supply terminal and a ground terminal. The inverter 411 inverts the control signal DOWN from the phase comparison unit 210 and supplies it to the gate of the pMOS transistor 422. The reference clock signal REFCLK is input to the gate of the nMOS transistor 423. The voltage VCR at the connection node between the pMOS transistor 422 and the nMOS transistor 423 is supplied to the adder 430 and the capacitive element 413.

[0126] With the circuit configuration described above, when a high-level control signal DOWN is supplied during the shutdown period, the voltage VCR rises. The amount of change in this voltage VCR (i.e., the amount of increase) is equal in absolute value to the amount of change in the control voltage VCTRL (i.e., the amount of decrease) caused by the control signal DOWN, but has a different sign. Hereinafter, the amount of change in voltage VCR will be referred to as the "compensation amount."

[0127] The capacitive element 412 holds the control voltage VCTRL of the control line 229 connected to the charge pump 220. The capacitive element 413 holds the voltage VCR.

[0128] The adder 430 adds the fluctuation amount (compensation amount) of the voltage VCR to the control voltage VCTRL under the control of the logic circuit 414. When the detection signal STOP is input, the logic circuit 414 controls the adder 430 to add the compensation amount. The adder 430 is an example of a computing unit described in the claims.

[0129] As in the first embodiment, an nMOS transistor 222 can be placed in the charge pump 220. In that case, the inverter 315 in the preceding stage of the charge pump 220 becomes unnecessary. Also, in the replica circuit 420, an nMOS transistor is placed in place of the pMOS transistor 422, and the inverter 411 in the preceding stage becomes unnecessary.

[0130] 26 is a circuit diagram showing an example of the configuration of the replica circuit 420 and the adder 430 according to the sixth embodiment of the present technology. The adder 430 includes switches 431 to 436, capacitive elements 437 and 438, and an operational amplifier 439.

[0131] One ends of the capacitance elements 437 and 438 are commonly connected to an inverting input terminal (-) of an operational amplifier 439. A non-inverting input terminal (+) of the operational amplifier 439 is connected to a ground terminal. The switch 431 opens and closes a path between the control line 229 and the other end of the capacitance element 437 in accordance with a control signal S1 from the logic circuit 414. The switch 432 opens and closes a path between the replica circuit 420 and the other end of the capacitance element 438 in accordance with a control signal S2 from the logic circuit 414.

[0132] The switch 433 opens and closes a path between the connection node of the switch 431 and the capacitance element 437 and the output terminal of the operational amplifier 439 in accordance with a control signal S3 from the logic circuit 414. The switch 434 opens and closes a path between the input terminal and output terminal of the operational amplifier 439 in accordance with a control signal S4 from the logic circuit 414.

[0133] The switch 435 opens and closes the path between the connection node of the switch 432 and the capacitance element 438 and the ground terminal in accordance with a control signal S5 from the logic circuit 414. The switch 436 opens and closes the path between the output terminal of the operational amplifier 439 and the control line 229 in accordance with a control signal S6 from the logic circuit 414.

[0134] Furthermore, the switches 431 to 436 are closed when the corresponding control signal is at a high level, and are open when the corresponding control signal is at a low level.

[0135] The switch 431 is an example of a first switch as set forth in the claims, and the switch 432 is an example of a second switch as set forth in the claims. The switch 433 is an example of a third switch as set forth in the claims, and the switch 434 is an example of a fourth switch as set forth in the claims. The switch 435 is an example of a fifth switch as set forth in the claims, and the switch 436 is an example of a sixth switch as set forth in the claims. The capacitance elements 437 and 438 are examples of first and second capacitance elements as set forth in the claims.

[0136] 27 is a timing chart showing an example of the operation of the DLL 200 according to the sixth embodiment of the present technology. The feedback clock signal FBCLK rises at timing T11, which is after timing T1 when the reference clock signal REFCLK stops. Immediately thereafter, the stop detection unit 320 detects the stop of the reference clock signal REFCLK and initializes the control signal DOWN at timing T15.

[0137] In accordance with the control signal DOWN from timing T11 to timing T15, the control voltage VCTRL drops from V1 to V3. If the amount of this change is ΔV, ΔV is expressed by the following equation. ΔV=V3-V1

[0138] On the other hand, the voltage VCR output from the replica circuit 420 rises during the period from timing T11 to timing T15, and if the amount of change (compensation amount) is ΔV', ΔV' is expressed by the following equation. ΔV'=-ΔV

[0139] At timing T16 after timing T15, the logic circuit 414 sets the control signals S1 to S3 to high level, and after the pulse period has elapsed, sets the control signals S1 and S3 to low level. Then, at timing T17 after timing T16, the logic circuit 414 sets the control signal S4 to high level. This control causes the voltage OPout at the output terminal of the operational amplifier 439 to rise to V3.

[0140] Then, the logic circuit 414 sets the control signal S2 to low level immediately after timing T17, and sets the control signal S5 to high level at timing T18. By this control, the compensation amount ΔV′ is added to the voltage OPout of the output terminal of the operational amplifier 439, and the voltage OPout increases to V1.

[0141] At timing T19 after timing T18, the logic circuit 414 sets the control signal S6 to a high level. This control compensates for the control voltage VCTRL using the compensation amount ΔV', and the control voltage VCTRL rises to V1, the level before the fluctuation. As a result, from timing T2 onwards, the recovery time becomes shorter than when no compensation is performed.

[0142] For example, in a comparative example that does not include the stop detection unit 320 and the voltage compensation unit 400, the recovery time can reach several tens of nanoseconds (ns), making it difficult to meet the requirements of standards such as MIPI. By including the stop detection unit 320 and the voltage compensation unit 400, the recovery time can be reduced to, for example, 10 nanoseconds (ns).

[0143] Although the phase comparator 310 that outputs the control signal DOWN during the suspension period is used, it is also possible to use a phase comparator 310 that outputs the control signal UP instead. In this case, the control signal UP is input to the replica circuit 420, a subtractor is provided instead of the adder 430, and the subtractor drops the control voltage VCTRL by the amount of increase in the control voltage VCTRL.

[0144] Moreover, the second and third embodiments can be applied to the sixth embodiment.

[0145] As described above, according to the sixth embodiment of the present technology, the voltage compensation unit 400 compensates for the control voltage VCTRL based on the amount of fluctuation in the control voltage VCTRL during the stop period, and therefore the recovery time can be made shorter than when no compensation is performed.

[0146] 7. Seventh Embodiment In the sixth embodiment described above, when the stop detection unit 320 detects a stop of the reference clock signal REFCLK, the voltage compensation unit 400 performs voltage compensation, but in this configuration, it is necessary to provide the stop detection unit 320 within the phase comparison unit 210. The DLL 200 of this seventh embodiment differs from the sixth embodiment in that the voltage compensation unit 400 performs compensation when the comparison result between the control voltage VCTRL and the lower limit voltage is inverted.

[0147] 28 is a block diagram showing an example configuration of a DLL 200 according to the seventh embodiment of the present technology. The DLL 200 according to the seventh embodiment differs from the sixth embodiment in that the stop detection unit 320 is not arranged in the phase comparison unit 210.

[0148] 29 is a circuit diagram showing an example configuration of a voltage compensation unit 400 according to a seventh embodiment of the present technology. The voltage compensation unit 400 according to the seventh embodiment differs from the sixth embodiment in that it further includes a comparator 415 and a pulse generator 416.

[0149] The comparator 415 compares the control voltage VCTRL with a predetermined lower limit voltage VIL and supplies the comparison result COMPout to the pulse generator 416.

[0150] The pulse generator 416 generates a pulse signal when the comparison result COMPout is inverted (in other words, when the control voltage VCTRL falls below the lower limit voltage VIL). The pulse generator 416 supplies the pulse signal to the logic circuit 414.

[0151] 30 is a timing chart showing an example of the operation of the DLL 200 according to the sixth embodiment of the present technology. After timing T11 in the stop period, the phase comparator 210 outputs a high-level control signal DOWN. This control signal DOWN gradually reduces the control voltage VCTRL.

[0152] Then, when the control voltage VCTRL falls below the lower limit voltage VIL at timing T15, the comparison result COMPout of the comparator 415 is inverted. If the amount of fluctuation in the control voltage VCTRL from timing T11 to T15 is ΔV, the absolute value of the amount of fluctuation (compensation amount) ΔV' of the voltage VCR output by the replica circuit 420 is equal to ΔV.

[0153] Immediately after timing T15, the adder 430 adds ΔV′ in the same manner as in the sixth embodiment, thereby compensating for the control voltage VCTRL.

[0154] If the suspension period continues, the control signal DOWN causes the control voltage VCTRL to drop again. Then, at timing T17, when the control voltage VCTRL falls below the lower limit voltage VIL, the comparison result COMPout of the comparator 415 is inverted again, and the voltage compensation unit 400 compensates the control voltage VCTRL. Thereafter, the same control is repeated until the suspension period elapses.

[0155] Although the phase comparator 310 that outputs the control signal DOWN during the stop period is used, a phase comparator 310 that outputs the control signal UP can also be used instead. In this case, the comparator 415 can compare the control voltage VCTRL with the upper limit voltage.

[0156] As described above, according to the seventh embodiment of the present technology, the voltage compensator 400 performs compensation when the comparison result between the control voltage VCTRL and the lower limit voltage (or the upper limit voltage) is inverted, so that the stop detector 320 can be eliminated.

[0157] 8. Eighth Embodiment In the sixth embodiment described above, voltage compensation unit 400 compensates for the voltage, but this requires the use of analog circuits including operational amplifiers and capacitance elements, making it difficult to reduce the circuit size. DLL 200 of this eighth embodiment differs from the sixth embodiment in that it compensates for the voltage using digital circuits.

[0158] 31 is a block diagram showing an example configuration of a DLL 200 according to an eighth embodiment of the present technology. The DLL 200 according to the eighth embodiment differs from the sixth embodiment in that the voltage compensation unit 400 is not connected to the control line 229.

[0159] Furthermore, the DLL 200 of the eighth embodiment receives the reference clock signal REFCLK and the reference clock signal REFCLKN that is 180 degrees out of phase with the reference clock signal REFCLK. The delay unit 250 delays the reference clock signals REFCLK and REFCLKN using different delay lines to generate feedback clock signals FBCLK and FBCLKN, and supplies them to the phase comparison unit 210.

[0160] 32 is a circuit diagram showing a configuration example of a phase comparator unit 210 according to an eighth embodiment of the present technology. The phase comparator unit 210 according to the eighth embodiment differs from the sixth embodiment in that it further includes a voltage compensator unit 400. The voltage compensator unit 400 includes a recovery phase comparator control circuit 440. The recovery phase comparator control circuit 440 includes an AND gate 441, a flip-flop 442, an inverter 443, and an AND gate 444.

[0161] Furthermore, the phase comparator 310 of the eighth embodiment includes flip-flops 316 and 317, a NOR (negative OR) gate 318, and an AND gate 319. The stop detection unit 320 of the eighth embodiment includes an AND gate 322, a flip-flop 323, an inverter 324, and an AND gate 325.

[0162] In the phase comparator 310, the flip-flop 316 captures and holds a high level in synchronization with the reference clock signals REFCLK and REFCLKN. The flip-flop 316 has a non-inverting input clock terminal and an inverting input clock terminal, with the reference clock signal REFCLK input to the non-inverting input side and the reference clock signal REFCLKN input to the inverting input side. The flip-flop 316 also outputs the held value as a control signal UP to the charge pump 220, the AND gate 319, and the recovery phase comparator control circuit 440.

[0163] Flip-flop 317 acquires and holds a high level in synchronization with feedback clock signals FBCLK and FBCLKN. Flip-flop 317 has a non-inverting input clock terminal and an inverting input clock terminal, with the feedback clock signal FBCLK input to the non-inverting input and the feedback clock signal FBCLKN input to the inverting input. Flip-flop 317 also outputs the held value as a control signal DOWN to charge pump 220, AND gate 319, and stop detection unit 320.

[0164] The AND gate 319 outputs the logical product of the control signals UP and DOWN to the NOR gate 318. The NOR gate 318 outputs the NOR of the signals from the recovery phase comparator control circuit 440, the AND gate 319, and the stop detection unit 320 as the control signal PFDRSTN. This control signal PFDRSTN is input to the clear terminals of the inverting inputs of the flip-flops 316 and 317.

[0165] In the stop detection unit 320 , the AND gate 322 outputs the logical product of the control signal READY from the control unit 134 and the control signal DOWN from the phase comparator 310 to the input terminal of the flip-flop 323 .

[0166] The flip-flop 323 receives and holds the signal from the AND gate 322 in synchronization with the feedback clock signal FBCLKN. The flip-flop 323 supplies the held control signal DOWN to an inverter 324 and an AND gate 325.

[0167] The inverter 324 inverts the signal from the flip-flop 323 and outputs it to the AND gate 325. The AND gate 325 supplies the logical product of the signal from the flip-flop 323 and the inverted signal from the inverter 324 to the NOR gate 318 as a reset signal.

[0168] In the recovery phase comparator control circuit 440 , an AND gate 441 outputs the logical product of the control signal READY and the control signal UP from the phase comparator 310 to the input terminal of a flip-flop 442 .

[0169] The flip-flop 442 receives and holds the signal from the AND gate 441 in synchronization with the reference clock signal REFCLKN. The flip-flop 442 supplies the held signal to an inverter 443 and an AND gate 444.

[0170] The inverter 443 inverts the signal from the flip-flop 442 and outputs it to the AND gate 444. The AND gate 444 supplies the logical product of the signal from the flip-flop 442 and the inverted signal from the inverter 443 to the NOR gate 318 as a reset signal.

[0171] With the above circuit configuration, the stop detection unit 320 outputs a reset signal when a predetermined period dt has elapsed since the start of output of the control signal DOWN during the stop period of the reference clock signal REFCLK, thereby initializing the control signal DOWN.

[0172] Furthermore, the recovery phase comparator control circuit 440 outputs a reset signal to initialize the control signal UP when a predetermined period dt has elapsed since the start of output of the control signal UP after the end of the stop period of the reference clock signal REFCLK.

[0173] As shown in the figure, the voltage compensation unit 400 is configured by a digital circuit, and therefore the circuit scale can be reduced compared to the sixth embodiment that uses an analog circuit.

[0174] 33 is a diagram showing an example of the operation of the flip-flop 316 according to the eighth embodiment of the present technology. The flip-flop 316 includes a clear terminal CLR, a clock terminal clk+, a clock terminal clk-, a data input terminal D, and an output terminal Q. In the diagram, "H" indicates a high level, and "L" indicates a low level. Furthermore, "↑" indicates a rising edge of a signal, and "↓" indicates a falling edge of a signal.

[0175] When a low level is input to the clear terminal CLR of the inverting input, a low level is output from the output terminal Q regardless of the values of the clock terminal and data input terminal D. When a high level is input to the clear terminal CLR and the state of the clock terminal clk+ of the non-inverting input is other than rising or the state of the clock terminal clk- of the inverting input is other than falling, the flip-flop 316 is in a holding state, and the held value is output from the output terminal Q. When a high level is input to the clear terminal CLR, the state of the clock terminal clk+ is rising and the state of the clock terminal clk- is falling, the flip-flop 316 is in a through state, and the value of the data input terminal D is output directly from the output terminal Q.

[0176] The circuit configuration of the flip-flop 317 is the same as that of the flip-flop 316 .

[0177] 34 is a timing chart showing an example of the operation of the DLL 200 according to the sixth embodiment of the present technology. When output of the control signal DOWN starts at timing T11 within the stop period, the stop detection unit 320 outputs a reset signal when a predetermined period has elapsed. Immediately thereafter, at timing T15, the reset signal initializes the control signal DOWN to a low level. This control causes the control voltage VCTRL to drop over a period dt, with the amount of fluctuation being ΔV.

[0178] Then, when output of the control signal UP begins at timing T2 upon recovery, the recovery phase comparator control circuit 440 outputs a reset signal when a predetermined period has elapsed. Immediately thereafter, at timing T5, the reset signal initializes the control signal UP to low level. This control causes the control voltage VCTRL to rise over a period dt, and its fluctuation (compensation amount) becomes ΔV', the absolute value of which is equal to ΔV.

[0179] As shown in the figure, when the reference clock signal REFCLK stops, the stop detection unit 320 outputs the control signal DOWN for a predetermined period. Then, when the reference clock signal REFCLK resumes, the recovery phase comparator control circuit 440 outputs the control signal UP for the same period as the output period of the control signal DOWN. This compensates for the control voltage VCTRL.

[0180] Although the phase comparator 310 that outputs the control signal DOWN during the suspension period is used, it is also possible to use a phase comparator 310 that outputs the control signal UP instead. In this case, the suspension detection unit 320 initializes the control signal UP during the suspension period, and the recovery phase comparator control circuit 440 initializes the control signal DOWN upon recovery.

[0181] As described above, according to the eighth embodiment of the present technology, the voltage is compensated by the recovery phase comparator control circuit 440, which is a digital circuit, and therefore the circuit size can be reduced compared to the sixth embodiment, which uses an analog circuit.

[0182] 9. Ninth Embodiment In the sixth embodiment described above, the voltage compensating unit 400 is arranged in the DLL 200, but the voltage compensating unit 400 can also be applied to a PLL. The ninth embodiment differs from the ninth embodiment in that the voltage compensating unit 400 is applied to a PLL.

[0183] 35 is a block diagram showing an example configuration of a PLL 205 according to the ninth embodiment of the present technology. The PLL 205 is provided in the receiving circuit 130 or the like. The PLL 205 includes a phase comparison unit 210, a charge pump 220, a voltage compensation unit 400, a filter 230, and a feedback unit 240.

[0184] The configurations of the phase comparison unit 210, charge pump 220, voltage compensation unit 400, and filter 230 of the ninth embodiment are the same as those of the sixth embodiment. A voltage controlled oscillator 260 and a frequency divider 270 are arranged in a feedback unit 240 of the ninth embodiment.

[0185] The voltage-controlled oscillator 260 generates a clock signal having a frequency corresponding to the control voltage VCTRL, and outputs the generated signal as an output clock signal OUTCLK to a subsequent circuit and also inputs it to the frequency divider 270. The frequency divider 270 divides the frequency of the clock signal to generate a feedback clock signal FBCLK and a feedback clock signal FBCLK_X, which are supplied to the phase comparison unit 210.

[0186] In FIG. 35, the frequency divider 270 can be omitted as shown in FIG.

[0187] As described above, according to the ninth embodiment of the present technology, the voltage compensation section 400 is disposed in the PLL 205, so that the recovery time of the PLL 205 can be shortened.

[0188] <10. Mobile Application Examples> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0189] FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0190] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 36, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0191] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0192] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0193] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0194] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0195] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0196] The microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0197] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0198] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0199] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 36, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0200] FIG. 37 is a diagram showing an example of the installation position of the imaging unit 12031.

[0201] In FIG. 37, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0202] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0203] 37 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0204] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0205] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0206] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0207] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0208] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capture unit 12031 of the above-described configuration. Specifically, the image capture device 100 in FIG. 1 can be applied to the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to shorten the lock time and speed up the interface.

[0209] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0210] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0211] The present technology can also be configured as follows. (1) a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs the comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback section that generates the feedback clock signal according to the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result when the reference clock signal has stopped; A semiconductor integrated circuit comprising: (2) The feedback section includes a delay section that delays the reference clock signal for a delay time corresponding to the control voltage and outputs the delayed reference clock signal as the feedback clock signal. The semiconductor integrated circuit according to (1) above. (3) the comparison result includes a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage; the phase comparator outputs one of the first and second control signals; The stop detection unit a front-stage flip-flop that holds one of the first and second control signals in synchronization with a clock signal having a delay time different from that of the feedback clock signal; a reset signal generating circuit that generates a reset signal for initializing the comparison result based on the control signal held in the previous stage flip-flop and the reference clock signal; Equipped with The phase comparator initializes the comparison result in accordance with the reset signal. The semiconductor integrated circuit according to (2) above. (4) The reset signal generating circuit a delay element that delays the control signal held in the previous stage flip-flop; a post-stage logic gate that generates a predetermined detection signal based on the held control signal and the delayed control signal; a subsequent flip-flop that retrieves and holds a predetermined value in synchronization with the reference clock signal, outputs the held value as the reset signal, and initializes the held value in accordance with the detection signal; The semiconductor integrated circuit according to (3) above, comprising: (5) the previous stage flip-flop outputs the held control signal as a detection signal; The reset signal generation circuit a subsequent flip-flop that captures and holds the detection signal in synchronization with the reference clock signal; an inverter that inverts the signal held in the subsequent flip-flop and outputs the inverted signal; a post-stage logic circuit that generates the reset signal based on the held detection signal and the inverted signal; The semiconductor integrated circuit according to (3) above, comprising: (6) A front-stage logic gate is further provided for inputting either the first or second control signal to the front-stage flip-flop when a predetermined period has elapsed since the control voltage was at its initial value. The semiconductor integrated circuit according to any one of (3) to (5). (7) The feedback section further includes a multiplexer that selects one of a plurality of clock signals with different delay times and supplies the selected clock signal to the preceding flip-flop. The semiconductor integrated circuit according to any one of (3) to (6). (8) The feedback unit includes a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage as the feedback clock signal. The semiconductor integrated circuit according to any one of (1) to (7). (9) The feedback section is a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal; a frequency divider that divides the output clock signal and outputs the divided signal as the feedback clock signal; Equipped with The semiconductor integrated circuit according to any one of (1) to (7). (10) The control voltage when the comparison result is initialized is held as a held value, and a voltage correction unit is further provided that corrects the control voltage to the held value when a stop period of the reference clock signal has elapsed. The semiconductor integrated circuit according to any one of (1) to (9). (11) The clock signal generating unit further includes a voltage compensator that compensates for the control voltage based on the amount of fluctuation in the control voltage during a period when the reference clock signal is stopped. The semiconductor integrated circuit according to (1) above. (12) The voltage compensation unit a replica circuit that generates a compensation amount according to the fluctuation amount during the suspension period; a computing unit that compensates the control voltage by the compensation amount when the stop period has elapsed; The semiconductor integrated circuit according to (11) above, comprising: (13) The computing unit is An operational amplifier and first and second capacitance elements each having one end connected in common to an input terminal of the operational amplifier; a first switch that opens and closes a path between a control line that supplies the control voltage and the other end of the first capacitive element; a second switch that opens and closes a path between the replica circuit and the other end of the second capacitive element; a third switch that opens and closes a path between the other end of the first capacitive element and the output terminal of the operational amplifier; a fourth switch that opens and closes a path between the input terminal and the output terminal of the operational amplifier; a fifth switch that opens and closes a path between the other end of the second capacitive element and a predetermined reference potential; a sixth switch that opens and closes a path between the control line and the output terminal of the operational amplifier; The semiconductor integrated circuit according to (12) above, comprising: (14) The voltage compensation unit a replica circuit that generates a compensation amount according to the fluctuation amount during the suspension period; a computing unit that compensates the control voltage by the compensation amount when the stop period has elapsed; The semiconductor integrated circuit according to (11) above. (15) The feedback section is a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal; a frequency divider that divides the output clock signal and outputs the divided signal as the feedback clock signal; Equipped with The semiconductor integrated circuit according to any one of (11) to (14). (16) a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs the comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback section that generates the feedback clock signal according to the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result when the reference clock signal has stopped; a transmitter circuit for supplying the reference clock signal; An electronic device comprising: (17) a phase comparison step of comparing the phase of an input reference clock signal with the phase of a feedback clock signal and outputting a comparison result; a voltage generating step of generating a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback step for generating the feedback clock signal according to the control voltage; a stop detection step of detecting whether the reference clock signal has stopped and initializing the comparison result if the reference clock signal has stopped; A method for controlling a semiconductor integrated circuit comprising: [Explanation of symbols]

[0212] 100 Imaging device 110 Solid-state imaging device 111, 141 Transmitting circuit 112, 130 receiving circuit 113 Internal circuit 120 receiving devices 131~133 Receiver 134 Control Unit 135, 136, 311, 312, 316, 317, 321, 323, 334, 336, 442 flip-flops 140 Sending Device 200 DLL 205 PLL 210 Phase comparator 220 Charge Pump 221, 224, 421, 424 current source 222, 223, 423 nMOS transistors 225, 422 pMOS transistors 230 filters 240 Return Section 241 Multiplexer 250 Delay Section 251, 252, 331 delay elements 260 Voltage Controlled Oscillator 270 divider 280 Voltage correction unit 281 Sample and hold circuit 282 Analog-to-Digital Converter 283, 414 Logic circuits 284 Digital-to-Analog Converter 285, 431-436 Switches 310 Phase comparator 313, 319, 322, 325, 339, 441, 444 AND gates 314, 338 NAND gates 315, 324, 337, 411, 443 Inverter 318 NOR Gate 320 Stop detection unit 330 Reset signal generation circuit 332, 333 logic gates 400 Voltage compensation section 412, 413, 437, 438 Capacitor elements 415 Comparator 416 Pulse Generator 420 Replica Circuit 430 Adder 439 Op-Amp 440 Recovery phase comparator control circuit 12031 Imaging unit

Claims

1. a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs the comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback section that generates the feedback clock signal according to the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result when the reference clock signal has stopped; Equipped with the feedback section includes a delay section that delays the reference clock signal for a delay time corresponding to the control voltage and outputs the delayed reference clock signal as the feedback clock signal; the comparison result includes a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage; the phase comparator outputs one of the first and second control signals; The stop detection unit a front-stage flip-flop that holds one of the first and second control signals in synchronization with a clock signal having a delay time different from that of the feedback clock signal; a reset signal generating circuit that generates a reset signal for initializing the comparison result based on the control signal held in the previous stage flip-flop and the reference clock signal; Equipped with The phase comparator initializes the comparison result in accordance with the reset signal. Semiconductor integrated circuit.

2. The reset signal generation circuit a delay element that delays the control signal held in the previous stage flip-flop; a post-stage logic gate that generates a predetermined detection signal based on the held control signal and the delayed control signal; a subsequent flip-flop that retrieves and holds a predetermined value in synchronization with the reference clock signal, outputs the held value as the reset signal, and initializes the held value in accordance with the detection signal; The semiconductor integrated circuit according to claim 1 , comprising:

3. The previous stage flip-flop outputs the held control signal as a detection signal, The reset signal generation circuit a subsequent flip-flop that captures and holds the detection signal in synchronization with the reference clock signal; an inverter that inverts the signal held in the subsequent flip-flop and outputs the inverted signal; a post-stage logic circuit that generates the reset signal based on the held detection signal and the inverted signal; The semiconductor integrated circuit according to claim 1 , comprising:

4. a first stage logic gate that inputs either the first or second control signal to the first stage flip-flop when a predetermined period has elapsed since the control voltage was at its initial value; 2. The semiconductor integrated circuit according to claim 1.

5. The feedback section further includes a multiplexer that selects one of a plurality of clock signals having different delay times and supplies the selected clock signal to the preceding flip-flop.

2. The semiconductor integrated circuit according to claim 1.

6. The feedback section includes a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage as the feedback clock signal.

2. The semiconductor integrated circuit according to claim 1.

7. The feedback section is a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal; a frequency divider that divides the output clock signal and outputs the divided signal as the feedback clock signal; Equipped with 2. The semiconductor integrated circuit according to claim 1.

8. The control voltage when the comparison result is initialized is held as a held value, and a voltage correction unit is further provided which corrects the control voltage to the held value when a stop period of the reference clock signal has elapsed.

2. The semiconductor integrated circuit according to claim 1.

9. A phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs the comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback section that generates the feedback clock signal according to the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result when the reference clock signal has stopped; a voltage compensating unit that compensates for the control voltage based on a fluctuation amount of the control voltage during a stop period of the reference clock signal; Equipped with the comparison result includes a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage; the stop detection unit initializes one of the first and second control signals when a predetermined period has elapsed since the start of output of the one of the first and second control signals during the stop period; The voltage compensator initializes the other of the first and second control signals when the predetermined period has elapsed since the start of output of the other of the first and second control signals after the stop period has elapsed. Semiconductor integrated circuit.

10. The voltage compensation unit: a replica circuit that generates a compensation amount according to the fluctuation amount during the suspension period; a computing unit that compensates the control voltage by the compensation amount when the stop period has elapsed; The semiconductor integrated circuit according to claim 9, comprising:

11. The computing unit An operational amplifier and first and second capacitance elements each having one end connected in common to an input terminal of the operational amplifier; a first switch that opens and closes a path between a control line that supplies the control voltage and the other end of the first capacitive element; a second switch that opens and closes a path between the replica circuit and the other end of the second capacitive element; a third switch that opens and closes a path between the other end of the first capacitive element and the output terminal of the operational amplifier; a fourth switch that opens and closes a path between the input terminal and the output terminal of the operational amplifier; a fifth switch that opens and closes a path between the other end of the second capacitive element and a predetermined reference potential; a sixth switch that opens and closes a path between the control line and the output terminal of the operational amplifier; The semiconductor integrated circuit according to claim 10, comprising:

12. The feedback section is a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the control voltage and outputs the clock signal as an output clock signal; a frequency divider that divides the output clock signal and outputs the divided signal as the feedback clock signal; Equipped with 10. The semiconductor integrated circuit according to claim 9.

13. a phase comparator that compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs the comparison result; a charge pump that generates a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback section that generates the feedback clock signal according to the control voltage; a stop detection unit that detects whether the reference clock signal has stopped and initializes the comparison result when the reference clock signal has stopped; a transmitter circuit for supplying the reference clock signal; Equipped with the feedback section includes a delay section that delays the reference clock signal for a delay time corresponding to the control voltage and outputs the delayed reference clock signal as the feedback clock signal; the comparison result includes a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage; the phase comparator outputs one of the first and second control signals; The stop detection unit a front-stage flip-flop that holds one of the first and second control signals in synchronization with a clock signal having a delay time different from that of the feedback clock signal; a reset signal generating circuit that generates a reset signal for initializing the comparison result based on the control signal held in the previous stage flip-flop and the reference clock signal; Equipped with The phase comparator initializes the comparison result in accordance with the reset signal. electronic equipment. a phase comparison step in which a phase comparator compares the phase of an input reference clock signal with the phase of a feedback clock signal and outputs a comparison result; a voltage generating step of generating a control voltage for controlling the frequency of the feedback clock signal based on the comparison result; a feedback step in which a feedback unit generates the feedback clock signal according to the control voltage; a stop detection step in which a stop detection unit detects whether the reference clock signal has stopped, and initializes the comparison result if the reference clock signal has stopped; Equipped with the feedback section includes a delay section that delays the reference clock signal for a delay time corresponding to the control voltage and outputs the delayed reference clock signal as the feedback clock signal; the comparison result includes a first control signal for increasing the control voltage and a second control signal for decreasing the control voltage; the phase comparator outputs one of the first and second control signals; The stop detection unit a front-stage flip-flop that holds one of the first and second control signals in synchronization with a clock signal having a delay time different from that of the feedback clock signal; a reset signal generating circuit that generates a reset signal for initializing the comparison result based on the control signal held in the previous stage flip-flop and the reference clock signal; Equipped with The phase comparator initializes the comparison result in accordance with the reset signal. A method for controlling a semiconductor integrated circuit.

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