Protocol determination circuit and protocol switching circuit

Abstract

The present invention improves noise resistance of a protocol determination circuit that determines a communication protocol between circuits. A protocol determination circuit (1) comprises a sampling circuit (11) and a majority circuit (12). The sampling circuit (11) performs samplings of a protocol specification signal (SS) multiple times, the protocol specification signal being either a value representing a first communication protocol I2C or a value representing a second communication protocol SPI. The majority circuit (12) outputs a majority signal (MAJOR_SS) indicating the communication protocol corresponding to the value that has been sampled more than half the number of times among the multiple times of the samplings.

Description

[Technical Field]

[0001] The present disclosure relates to a protocol determination circuit that determines a communication protocol between circuits, and a protocol switching circuit that includes the protocol determination circuit. [Background technology]

[0002] Conventionally, a configuration for determining a communication protocol between circuits has been known. For example, Japanese Patent Application Laid-Open No. 63-250759 (Patent Document 1) discloses an integrated circuit device that switches communication modes between I2C (Inter-Integrated Circuit) mode and SPI (Serial Peripheral Interface) mode. In this integrated circuit device, the I2C mode is selected in the initial state after power-on reset. If the clock input signal is High at the falling edge of the chip select signal (when it switches from High to Low), the SPI mode is selected and communication is performed. If communication is started without the chip select signal falling, communication is performed in the initial I2C mode. If a stop condition is met in the I2C mode, where the data input signal rises (changes from Low to High) and the clock input signal is High, or if a rising edge occurs in the chip select signal in the SPI mode, it is determined that a communication termination condition is met and the communication mode is returned to the initial I2C mode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 63-250759 Summary of the Invention [Problem to be solved by the invention]

[0004] Normally, in I2C communication, the communication mode is switched on the assumption that the chip select signal does not change, while in SPI communication, the communication mode is switched on the assumption that the clock signal is high at the falling edge of the chip select signal. Therefore, if the chip select signal changes in I2C mode due to superimposed noise, or if the clock signal goes low at the falling edge of the chip select signal in SPI mode, the integrated circuit device disclosed in Patent Document 1 may not be able to properly determine the protocol, making communication impossible.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to improve the noise resistance of a protocol determination circuit that determines a communication protocol between circuits. [Means for solving the problem]

[0006] A protocol determination circuit according to the present disclosure includes a sampling circuit and a majority circuit. The sampling circuit samples a protocol designation signal, which is either a value representing a first communication protocol or a value representing a second communication protocol, multiple times. The majority circuit outputs a majority signal indicating the communication protocol corresponding to the value sampled the majority of the multiple times. [Effects of the Invention]

[0007] According to the protocol determination circuit of the present disclosure, the noise resistance of the protocol determination circuit that determines the communication protocol between circuits can be improved by using a majority signal based on multiple samplings of the protocol designation signal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of a protocol switching circuit according to a first embodiment. [Figure 2] 2 is a block diagram showing an example of the configuration of a protocol determination circuit shown in FIG. 1; [Figure 3] 3 is a time chart according to the first embodiment of the signals shown in FIGS. 1 and 2 when I2C communication is selected by a chip select signal. [Figure 4] 3 is a time chart according to the first embodiment of the signals shown in FIGS. 1 and 2 when SPI communication is selected by a chip select signal. [Figure 5] 3 is a time chart according to the second embodiment of the present invention showing the signals shown in FIGS. 1 and 2 when I2C communication is selected by a chip select signal. [Figure 6] 3 is a time chart according to the second embodiment of the present invention showing the signals shown in FIGS. 1 and 2 when SPI communication is selected by a chip select signal. [Figure 7] FIG. 11 is a block diagram showing an example of the configuration of a protocol switching circuit according to a third embodiment. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration of a protocol switching circuit according to a fourth embodiment. [Figure 9] FIG. 13 is a block diagram showing an example of the configuration of a protocol switching circuit according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and their description will not be repeated in principle.

[0010] Embodiment 1 Fig. 1 is a block diagram showing an example configuration of a protocol switching circuit 100 according to the first embodiment. As shown in Fig. 1, the protocol switching circuit 100 includes input terminals Pi1, Pi2, and Pi3, an output terminal Po, an input / output terminal Pio, a protocol determination circuit 1, an SPI communication circuit 2, a tri-state buffer 3, an I2C communication circuit 4, and a bidirectional buffer 5. Hereinafter, the protocol determination circuit 1, the SPI communication circuit 2, and the I2C communication circuit 4 will also be collectively referred to as internal circuits.

[0011] The input terminal Pi1 receives a reset signal RST. The reset signal RST initializes the internal circuitry. The input terminal Pi2 receives a serial clock signal SCL in I2C (first communication protocol) and SPI (second communication protocol). The serial clock signal SCL is a clock signal referenced when the internal circuitry is operating. The input terminal Pi3 receives a chip select signal SS (protocol designation signal) that indicates the slave selected in SPI. The chip select signal SS is set to inactive logic (first value) during I2C communication and to active logic (second value) during SPI communication. Note that the active logic of the chip select signal SS is low or 0, and the inactive logic is high or 1.

[0012] The output terminal Po outputs the master-in / slave-out signal MISO from the slave to the master in SPI. During I2C communication, the master-in / slave-out signal MISO becomes high impedance. The input / output terminal Pio receives the master-out / slave-in signal MOSI from the master to the slave in SPI. The input / output terminal Pio receives and outputs the serial data signal SDA in I2C.

[0013] The protocol determination circuit 1 receives a reset signal RST from the input terminal Pi1, a serial clock signal SCL from the input terminal Pi2, and a chip select signal SS from the input terminal Pi3. During initial communication after the reset signal RST is released (changed from low to high), the protocol determination circuit 1 samples the chip select signal SS multiple times (e.g., an odd number of times greater than three) at the rising edges of the serial clock signal SCL. The protocol determination circuit 1 determines whether the communication protocol is I2C or SPI by majority vote among the multiple samples of the chip select signal SS. Specifically, the protocol determination circuit 1 determines the protocol as SPI if the number of active logics is large among the multiple samples of the chip select signal SS, and determines the protocol as I2C if the number of inactive logics is large among the multiple samples of the chip select signal SS. The protocol determination circuit 1 latches the determination result as a majority vote signal MAJOR_SS and holds it until the next reset signal RST becomes valid. The protocol determination circuit 1 outputs the majority vote signal MAJOR_SS to the SPI communication circuit 2 and the I2C communication circuit 4.

[0014] The SPI communication circuit 2 receives a reset signal RST from the input terminal Pi1, a serial clock signal SCL from the input terminal Pi2, a chip select signal SS from the input terminal Pi3, a master-out / slave-in signal MOSI or a serial data signal SDA from the bidirectional buffer 5, and a majority signal MAJOR_SS from the protocol determination circuit 1. When the majority signal MAJOR_SS indicates SPI (active logic), the SPI communication circuit 2 outputs an output enable signal and output data to the tri-state buffer 3 based on SPI. When the majority signal MAJOR_SS indicates I2C (inactive logic), the SPI communication circuit 2 controls the tri-state buffer 3 so that its output becomes high impedance. When the tri-state buffer 3 receives the output enable signal, the tri-state buffer 3 outputs the signal received from the SPI communication circuit 2.

[0015] The I2C communication circuit 4 receives a reset signal RST from the input terminal Pi1, a serial clock signal SCL from the input terminal Pi2, a master-out / slave-in signal MOSI or a serial data signal SDA from the bidirectional buffer 5, and a majority signal MAJOR_SS from the protocol determination circuit 1. If the majority signal MAJOR_SS indicates I2C, the I2C communication circuit 4 outputs an output enable signal to the bidirectional buffer 5 based on I2C. If the majority signal MAJOR_SS indicates SPI, the bidirectional buffer 5 is controlled so that it outputs the master-out / slave-in signal MOSI received from the input / output terminal Pio. Note that a fixed value of Low is input to the bidirectional buffer 5 to comply with the I2C I / O buffer standard.

[0016] Fig. 2 is a block diagram showing an example of the configuration of the protocol determination circuit 1 of Fig. 1. As shown in Fig. 2, the protocol determination circuit 1 includes input terminals Pi11, Pi12, and Pi13, an output terminal Po10, a one-shot 2-bit counter 10, an enable shift register circuit 11 (sampling circuit), and a majority circuit 12. Note that Fig. 2 describes an example of the configuration of the protocol determination circuit 1 when the chip select signal SS is sampled three times, but the number of times the chip select signal SS is sampled may be any number of times and is not limited to three.

[0017] 2, the input terminal Pi11 receives a reset signal RST, the input terminal Pi12 receives a serial clock signal SCL, the input terminal Pi13 receives a chip select signal SS, and the output terminal Po10 outputs a majority signal MAJOR_SS.

[0018] The one-shot 2-bit counter 10 includes a 2-bit counter 101 and a comparator 102. The 2-bit counter 101 receives a reset signal RST from an input terminal Pi11, a serial clock signal SCL from an input terminal Pi12, and a sampling enable signal SMP_EN from the comparator 102. The 2-bit counter 101 initializes a count signal CNT to 0 while the reset signal RST is low. The 2-bit counter 101 counts up the count signal CNT at the rising edge of the serial clock signal SCL. The 2-bit counter 101 outputs the count signal CNT to the comparator 102. If the count signal CNT is not 3, the comparator 102 outputs the sampling enable signal SMP_EN as high. If the count signal CNT is 3, the comparator 102 outputs the sampling enable signal SMP_EN as low. When the sampling enable signal SMP_EN is Low, the 2-bit counter 101 stops counting the count signal CNT.

[0019] The enable shift register circuit 11 includes enable flip-flop circuits 111, 112, and 113. The enable flip-flop circuit 111 receives a serial clock signal SCL from an input terminal Pi12, a chip select signal SS from an input terminal Pi13, and a sampling enable signal SMP_EN from the one-shot 2-bit counter 10. When the sampling enable signal SMP_EN is High, the enable flip-flop circuit 111 samples the value of the chip select signal SS at the rising edge of the serial clock signal SCL and outputs the sampled value as the chip select signal SS_D1 to the enable flip-flop circuit 112 and the majority circuit 12. When the sampling enable signal SMP_EN is Low, the enable flip-flop circuit 111 stops sampling the chip select signal SS and holds the value of the chip select signal SS_D1. When the sampling enable signal SMP_EN is Low, the value of the chip select signal SS_D1 held by the enable flip-flop circuit 111 is the value of the chip select signal SS sampled by the enable flip-flop circuit 111 for the third time.

[0020] The enable flip-flop circuit 112 receives the serial clock signal SCL from the input terminal Pi12, the chip select signal SS_D1 from the enable flip-flop circuit 111, and the sampling enable signal SMP_EN from the one-shot 2-bit counter 10. When the sampling enable signal SMP_EN is High, the enable flip-flop circuit 112 samples the value of the chip select signal SS_D1 at the rising edge of the serial clock signal SCL and outputs the sampled value as the chip select signal SS_D2 to the enable flip-flop circuit 113 and the majority circuit 12. When the sampling enable signal SMP_EN is Low, the enable flip-flop circuit 112 stops sampling the chip select signal SS_D1 and holds the value of the chip select signal SS_D2. When the sampling enable signal SMP_EN is Low, the value of the chip select signal SS_D2 held by the enable flip-flop circuit 112 is the value of the chip select signal SS sampled the second time by the enable flip-flop circuit 111.

[0021] The enable flip-flop circuit 113 receives the serial clock signal SCL from the input terminal Pi12, the chip select signal SS_D2 from the enable flip-flop circuit 112, and the sampling enable signal SMP_EN from the one-shot 2-bit counter 10. When the sampling enable signal SMP_EN is High, the enable flip-flop circuit 113 samples the value of the chip select signal SS_D2 at the rising edge of the serial clock signal SCL and outputs the sampled value as the chip select signal SS_D3 to the majority circuit 12. When the sampling enable signal SMP_EN is Low, the enable flip-flop circuit 113 stops sampling the chip select signal SS_D2 and holds the value of the chip select signal SS_D3. When the sampling enable signal SMP_EN is Low, the value of the chip select signal SS_D3 held by the enable flip-flop circuit 113 is the value of the chip select signal SS sampled the first time by the enable flip-flop circuit 111.

[0022] The majority circuit 12 includes AND circuits 121, 122, and 123, an OR circuit 124, and an enable flip-flop circuit 125. The AND circuit 121 receives chip select signals SS_D1 and SS_D3 from the enable flip-flop circuits 111 and 113, respectively, and outputs the logical product of the two to the OR circuit 124. The AND circuit 122 receives chip select signals SS_D3 and SS_D2 from the enable flip-flop circuits 113 and 112, respectively, and outputs the logical product of the two to the OR circuit 124. The AND circuit 123 receives chip select signals SS_D2 and SS_D1 from the enable flip-flop circuits 112 and 111, respectively, and outputs the logical product of the two to the OR circuit 124. The OR circuit 124 outputs the logical sum of the output signals of the AND circuits 121 to 123 to the enable flip-flop circuit 125. The logical sum becomes active logic when two or more (majority) of the chip select signals SS_D1 to SS_D3 are active logic, and becomes inactive logic when two or more (majority) are inactive logic.

[0023] The enable flip-flop circuit 125 receives the output signal from the OR circuit 124, the sampling enable signal SMP_EN from the one-shot 2-bit counter 10, the reset signal RST from the input terminal Pi11, and the serial clock signal SCL from the input terminal Pi12. When the sampling enable signal SMP_EN is Low, the enable flip-flop circuit 125 samples the value of the output signal from the OR circuit 124 at the rising edge of the serial clock signal SCL and outputs the sampled value as the majority signal MAJOR_SS to the output terminal Po10. When the sampling enable signal SMP_EN is High, the enable flip-flop circuit 125 stops sampling the value of the output signal from the OR circuit 124.

[0024] By sampling the chip select signal SS an odd number of times, either the active logic or the inactive logic always constitutes a majority in the sampling results, simplifying the configuration of the protocol switching circuit 100 and the control of the protocol switching circuit 100. The chip select signal SS may be sampled an even number of times. If the sampling results indicate an equal number of active logics and inactive logics, the protocol determination circuit 100 outputs an output signal (High) indicating a protocol determination error to a control circuit (e.g., a microcomputer) (not shown) of the protocol switching circuit 100. The control circuit that receives the protocol determination error restarts control of the protocol switching circuit 100, starting with setting the reset signal RST to Low, and determines the communication protocol again.

[0025] FIG. 3 is a time chart of the signals shown in FIGS. 1 and 2 according to the first embodiment when I2C communication is selected by the chip select signal SS. As shown in FIG. 3, the reset signal RST starts low, indicating a reset state, and transitions to high, indicating a reset release state, at time t0. The count signal CNT is initialized to 0 until time t0. The sampling enable signal SMP_EN starts high. The serial clock signal SCL has an intermittent clock waveform. That is, the serial clock signal SCL forms a clock waveform that alternates between high and low at a predetermined cycle during serial communication based on the I2C and SPI communication standards, and maintains high when not communicating.

[0026] From the first communication start time ts after time t0, the chip select signal SS is set to inactive logic. The chip select signal SS is sampled three times at times t1, t2, and t3, which correspond to successive rising edges of the serial clock signal SCL, and the sampled signal is held in the chip select signal SS_D1. The count signal CNT is incremented from 0 to 1 at time t1, from 1 to 2 at time t2, and from 2 to 3 at time t3. The sampling enable signal SMP_EN transitions from high to low at time t3.

[0027] The values of chip select signal SS_D1 at times t1 and t2 are held in chip select signal SS_D2 at times t2 and t3, respectively. The value of chip select signal SS_D2 at time t2 is held in chip select signal SS_D3 at time t3. At time t4, which is the rising edge of serial clock signal SCL following time t3 and when sampling enable signal SMP_EN is low, majority signal MAJOR_SS is set to the majority value of chip select signals SS_D1 to SS_D3. Majority signal MAJOR_SS is latched and held until reset signal RST next goes to the reset state (low). In FIG. 3, each of chip select signals SS_D1 to SS_D3 is high at time t4, so majority signal MAJOR_SS is set to high.

[0028] 4 is a time chart of the signals shown in FIGS. 1 and 2 in the first embodiment when SPI communication is selected by the chip select signal SS. As shown in FIG. 4, the reset signal RST starts low, indicating a reset state, and transitions to high, indicating a reset release state, at time t10. The count signal CNT is initialized to 0 until time t10.

[0029] From the first communication start time ts1 after time t10 onwards, the chip select signal SS is set to active logic. The chip select signal SS is sampled three times at times t11, t12, and t13, which are the timings of consecutive rising edges of the serial clock signal SCL, and the sampled signal is held in the chip select signal SS_D1. The count signal CNT is incremented from 0 to 1 at time t11, from 1 to 2 at time t12, and from 2 to 3 at time t13. The sampling enable signal SMP_EN transitions from high to low at time t13.

[0030] The values of chip select signal SS_D1 at times t11 and t12 are held in chip select signal SS_D2 at times t12 and t13, respectively. The value of chip select signal SS_D2 at time t12 is held in chip select signal SS_D3 at time t13. At time t14, which is the rising edge of serial clock signal SCL following time t13 and when sampling enable signal SMP_EN is Low, majority signal MAJOR_SS is set to the value of the majority of chip select signals SS_D1 to SS_D3. In FIG. 4, since each of chip select signals SS_D1 to SS_D3 is Low at time t14, majority signal MAJOR_SS is set Low.

[0031] In the protocol determination circuit 1, even if the sampling result is inverted from the original value of the chip select signal SS due to noise superimposed on the chip select signal SS during one of multiple samplings, as long as the original value of the chip select signal SS is sampled the majority of the times. Furthermore, after the value of the chip select signal SS is set to the majority signal MAJOR_SS during the first communication, the majority signal MAJOR_SS is maintained until the reset signal is reset. Therefore, even if the chip select signal SS is inverted from the original value due to noise during subsequent communications, communication can continue based on the communication protocol corresponding to the original value of the chip select signal SS.

[0032] As described above, the protocol determination circuit and protocol switching circuit according to the first embodiment can improve the noise resistance of the protocol determination circuit that determines the communication protocol between circuits.

[0033] Embodiment 2 In the I2C communication standard, the serial clock signal SCL is driven by an open-drain buffer. The high level of the serial clock signal SCL is achieved by pulling up the potential of the serial clock signal SCL using the resistance of the open-drain buffer, which has high impedance. This reduces the slew rate of the rising edge of the serial clock signal SCL, lengthening the period during which the potential of the serial clock signal SCL is near the threshold. As a result, chattering due to noise is likely to occur at the rising edge of the serial clock signal SCL. On the other hand, when the serial clock signal SCL is at low level, the open-drain buffer is driven at low level. This increases the slew rate of the falling edge, shortening the period during which the potential of the serial clock signal SCL is near the threshold. As a result, chattering due to noise is unlikely to occur at the falling edge of the serial clock signal SCL.

[0034] Therefore, in the second embodiment, the chip select signal SS is sampled at the falling edge of the serial clock signal SCL. In the second embodiment, Figures 3 and 4 of the first embodiment are replaced with Figures 5 and 6, respectively. According to the second embodiment, the chip select signal SS is sampled at a timing when chattering due to noise is less likely to occur than in the first embodiment, so that the noise resistance of the protocol determination circuit that determines the communication protocol between circuits can be further improved compared to the first embodiment.

[0035] 5 is a timing chart of the signals shown in FIGS. 1 and 2 in the second embodiment when I2C communication is selected by the chip select signal SS. As shown in FIG. 5, the reset signal RST starts low, indicating a reset state, and transitions to high, indicating a reset release state, at time t20. The count signal CNT is initialized to 0 until time t20.

[0036] From the initial communication start time ts2 after time t20 onwards, the chip select signal SS is set to inactive logic. The chip select signal SS is sampled three times at times t21, t22, and t23, which correspond to successive falling edges of the serial clock signal SCL, and the sampled signal is held in the chip select signal SS_D1. The count signal CNT is incremented from 0 to 1 at time t21, from 1 to 2 at time t22, and from 2 to 3 at time t23. The sampling enable signal SMP_EN transitions from high to low at time t23.

[0037] The values of chip select signal SS_D1 at times t21 and t22 are held in chip select signal SS_D2 at times t22 and t23, respectively. The value of chip select signal SS_D2 at time t22 is held in chip select signal SS_D3 at time t23. At time t24, which is the falling edge of serial clock signal SCL following time t23 and when sampling enable signal SMP_EN is low, majority signal MAJOR_SS is set to the value of the majority of chip select signals SS_D1 to SS_D3. In FIG. 5, since each of chip select signals SS_D1 to SS_D3 is high at time t24, majority signal MAJOR_SS is set to high.

[0038] 6 is a time chart of the signals shown in FIGS. 1 and 2 in the second embodiment when SPI communication is selected by the chip select signal SS. As shown in FIG. 6, the reset signal RST starts low, indicating a reset state, and transitions to high, indicating a reset release state, at time t30. The count signal CNT is initialized to 0 until time t30.

[0039] From the first communication start time ts3 after time t30 onwards, the chip select signal SS is set to active logic. The chip select signal SS is sampled three times at times t31, t32, and t33, which are the timings of consecutive falling edges of the serial clock signal SCL, and the sampled signal is held in the chip select signal SS_D1. The count signal CNT is incremented from 0 to 1 at time t31, from 1 to 2 at time t32, and from 2 to 3 at time t33. The sampling enable signal SMP_EN transitions from high to low at time t33.

[0040] The values of chip select signal SS_D1 at times t31 and t32 are held in chip select signal SS_D2 at times t32 and t33, respectively. The value of chip select signal SS_D2 at time t32 is held in chip select signal SS_D3 at time t33. At time t34, which is the falling edge of serial clock signal SCL following time t33 and when sampling enable signal SMP_EN is low, majority signal MAJOR_SS is set to the value of the majority of chip select signals SS_D1 to SS_D3. In FIG. 6, since each of chip select signals SS_D1 to SS_D3 is low at time t34, majority signal MAJOR_SS is set to low.

[0041] As described above, the protocol determination circuit and protocol switching circuit according to the second embodiment can further improve the noise resistance of the protocol determination circuit that determines the communication protocol between circuits compared to the first embodiment.

[0042] When multiple I2C slave devices are connected to the same communication line, it is necessary to set a unique slave address for each of the multiple I2C slave devices. For this reason, it is desirable to be able to select a slave address during I2C communication. Therefore, in the third, fourth, and fifth embodiments, a configuration will be described that realizes an I2C slave device selection function in addition to the protocol determination function of the first and second embodiments.

[0043] Embodiment 3 Fig. 7 is a block diagram showing an example configuration of a protocol switching circuit 300 according to embodiment 3. The configuration of protocol switching circuit 300 is obtained by adding (N-1) comparators 6 (N is a natural number of 2 or more) and an I2C slave address determination circuit 7 to the configuration of protocol switching circuit 100 in Fig. 1. Other than this, the configuration of protocol switching circuit 300 is the same as the configuration of protocol switching circuit 100, and therefore description of the similar configuration will not be repeated.

[0044] As shown in FIG. 7, the output terminal Po is connected to the non-inverting input terminal (+) (first input terminal) of each of the (N-1) comparators 6. The master-in / slave-out signal MISO is input to the non-inverting input terminal of the comparator 6 from the output terminal Po. The master-in / slave-out signal MISO (output terminal Po) becomes high impedance when the chip select signal SS selects I2C communication (during I2C communication). When the power supply voltage is VDD, voltages of VDD × (1 / N), VDD × (2 / N), ..., VDD × (N-1) / N are input to the inverting input terminal (-) (second input terminal) of each of the (N-1) comparators. That is, during I2C communication, a voltage K / N times the power supply voltage VDD is input to the inverting input terminal of the Kth comparator 6 (K is a natural number between 1 and (N-1)) included in the (N-1) comparators 6.

[0045] The outputs of the (N-1) comparators 6 are input to the I2C slave address determination circuit 7. The I2C slave address determination circuit 7 outputs a specific slave address corresponding to the outputs of the (N-1) comparators 6 to the I2C communication circuit 4. The I2C communication circuit 4 communicates with the slave device identified by the specific slave address.

[0046] The I2C slave address determination circuit 7 has the same configuration as the protocol determination circuit 1. By making the configuration of the I2C slave address determination circuit 7 the same as the configuration of the protocol determination circuit 1, the resistance of the I2C slave address determination circuit 7 to noise can be improved.

[0047] The protocol switching circuit 300 can select a specific slave address for I2C communication from N different address values depending on the voltage of the master-in / slave-out signal MISO (output terminal Po) during I2C communication. Also, by using the master-in / slave-out signal MISO, which is not used during I2C communication, for controlling the selection of the slave address, the I2C slave address selection function can be realized inexpensively without increasing the number of control terminals.

[0048] As described above, the protocol determination circuit and protocol switching circuit according to the third embodiment can improve the noise resistance of the protocol determination circuit that determines the communication protocol between circuits.

[0049] Embodiment 4 8 is a block diagram showing an example configuration of a protocol switching circuit 400 according to the fourth embodiment. The configuration of protocol switching circuit 400 is the same as that of protocol switching circuit 300 in FIG. 7 except that N is set to 3 and an internal bias circuit 8 is added to the configuration of protocol switching circuit 300. Other than this, the configuration of protocol switching circuit 400 is the same as that of protocol switching circuit 300, and therefore description of the similar configuration will not be repeated. Note that N is not limited to 3.

[0050] As shown in Figure 8, the internal bias circuit 8 includes resistors R1 and R2 connected in series between a power supply and ground. The junction of resistors R1 and R2 is connected to each of the non-inverting input terminals of two comparators 6. When the impedance of the master-in / slave-out signal MISO terminal is open, the voltage at this junction is VDD / 2. In other words, when the impedance of the master-in / slave-out signal MISO terminal is open, the internal bias circuit 8 outputs a voltage that is half the power supply voltage VDD to each of the non-inverting input terminals of the two comparators 6.

[0051] According to the protocol switching circuit 400, the slave address during I2C communication can be selected from three types by setting the impedance state of the master-in / slave-out signal MISO to short to power, open, or short to ground. Because there is no need to add any external components to the protocol switching circuit 400, the slave address selection function during I2C communication can be realized inexpensively.

[0052] 8 is configured such that a resistive element is not required as an external component when N=3 in the protocol switching circuit 300 shown in FIG. 7. Generally, the output of the internal bias circuit 8 needs to be the average value of the voltages at the inverting input terminals of multiple adjacent comparators 6. In other words, the internal bias circuit 8 needs to output a voltage obtained by multiplying the power supply voltage VDD by (K+0.5) / N, which is the average value of K / N and (K+1) / N. (This voltage is (K+0.5) / N times the power supply voltage VDD.) In configurations other than the protocol switching circuit 400, a resistive element is required as an external component when the impedance state of the master-in / slave-out signal MISO is to be set to a state other than the three states of short to power, open, and short to ground.

[0053] As described above, the protocol determination circuit and protocol switching circuit according to the fourth embodiment can improve the noise resistance of the protocol determination circuit that determines the communication protocol between circuits.

[0054] Embodiment 5. 9 is a block diagram showing an example configuration of a protocol switching circuit 500 according to embodiment 5. In the configuration of protocol switching circuit 500, the I2C slave address determination circuit 7 in FIG. 8 is replaced with a circuit 7A, and a switch 9 is added. Other than this, the configuration of protocol switching circuit 500 is similar to the configuration of protocol switching circuit 400, and therefore description of the similar configuration will not be repeated.

[0055] 9, the switch 9 is connected between the internal bias circuit 8 and the power supply. The I2C slave address determination circuit 7A outputs a sampling enable signal SMP_EN5 to the two comparators 6 and the switch 9. The sampling enable signal SMP_EN5 indicates the period during which the outputs of the two comparators 6 are sampled.

[0056] After the sampling period indicated by the sampling enable signal SMP_EN5 ends (SMP_EN5=Low), the protocol switching circuit 500 performs power-down control on the comparator 6 and the internal bias circuit 8. The protocol switching circuit 500 can reduce the power required for the slave address selection function during I2C communication.

[0057] As described above, the protocol determination circuit and protocol switching circuit according to the fifth embodiment can improve the noise resistance of the protocol determination circuit that determines the communication protocol between circuits.

[0058] The embodiments disclosed herein are intended to be combined as appropriate within the scope of compatibility. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0059] 1 Protocol decision circuit, 2, 4 Communication circuit, 3 Tri-state buffer, 5 Bidirectional buffer, 6 Comparator, 7, 7A I2C slave address decision circuit, 8 Bias circuit, 9 Switch, 10 One-shot 2-bit counter, 11 Shift register circuit with enable, 12 Majority circuit, 100 Protocol switching circuit, 101 2-bit counter, 102 Comparator, 111 to 113, 125 Flip-flop circuit with enable, 121 to 123 AND circuit, 124 OR circuit, CNT Count signal, MAJOR_SS Majority signal, MISO Master-in / Slave-out signal, MOSI Master-out / Slave-in signal, Pi1 to Pi3, Pi11 to Pi13 Input terminal, Pio Input / output terminal, Po, Po10 Output terminal, RST Reset signal, SCL Serial clock signal, SDA Serial data signal, SMP_EN, SMP_EN5 Sampling enable signal, SS Chip select signal, VDD power supply voltage, t0 to t4, t10 to t14, t20 to t24, t30 to t34 times, ts, ts1 to ts3 communication start times.

Claims

1. a sampling circuit that performs multiple samplings of a protocol designation signal that is either a value representing a first communication protocol or a value representing a second communication protocol; a majority circuit that outputs a majority signal indicating a communication protocol corresponding to values sampled a majority of the plurality of times, and receives a reset signal; The majority circuit determines whether the value representing the first communication protocol or the value representing the second communication protocol is a protocol determination circuit from the multiple sampled values during the first communication after the reset signal is released.

2. 2. The protocol determination circuit according to claim 1, wherein the sampling circuit performs each of the plurality of samplings at a timing when a clock signal that alternately repeats a first value and a second value greater than the first value at a predetermined period changes from the second value to the first value.

3. the first communication protocol is I2C; 2. The protocol determination circuit according to claim 1, wherein the second communication protocol is SPI.

4. a protocol determination circuit according to any one of claims 1 to 3; a first communication circuit that performs communication based on the first communication protocol when the majority signal indicates the first communication protocol; a second communication circuit that performs communication based on the second communication protocol when the majority signal indicates the second communication protocol;

5. A protocol switching circuit including a protocol determination circuit, The protocol determination circuit a sampling circuit that performs multiple samplings of a protocol designation signal that is either a value representing a first communication protocol or a value representing a second communication protocol; a majority circuit that outputs a majority signal indicating a communication protocol corresponding to values sampled a majority of the times among the plurality of samplings; The protocol switching circuit a first communication circuit that performs communication based on the first communication protocol when the majority signal indicates the first communication protocol; a second communication circuit that performs communication based on the second communication protocol when the majority signal indicates the second communication protocol; an output terminal for outputting a master-in / slave-out signal from the slave to the master when the majority signal indicates the second communication protocol; (N-1) comparators (N is a natural number equal to or greater than 2); a slave address determination circuit; the output terminal is connected to a first input terminal of each of the (N-1) comparators; A voltage K / N times the voltage of the power supply is input to a second input terminal of a Kth comparator (K is a natural number equal to or greater than 1 and equal to or less than (N-1)) included in the (N-1) comparators, The outputs of the (N-1) comparators are input to the slave address determination circuit, the slave address determination circuit outputs a specific slave address corresponding to the outputs of the (N-1) comparators to the first communication circuit; The first communication circuit communicates with a slave device identified by the specific slave address.

6. an internal bias circuit connected to the output terminal; 6. The protocol switching circuit according to claim 5, wherein the internal bias circuit outputs a voltage that is (K+0.5) / N times the voltage of the power supply to the first input terminal of each of the (N-1) comparators when the impedance of the master-in / slave-out signal is open.

7. 7. The protocol switching circuit according to claim 6, wherein the slave address determination circuit outputs a sampling enable signal indicating a period for sampling the outputs of the (N-1) comparators to the (N-1) comparators and the internal bias circuit, and performs power-down control on the (N-1) comparators and the internal bias circuit after the period ends.

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