Information processing device, information processing method, and program

Abstract

To efficiently manage machine codes.SOLUTION: An information processing apparatus includes: an addition unit which adds a type based on homotopy type theory to one or more machine codes obtained through conversion by a compiler; and a determination unit which determines, when a conversion from one of the machine codes to the other machine code satisfies a predetermined rule based on the homotopy type theory, that the one machine code is identical with the other machine code. The addition unit adds the same type to the one machine code and the other machine code determined to be identical with each other by the determination unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device, an information processing method, and a program. [Background technology]

[0002] Conventionally, there are known methods for optimizing a compiler. For example, Patent Document 1 discloses a technique for adjusting a compiler based on the structure of a plurality of first graphs that indicate the content of the functions performed by the logic circuit of an FPGA and the structure of a second graph that the compiler generates from the content of a predetermined process for generating machine code. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-200736 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the prior art, even if multiple machine codes generated by a compiler have the same function, if the details of the code differ, they are treated as separate machine codes, which results in inefficient management of the machine codes.

[0005] The present invention has been made in consideration of the above circumstances, and one of its objects is to provide an information processing device, an information processing method, and a program that can efficiently manage machine code. [Means for solving the problem]

[0006] An information processing device according to one aspect of the present invention comprises an assignment unit that assigns a type based on homotopy type theory to one or more machine codes obtained by conversion by a compiler, and a judgment unit that determines that one or more machine codes are identical to another machine code if the conversion of that machine code to another machine code satisfies a predetermined rule based on homotopy type theory, and the assignment unit assigns the same type to the machine code and the other machine code that are determined to be identical by the judgment unit. [Effects of the Invention]

[0007] According to one aspect of the present invention, machine code can be managed efficiently. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram illustrating an example of a configuration of an information processing device 100 according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing an example of source code 142 compiled by the compilation execution unit 110. [Figure 3] FIG. 10 is a diagram showing an example of machine code 144 compiled by the compilation execution unit 110. [Figure 4] FIG. 10 is a diagram showing another example of machine code 144 compiled by the compilation execution unit 110. [Figure 5] FIG. 1 is a diagram for explaining an overview of homotopy type theory. [Figure 6] FIG. 10 is a diagram showing another example of source code 142 compiled by the compilation execution unit 110. [Figure 7] FIG. 10 is a diagram showing another example of machine code 144 compiled by the compilation execution unit 110. [Figure 8] FIG. 10 is a conceptual diagram for explaining the possibility of converting machine code 144_b into machine code 144_c. [Figure 9] FIG. 10 is a diagram illustrating an example of the configuration of an information processing device 100 according to a second embodiment. [Figure 10] 10 is a diagram illustrating an example of the configuration of a logic block LB of an FPGA 214. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] First Embodiment Hereinafter, with reference to the drawings, an information processing device, an information processing method, and a program according to embodiments of the present invention will be described. FIG. 1 is a diagram illustrating an example of the configuration of an information processing device 100 according to a first embodiment. As illustrated in FIG. 1, the information processing device 100 includes, for example, a compilation execution unit 110, a determination unit 120, an attachment unit 130, and a storage unit 140. The compilation execution unit 110, the determination unit 120, and the attachment unit 130 may be realized by, for example, a processor of the information processing device 100 executing a program, or may be realized by hardware (controllers) such as an LSI (Large Scale Integration), an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable Gate Array). The storage unit 140 may be realized by, for example, a ROM (Read Only Memory), a flash memory, an SD card, a RAM (Random Access Memory), an HDD (Hard Disk Drive), a register, or the like. The storage unit 140 stores source code 142 programmed in an arbitrary programming language and machine code 144, which is a machine language obtained by compiling the source code 142.

[0010] The compilation execution unit 110 functions as a compiler corresponding to the programming language in which the source code 142 is written, and converts the source code 142 into machine code 144. FIG. 2 is a diagram showing an example of the source code 142 compiled by the compilation execution unit 110. The function func described in the source code 142 shown in FIG. 2 accepts an input value i, and outputs the input value i if the input value i is greater than zero, while outputting the input value i with its sign inverted if the input value i is equal to or less than zero. In other words, the source code 142 in FIG. 2 represents a function in the C language that receives an integer value as input and outputs the absolute value of the input integer value.

[0011] The compilation execution unit 110 converts the source code 142 into machine code 144 and stores the converted machine code 144 in the storage unit 140. Fig. 3 is a diagram showing an example of the machine code 144 compiled by the compilation execution unit 110. The machine code 144 is usually written in the form of binary code, but for convenience of explanation, in Fig. 3, the machine code 144 is written in the form of assembly code. Fig. 3 shows machine code 144_a obtained by compiling the source code 142 shown in Fig. 2.

[0012] In the fifth line of machine code 144_a, the input value is compared with zero, and if the input value is less than or equal to zero, the process jumps to the address indicated in L2, the input value is inverted, and the sign is inverted and output, whereas if the input value is greater than zero, the process jumps to the address indicated in L3, and the input value is output as is.

[0013] Fig. 4 is a diagram showing another example of machine code 144 compiled by the compilation execution unit 110. Fig. 4 shows machine code 144_b, which is different from machine code 144_a and is obtained by compiling source code 142 shown in Fig. 2.

[0014] On line 5 of machine code 144_b, zero is compared with the input value, and if zero is greater than or equal to the input value, processing jumps to the address indicated in L2, the input value is inverted, and the sign is output. On the other hand, if zero is less than the input value, processing jumps to the address indicated in L3, and the input value is output as is. In other words, machine code 144_a and machine code 144_b have different descriptions on lines 5 and 6, but they have in common the fact that they have the same function of inputting an integer value and outputting the absolute value of the input integer value.

[0015] In this way, multiple machine codes 144 with different descriptions but the same function may be generated by compiling the same source code 142. In the prior art, these multiple machine codes 144 with different descriptions but the same function may be treated as different machine codes, which may result in inefficient management of the machine codes.

[0016] To solve the above problems, the present invention applies homotopy type theory. Homotopy type theory is a theory that integrates homotopy theory, which belongs to the field of topology, and type theory, which belongs to the field of mathematical foundations, from a more general perspective, and deals with the concept of extended identity. Note that "applying homotopy type theory" here means, for example, creating and executing arbitrary program code based on homotopy type theory, and does not necessarily mean generating mathematical formulas, functions, etc. that directly express homotopy type theory.

[0017] Figure 5 is a diagram for explaining the outline of homotopy type theory. In Figure 5, a, b, and c indicate points in space, p indicates a path from point a to point b, and q indicates a path from point b to point c. In homotopy type theory, when there is a path connecting two points in space, the two points are interpreted as having identity, and p:a= A b holds. Here, A indicates the type that points a and b have, and p:a= Ab means that point a and point b have identity with respect to type A. That is, there exists a path from point a to point b if and only if point a and point b have the same type. A path has the following properties:

[0018] [Reflex Law] For any point a in space, there exists a path p from point a itself, i.e., p:a= A a holds. In this case, the path p is also written as id, and is sometimes called the identity map.

[0019] [Symmetrical Temperament] If there is a path p from point a to point b in space, then there is also a path q from point b to point a. That is, p:a= A If b holds, then q:b= A There exists a path q such that a holds. In this case, path q is, for example, a path that traces path p from point a to point b in the reverse direction, and is denoted as !p. !p is sometimes called an inverse mapping.

[0020] [Transitive law] If there is a path p from point a to point b in space, and a path q from point b to point c, then there is also a path r from point a to point c. That is, p:a= A b and q:b= A If c holds, then r:a= A There exists a path r such that c holds. In this case, path r is, for example, a path that connects path p from point a to point b with path q from point b to point c, and is written as q〇p. q〇p is sometimes called a composite map.

[0021] The determination unit 120 determines that one or more machine codes 144 compiled by the compilation execution unit 110 are identical to another machine code 144 when conversion from the machine code 144 to another machine code 144 satisfies a predetermined rule based on the homotopy type theory. The assignment unit 130 assigns the same type based on the homotopy type theory to the machine code 144 determined by the determination unit 120 to be identical to the other machine code 144.

[0022] In the first embodiment, the predetermined rule is that conversion of one machine code 144 into another machine code 144 does not change the function of the machine code 144, i.e., the input and output of the machine code 144. In the case of the machine code 144_a in Fig. 3 and the machine code 144_b in Fig. 4, both of these machine codes have the same function of inputting an integer value and outputting the absolute value of the input integer value.

[0023] Therefore, the determination unit 120 determines that the conversion p from the machine code 144_a in Fig. 3 to the machine code 144_b in Fig. 4 satisfies a predetermined rule, and determines that the machine code 144_a and the machine code 144_b are identical. The assignment unit 130 assigns the same type, for example, type X, to the machine code 144_a and the machine code 144_b that are determined to be identical. That is, p:a= X b holds.

[0024] Fig. 6 is a diagram showing another example of source code 142 compiled by the compilation execution unit 110. A function func described in the source code 142 shown in Fig. 6 accepts an input value i, and outputs the input value i+1 if the input value i is greater than zero, while outputting the input value i with its sign inverted if the input value i is equal to or less than zero.

[0025] 7 is a diagram showing another example of machine code 144 compiled by the compilation execution unit 110. FIG. 7 shows machine code 144_c obtained by compiling source code 142 shown in FIG. 6. In the fifth line of machine code 144_c, an input value is compared with zero, and if the input value is equal to or less than zero, processing jumps to the address shown in L2, the sign of the input value is inverted, and the input value is output. On the other hand, if the input value is greater than zero, 1 is added to the input value, and then processing jumps to the address shown in L3, and the input value is output as is.

[0026] Comparing the machine code 144_b shown in FIG. 4 with the machine code 144_c shown in FIG. 7, it is found that 1 is added to the input value on the eighth line of the machine code 144_c shown in FIG. 7. As a result, although the inputs of the machine code 144_b and the machine code 144_c are the same, the outputs of the machine code 144_b and the machine code 144_c are different. This means that the function is changed by converting the machine code 144_b to the machine code 144_c. Therefore, the determination unit 120 determines that the machine code 144_b and the machine code 144_c are not the same, and the assignment unit 130 assigns a type, for example, type Y, to the machine code 144_c, which is different from the type of the machine code 144_b.

[0027] 8 is a conceptual diagram for explaining the possibility of conversion from machine code 144_b to machine code 144_c. As described above, conversion from machine code 144_a to machine code 144_b satisfies the predetermined rule, so a path p from machine code 144_a to machine code 144_b is formed, and the machine code 144_a and machine code 144_b are assigned the same type X. On the other hand, machine code 144_c has a different function from the machine code 144_a and machine code 144_b, so conversion from machine code 144_b to machine code 144_c does not satisfy the predetermined rule, so a path from machine code 144_b to machine code 144_c is not formed. As a result, a type Y different from that of machine code 144_a and machine code 144_b is assigned to machine code 144_c.

[0028] According to the first embodiment described above, if the conversion of one machine code into another satisfies predetermined rules based on homotopy type theory, the machine codes are determined to be identical, and the same type is assigned to the machine codes determined to be identical. This allows machine codes that have different descriptions but are substantially identical to be treated as the same, enabling efficient management of machine codes.

[0029] In the above description, the predetermined rule is set such that conversion from one machine code 144 to another machine code 144 does not change the function of the machine code 144. However, the present invention is not limited to such a configuration. For example, the predetermined rule may be that conversion from one machine code to another machine code does not change the function of the machine code and the difference between the processing speeds of these machine codes is within a threshold. This makes it possible to exclude machine codes that have the same function but slow processing speeds.

[0030] Second Embodiment In the first embodiment, an example was described in which source code 142 stored in a storage unit 140 is compiled into machine code 144 for a general-purpose computer. However, the present invention is not limited to such a configuration, and can also be applied to hardware such as an FPGA, which is an integrated circuit in which a user can define or change internal logic blocks LB after manufacturing. The second embodiment applies homotopy type theory to an FPGA.

[0031] 9 is a diagram illustrating an example of the configuration of an information processing device 100 according to the second embodiment. As illustrated in FIG. 9, the information processing device 100 includes, for example, an LLVM 210, a logic synthesis tool 212, an FPGA 214, a determination unit 220, an assignment unit 230, and a storage unit 240. The storage unit 240 stores source code 142 that defines the configuration of a logic block LB of the FPGA 214, an HDL 244 that is a hardware description language obtained by the LLVM 210 compiling the source code 142, and a netlist 246 obtained by the logic synthesis tool 212 further compiling the HDL 244. More specifically, the LLVM 210 generates an intermediate representation from the source code 142 using an intermediate representation (IR) builder, and generates the HDL 244 from the intermediate representation using an optimizer. The logic synthesis tool 212 compiles the HDL 244 compiled by the LLVM 210 into a netlist 246 that can be manufactured by the FPGA 214 and stores it in the storage unit 240.

[0032] Fig. 10 is a diagram showing an example of the configuration of a logic block LB of the FPGA 214. Fig. 10 exemplifies the circuit configuration of the logic block LB realized by the netlist 246 compiled by the logic synthesis tool 212. In Fig. 10, the logic block LB1 has a circuit configuration a, which includes an AND gate, a NOT gate, and an OR gate.

[0033] The determination unit 120 determines that the circuit configuration and the other circuit configuration are identical when conversion from the circuit configuration of the logic block LB realized by the netlist 246 to another circuit configuration satisfies a predetermined rule based on the homotopy type theory. The assignment unit 130 assigns the same type based on the homotopy type theory to the circuit configuration that is determined to be identical by the determination unit 120 and the other circuit configuration.

[0034] In the second embodiment, the predetermined rule is that conversion from one circuit configuration to another does not change the function of the circuit configuration, i.e., the input and output of the circuit configuration. In the case of FIG. 10, circuit configuration b, which includes two NAND gates, has the same function as circuit configuration a. Therefore, the determination unit 120 determines that conversion p, from a logic block LB having circuit configuration a to a logic block LB having circuit configuration b, satisfies the predetermined rule, and determines that circuit configuration a and circuit configuration b are identical. The assignment unit 130 assigns the same type, for example, type Z, to circuit configurations a and b, which are determined to be identical. That is, p:a= Z b holds.

[0035] In the above explanation, identity is determined by comparing the circuit configuration of a single logic block LB. However, the present invention is not limited to such a configuration, and multiple logic blocks LB may be treated as a single unit and compared to determine the identity of their circuit configurations.

[0036] Furthermore, in the above description, the predetermined rule is set as a rule that conversion from one circuit configuration to another does not change the function of the circuit configuration. However, the present invention is not limited to such a rule. As in the first embodiment, for example, the predetermined rule may be that conversion from one circuit configuration to another does not change the function of the circuit configuration, and the difference between the processing speeds of these circuit configurations is within a threshold. This makes it possible to exclude circuit configurations that have the same function but a slower processing speed.

[0037] According to the second embodiment described above, if a conversion from one circuit configuration of an FPGA logic block to another circuit configuration satisfies a predetermined rule based on homotopy type theory, the circuit configurations are determined to be identical, and the same type is assigned to the circuit configurations determined to be identical. This allows circuit configurations that have different configurations but the same function to be treated as identical, thereby enabling efficient management of circuit configurations.

[0038] The above describes the form for carrying out the present invention using an embodiment, but the present invention is not limited to such an embodiment, and various modifications and substitutions can be made within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0039] 100 Information processing device 110 Compilation execution unit 120, 220 Judgment section 130, 230 Granting Department 140, 240 storage section 142, 242 source code 144 Machine Code 210 LLVM 212 Logic synthesis tools 214 FPGA 244 HDL 246 Netlist

Claims

1. an assigning unit that assigns a type based on homotopy type theory to one or more machine codes obtained by the conversion by the compiler; a determination unit that determines that one or more of the machine codes have identity with another machine code when conversion from the one or more machine codes to another machine code satisfies a predetermined rule based on the homotopy type theory, the assigning unit assigns the same type to the machine code and the other machine code determined by the determining unit to have the same type; the predetermined rule is that a transformation of the machine code into another machine code does not change the functionality of the machine code; Information processing device.

2. the predetermined rule is that conversion of the machine code into another machine code does not change the function of the machine code, and a difference between a processing speed of the machine code and a processing speed of the other machine code is within a threshold value; The information processing device according to claim 1 .

3. An assignment unit that assigns types based on homotopy type theory to one or more machine codes obtained by conversion by a compiler; a determination unit that determines that one or more of the machine codes have identity with another machine code when conversion from the one or more machine codes to another machine code satisfies a predetermined rule based on the homotopy type theory, the assigning unit assigns the same type to the machine code and the other machine code determined by the determining unit to have the same type; the predetermined rule is that conversion of the machine code into another machine code does not change the function of the machine code, and a difference between a processing speed of the machine code and a processing speed of the other machine code is within a threshold value; Information processing device.

4. The computer assigning a type based on homotopy type theory to one or more machine codes obtained by the transformation by the compiler; determining that the one or more machine codes have identity with each other when a conversion from one machine code to another machine code satisfies a predetermined rule based on the homotopy type theory; assigning the same type to the machine code and the other machine code that are determined to have the same identity; the predetermined rule is that a transformation of the machine code into another machine code does not change the functionality of the machine code; Information processing methods.

5. On the computer, assigning a type based on homotopy type theory to one or more machine codes obtained by the conversion by the compiler; determining that one or more of the machine codes have identity with another machine code when conversion of the one or more machine codes into the other machine code satisfies a predetermined rule based on the homotopy type theory; assigning the same type to the machine code and the other machine code that are determined to have the same identity; the predetermined rule is that a transformation of the machine code into another machine code does not change the functionality of the machine code; program.

6. The computer assigning a type based on homotopy type theory to one or more machine codes obtained by the transformation by the compiler; determining that the one or more machine codes have identity with each other when a conversion from one machine code to another machine code satisfies a predetermined rule based on the homotopy type theory; assigning the same type to the machine code and the other machine code that are determined to have the same identity; the predetermined rule is that conversion of the machine code into another machine code does not change the function of the machine code, and a difference between a processing speed of the machine code and a processing speed of the other machine code is within a threshold value; Information processing methods.

7. On the computer, assigning a type based on homotopy type theory to one or more machine codes obtained by the conversion by the compiler; determining that one or more of the machine codes have identity with another machine code when conversion of the one or more machine codes into the other machine code satisfies a predetermined rule based on the homotopy type theory; the predetermined rule is that conversion of the machine code into another machine code does not change the function of the machine code, and a difference between a processing speed of the machine code and a processing speed of the other machine code is within a threshold value; program.

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