Image forming apparatus and control method for image forming apparatus

Abstract

To prevent a processing speed from decreasing by efficiently writing settings, through serial communication, into a circuit having a temporary memory for buffering, provided between an image generating part and an image forming part, so as to enable printing operation to be performed at a higher speed.SOLUTION: In communication I / F2011 of an image generating part 2001, settings for image data are written into a temporary memory part 2002 through serial communication, before the image data are transmitted from the image generating part 2001 to the temporary memory part 2002 (S7003). In the communication I / F2011, partial information about an address used in previous writing is memorized in a cache part 5001 (S7004), and when partial information about an address which is used in subsequent writing matches the memorized partial information about the address, the writing of the partial information about the address is omitted (S7001→S7002→communication completion).SELECTED DRAWING: Figure 6B

Description

[Technical Field]

[0001] The present invention relates to an image forming apparatus and a control method for an image forming apparatus. [Background technology]

[0002] Digital multifunction peripherals (MFPs) that have functions such as a scanner, printer, and copier are in use. The operation of a digital multifunction peripheral is generally controlled by a controller that performs image processing and controls image input and output. An ASIC (Application Specific Integrated Circuit) may be used as the controller.

[0003] In recent years, digital multifunction peripherals have been required to perform printing operations at high speed. Printing operations require real-time processing, which means that the operation does not stop after the start of the operation, at least until the input and output of image data for the page being processed is complete. Here, the controller's processing speed may temporarily decrease. To perform printing operations using real-time processing, it is necessary to ensure that image data transfer between the controller and the printer, etc., continues normally, even if the controller's processing speed temporarily decreases. For this reason, digital multifunction peripherals are equipped with a short buffer for temporarily storing image data. This short buffer is implemented inside the ASIC. A related technique is disclosed in Patent Document 1. Patent Document 1 discloses an image processing device having a short buffer.

[0004] Furthermore, to shorten the time interval between data transfers between the controller and the printer engine, a memory circuit with temporary buffering memory is provided between the controller and the printer engine. This memory circuit is configured, for example, with an FPGA (Field Programmable Gate Array). To use this memory circuit, it is necessary to access the registers of the memory circuit from the controller and make various settings. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-212027 Summary of the Invention [Problem to be solved by the invention]

[0006] When printing multiple pages of image data, if the memory circuit settings for the next page's image data are not completed while the current image data is being transferred, the processing speed will decrease. When a serial communication interface is used to access the memory circuit register from the controller, the above-mentioned situation may occur depending on the communication method. Therefore, there was a need for efficient serial communication when accessing the memory circuit register from the controller.

[0007] The present invention has been made to solve the above-mentioned problems, and aims to provide a mechanism that enables high-speed printing operations by efficiently writing settings via serial communication to a circuit with temporary buffer memory located between the image generation unit and the image forming unit, thereby preventing a decrease in processing speed. [Means for solving the problem]

[0008] The present invention is characterized by comprising an image generation unit that generates image data, an image formation unit that controls image formation based on the image data, a circuit provided between the image generation unit and the image formation unit, a memory circuit that temporarily stores the image data, and a serial interface that writes settings for the image data to the memory circuit before the image data is sent to the memory circuit, the serial interface storing partial information of the address used in the previous write, and omitting writing of the partial information of the address if the partial information of the address to be used for further write matches the partial information of the stored address. [Effects of the Invention]

[0009] According to the present invention, settings can be efficiently written via serial communication to a circuit with temporary buffer memory located between the image generation unit and the image forming unit, thereby preventing a decrease in processing speed and enabling faster printing operations. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view illustrating an image forming apparatus according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram of a laser scanner unit according to the embodiment. [Figure 3] FIG. 2 is a detailed block diagram of an image control unit according to the embodiment. [Figure 4] 5 is a timing chart of a data bus between an image control unit and a temporary storage unit and between the temporary storage unit and an image forming unit according to the present embodiment. [Figure 5A] FIG. 2 is a diagram for explaining communication between communication I / Fs according to the embodiment. [Figure 5B] FIG. 2 is a diagram for explaining communication between communication I / Fs according to the embodiment. [Figure 5C] FIG. 2 is a diagram for explaining communication between communication I / Fs according to the embodiment. [Figure 6A] FIG. 2 is a block diagram illustrating a communication control method between communication I / Fs according to the present embodiment. [Figure 6B] 4 is a flowchart illustrating a method for controlling communication between communication I / Fs according to the present embodiment. [Figure 6C] 10A and 10B are diagrams showing examples of settings for reducing communication traffic in the communication control method between communication I / Fs according to the present embodiment. [Figure 7] 5A and 5B are diagrams illustrating a sequence from job input to printing completion in the image forming apparatus according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, an embodiment of the present invention will be described with reference to the drawings. <System configuration description> DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments do not limit the scope of the present invention as claimed, and not all of the combinations of features described in the present embodiments are necessarily essential to the solution of the present invention.

[0012] An image forming apparatus will be described as an embodiment of an information processing apparatus according to the present invention. FIG. 1 is a cross-sectional view illustrating the configuration of an electrophotographic copying machine (hereinafter referred to as "image forming apparatus") 100 according to one embodiment of the present invention. Note that the image forming apparatus is not limited to a copying machine, and may be, for example, a facsimile machine, a printing machine, a printer, etc. The image forming apparatus may be either a monochrome or color type. Furthermore, the printing method of the image forming apparatus is not limited to an electrophotographic type.

[0013] The configuration and functions of the image forming apparatus 100 will be described below with reference to FIG. As shown in FIG. 1, the image forming apparatus 100 includes an image reading device (hereinafter referred to as a “reader”) 700 and an image printing device 701.

[0014] First, the reading configuration and functions of the reader 700 will be described. In the reader 700, light reflected from a document placed on a document table glass 702 and illuminated by an illumination lamp 703 at the reading position is guided to a color sensor 706 by an optical system consisting of reflecting mirrors 704A, 704B, and 704C and a lens 705. The reader 700 reads the light incident on the color sensor 706 as described above for each color—blue (hereinafter referred to as "B"), green (hereinafter referred to as "G"), and red (hereinafter referred to as "R")—and converts it into electrical image signals. The reader 700 then performs color conversion processing based on the intensities of the B, G, and R image signals to obtain image data, and outputs the image data to an image control unit 1007 (see FIG. 2), which will be described later.

[0015] Next, the printing configuration and functions of the image printing device 701 will be described. A sheet storage tray 718 is provided inside the image printing device 701. The recording medium stored in the sheet storage tray 718 is fed by a paper feed roller 719 and sent to a stationary registration roller (hereinafter referred to as a "registration roller") 723 by transport rollers 722, 721, and 720. The leading edge of the recording medium transported in the transport direction by the transport roller 720 abuts on the nip portion of the stationary registration roller 723. Then, while the leading edge of the recording medium abuts on the nip portion of the stationary registration roller 723, the transport roller 720 further transports the recording medium, causing the recording medium to bend. As a result, an elastic force acts on the recording medium, causing the leading edge of the recording medium to abut along the nip portion of the registration roller 723. In this way, skew correction of the recording medium is performed. After skew correction of the recording medium, the registration roller 723 begins transporting the recording medium at a timing described below. Note that a recording medium is a medium on which an image is formed by an image forming apparatus, and examples of recording media include paper, resin sheets, cloth, overhead projector sheets, and labels.

[0016] Meanwhile, the image data obtained by the reader 700 is corrected by an image control unit 1007, output according to a timing described below, and input to a laser scanner unit 707 including a laser and a polygon mirror. The outer circumferential surface of the photosensitive drum 708 is charged by a charger 709. After the outer circumferential surface of the photosensitive drum 708 is charged, a laser beam corresponding to the image data input to the laser scanner unit 707 is irradiated from the laser scanner unit 707 onto the outer circumferential surface of the photosensitive drum 708. As a result, an electrostatic latent image is formed on a photosensitive layer (photoconductor) covering the outer circumferential surface of the photosensitive drum 708. The operation of the laser scanner unit 707 will be described later with reference to FIG. 2.

[0017] The electrostatic latent image is then developed with toner in a developing unit 710, and a toner image is formed on the outer peripheral surface of the photosensitive drum 708. The toner image formed on the photosensitive drum 708 is transferred to a recording medium by a transfer charger 711 provided at a position (transfer position) opposite the photosensitive drum 708. Note that a registration roller 723 feeds the recording medium to the transfer position in a timed manner so that the toner image is transferred to a predetermined position on the recording medium.

[0018] As described above, the recording medium onto which the toner image has been transferred is sent to the fixing device 724, where it is heated and pressurized to fix the toner image onto the recording medium. The recording medium onto which the toner image has been fixed is then discharged onto a paper discharge tray 725 outside the apparatus. In this way, an image is formed on a recording medium by the image forming apparatus 100. The configuration and functions of the image forming apparatus 100 have been described above.

[0019] 2 is a diagram showing an example of the configuration of the laser scanner unit 707. The configuration of the laser scanner unit 707 will be described below. 2, laser light is emitted from both ends of the laser light source 1000. The laser light emitted from one end of the laser light source 1000 is incident on a photodiode (PD) 1003. The photodiode (PD) 1003 converts the incident laser light into an electrical signal and outputs it as a PD signal to a laser control unit 1008. Based on the input PD signal, the laser control unit 1008 controls the output light amount of the laser light source 1000 (auto power control, hereinafter referred to as "APC") so that the output light amount of the laser light source 1000 becomes a predetermined light amount. On the other hand, the laser light emitted from the other end of the laser light source 1000 passes through a collimator lens 1001 and is irradiated onto a polygon mirror 1002 serving as a rotating polygon mirror.

[0020] The polygon mirror 1002 is rotated by a polygon motor (not shown), which is controlled by a drive signal (Acc / Dec) output from an engine control unit 1009. The laser light irradiated onto the rotating polygon mirror 1002 is deflected by the polygon mirror 1002. The outer peripheral surface of the photosensitive drum 708 is scanned with the laser light deflected by the polygon mirror 1002 from right to left as shown in FIG. The laser light scanning the outer peripheral surface of the photosensitive drum 708 is corrected by an F-θ lens 1005 so as to scan the outer peripheral surface of the photosensitive drum 708 at a constant speed, and is irradiated onto the outer peripheral surface of the photosensitive drum 708 via a folding mirror 1006.

[0021] Furthermore, the laser light deflected by the polygon mirror 1002 is incident on a BD (Beam Detect) sensor 1004 serving as a light receiving unit including a light receiving element that receives the laser light. In this embodiment, the BD sensor 1004 is disposed at a position where the laser light is irradiated onto the outer peripheral surface of the photosensitive drum 708 after the BD sensor 1004 detects the laser light during the period from when the BD sensor 1004 detects the laser light until when the BD sensor 1004 detects the laser light again. Specifically, for example, as shown in FIG. 2, the BD sensor 1004 is disposed in a region outside the region represented by angle α within the region through which the laser light reflected by the polygon mirror 1002 passes and in a region upstream in the direction in which the laser light is steered.

[0022] The BD sensor 1004 generates a BD signal based on the detected laser light and outputs it to the engine control unit 1009. Based on the input BD signal, the engine control unit 1009 controls the polygon motor so that the rotation period of the polygon mirror 1002 becomes a predetermined period. When the period of the BD signal becomes a period corresponding to the predetermined period, the engine control unit 1009 determines that the rotation period of the polygon mirror 1002 has become the predetermined period. The engine control unit 1009 outputs an image creation BD signal to the image control unit 1007 in response to the input BD signal. The image creation BD signal is synchronized with the BD signal. The image creation BD signal corresponds to a signal indicating one scanning cycle in which the laser light operates on the photosensitive drum 708.

[0023] The image control unit 1007 outputs the corrected image data to the laser control unit 1008 in accordance with the input image creation BD signal and an image depiction start timing signal (hereinafter referred to as "TOP signal") input from a registration sensor 723s provided downstream of the registration roller 723. The operation of the image control unit 1007 is a feature of the present invention, and will be described in detail later.

[0024] The image forming unit laser control unit 1008 turns on the laser light source 1000 based on input image data, thereby generating laser light for forming an image on the outer peripheral surface of the photosensitive drum 708. In this manner, the laser control unit 1008 is controlled by the image control unit 1007 as an information processing device. The generated laser light is irradiated onto the outer peripheral surface of the photosensitive drum 708 in the manner described above. This concludes the description of the configuration of the laser scanner unit 707.

[0025] FIG. 3 is a block diagram showing an example of the configuration of the image control unit 1007. The image control unit 1007 includes an image generation unit 2001 , a temporary storage unit 2002 , and an image formation unit 2003 .

[0026] First, the image generation unit 2001 will be described. The image generation unit 2001 includes an image processing unit 2004 , an internal buffer 2005 , a CPU 2008 , a RAM 2009 , a ROM 2010 , and a communication I / F 2011 . The image processing unit 2004 performs color conversion processing on the image data input from the reader 700 to black in the case of monochrome, and to yellow, cyan, magenta, and black in the case of color. The internal buffer 2005 is a short buffer for temporarily storing image data processed by the image generation unit 2001, and transmits the image data to the temporary storage unit 2002 along a data bus, which will be described later.

[0027] The CPU 2008 performs overall control of the processes executed by the image generation unit 2001 and the temporary storage unit 2002 based on a control program stored in the ROM 2010 . The RAM 2009 is a memory such as a DRAM, which temporarily stores data and acts as a working memory. The ROM 2010 is a non-volatile memory that stores boot programs and control programs for the image generating unit 2001 and temporary storage unit 2002 . The communication I / F 2011 is a serial communication I / F (serial interface) or the like, and performs register setting in the temporary storage unit 2002, sending and receiving status, and notifying the image forming unit 2003 that image preparation is complete.

[0028] Next, the temporary storage unit 2002 will be described. The temporary storage unit 2002 is a storage circuit having a buffer unit 2006 and a communication I / F 2012. The temporary storage unit 2002 can be configured, for example, by an FPGA (Field Programmable Gate Array).

[0029] The buffer unit 2006 functions as a temporary buffer memory between the image generation unit 2001 and the image forming unit 2003. The buffer unit 2006 temporarily stores image data input from the image generation unit 2001, and outputs the data in response to a request signal from the image forming unit 2003. At this time, the operating frequency of the data bus between the image generation unit 2001 and the buffer unit 2006 (hereinafter referred to as "f in ") and the operating frequency of the data bus between the buffer unit 2006 and the image forming unit 2003 (hereinafter referred to as "f out The buffer unit 2006 shortens the time interval between data transfers between the image generation unit 2001 and the image formation unit 2003, and synchronizes the image data transfer to the image formation unit 2003, thereby making it possible to meet the required performance.

[0030] The communication I / F 2012 is a serial communication I / F (serial interface) or the like, and transmits and receives register settings and status from the image generation unit 2001. To use the temporary storage unit 2002, the image generation unit 2001 needs to access the registers of the temporary storage unit 2002 and perform various settings.

[0031] Next, the image forming unit 2003 will be described. The image forming unit 2003 includes a laser signal conversion unit 2007 , a CPU 2013 , a RAM 2014 , a ROM 2015 , and a communication I / F 2016 . The laser signal conversion unit 2007 generates an image request signal from the TOP signal input from the registration sensor 723s and the image creation BD signal input from the engine control unit 1009, and inputs the generated signal to the temporary storage unit 2002. The laser signal conversion unit 2007 then converts the image data input from the temporary storage unit 2002 into a laser signal, and outputs the laser signal to the laser control unit 1008.

[0032] The CPU 2013 performs overall control of each process executed by the image forming unit 2003 based on a control program stored in a ROM 2015 . The RAM 2014 is a memory such as a DRAM, which temporarily stores data and functions as a work memory. The ROM 2015 is a non-volatile memory that stores the boot program and control program of the image forming unit 2003 . The communication I / F 2016 is a serial communication I / F or the like, and notifies the temporary storage unit 2002 that an image is ready.

[0033] The image generation unit 2001 and the temporary storage unit 2002 are connected to each other by the same data buses 2017 and 2018, and the temporary storage unit 2002 and the image formation unit 2003 are connected to each other by the same data buses 2017 and 2018. The following description will be made with reference to FIG.

[0034] Figure 4 is a diagram showing an example of the schematic configuration of the data buses 2017 and 2018. Below, we will explain the signals that make up the data buses 2017 and 2018. Note that here, the side that receives data will be called the "slave side," and the side that transmits data will be called the "master side."

[0035] The image request signal is a signal sent from the slave to the master, and indicates the start of image transfer. When this signal is asserted, the master starts image transfer. The image creation BD signal is a signal sent from the slave side to the master side, and is a "main scanning synchronization signal" that indicates the beginning of one line of image data. When the master side receives this signal, it synchronizes with this signal and sends an image synchronization signal to the slave side. Image data is transmitted from the master side to the slave side for each line in synchronization with the assertion of an image synchronization signal.

[0036] 5A, 5B, and 5C are diagrams for explaining communication between the communication I / F 2011 and the communication I / F 2012. Hereinafter, FIGS. 5A, 5B, and 5C will be collectively referred to as "FIG. 5." FIG. 5( a ) shows a detailed block diagram of the communication I / F 2011 and the communication I / F 2012 . FIG. 5B shows a communication format when the communication I / F 2011 accesses the communication I / F 2012. FIG. 5C shows a sequence of write access from the communication I / F 2011 to the communication I / F 2012. FIG. 5D shows a sequence of read access from the communication I / F 2011 to the communication I / F 2012.

[0037] 5(a), the communication I / F 2012 has a top register unit 3001 and a module register unit 3002. The top register unit 3001 further has a top address register unit 4001, a bottom address register unit 4002, a top data register unit 4003, and a bottom data register unit 4004. The communication I / F 2011 accesses the module register unit 3002 via the registers 4001 to 4004 of the top register unit 3001 of the communication I / F 2012. Details will be described later using the write access sequence shown in Fig. 5(c) and the read access sequence shown in Fig. 5(d).

[0038] The module register unit 3002 is a register having various functions for using the temporary storage unit 2002. There are a plurality of module register units, and examples of the functions that are mainly used are described below. -Specify the number of pixels in the main scanning direction Specify the number of lines to input -Specify the main scanning start position of the image capture range -Specify the starting position of the image capture range in the sub-scanning direction -Specify the number of lines where an interrupt occurs The above is an example of a function that is mainly used, and the present invention is not limited to the above.

[0039] When the communication I / F 2011 accesses the communication I / F 2012, communication must be performed in accordance with a communication format 3003 shown in FIG. 5(b). The communication format 3003 is composed of a first byte 4005 consisting of a command and an internal address, and a second byte 4006 consisting of write data.

[0040] In the first byte 4005, the command specifies whether it is a "write access" or a "read access." Also, the internal address specifies whether the access is to the upper address register unit 4001, the lower address register unit 4002, the upper data register unit 4003, or the lower data register unit 4004. The 2nd Byte 4006 specifies the data to be written to the register specified by the internal address of the 1st Byte 4005. However, if the command is a read access, the 2nd Byte 4006 can be omitted.

[0041] A write access from the communication I / F 2011 to the communication I / F 2012 based on the communication format 3003 is performed in a sequence as shown in FIG. 5(c). The communication I / F 2011 specifies write access in the command of the first byte, specifies the upper address register unit 4001 in the internal address, and communicates with the top register unit 3001 of the communication I / F 2012 . The top register unit 3001 notifies the communication I / F 2011 that the data was received correctly, and returns the received data to the communication I / F 2011 as is. The communication I / F 2011 checks whether the data sent to the top register unit 3001 matches the data received from the top register unit 3001, and then proceeds to the next step. In the following explanation, the explanation of the step of notifying that the data was received correctly will be omitted.

[0042] As described above, the first byte specifies write access to the upper address register unit 4001. Therefore, the second byte specifies the upper address of the desired function register among the function registers managed by the module register unit 3002, and communication is performed from the communication I / F 2011 to the top register unit 3001 of the communication I / F 2012. The top register unit 3001 stores the second byte received from the communication I / F 2011 as the upper address.

[0043] Using a similar procedure, the communication I / F 2011 specifies, in the first byte, a write access to the lower address register unit 4002, and communicates with the top register unit 3001 of the communication I / F 2012. Thereafter, the communication I / F 2011 specifies, in the second byte, the lower address of the desired function register of each function register managed by the module register unit 3002, and communicates with the top register unit 3001 of the communication I / F 2012. The top register unit 3001 stores the second byte received from the communication I / F 2011 as the lower address.

[0044] Next, the communication I / F 2011 specifies write access in the command of the first byte, specifies the upper data register unit 4003 in the internal address, and communicates with the top register unit 3001 of the communication I / F 2012. After that, the communication I / F 2011 specifies upper data to be written to the function register in the second byte, and communicates with the top register unit 3001 of the communication I / F 2012. When the top register unit 3001 receives the second byte of data from the communication I / F 2011, it writes the upper data to the module register unit 3002 specified by the upper address register unit 4001 and the lower address register unit 4002. The lower data is also written in the same manner. The above is the method for making write access from the communication I / F 2011 to the module register unit 3002 via the top register unit 3001 of the communication I / F 2012.

[0045] Next, read access will be described. A read access from the communication I / F 2011 to the communication I / F 2012 based on the communication format 3003 in FIG. 5(b) is performed in a sequence as shown in FIG. 5(d).

[0046] The upper address register section 4001 and the lower address register section 4002 are designated by the same procedure as for write access. Thereafter, the communication I / F 2011 specifies read access in the command of the first byte, specifies the upper data register unit 4003 as the internal address, and communicates with the top register unit 3001 of the communication I / F 2012. In this case, since the command is a read access, communication of the second byte is not necessary.

[0047] When the top register unit 3001 receives a read access notification to the upper data register unit 4003, it reads upper data from the module register unit 3002 specified by the upper address register unit 4001 and the lower address register unit 4002. The top register unit 3001 transmits the read data to the communication I / F 2011. At this time, the communication I / F 2011 cannot perform the next communication until it receives the read data from the top register unit 3001. The lower level data is also read using the same operation. The above is the method for performing read access from the communication I / F 2011 to the module register unit 3002 via the top register unit 3001 of the communication I / F 2012.

[0048] Hereinafter, a method for controlling communication between communication I / Fs to which the present invention is applied will be described with reference to FIGS. 6A, 6B, and 6C. FIG. 6A is a block diagram illustrating a communication control method between communication I / Fs to which the present invention is applied. 6A, the communication I / F 2011 has a cache unit 5001. The communication I / F 2011 caches information written to the top register unit 3001 in the cache unit 5001. The information is stored in the cache unit 5001 when writing to the top register unit 3001 is completed.

[0049] The cache unit 5001 further includes a high-order address cache unit 6001, a low-order address cache unit 6002, a high-order data cache unit 6003, and a low-order data cache unit 6004. The high-order address cache unit 6001 corresponds to the high-order address register unit 4001. The low-order address cache unit 6002 corresponds to the low-order address register unit 4002. The high-order data cache unit 6003 corresponds to the high-order data register unit 4003. The low-order data cache unit 6004 corresponds to the low-order data register unit 4004.

[0050] When the image forming apparatus 100 is started up or returns from a power saving state (returns from sleep), the caches 6001 to 6004 of the cache unit 5001 are initialized to ensure consistency with the registers 4001 to 4004. This may be done by reading (obtaining) data from the registers 4001 to 4004 and reflecting it in the caches 6001 to 6004, or by ensuring that communication is always performed when the registers 4001 to 4004 are first accessed, and then reflecting it in the cache.

[0051] A method for partially omitting communication in the above configuration will be described with reference to FIG. 6B. FIG. 6B is a flowchart illustrating a method for controlling communication between communication I / Fs to which the present invention is applied. The CPU 2008 of the image generation unit 2001 initiates a communication request to the communication I / F 2011 to access the temporary storage unit 2002 based on a program running on the RAM 2009. This communication request is initiated each time a write command or a read command is transmitted from the communication I / F 2011 to the top register unit 3001 of the communication I / F 2012 in FIG. 5(c) or FIG. 5(d).

[0052] When the communication I / F 2011 receives the above-mentioned communication request, it checks (7001) whether the communication request is for communication to the upper address register unit 4001 or the lower address register unit 4002. If the communication request is for communication to the upper address register unit 4001 or the lower address register unit 4002 (Yes in S7001), the communication I / F 2011 proceeds to S7002.

[0053] In S7002, the communication I / F 2011 checks whether the data to be communicated matches the cache. Specifically, the communication I / F 2011 checks whether the contents of the communication request match the contents of the upper address cache unit 6001 in the case of a communication request to the upper address register unit 4001, or the contents of the lower address cache unit 6002 in the case of a communication request to the lower address register unit 4002. If they match (Yes in S7002), the communication I / F 2011 ends the processing of this flowchart without communicating with the communication I / F 2012.

[0054] On the other hand, if the contents of the communication request do not match the cache (No in S7002), the communication I / F 2011 advances the process to S7003. Furthermore, in the above S7001, if the communication request is neither for communication to the upper address register unit 4001 nor for communication to the lower address register unit 4002 (No in S7001), the communication I / F 2011 also advances the process to S7003.

[0055] In step S7003, the communication I / F 2011 communicates with the communication I / F 2012. Next, in S7004, the communication I / F 2011 confirms that the communication has been performed reliably, reflects the communicated content in one of the caches 6001 to 6004 corresponding to the communication request, and ends the processing of this flowchart. As a result, it is possible to omit communication only to the address register if the data is cached.

[0056] FIG. 6C is a diagram showing an example of settings for reducing communication traffic in a communication control method between communication I / Fs to which the present invention is applied. 6C illustrates some of the upper and lower addresses associated with the functions of the module register unit 3002. These functions can be set for all channels (CMYK) at once or for each channel. Here, a pattern in which communication can be omitted using a higher address and a pattern in which communication can be omitted using a lower address will be described.

[0057] First, a pattern in which communication can be omitted using a higher address will be described using an example in which settings are reflected on all channels at once. In order to specify the number of pixels in the main scanning direction (for all channels), it is necessary to write "0x00" to the upper address register unit 4001. If communication is performed according to the flowchart in FIG. 6B here, in S7001, it corresponds to communication to the upper address register unit 4001, so the process proceeds to S7002. In S7002, it is confirmed whether the communication content "0x00" to the upper address register unit 4001 matches the cache. In this example, it is assumed that the cache differs from the previous communication, so the process proceeds to step S7003. In step S7003, communication is performed to the communication I / F 2012, and writing is performed to the upper address register unit 4001. Thereafter, in step S7004, the upper address cache unit 6001 of the communication I / F 5001 is updated to store "0x00". In a similar procedure, "0x00" is written to the lower address register unit 4002, and the lower address cache unit 6002 is updated to store "0x00".

[0058] 6B, in S7001, the upper data register unit 4003 and the lower data register unit 4004 do not correspond to communication with the upper address register unit 4001 or the lower address register unit 4002, so the process proceeds directly to S7003. In S7003, an arbitrary value is written to the upper data register unit 4003 or the lower data register unit 4004 of the communication I / F 2012. In S7004, the upper data cache unit 6003 and the lower data cache unit 6004 are updated.

[0059] Next, to specify the number of lines to be input (for all channels), it is necessary to write "0x00" to the upper address register unit 4001. However, since "0x00" was written to the upper address register unit 4001 in the previous communication in S7002 of FIG. 6B and "0x00" is cached in the upper address cache unit 6001, this step can be omitted without actually communicating with the communication I / F 2012.

[0060] Also, it is necessary to write "0x01" to the lower address register unit 4002. In S7002 of Fig. 6B, "0x00" was written to the lower address register unit 4002 in the previous communication, and "0x00" is cached in the lower address cache unit 6002, so the contents do not match. Therefore, steps S7003 and S7004 must be performed (they cannot be omitted).

[0061] Then, any value must be communicated in steps S7001, S7003, and S7004 for the upper data register unit 4003 and the lower data register unit 4004. The above are examples of patterns in which writing to the upper address register unit 4001 can be omitted.

[0062] Next, a pattern in which communication can be omitted using lower addresses will be explained using an example in which settings are reflected for each channel. In order to specify the number of pixels in the main scanning direction (ch0), it is necessary to write "0x10" to the upper address register unit 4001. If communication is performed according to the flowchart in FIG. 6B, in S7001, it corresponds to communication to the upper address register unit 4001, so the process proceeds to step S7002. In S7002, it is confirmed whether the communication content "0x10" to the upper address register unit 4001 matches the cache. In this example, it is assumed that the cache differs from the previous communication, so the process proceeds to step S7003. In step S7003, communication is performed to the communication I / F 2012, and writing is performed to the upper address register unit 4001. Then, in step S7004, the upper address cache unit 6001 of the communication I / F 5001 is updated to store "0x10". In a similar procedure, "0x00" is written to the lower address register unit 4002, and the lower address cache unit 6002 is updated to store "0x00".

[0063] 6B, for the upper data register unit 4003 and the lower data register unit 4004, the process proceeds to S7003 because in S7001 this does not apply to communication with the upper address register unit 4001 or the lower address register unit 4002. In S7003, an arbitrary value is written to the upper data register unit 4003 or the lower data register unit 4004 of the communication I / F 2012, and then in S7004 the values are updated to the upper data cache unit 6003 and the lower data cache unit 6004.

[0064] In the above state, to next specify the number of pixels in the scanning direction (ch3), it is necessary to write "0x40" to the upper address register unit 4001. In this case, in S7002 of Fig. 6B, "0x10" was written to the upper address register unit 4001 in the previous communication, and "0x10" is cached in the upper address cache unit 6001. Therefore, since the contents do not match, it is necessary to perform communication by performing steps 7003 and 7004 (i.e., they cannot be omitted).

[0065] Also, although it is necessary to write "0x00" to the lower address register unit 4002, this can be omitted. Specifically, in S7002, "0x00" was written to the lower address register unit 4002 in the previous communication, and "0x00" is cached in the lower address cache unit 6002. For this reason, it is possible to omit this step without actually communicating with the communication I / F 2012. It should be noted that for the upper data register section 4003 and the lower data register section 4004, it is necessary to communicate any value in steps 7001, 7003, and 7004. The above are examples of patterns in which writing to the lower address register unit 4002 can be omitted.

[0066] FIG. 7 is a diagram for explaining the sequence from job input to printing completion in the image forming apparatus 100 to which the present invention is applied. When the image generation unit 2001 receives a print instruction from the user, it performs settings related to the image data of the first page and reflects the settings in the temporary storage unit 2002 via the communication I / F 2011 (8001).

[0067] Next, the image generating unit 2001 transfers the image data from the image generating unit 2001 to the temporary storage unit via the data bus 2017 (8002). When the temporary storage unit 2002 receives the image data from the image generation unit 2001, it transfers the image data to the image formation unit 2003 via the data bus 2018 (8003). The image forming unit 2003 receives the image data from the temporary storage unit 2002 and transfers the image data to the engine control unit 1009 (8004). The engine control unit 1009 prints the image in accordance with the received image data.

[0068] In addition, the image generating unit 2001 performs settings related to the image data of the next page via the communication I / F 2001 (8005) in parallel with the process of transferring the image data to the temporary storage unit 2002 via the data bus 2017 shown in 8002 above. When the image data transfer in step 8002 is completed, the image generating unit 2001 reflects the contents set in step 8005 in the temporary storage unit 2002 via the communication I / F 2001 (step 8006).

[0069] The above steps 8002 to 8006 are repeated from the first page to the page just before the last. When the repetition of steps 8002 to 8006 is completed, the image data of the last page is transferred from the image generation unit 2001 to the temporary storage unit 2002 (8007). The image data is also transferred from the temporary storage unit 2002 to the image forming unit 2003 (8008), and from the image forming unit 2003 to the engine control unit 1009 (8009). The engine control unit 1009 prints according to the image data of the last page, thereby completing the job.

[0070] 6B, the communication control between communication I / Fs to which the present invention is applied can be applied to the above steps 8001, 8005, and 8006. That is, in the above steps 8001, 8005, and 8006, if the partial address information (upper address or lower address) used for writing matches the partial address information stored in the cache unit 5001, writing of the partial address information can be omitted.

[0071] As described above, in this embodiment, before image data is transmitted from the image generation unit 2001 to the temporary storage unit 2002, settings for the image data are written to the temporary storage unit 2002. At this time, the image generation unit 2001 writes a register address to the temporary storage unit 2002 and caches the register address. The temporary storage unit 2002 stores the register address written immediately before and does not change it. Furthermore, when the image generation unit 2001 accesses a register in the temporary storage unit 2002, the image generation unit 2001 determines whether the access is to a register address or data corresponding to the register address. In the case of a register address, the upper and lower byte are checked to see if the contents to be written match the contents of the cache, and if they match, writing to the temporary storage unit 2002 is skipped.

[0072] With the above configuration, according to this embodiment, two bytes can be omitted if the register addresses match perfectly, and one byte can be omitted if either the upper or lower byte of the register addresses match. Conventionally, four bytes of communication were required to access one register. However, according to this embodiment, communication efficiency can be reduced to one-half to three-quarters of the conventional amount. Although a serial communication interface is used for register access from the image generation unit 2001 to the temporary storage unit 2002, omitting this communication as described above allows for efficient serial communication. Therefore, when printing multiple sheets of image data, the temporary storage unit 2002 can be configured for the image data of the next page while the image data of the current page is being transferred. In this way, settings can be efficiently written via serial communication to a circuit with temporary buffer memory located between the image generation unit and the image forming unit. As a result, a decrease in processing speed in an image forming apparatus such as a digital multifunction peripheral can be suppressed, enabling faster printing operations. Furthermore, even if the amount of image processing on the printer engine side increases and the register access required also increases accordingly, and more register access becomes necessary, the present invention can achieve faster printing operations by performing efficient serial communication.

[0073] It goes without saying that the configurations and contents of the various data described above are not limited to those described above, and that the data may be configured in various configurations and contents depending on the application and purpose. Although one embodiment has been described above, the present invention can be embodied as, for example, a system, an apparatus, a method, a program, a storage medium, etc. Specifically, the present invention may be applied to a system made up of multiple devices, or may be applied to an apparatus made up of a single device. Furthermore, the present invention also includes any combination of the above embodiments.

[0074] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions. Furthermore, the present invention may be applied to a system made up of multiple devices, or to an apparatus made up of a single device. The present invention is not limited to the above-described embodiments, and various modifications (including organic combinations of the embodiments) are possible based on the spirit of the present invention, and are not excluded from the scope of the present invention. In other words, all configurations that combine the above-described embodiments and their modifications are included in the present invention. [Explanation of symbols]

[0075] 100 Image forming device 2001 Image Generation Unit 2002 Temporary storage 2003 Image Formation Department 2011,2012 Communication I / F 2017,2018 Data Bus 3001 Top register section 5001 Cache section

Claims

1. an image generation unit that generates image data; an image forming unit that controls image formation based on the image data; a memory circuit provided between the image generating unit and the image forming unit, the memory circuit temporarily storing the image data; a serial interface that writes settings for the image data into the storage circuit before the image data is transmitted to the storage circuit, the serial interface storing partial address information used in a previous write operation, and omitting writing of the partial address information when the partial address information to be used in a further write operation matches the stored partial address information; An image forming apparatus comprising:

2. 2. The image forming apparatus according to claim 1, wherein the partial information of the address is a high-order address or a low-order address.

3. 3. The image forming apparatus according to claim 1, wherein the serial interface stores the partial address information at a timing when writing to the memory circuit is completed.

4. An image forming apparatus according to any one of claims 1 to 3, characterized in that the serial interface ensures consistency between the partial address information written in the memory circuit and the storage of the partial address information at a predetermined timing.

5. 5. The image forming apparatus according to claim 4, wherein the serial interface obtains partial information of the address written in the memory circuit and stores the obtained partial information of the address to ensure the consistency.

6. 5. The image forming apparatus according to claim 4, wherein the serial interface ensures the consistency by not omitting writing of partial information of the address when writing to the memory circuit at the predetermined timing.

7. 7. The image forming apparatus according to claim 4, wherein the predetermined timing includes timing related to startup of the image forming apparatus and timing related to recovery from a power saving state.

8. A control method for an image forming apparatus having an image generation unit that generates image data, an image formation unit that controls image formation based on the image data, a memory circuit that is a circuit provided between the image generation unit and the image formation unit and that temporarily stores the image data, and a serial interface that writes settings for the image data into the memory circuit before the image data is transmitted to the memory circuit, a step in which the serial interface stores partial information of the address used in the previous write; a step of omitting writing of the partial address information by the serial interface when the partial address information to be used for further writing matches the partial address information stored in the serial interface; 1. A method for controlling an image forming apparatus, comprising:

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