Semiconductor Devices

Abstract

This semiconductor device is provided with a plurality of semiconductor elements electrically connected in parallel to each other, a pad portion in electrical communication with the plurality of semiconductor elements, and a terminal portion in electrical communication with the pad portion. The plurality of semiconductor elements, as viewed in a thickness direction thereof, are arrayed along a first direction orthogonal to the thickness direction. The pad portion includes a closed region enclosed by three line segments each formed by connecting two of a first vertex, a second vertex, and a third vertex that are not on the same line. The first vertex, as viewed in the thickness direction, overlaps an outermost one of the plurality of semiconductor elements that is on one side in the first direction. The second vertex, as viewed in the thickness direction, overlaps an outermost one of the plurality of semiconductor elements that is on the other side in the first direction. The third vertex, as viewed in the thickness direction, is positioned on a perpendicular bisector of a line segment connecting the first vertex and the second vertex.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices including power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. In such semiconductor devices, multiple semiconductor elements are sometimes connected in parallel to increase capacity and power output (see, for example, Patent Document 1). The semiconductor device described in Patent Document 1 includes two semiconductor elements, first and second terminals, first and second connecting conductors, and wires. In Patent Document 1, each of the two semiconductor elements is an IGBT. Each of the two semiconductor elements is mounted on a first connecting conductor, and the collector electrodes of the two semiconductor elements are electrically connected to the first connecting conductor. The first connecting conductor is connected to the first terminal, which may be, for example, a collector terminal. A wire is bonded to each of the emitter electrodes of the two semiconductor elements, and the emitter electrodes are electrically connected to the second connecting conductor via the wire. The second connecting conductor is connected to the second terminal, which may be, for example, an emitter terminal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-148077 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, for example, there is a difference in distance between the current paths from the first terminal to each semiconductor element. This difference in distance can cause a bias in the magnitude of the current flowing through each semiconductor element. This bias increases the burden on one semiconductor element, causing its lifespan to be shorter than that of the other semiconductor element.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress bias in current flowing through a plurality of semiconductor elements connected in parallel. [Means for solving the problem]

[0006] The semiconductor device disclosed herein includes a plurality of first semiconductor elements, each having a first element main surface and a first element back surface spaced apart in the thickness direction and electrically connected in parallel to one another, a pad portion electrically connected to the plurality of first semiconductor elements, and a first terminal portion electrically connected to the pad portion. The plurality of first semiconductor elements are arranged along a first direction perpendicular to the thickness direction when viewed in the thickness direction. The pad portion includes a closed region surrounded by three line segments formed by connecting two first vertices, two second vertices, and two third vertices that are not on the same line. When viewed in the thickness direction, the first vertex overlaps with the outermost first semiconductor element of the plurality of first semiconductor elements on one side of the first direction. When viewed in the thickness direction, the second vertex overlaps with the outermost first semiconductor element of the plurality of first semiconductor elements on the other side of the first direction. When viewed in the thickness direction, the third vertex is located on the perpendicular bisector of the line segment connecting the first vertex and the second vertex. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, it is possible to suppress the difference in current flowing through a plurality of semiconductor elements connected in parallel. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2]FIG. 2 is a perspective view of FIG. 1 in which the resin member is omitted. [Figure 3] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 4 is a plan view of FIG. 3 in which a resin member is indicated by imaginary lines. [Figure 5] 5 is a diagram showing two input terminals and an output terminal in the plan view of FIG. 4, indicated by imaginary lines. [Figure 6] FIG. 6 is a partially enlarged view of a part of FIG. 5. [Figure 7] FIG. 1 is a front view showing a semiconductor device according to a first embodiment. [Figure 8] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 9] FIG. 1 is a left side view showing a semiconductor device according to a first embodiment. [Figure 10] FIG. 6 is a cross-sectional view taken along line XX in FIG. 5. [Figure 11] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment, in which a resin member is indicated by imaginary lines. [Figure 12] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment, in which two input terminals, an output terminal, and a resin member are indicated by imaginary lines. [Figure 13] 13 is a diagram in which the main part is extracted from the plan view of FIG. 12. FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment, in which a resin member is indicated by imaginary lines. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the accompanying drawings. In the following description, identical or similar components will be designated by the same reference numerals and redundant description will be omitted.

[0010] 1 to 10 show a semiconductor device A1 according to a first embodiment. The semiconductor device A1 includes a plurality of semiconductor elements 10 and 20, a support substrate 30, a plurality of terminals, a plurality of connecting members, and a resin member 60. The plurality of terminals include two input terminals 41 and 42, an output terminal 43, a pair of control terminals 44A and 44B, and a pair of detection terminals 45A and 45B. The plurality of connecting members include a plurality of gate wires 51, a plurality of detection wires 52, a pair of first connecting wires 53, a pair of second connecting wires 54, and a plurality of lead plates 55.

[0011] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a perspective view of FIG. 1 with the resin member 60 omitted. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a view showing the resin member 60 in the plan view of FIG. 3 by using imaginary lines (two-dot chain lines). FIG. 5 is a view showing two input terminals 41, 42 and an output terminal 43 by using imaginary lines in the plan view of FIG. 4. FIG. 6 is a partially enlarged view of a part of FIG. 5. FIG. 7 is a front view showing the semiconductor device A1. FIG. 8 is a bottom view showing the semiconductor device A1. FIG. 9 is a side view (left side view) showing the semiconductor device A1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 5.

[0012] For convenience of explanation, three mutually orthogonal directions (x direction, y direction, and z direction) will be referred to as appropriate. The z direction is the thickness direction of the semiconductor device A1. The x direction is the left-right direction in the plan view of the semiconductor device A1 (see Figure 3). The y direction is the up-down direction in the plan view of the semiconductor device A1 (see Figure 3). One of the x directions is the x1 direction, and the other of the x directions is the x2 direction. Similarly, one of the y directions is the y1 direction, the other of the y directions is the y2 direction, one of the z directions is the z1 direction, and the other of the z directions is the z2 direction. In the following explanation, "plan view" refers to when viewed in the z direction. The z direction is an example of the "thickness direction," the x direction is an example of the "second direction," and the y direction is an example of the "first direction."

[0013] The multiple semiconductor elements 10, 20 are configured using a semiconductor material primarily composed of, for example, SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like, but preferably a wide bandgap semiconductor material is used. Each of the semiconductor elements 10, 20 is, for example, a MOSFET. Each of the semiconductor elements 10, 20 is not limited to a MOSFET and may be other transistors, such as a field effect transistor including a MISFET (metal-insulator-semiconductor FET) or a bipolar transistor such as an IGBT. Each of the semiconductor elements 10, 20 is the same element and is, for example, an n-channel MOSFET. Each of the semiconductor elements 10, 20 has a rectangular shape in a plan view, but is not limited to this.

[0014] The semiconductor device A1 includes, for example, four semiconductor elements 10 and four semiconductor elements 20. The number of the semiconductor elements 10, 20 is not limited to this configuration and can be changed depending on the performance required of the semiconductor device A1. The semiconductor device A1 is, for example, a half-bridge switching circuit. In this case, the multiple semiconductor elements 10 form an upper arm circuit of the semiconductor device A1, and the multiple semiconductor elements 20 form a lower arm circuit of the semiconductor device A1. In a configuration described below, the multiple semiconductor elements 10 are electrically connected in parallel, and the multiple semiconductor elements 20 are electrically connected in parallel. Furthermore, the multiple semiconductor elements 10 and the multiple semiconductor elements 20 are connected in series to form a bridge.

[0015] As shown in FIG. 10, each of the multiple semiconductor elements 10 has an element main surface 10a and an element back surface 10b. In each semiconductor element 10, the element main surface 10a and the element back surface 10b are spaced apart in the z direction. The element main surface 10a faces the z2 direction, and the element back surface 10b faces the z1 direction. The element main surface 10a is an example of a "first element main surface," and the element back surface 10b is an example of a "first element back surface."

[0016] Each of the semiconductor elements 10 includes a principal surface electrode 11, a control electrode 12, a back surface electrode 13, and an insulating film 14. As shown in FIGS. 6 and 10 , the principal surface electrode 11 and the control electrode 12 are provided on the element principal surface 10 a. The principal surface electrode 11 is, for example, a source electrode through which a source current flows. The control electrode 12 is, for example, a gate electrode to which a gate voltage for driving each semiconductor element 10 is applied. In a plan view, the principal surface electrode 11 is larger than the control electrode 12. In the example shown in FIG. 6 and other figures, the principal surface electrode 11 is configured as a single region, but it may be divided into multiple regions. As shown in FIG. 10 , the back surface electrode 13 is provided on the element rear surface 10 b. The back surface electrode 13 is, for example, a drain electrode through which a drain current flows. The back surface electrode 13 is formed over substantially the entire surface of the element rear surface 10 b. As shown in FIGS. 6 and 10 , the insulating film 14 is provided on the element principal surface 10 a. The insulating film 14 has electrical insulating properties. The insulating film 14 surrounds the principal surface electrodes 11 and the control electrodes 12 in a plan view, and insulates the principal surface electrodes 11 from the control electrodes 12. The insulating film 14 is formed by laminating, for example, a SiO2 (silicon dioxide) layer, a SiN4 (silicon nitride) layer, and a polybenzoxazole layer in this order, with the polybenzoxazole layer being the surface layer of each semiconductor element 10. The configuration of the insulating film 14 is not limited to that described above, and for example, a polyimide layer may be laminated instead of the polybenzoxazole layer.

[0017] When a first drive signal (e.g., gate voltage) is input to the control electrode 12 (gate electrode), each semiconductor element 10 switches between a conductive state and a cutoff state in response to the first drive signal. This operation of switching between the conductive state and the cutoff state is called a switching operation. In the conductive state, current flows from the back electrode 13 (drain electrode) to the main surface electrode 11 (source electrode), and in the cutoff state, this current does not flow.

[0018] As shown in FIGS. 5, 6, and 10, the semiconductor elements 10 are mounted on a support substrate 30. In the example shown in FIG. 5, the semiconductor elements 10 are arranged along the y direction and spaced apart from one another. Each semiconductor element 10 is conductively bonded to the support substrate 30 (a conductive substrate 32A described below) via a conductive bonding material (not shown) (for example, a sintered metal such as sintered silver or sintered copper, a metal paste material such as silver or copper, or solder). When each semiconductor element 10 is bonded to the conductive substrate 32A, the element back surface 10b faces the conductive substrate 32A. Each semiconductor element 10 is an example of a "first semiconductor element." In each semiconductor element 10, the principal surface electrode 11 is an example of a "first principal surface electrode," the control electrode 12 is an example of a "first control electrode," and the back surface electrode 13 is an example of a "first back surface electrode."

[0019] As shown in FIG. 5, the multiple semiconductor elements 10 include two outer elements 10A and multiple inner elements 10B. The two outer elements 10A are each located outermost in the y direction among the multiple semiconductor elements 10. The multiple inner elements 10B are sandwiched between two outer elements 10A in the y direction among the multiple semiconductor elements 10. In this embodiment, the semiconductor device A1 includes four semiconductor elements 10, and therefore the number of inner elements 10B is two. In a configuration different from the semiconductor device A1, when the number of semiconductor elements 10 is two, there is no inner element 10B, and when the number of semiconductor elements is three, there is one inner element 10B.

[0020] As shown in FIG. 10 , each of the multiple semiconductor elements 20 has an element main surface 20a and an element back surface 20b. In each semiconductor element 20, the element main surface 20a and the element back surface 20b are spaced apart in the z direction. The element main surface 20a faces the z2 direction, and the element back surface 20b faces the z1 direction. The element main surface 20a is an example of a "second element main surface," and the element back surface 20b is an example of a "second element back surface."

[0021] Each of the semiconductor elements 20 includes a principal surface electrode 21, a control electrode 22, a back surface electrode 23, and an insulating film 24. As shown in FIGS. 6 and 10 , the principal surface electrode 21 and the control electrode 22 are provided on the element principal surface 20 a. The principal surface electrode 21 is, for example, a source electrode through which a source current flows. The control electrode 22 is, for example, a gate electrode to which a gate voltage for driving each semiconductor element 20 is applied. In a plan view, the principal surface electrode 21 is larger than the control electrode 22. In the example shown in FIG. 6 and other figures, the principal surface electrode 21 is configured as a single region, but may be divided into multiple regions. As shown in FIG. 10 , the back surface electrode 23 is provided on the element back surface 20 b. The back surface electrode 23 is, for example, a drain electrode through which a drain current flows. The back surface electrode 23 is formed over substantially the entire surface of the element back surface 20 b. As shown in FIGS. 6 and 10 , the insulating film 24 is provided on the element principal surface 20 a. The insulating film 24 has electrical insulating properties. The insulating film 24 surrounds the principal surface electrode 21 and the control electrode 22 in a plan view. The insulating film 24 insulates the principal surface electrode 21 from the control electrode 22 on the element principal surface 20a. The insulating film 24 is made of the same material as the insulating film 14, for example.

[0022] When a second drive signal (e.g., a gate voltage) is input to the control electrode 22 (gate electrode), each semiconductor element 20 switches between a conductive state and a cut-off state in response to the second drive signal (i.e., performs a switching operation). In the conductive state, a current flows from the back electrode 23 (drain electrode) to the main surface electrode 21 (source electrode), and in the cut-off state, this current does not flow.

[0023] As shown in FIGS. 5, 6, and 10, the semiconductor elements 20 are mounted on a support substrate 30. In the example shown in FIG. 5, the semiconductor elements 20 are arranged along the y direction and spaced apart from one another. When viewed in the x direction, each semiconductor element 20 overlaps a corresponding semiconductor element 10. Each semiconductor element 20 is conductively bonded to the support substrate 30 (a conductive substrate 32B described below) via a conductive bonding material (not shown) (e.g., a sintered metal such as sintered silver or sintered copper, a metal paste material such as silver or copper, or solder). When each semiconductor element 20 is bonded to the conductive substrate 32B, the element back surface 20b faces the conductive substrate 32B. Each semiconductor element 20 is an example of a "second semiconductor element." In each semiconductor element 20, the principal surface electrode 21 is an example of a "second principal surface electrode," the control electrode 22 is an example of a "second control electrode," and the back surface electrode 23 is an example of a "second back surface electrode."

[0024] As shown in FIG. 5, the plurality of semiconductor elements 20 includes two outer elements 20A and a plurality of inner elements 20B. The two outer elements 20A are each located outermost in the y direction among the plurality of semiconductor elements 20. The plurality of inner elements 20B are sandwiched between two outer elements 20A in the y direction among the plurality of semiconductor elements 20. In this embodiment, the semiconductor device A1 includes four semiconductor elements 20, and therefore the number of inner elements 20B is two. In a configuration different from the semiconductor device A1, when the number of semiconductor elements 20 is two, there is no inner element 20B, and when the number of semiconductor elements is three, there is one inner element 20B.

[0025] The support substrate 30 supports the multiple semiconductor elements 10 and 20. The support substrate 30 includes a pair of insulating substrates 31A and 31B, a pair of conductive substrates 32A and 32B, a pair of insulating layers 33A and 33B, a pair of gate layers 34A and 34B, and a pair of detection layers 35A and 35B.

[0026] The pair of insulating substrates 31A, 31B are electrically insulating. Each of the insulating substrates 31A, 31B is made of, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride). Each of the insulating substrates 31A, 31B is not limited to ceramics and may be an insulating resin sheet or the like. Each of the insulating substrates 31A, 31B has, for example, a rectangular shape in a plan view. As shown in Figures 5 and 10, the pair of insulating substrates 31A, 31B are aligned in the x direction and spaced apart from each other. The insulating substrate 31A is located on the x2 direction side of the insulating substrate 31B.

[0027] As shown in FIG. 10 and other figures, each of the insulating substrates 31A and 31B has a main surface 311 and a back surface 312. In each of the insulating substrates 31A and 31B, the main surface 311 and the back surface 312 are spaced apart in the z direction. The main surface 311 faces the z2 direction, and the back surface 312 faces the z1 direction. The main surface 311, together with the pair of conductive substrates 32A and 32B and the plurality of semiconductor elements 10 and 20, is covered by a resin member 60. The back surface 312 is exposed from the resin member 60 (a resin back surface 62, which will be described later) as shown in FIG. 8. The back surface 312 is connected to, for example, a heat sink (not shown).

[0028] Each of the pair of conductive substrates 32A and 32B is a plate-shaped member made of metal. The metal may be, for example, copper (Cu) or a Cu alloy. The pair of conductive substrates 32A and 32B is not limited to being made of metal, and may be, for example, graphite with metal layers (e.g., Cu or Al) formed on both sides in the thickness direction (z direction). The pair of conductive substrates 32A and 32B, together with two input terminals 41 and 42 and an output terminal 43, form a conduction path to the plurality of semiconductor elements 10 and 20. The surface of each of the conductive substrates 32A and 32B on the z2 direction side may be plated. The pair of conductive substrates 32A and 32B are spaced apart in the x direction, as shown in, for example, FIGS. 5 and 10 . In the example shown in, for example, FIGS. 5 and 10 , the conductive substrate 32A is positioned further in the x2 direction than the conductive substrate 32B.

[0029] 10 and other figures, each of the conductive substrates 32A and 32B has a main surface 321 and a back surface 322. In each of the conductive substrates 32A and 32B, the main surface 321 and the back surface 322 are spaced apart in the z direction. The main surface 321 faces the z2 direction, and the back surface 322 faces the z1 direction.

[0030] As shown in FIG. 10 and other figures, the conductive substrate 32A is bonded to the insulating substrate 31A via a bonding material (not shown). This bonding material may be either conductive or insulating. When the conductive substrate 32A is bonded to the insulating substrate 31A, a back surface 322 of the conductive substrate 32A faces a main surface 311 of the insulating substrate 31A. The conductive substrate 32A has a plurality of semiconductor elements 10 mounted on the main surface 321. Each semiconductor element 10 is bonded to the conductive substrate 32A via a conductive bonding material, and the back surface electrode 13 (drain electrode) of each semiconductor element 10 is electrically connected to the conductive substrate 32A. In this embodiment, the conductive substrate 32A is an example of a "first conductive member."

[0031] As shown in FIG. 10 and other figures, the conductive substrate 32B is bonded to the insulating substrate 31B via a bonding material (not shown). This bonding material may be either conductive or insulating. When the conductive substrate 32B is bonded to the insulating substrate 31B, the back surface 322 of the conductive substrate 32B faces the main surface 311 of the insulating substrate 31B. The conductive substrate 32B has a plurality of semiconductor elements 20 mounted on the main surface 321. Each semiconductor element 20 is bonded to the conductive substrate 32B via a conductive bonding material, and the back surface electrode 13 (drain electrode) of each semiconductor element 20 is electrically connected to the conductive substrate 32B. In this embodiment, the conductive substrate 32B is an example of a "second conductive member."

[0032] The pair of insulating layers 33A, 33B are electrically insulating and are made of, for example, glass epoxy resin. As shown in FIG. 5, the pair of insulating layers 33A, 33B are each strip-shaped extending in the y direction. As shown in FIGS. 5 and 10, the insulating layer 33A is bonded to the main surface 321 of the conductive substrate 32A. The insulating layer 33A is located further in the x2 direction than the plurality of semiconductor elements 10. As shown in FIGS. 5 and 10, the insulating layer 33B is bonded to the main surface 321 of the conductive substrate 32B. The insulating layer 33B is located further in the x1 direction than the plurality of semiconductor elements 20. The insulating layer 33A insulates the conductive substrate 32A from the gate layer 34A and the detection layer 35A, and the insulating layer 33B insulates the conductive substrate 32B from the gate layer 34B and the detection layer 35B.

[0033] The pair of gate layers 34A, 34B are conductive and are made of, for example, copper or a copper alloy. As shown in FIG. 5 and other figures, each of the pair of gate layers 34A, 34B includes a strip portion 341 and multiple hook portions 342. The strip portion 341 is strip-shaped in plan view and extends in the y direction. The multiple hook portions 342 protrude from the strip portion 341. Each of the gate layers 34A, 34B may be composed of only the strip portion 341 without the multiple hook portions 342. As shown in FIGS. 5 and 10, the gate layer 34A is disposed on the insulating layer 33A. Multiple gate wires 51 are bonded to the gate layer 34A, and the gate layer 34A is electrically connected to the control electrodes 12 (gate electrodes) of the semiconductor elements 10 via the gate wires 51. As shown in FIGS. 5 and 10, the gate layer 34B is disposed on the insulating layer 33B. The gate layer 34B is bonded to a plurality of gate wires 51, and is electrically connected to the control electrodes 22 (gate electrodes) of the semiconductor elements 20 via the gate wires 51.

[0034] The pair of detection layers 35A, 35B are conductive and made of, for example, copper or a copper alloy. As shown in FIG. 5, each of the pair of detection layers 35A, 35B includes a strip portion 351 and multiple hook portions 352. The strip portion 351 is strip-shaped in a plan view and extends in the y direction. Each of the multiple hook portions 352 protrudes from the strip portion 351. Each of the detection layers 35A, 35B may be composed only of the strip portion 351 without the multiple hook portions 352. As shown in FIGS. 5 and 10, the detection layer 35A is disposed on the insulating layer 33A together with the gate layer 34A. Multiple detection wires 52 are bonded to the detection layer 35A, and the detection layer 35A is electrically connected to the principal surface electrode 11 (source electrode) of each semiconductor element 10 via the detection wires 52. 5 and 10, the detection layer 35B is disposed on the insulating layer 33B together with the gate layer 34B. A plurality of detection wires 52 are joined to the detection layer 35B, and the detection layer 35B is electrically connected to the main surface electrode 21 (source electrode) of each semiconductor element 20 via the detection wires 52.

[0035] As shown in FIGS. 5 and 10 , the gate layer 34A and the detection layer 35A are aligned in the x direction on the insulating layer 33A and spaced apart from each other. In the example shown in FIGS. 5 and 10 , the gate layer 34A is positioned closer to the semiconductor elements 10 in the x direction than the detection layer 35A. That is, the gate layer 34A is located on the x1-direction side of the detection layer 35A. Note that the positions of the gate layer 34A and the detection layer 35A in the x direction may be reversed. Also, as shown in FIGS. 5 and 10 , the gate layer 34B and the detection layer 35B are aligned in the x direction on the insulating layer 33B and spaced apart from each other. In the example shown in FIGS. 5 and 10 , the gate layer 34B is positioned closer to the semiconductor elements 20 in the x direction than the detection layer 35B. That is, the gate layer 34B is located on the x2-direction side of the detection layer 35B. Note that the positions of the gate layer 34B and the detection layer 35B in the x direction may be reversed.

[0036] The configuration of the support substrate 30 is not limited to the above example. For example, two conductive substrates 32A, 32B may be bonded to a single insulating substrate. That is, the pair of insulating substrates 31A, 31B may be integrally formed without being divided. Furthermore, a metal layer may be formed on the rear surface 312 of each of the insulating substrates 31A, 31B to improve the bonding strength with the heat sink. Furthermore, the shape, size, and arrangement of the pair of insulating substrates 31A, 31B and the pair of conductive substrates 32A, 32B may be appropriately changed based on the number and arrangement of the multiple semiconductor elements 10, 20.

[0037] The multiple terminals are external terminals used when mounting the semiconductor device A1 on a circuit board of an electrical device or the like. As described above, the multiple terminals include two input terminals 41, 42, an output terminal 43, a pair of control terminals 44A, 44B, and a pair of detection terminals 45A, 45B. Each terminal is made of a metal plate. The metal plate is made of a material, for example, Cu or a Cu alloy. Each terminal is made of a material with lower electrical conductivity than each of the conductive substrates 32A, 32B. In other words, the electrical resistivity of each terminal is higher than the electrical resistivity of each of the conductive substrates 32A, 32B. The multiple terminals are formed, for example, from the same lead frame.

[0038] A power supply voltage is applied to the two input terminals 41 and 42. For example, the input terminal 41 is a positive terminal (P terminal) and the input terminal 42 is a negative terminal (N terminal). As shown in FIGS. 1 to 4, the two input terminals 41 and 42 are located closer to the x1 direction in the semiconductor device A1. The two input terminals 41 and 42 are spaced apart from each other.

[0039] As shown in FIG. 4 and other figures, the input terminal 41 includes a pad portion 411 and a terminal portion 412.

[0040] The pad portion 411 is covered with a resin member 60. As shown in FIGS. 2, 4, 5, and 10, the pad portion 411 is conductively joined to the conductive substrate 32B via a conductive block material 419. The constituent material of the block material 419 is not particularly limited, but examples thereof include Cu, a Cu alloy, a CuMo (copper molybdenum) composite, and a CIC (copper-inver-copper) composite. The pad portion 411 is joined to the block material 419, and the block material 419 is joined to the conductive substrate 32B. The joining of the pad portion 411 and the block material 419 and the joining of the block material 419 and the conductive substrate 32B may each be any of joining using a conductive bonding material, laser joining, ultrasonic joining, or the like. The bonding between the pad portion 411 and the conductive substrate 32B is not limited to a configuration via the block material 419, and the pad portion 411 may be partially bent so that the pad portion 411 is directly bonded to the conductive substrate 32B.

[0041] The terminal portion 412 is exposed from the resin member 60. As shown in FIG. 4 and other figures, the terminal portion 412 extends in the x1 direction from the resin member 60 in a plan view. The terminal portion 412 has, for example, a rectangular shape in a plan view. As shown in FIGS. 4 and 5, the terminal portion 412 is located in the y1 direction away from the center of the resin member 60 in the y direction. The terminal portion 412 is an example of a "second terminal portion."

[0042] 4 and other figures, input terminal 42 includes pad portion 421, terminal portion 422, and connecting portion 423. Pad portion 421, terminal portion 422, and connecting portion 423 are each plate-shaped and integrally formed.

[0043] The pad portion 421 is covered with a resin member 60. Because the pad portion 421 is covered with the resin member 60, the input terminal 42 is supported by the resin member 60. The pad portion 421 is conductively joined to the principal surface electrode 11 of each semiconductor element 10 via a conductive block material 429, as shown in FIGS. 5, 6, and 10. The material of the block material 429 is the same as the material of the block material 419, and may be, for example, Cu, a Cu alloy, a CuMo composite material, or a CIC composite material, but is not limited to these. The pad portion 421 is joined to the block material 429, and the block material 429 is joined to the principal surface electrode 11 of each semiconductor element 10. The pad portion 421 and the block material 429 may be joined using a conductive bonding material, laser bonding, or ultrasonic bonding. The block material 429 and the principal surface electrodes 11 of each semiconductor element 10 are joined using, for example, a conductive joining material (such as solder, metal paste, or sintered metal). The pad portion 421 is, for example, rectangular in plan view. In plan view, each edge of the pad portion 421 along the x direction overlaps each of the outer elements 10A, 20A. In plan view, the pad portion 421 straddles the conductive substrate 32A and the conductive substrate 32B. As shown in FIG. 4, in plan view, a portion of each of the multiple semiconductor elements 10 is exposed from the pad portion 421. In other words, in plan view, a portion of each semiconductor element 10 does not overlap the pad portion 421.

[0044] As shown in FIG. 4, the pad portion 421 is formed to include a closed region R1 in plan view. For ease of understanding, dots are drawn in the closed region R1 in FIG. 4. The closed region R1 is an area surrounded by three line segments L12, L23, and L31. The line segment L12 is a line segment connecting the first vertex P1 and the second vertex P2. The line segment L23 is a line segment connecting the second vertex P2 and the third vertex P3. The line segment L31 is a line segment connecting the third vertex P3 and the first vertex P1. In plan view, the first vertex P1, the second vertex P2, and the third vertex P3 are not on the same line.

[0045] As shown in FIG. 4, the first vertex P1 overlaps with the semiconductor element 10 (the outer element 10A on the y1 direction side) that is outermost in the y1 direction among the multiple semiconductor elements 10 in a planar view. The first vertex P1 overlaps, for example, with the center of the outer element 10A on the y1 direction side in a planar view. Note that, because the main surface electrodes 11 of each semiconductor element 10 are electrically connected to the pad portion 421 via each block 429, the first vertex P1 may also overlap with the center of the block 429 joined to the outer element 10A on the y1 direction side in a planar view. As shown in FIG. 4, the first vertex P1 overlaps with the conductive substrate 32A in a planar view.

[0046] As shown in FIG. 4, the second vertex P2 overlaps with the semiconductor element 10 (the outer element 10A on the y2 direction side) that is outermost in the y2 direction among the multiple semiconductor elements 10 in a planar view. The second vertex P2 overlaps, for example, with the center of the outer element 10A on the y2 direction side in a planar view. Note that, because the main surface electrodes 11 of each semiconductor element 10 are electrically connected to the pad portion 421 via each block 429, the second vertex P2 may overlap with the center of the block 429 joined to the outer element 10A on the y2 direction side in a planar view. As shown in FIG. 4, the second vertex P2 overlaps with the conductive substrate 32A in a planar view.

[0047] As shown in Fig. 4, the third vertex P3 is located on the perpendicular bisector L0 of the line segment L12 in a plan view. Also, as shown in Fig. 4, the third vertex P3 is located on the contact edge 421a of the pad portion 421 in a plan view. The contact edge 421a is a portion (side) of the pad portion 421 that is in contact with the connecting portion 423 (a first portion 424 described below) in a plan view. As shown in Fig. 4, the third vertex P3 overlaps the conductive substrate 32B in a plan view.

[0048] The terminal portion 422 is exposed from the resin member 60. As shown in FIG. 4 and other figures, the terminal portion 422 extends in the x1 direction from the resin member 60 in a plan view. The terminal portion 422 has, for example, a rectangular shape in a plan view. The terminal portion 422 is aligned with the terminal portion 412 in the y direction and overlaps with the terminal portion 412 when viewed in the y direction. In the present embodiment, as shown in FIGS. 1 to 5 and other figures, the terminal portion 422 is positioned further in the y2 direction than the terminal portion 412. As shown in FIGS. 4 and 5 and other figures, the terminal portion 422 is positioned further in the y2 direction than the center of the resin member 60 in the y direction. The terminal portion 422 is an example of a "first terminal portion."

[0049] The connecting portion 423 connects the pad portion 421 and the terminal portion 422. The connecting portion 423 is partially bent. The connecting portion 423 includes a first portion 424, a second portion 425, and a third portion 426.

[0050] The first portion 424 contacts the pad portion 421 (contact edge 421a). The first portion 424 is rectangular in plan view, and in the example shown in FIG. 4, is strip-shaped extending in the x direction. The first portion 424 extends in the x direction from a central portion in the y direction of the edge of the pad portion 421 on the x1 direction side. The dimension of the first portion 424 in the y direction is smaller than that of the pad portion 421. As shown in FIG. 4, the first portion 424 overlaps the perpendicular bisector L0 in plan view. The first portion 424 has a pair of edges 424a. Each of the pair of edges 424a is connected to the pad portion 421 and extends from the pad portion 421 in the x1 direction. The pair of edges 424a is located on each of the two inner elements 10B when viewed in the x direction. When the number of inner elements 10B is one, each of the pair of edges 424a is located on that one inner element 10B when viewed in the x direction.

[0051] The second portion 425 is connected to the first portion 424 and the third portion 426. The second portion 425 extends in the y direction from the end portion of the edge 424a of the first portion 424 on the y2 direction side, on the x1 direction side. The second portion 425 is strip-shaped in a plan view. Note that, in order to suppress misalignment of the input terminal 42, an insulating block material may be sandwiched between the second portion 425 and the conductive substrate 32B.

[0052] The third portion 426 is connected to the second portion 425 and the terminal portion 422. The third portion 426 extends in the x direction from a portion of the x1-direction edge of the second portion 425 on the y2-direction side. The dimension of the third portion 426 in the y direction is approximately the same as the dimension of the terminal portion 422 in the y direction.

[0053] The output terminal 43 is a terminal that outputs AC power (voltage) or DC power (voltage) converted by the multiple semiconductor elements 10, 20. As shown in FIGS. 1 to 4, the output terminal 43 is located closer to the x2 direction in the semiconductor device A1. The output terminal 43 includes a pad portion 431 and a terminal portion 432.

[0054] The pad portion 431 is covered with a resin member 60. As shown in FIGS. 2, 4, 5, and 10, the pad portion 431 is conductively bonded to the conductive substrate 32A via a conductive block 439. The material of the block 439 may be, similar to the material of the blocks 419 and 429, for example, Cu, a Cu alloy, a CuMo composite, or a CIC composite, but is not limited to these. The pad portion 431 is bonded to the block 439, which is in turn bonded to the conductive substrate 32A. The bonding between the pad portion 431 and the block 439 and the bonding between the block 439 and the conductive substrate 32A may each be bonded using a conductive bonding material, laser bonding, ultrasonic bonding, or the like. The bonding between the pad portion 431 and the conductive substrate 32A is not limited to the configuration via the block 439. The pad portion 431 may be directly bonded to the conductive substrate 32A by partially bending the pad portion 431.

[0055] The terminal portion 432 is exposed from the resin member 60. As shown in Fig. 4, the terminal portion 432 extends in the x2 direction from the resin member 60. The terminal portion 432 has, for example, a rectangular shape in a plan view. The terminal portion 432 is an example of a "third terminal portion."

[0056] The pair of control terminals 44A, 44B and the pair of detection terminals 45A, 45B are arranged, for example, along the x direction. The pair of control terminals 44A, 44B and the pair of detection terminals 45A, 45B have substantially the same shape. The pair of control terminals 44A, 44B and the pair of detection terminals 45A, 45B each form an L shape when viewed in the x direction. As shown in FIG. 9 , the pair of control terminals 44A, 44B and the pair of detection terminals 45A, 45B overlap each other when viewed in the x direction. As shown in FIGS. 5 and 6 , the control terminal 44A and the detection terminal 45A are located adjacent to the conductive substrate 32A in the y direction in a plan view, and the control terminal 44B and the detection terminal 45B are located adjacent to the conductive substrate 32B in the y direction in a plan view, as shown in FIGS. 5 and 6 . The pair of control terminals 44A, 44B and the pair of detection terminals 45A, 45B each protrude from, for example, a surface of the resin member 60 facing the y1 direction (a resin side surface 633 described below).

[0057] As shown in Figures 5 and 6, the pair of control terminals 44A, 44B are each electrically connected to the pair of gate layers 34A, 34B via first connecting wires 53. A first drive signal (gate voltage) for driving the plurality of semiconductor elements 10 is input to the control terminal 44A. Therefore, the control terminal 44A is a terminal for inputting the first drive signal, and a second drive signal (gate voltage) for driving the plurality of semiconductor elements 20 is input to the control terminal 44B. Therefore, the control terminal 44B is a terminal for inputting the second drive signal.

[0058] 6, each of the pair of control terminals 44A, 44B includes a pad portion 441 and a terminal portion 442. In each of the control terminals 44, 44B, the pad portion 441 is covered with a resin member 60. With this configuration, each of the control terminals 44A, 44B is supported by the resin member 60. The terminal portion 442 is connected to the pad portion 441 and is exposed from the resin member 60. Each of the control terminals 44A, 44B is bent at the terminal portion 442.

[0059] As shown in FIGS. 5 and 6 , the pair of detection terminals 45A, 45B are electrically connected to the pair of detection layers 35A, 35B via second connection wires 54. The detection terminal 45A detects the voltage (voltage corresponding to the source current) applied to each of the principal surface electrodes 11 of the plurality of semiconductor elements 10. Thus, the detection terminal 45A serves as a source signal detection terminal for the plurality of semiconductor elements 10. The detection terminal 45B detects the voltage (voltage corresponding to the source current) applied to each of the principal surface electrodes 21 of the plurality of semiconductor elements 20. Thus, the detection terminal 45B serves as a source signal detection terminal for the plurality of semiconductor elements 20.

[0060] 6, each of the pair of detection terminals 45A, 45B includes a pad portion 451 and a terminal portion 452. In each of the detection terminals 45A, 45B, the pad portion 451 is covered with a resin member 60. With this configuration, each of the detection terminals 45A, 45B is supported by the resin member 60. The terminal portion 452 is connected to the pad portion 451 and is exposed from the resin member 60. Each of the detection terminals 45A, 45B is bent at the terminal portion 452.

[0061] Each of the plurality of connection members provides electrical continuity between two members spaced apart from each other. As described above, the plurality of connection members include the plurality of gate wires 51, the plurality of detection wires 52, the pair of first connection wires 53, the pair of second connection wires 54, and the plurality of lead plates 55.

[0062] The plurality of gate wires 51, the plurality of detection wires 52, the pair of first connecting wires 53, and the pair of second connecting wires 54 are each so-called bonding wires. The constituent materials of the plurality of gate wires 51, the plurality of detection wires 52, the pair of first connecting wires 53, and the pair of second connecting wires 54 are, for example, Al, Au, Cu, or alloys thereof. The plurality of lead plates 55 are each a conductive plate-like member. The constituent materials of the plurality of lead plates 55 may be, for example, Cu, a Cu alloy, a CuMo composite, or a CIC composite, but are not limited to these.

[0063] 5 and 6, one end of each of the plurality of gate wires 51 is joined to either the control electrode 12 of each semiconductor element 10 or the control electrode 22 of each semiconductor element 20, and the other end is joined to either of the pair of gate layers 34A, 34B. As shown in Fig. 5, the other end of each gate wire 51 is joined to an appropriate hook portion 342. The plurality of gate wires 51 include those that connect the control electrode 12 of each semiconductor element 10 to the gate layer 34A and those that connect the control electrode 22 of each semiconductor element 20 to the gate layer 34B.

[0064] 5 and 6, one end of each of the plurality of detection wires 52 is joined to either the principal surface electrode 11 of each semiconductor element 10 or the principal surface electrode 21 of each semiconductor element 20, and the other end is joined to either of the pair of detection layers 35A, 35B. As shown in Fig. 5, the other end of each detection wire 52 is joined to an appropriate hook portion 352. The plurality of detection wires 52 include those that connect the principal surface electrode 11 of each semiconductor element 10 to the detection layer 35A and those that connect the principal surface electrode 21 of each semiconductor element 20 to the detection layer 35B.

[0065] As shown in FIGS. 5 and 6, one of the pair of first connecting wires 53 has one end joined to the gate layer 34A and the other end joined to the control terminal 44A. This provides electrical continuity between the gate layer 34A and the control terminal 44A via the first connecting wire 53. As shown in FIGS. 5 and 6, the other of the pair of first connecting wires 53 has one end joined to the gate layer 34B and the other end joined to the control terminal 44B. This provides electrical continuity between the gate layer 34B and the control terminal 44B via the first connecting wire 53. Each second connecting wire 54 is joined to a side of the strip-shaped portion 351 of each detection layer 35A, 35B that is closer to the detection terminals 45A, 45B in the y direction.

[0066] As shown in FIGS. 5 and 6, one of the pair of second connecting wires 54 has one end joined to the detection layer 35A and the other end joined to the detection terminal 45A. This establishes electrical continuity between the detection layer 35A and the detection terminal 45A via the second connecting wire 54. As shown in FIGS. 5 and 6, the other of the pair of detection wires 52 has one end joined to the detection layer 35B and the other end joined to the detection terminal 45B. This establishes electrical continuity between the detection layer 35B and the detection terminal 45B via the second connecting wire 54. Each second connecting wire 54 is joined to a side of the strip-shaped portion 351 of each detection layer 35A, 35B that is closer to the detection terminal 45A, 45B in the y direction.

[0067] 5, 6 and 10, the plurality of lead plates 55 electrically connect the main surface electrodes 21 of the semiconductor elements 20 to the conductive substrate 32A. Each lead plate 55 includes a pair of joints 551, 552.

[0068] In each lead plate 55, a joint 551 is joined to the main surface electrode 21 of each semiconductor element 20 by a conductive bonding material (not shown, for example, solder, metal paste, or sintered metal). A joint 552 is joined to the conductive substrate 32A via a conductive block 559. The block 559 may be made of, for example, Cu, a Cu alloy, a CuMo composite, or a CIC composite, but is not limited to these. The joint 552 is joined to the block 559, and the block 559 is joined to the conductive substrate 32A. The bonding between the joint 552 and the block 559 and the bonding between the block 559 and the conductive substrate 32A may each be performed by bonding using a conductive bonding material, laser bonding, ultrasonic bonding, or the like. The joining of the joint 552 and the conductive substrate 32A is not limited to a configuration via the block material 559, but the joint 552 may be directly joined to the conductive substrate 32A by partially bending the joint 552 or by forming the joint 552 thicker than the joint 551.

[0069] As shown in FIGS. 1 and 3 to 10, the resin member 60 covers the semiconductor elements 10 and 20, the support substrate 30 (excluding the back surfaces 312 of the pair of insulating substrates 31A and 31B), a portion of each of the terminals (the two input terminals 41 and 42, the output terminal 43, the pair of control terminals 44A and 44B, and the pair of detection terminals 45A and 45B), and the connection members (the gate wires 51, the detection wires 52, the pair of first connection wires 53, the pair of second connection wires 54, and the lead plates 55). The resin member 60 is made of, for example, epoxy resin. As shown in FIGS. 4, 5, and 10, the resin member 60 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0070] As shown in FIG. 10 and other figures, the resin main surface 61 and the resin back surface 62 are spaced apart in the z direction. The resin main surface 61 faces the z2 direction, and the resin back surface 62 faces the z1 direction. As shown in FIG. 8, the resin back surface 62 has a frame shape surrounding each back surface 312 of the pair of insulating substrates 31A and 31B in a plan view. Each back surface 312 of the pair of insulating substrates 31A and 31B is exposed from the resin back surface 62. Each of the multiple resin side surfaces 631 to 634 is connected to both the resin main surface 61 and the resin back surface 62 and is sandwiched between them in the z direction. As shown in FIGS. 3 to 5, 7, and 8, the resin side surface 631 and the resin side surface 632 are spaced apart in the x direction. The resin side surface 631 faces the x1 direction, and the resin side surface 632 faces the x2 direction. Two input terminals 41 and 42 protrude from resin side surface 631, and output terminal 43 protrudes from resin side surface 632. As shown in FIGS. 3 to 5, 8, and 9, resin side surface 633 and resin side surface 634 are spaced apart in the y direction. Resin side surface 633 faces the y1 direction, and resin side surface 634 faces the y2 direction. A pair of control terminals 44A and 44B and a pair of detection terminals 45A and 45B protrude from resin side surface 633.

[0071] 8 and 10, the resin member 60 includes a recess 65 recessed in the z direction from the resin rear surface 62. In plan view, the recess 65 is formed in a ring shape surrounding the support substrate 30, as shown in Fig. 8. Note that the shape, arrangement, number, etc. of the recess 65 are not limited to the examples shown in Figs. 8 and 10. Furthermore, the resin member 60 does not necessarily have to have the recess 65 formed therein.

[0072] The functions and effects of the semiconductor device A1 are as follows.

[0073] The semiconductor device A1 includes a pad portion 421 (input terminal 42) electrically connected to multiple semiconductor elements 10. The pad portion 421 is formed to include a closed region R1 surrounded by three line segments L12, L23, and L31. The line segment L12 connects the first vertex P1 and the second vertex P2, the line segment L23 connects the second vertex P2 and the third vertex P3, and the line segment L31 connects the third vertex P3 and the first vertex P1. In a planar view, the first vertex P1 overlaps the outermost semiconductor element 10 in the y1 direction (the outer element 10A on the y1 direction side) among the multiple semiconductor elements 10. In a planar view, the second vertex P2 overlaps the outermost semiconductor element 10 in the y2 direction (the outer element 10A on the y2 direction side) among the multiple semiconductor elements 10. In a planar view, the third vertex P3 is located on the perpendicular bisector L0 of the line segment L12. This configuration ensures a current path from each semiconductor element 10 to the third vertex P3 in the pad portion 421. Because there is almost no difference between the distance to the first vertex P1 and the distance to the second vertex P2 of a point on the perpendicular bisector L0, there is almost no difference between the distance from the third vertex P3 to the first vertex P1 and the distance from the third vertex P3 to the second vertex P2. In other words, the path difference between the current paths from each semiconductor element 10 to the third vertex P3 in the pad portion 421 is reduced. Therefore, in the semiconductor device A1, by ensuring a current path that passes through the third vertex P3 for the current from each semiconductor element 10 to the terminal portion 422 via the pad portion 421, it is possible to reduce bias in the current flowing through the multiple semiconductor elements 10 connected in parallel.

[0074] In the semiconductor device A1, the input terminal 42 includes a connecting portion 423 connecting the pad portion 421 and the terminal portion 422. The connecting portion 423 includes a first portion 424 that contacts the pad portion 421, and the first portion 424 overlaps the perpendicular bisector L0 in a plan view. With this configuration, when a current flows from the pad portion 421 to the connecting portion 423, the current first passes through the first portion 424. If the first portion 424 does not overlap the perpendicular bisector L0 in a plan view, the current path from each semiconductor element 10 to the terminal portion 422 may not pass through the third vertex P3. On the other hand, in the semiconductor device A1, by overlapping the first portion 424 with the perpendicular bisector L0 in a plan view, the current path from each semiconductor element 10 to the terminal portion 422 can pass through the third vertex P3. Therefore, by ensuring a current path that passes through the third vertex P3, the semiconductor device A1 can suppress bias in the current flowing through the multiple semiconductor elements 10 connected in parallel.

[0075] In particular, in the semiconductor device A1, the dimension of the first portion 424 in the y direction is smaller than the dimension of the pad portion 421 in the y direction. With this configuration, the current flowing through the pad portion 421 is concentrated in the first portion 424 when input to the first portion 424. Therefore, in the current path from each semiconductor element 10 to the terminal portion 422, the number of paths that do not pass through the third vertex P3 can be reduced. Furthermore, the pair of edges 424a of the first portion 424 are located on the two inner elements 10B, respectively, when viewed in the x direction. With this configuration, the contact area between the first portion 424 (connecting portion 423) and the pad portion 421 is limited to a narrower area, so that the number of paths that do not pass through the third vertex P3 can be further reduced in the current path from each semiconductor element 10 to the terminal portion 422.

[0076] In the semiconductor device A1, the gate layer 34A includes a strip portion 341 and multiple hook portions 342. One end of each gate wire 51 is bonded to a corresponding semiconductor element 10, and the other end is appropriately bonded to each hook portion 342. This configuration allows the lengths of the signal paths of the first drive signal for driving the multiple semiconductor elements 10 connected in parallel to be uniform. If the signal paths of the first drive signal are uneven, the semiconductor element with the shortest signal path will be driven first. This can cause uneven driving states among the multiple semiconductor elements 10 connected in parallel, potentially resulting in overvoltage or overcurrent in one of the semiconductor elements 10. Therefore, in the semiconductor device A1, by uniforming the signal path lengths of the first drive signal input to each semiconductor element 10, the driving states of each semiconductor element 10 can be more uniform than when each gate layer 34A does not have multiple hook portions 342. The same applies to the relationship between the gate layer 34B and each semiconductor element 20.

[0077] Fig. 11 shows a semiconductor device A2 according to the second embodiment. Fig. 11 is a plan view showing the semiconductor device A2, and shows the resin member 60 by imaginary lines.

[0078] The semiconductor device A2 differs from the semiconductor device A1 in the planar shape of the pad portion 421 of the input terminal 42. Except for this, the semiconductor device A2 is configured similarly to the semiconductor device A1.

[0079] The pad portion 421 of the semiconductor device A2 is formed in a substantially triangular shape in a plan view. As shown in Fig. 11, the triangular pad portion 421 is also formed to include a closed region R1. For ease of understanding, the closed region R1 is depicted by dots in Fig. 11. In the example shown in Fig. 11, the pad portion 421 is formed along the closed region R1 in a plan view.

[0080] In the semiconductor device A2, as in the semiconductor device A1, the pad portion 421 is formed to include the closed region R1. Therefore, in the semiconductor device A2, as in the semiconductor device A1, a current path passing through the third vertex P3 is ensured for the current from each semiconductor element 10 to the terminal portion 422 via the pad portion 421, thereby making it possible to suppress bias in the current flowing through the multiple semiconductor elements 10 connected in parallel.

[0081] In the semiconductor device A2, in a plan view, substantially the entire pad portion 421 is the closed region R1. With this configuration, current flowing to portions other than the closed region R1 in the pad portion 421 is suppressed. Therefore, the semiconductor device A2 can suppress the flow of unnecessary current in the pad portion 421.

[0082] 12 to 14 show a semiconductor device A3 according to a third embodiment. FIG. 12 is a plan view of the semiconductor device A3, showing the resin member 60, two input terminals 41 and 42, and an output terminal 43 in phantom lines. FIG. 13 is a diagram of a main portion extracted from the plan view shown in FIG. 12. In FIG. 13, the plan view shown in FIG. 12 mainly includes the semiconductor elements 10 and 20, a portion of the support substrate 30 (a pair of insulating substrates 31A and 31B, a pair of conductive substrates 32A and 32B), and a plurality of lead plates 55, but omits the pair of insulating layers 33A and 33B, the pair of gate layers 34A and 34B, the pair of detection layers 35A and 35B, the plurality of gate wires 51, the plurality of detection wires 52, the pair of first connection wires 53, and the pair of second connection wires 54. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12.

[0083] 12 to 14, the semiconductor device A3 is different from the semiconductor device A1 in the configuration of the conductive substrate 32B. Except for this, the semiconductor device A3 is configured similarly to the semiconductor device A1.

[0084] The conductive substrate 32B of the semiconductor device A3 has, in plan view, a pair of edges extending along the x direction, each of which has a recessed portion inward in the y direction. The conductive substrate 32B includes a pad portion 320a and a connecting portion 320b.

[0085] The pad portion 320a is a portion on which a plurality of semiconductor elements 20 are mounted. The pad portion 320a is rectangular in plan view. As shown in FIG. 13, the pad portion 320a is formed to include a closed region R2 in plan view. For ease of understanding, the closed region R2 is depicted by dots in FIG. 13. The closed region R2 is an area surrounded by three line segments L45, L56, and L64. The line segment L45 is a line segment connecting the first vertex P4 and the second vertex P5. The line segment L56 is a line segment connecting the second vertex P5 and the third vertex P6. The line segment L64 is a line segment connecting the third vertex P6 and the first vertex P4. In plan view, the first vertex P4, the second vertex P5, and the third vertex P6 are not on the same line.

[0086] In a plan view, the first vertex P4 overlaps with the semiconductor element 20 (the outer element 20A on the y1 direction side) that is outermost in the y1 direction among the multiple semiconductor elements 20. For example, the first vertex P4 overlaps with the center of the outer element 20A on the y1 direction side in a plan view. In this embodiment, the back surface electrode 23 of the semiconductor element 20 is formed over substantially the entire area of the element back surface 20b of the semiconductor element 20, and therefore the first vertex P4 overlaps with the center of the back surface electrode 23 of the outer element 20A on the y1 direction side in a plan view.

[0087] In a plan view, the second vertex P5 overlaps with the semiconductor element 20 (the outer element 20A on the y2 direction side) that is outermost in the y2 direction among the multiple semiconductor elements 20. For example, the second vertex P5 overlaps with the center of the outer element 20A on the y2 direction side in a plan view. In this embodiment, the back surface electrode 23 of the semiconductor element 20 is formed over substantially the entire area of the element back surface 20b of the semiconductor element 20, and therefore the second vertex P5 overlaps with the center of the back surface electrode 23 of the outer element 20A on the y2 direction side in a plan view.

[0088] As shown in Fig. 13, the third vertex P6 is located on the perpendicular bisector L9 of the line segment L45 in a plan view. Also, as shown in Fig. 13, the third vertex P6 is located on the contact edge 320z of the pad portion 320a in a plan view. The contact edge 320z is a portion (side) of the pad portion 320a that contacts the connecting portion 320b (a first portion 320c described below) in a plan view.

[0089] The connecting portion 320b connects the pad portion 320a and the input terminal 41. As shown in Figures 12 and 13, the input terminal 41 is joined to the connecting portion 320b via a block member 419, and thus the connecting portion 320b connects the pad portion 320a and the terminal portion 412 (input terminal 41). As shown in Figure 13, the connecting portion 320b includes a first portion 320c and a second portion 320d.

[0090] The first portion 320c is in contact with the pad portion 320a. The first portion 320c is rectangular in plan view. The first portion 320c extends in the x direction from the center in the y direction of the edge of the pad portion 320a on the x1 direction side. The first portion 320c is smaller in the y direction than the pad portion 320a. As shown in FIG. 13, the first portion 320c overlaps with the perpendicular bisector L9 in plan view. The first portion 320c causes the conductive substrate 32B to be recessed as described above.

[0091] A block material 419 is joined to the second portion 320d. The second portion 320d is connected to the first portion 320c and to the input terminal 41 via the block material 419. The second portion 320d has a rectangular shape in a plan view. The y-direction dimension of the second portion 320d is larger than the y-direction dimension of the first portion 320c and is, for example, approximately the same as the y-direction dimension of the pad portion 320a.

[0092] In the conductive substrate 32B, the y-direction dimension of the first portion 320c is smaller than the y-direction dimensions of the pad portion 320a and the second portion 320d, and therefore, as described above, a portion recessed inward in the y-direction is formed.

[0093] In the semiconductor device A3, similarly to the semiconductor devices A1 and A2, the pad portion 421 is formed to include the closed region R1. Therefore, similarly to the semiconductor devices A1 and A2, the semiconductor device A3 ensures a current path passing through the third vertex P3 for current flowing from each semiconductor element 10 to the terminal portion 422 via the pad portion 421, thereby making it possible to suppress bias in the current flowing through the multiple semiconductor elements 10 connected in parallel.

[0094] In the semiconductor device A3, the conductive substrate 32B includes a pad portion 320a. The pad portion 320a is formed to include a closed region R2 surrounded by three line segments L45, L56, and L64. The line segment L45 connects the first vertex P4 and the second vertex P5, the line segment L56 connects the second vertex P5 and the third vertex P6, and the line segment L64 connects the third vertex P6 and the first vertex P4. In a planar view, the first vertex P4 overlaps the semiconductor element 20 that is located furthest in the y1 direction among the multiple semiconductor elements 20. In a planar view, the second vertex P5 overlaps the semiconductor element 20 that is located furthest in the y2 direction among the semiconductor elements 20. The third vertex P6 is located on the perpendicular bisector L9 of the line segment L45. With this configuration, a current path can be secured in the pad portion 320a, for example, from each semiconductor element 20 to the third vertex P6. Therefore, the semiconductor device A3 can suppress bias in the current flowing through multiple semiconductor elements 20 connected in parallel by ensuring a current path that passes through the third vertex P6 for the current that flows from each semiconductor element 20 to the terminal portion 412 via the pad portion 320a.

[0095] In the semiconductor device A3, the conductive substrate 32B includes a connecting portion 320b connecting the pad portion 320a and the terminal portion 412 (input terminal 41). The connecting portion 320b includes a first portion 320c that contacts the pad portion 320a, and the first portion 320c overlaps the perpendicular bisector L9 in a plan view. With this configuration, when a current flows from the pad portion 320a to the connecting portion 320b, the current first passes through the first portion 320c. If the first portion 320c does not overlap the perpendicular bisector L9 in a plan view, the current path from each semiconductor element 20 to the terminal portion 412 may not pass through the third vertex P6. On the other hand, in the semiconductor device A3, by overlapping the first portion 320c with the perpendicular bisector L9 in a plan view, the current path from each semiconductor element 20 to the terminal portion 412 can pass through the third vertex P6. Therefore, by ensuring a current path that passes through the third vertex P6, the semiconductor device A3 can suppress bias in the current flowing through the multiple semiconductor elements 20 connected in parallel. This configuration is effective when the electrical resistivity of the conductive substrate 32B is equal to or higher than the electrical resistivity of the input terminal 42.

[0096] In particular, in the semiconductor device A3, the y-direction dimension of the first portion 320c is smaller than the y-direction dimension of the pad portion 320a. With this configuration, the current flowing through the pad portion 320a is concentrated in the first portion 320c when input to the first portion 320c. This reduces the number of paths that do not pass through the third vertex P6 in the current paths from each semiconductor element 20 to the terminal portion 412. Furthermore, a pair of edges of the first portion 320c are located on the two inner elements 20B, respectively, when viewed in the x-direction. With this configuration, the contact area between the first portion 320c (the connecting portion 320b) and the pad portion 320a is limited to a narrower area, further reducing the number of paths that do not pass through the third vertex P6 in the current paths from each semiconductor element 20 to the terminal portion 412.

[0097] 15 and 16 show a semiconductor device A4 according to the fourth embodiment. Fig. 15 is a plan view showing the semiconductor device A4, with the resin member 60 indicated by imaginary lines. For ease of understanding, the closed region R1 is depicted by dots in Fig. 15. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 15.

[0098] 15, the semiconductor device A4 is different from the semiconductor device A1 in the configuration of the support substrate 30. Except for this, the semiconductor device A4 is configured similarly to the semiconductor device A1.

[0099] The support substrate 30 of the semiconductor device A4 is a so-called DBC (Direct Bonded Copper) substrate. This support substrate 30 may be a DBA (Direct Bonded Aluminum) substrate instead of a DBC substrate. As shown in FIG. 15 , the support substrate 30 of the semiconductor device A4 includes an insulating substrate 36, a pair of main surface metal layers 37A and 37B, and a back surface metal layer 38.

[0100] Like the insulating substrates 31A and 31B, the insulating substrate 36 is made of, for example, ceramics with excellent thermal conductivity. The insulating substrate 36 has, for example, a rectangular shape in a plan view. As shown in FIG. 15, the insulating substrate 36 has a main surface 361 and a back surface 362. The main surface 361 and the back surface 362 are spaced apart in the z direction. The main surface 361 faces the z2 direction, and the back surface 362 faces the z1 direction.

[0101] As shown in FIG. 15 , the pair of main surface metal layers 37A, 37B are formed on the main surface 361 of the insulating substrate 36. In a configuration in which the support substrate 30 is a DBC substrate, the constituent material of the pair of main surface metal layers 37A, 37B is, for example, Cu. In a configuration in which the support substrate 30 is a DBA substrate, the constituent material is Al instead of Cu. The pair of main surface metal layers 37A, 37B are spaced apart in the x direction. The main surface metal layer 37A is located on the x2 direction side of the main surface metal layer 37B. Similar to the conductive substrate 32A, multiple semiconductor elements 10 are mounted on the main surface metal layer 37A. Similar to the conductive substrate 32B, multiple semiconductor elements 20 are mounted on the main surface metal layer 37B. Each of the main surface metal layers 37A, 37B is thinner than each of the conductive substrates 32A, 32B. In this embodiment, the main surface metal layer 37A is an example of a "first conductive member," and the main surface metal layer 37B is an example of a "second conductive member."

[0102] The back surface metal layer 38 is formed on the back surface 362 of the insulating substrate 36. The constituent material of the back surface metal layer 38 is the same as that of each of the main surface metal layers 37A, 37B. The back surface metal layer 38 may be covered with the resin member 60, or the surface facing the z1 direction may be exposed from the resin member 60 (resin back surface 62).

[0103] The configuration of the support substrate 30 of the semiconductor device A4 can be modified as follows. For example, instead of a single insulating substrate 36, the support substrate 30 may be divided into a pair of main surface metal layers 37A, 37B. That is, as with the semiconductor device A1, the support substrate 30 may be divided into two insulating substrates, each having a pair of main surface metal layers 37A, 37B formed thereon. Also, for example, instead of a single back surface metal layer 38, the support substrate 30 may be divided into two back surface metal layers. In this case, the two back surface metal layers are spaced apart in the x direction and overlap the pair of main surface metal layers 37A, 37B, respectively, in a plan view. Also, for example, the pair of conductive substrates 32A, 32B described above may be mounted on the pair of main surface metal layers 37A, 37B, respectively.

[0104] In the semiconductor device A4, as in each of the semiconductor devices A1 to A3, the pad portion 421 is formed to include the closed region R1. Therefore, in the semiconductor device A4, as in each of the semiconductor devices A1 to A3, a current path passing through the third vertex P3 is ensured for the current from each semiconductor element 10 to the terminal portion 422 via the pad portion 421, thereby making it possible to suppress bias in the current flowing through the multiple semiconductor elements 10 connected in parallel.

[0105] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the semiconductor device according to the present disclosure includes the following embodiments. Appendix 1. a plurality of first semiconductor elements each having a first element main surface and a first element back surface spaced apart in a thickness direction and electrically connected in parallel to one another; a pad portion electrically connected to the plurality of first semiconductor elements; a first terminal portion electrically connected to the pad portion; It is equipped with the plurality of first semiconductor elements are arranged along a first direction perpendicular to the thickness direction when viewed in the thickness direction, the pad portion is formed to include a closed area surrounded by three line segments formed by connecting two first vertices, two second vertices, and two third vertices that are not on the same line, the first vertex overlaps with an outermost first semiconductor element on one side in the first direction among the plurality of first semiconductor elements as viewed in the thickness direction, the second vertex overlaps with an outermost first semiconductor element on the other side of the first direction among the plurality of first semiconductor elements as viewed in the thickness direction, The semiconductor device, wherein the third vertex is located on the perpendicular bisector of the line segment connecting the first vertex and the second vertex when viewed in the thickness direction. Appendix 2. a connecting portion that connects the pad portion and the first terminal portion, the connecting portion includes a first portion that contacts the pad portion, 2. The semiconductor device according to claim 1, wherein the first portion overlaps the perpendicular bisector when viewed in the thickness direction. Appendix 3. the first portion has a pair of edges spaced apart from each other in the first direction and each extending along the thickness direction and a second direction perpendicular to the first direction; 3. The semiconductor device according to claim 2, wherein each of the pair of edges is connected to the pad portion when viewed in the thickness direction. Appendix 4. the pad portion and the first portion each have a rectangular shape when viewed in the thickness direction, 4. The semiconductor device according to claim 3, wherein the first portion has a smaller dimension in the first direction than the pad portion. Appendix 5. the plurality of first semiconductor elements include two inner elements that are located between a first semiconductor element that overlaps the first vertex when viewed in the thickness direction and a first semiconductor element that overlaps the second vertex when viewed in the thickness direction and that are adjacent to each other across the perpendicular bisector, 5. The semiconductor device according to claim 3, wherein each of the pair of edges is located above the two inner elements when viewed in the second direction. Appendix 6. 6. The semiconductor device according to claim 3, wherein each of the plurality of first semiconductor elements has a portion that does not overlap with the pad portion when viewed in the thickness direction. Appendix 7. each of the plurality of first semiconductor elements includes a first main surface electrode formed on a main surface of the first element and a first back surface electrode formed on a back surface of the first element; 7. The semiconductor device according to claim 3, wherein the pad portion is located on the first element main surface in the thickness direction and is electrically connected to the first main surface electrodes of each of the plurality of first semiconductor elements. Appendix 8. a first conductive member on which the plurality of first semiconductor elements are mounted; 8. The semiconductor device according to claim 7, wherein each of the plurality of first semiconductor elements has the first back surface electrode joined to the first conductive member. Appendix 9. 9. The semiconductor device according to claim 8, wherein the pad portion, the first terminal portion, and the connecting portion are each plate-shaped and integrally formed. Appendix 10. further comprising a plurality of second semiconductor elements each having a second element main surface and a second element back surface spaced apart in the thickness direction and electrically connected in parallel to one another; 10. The semiconductor device according to claim 9, wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements are electrically connected in series. Appendix 11. a second conductive member on which the plurality of second semiconductor elements are mounted; 11. The semiconductor device according to claim 10, wherein the first conductive member and the second conductive member are arranged side by side and spaced apart in the second direction. Appendix 12. The semiconductor device described in Appendix 11, wherein each of the plurality of second semiconductor elements includes a second main surface electrode formed on a main surface of the second element and a second back surface electrode formed on a back surface of the second element. Appendix 13. 13. The semiconductor device according to claim 12, wherein each of the plurality of second semiconductor elements has the second back surface electrode joined to the second conductive member. Appendix 14. 14. The semiconductor device according to claim 13, further comprising a plurality of connecting members that electrically connect the first conductive member to the second main surface electrodes of each of the plurality of second semiconductor elements. Appendix 15. a second terminal portion electrically connected to the second conductive member; 15. The semiconductor device according to claim 14, further comprising: a third terminal portion electrically connected to the first conductive member. Appendix 16. 16. The semiconductor device according to claim 15, wherein the pad portion straddles the first conductive member and the second conductive member when viewed in the thickness direction. Appendix 17. the first vertex and the second vertex overlap the first conductive member when viewed in the thickness direction, 17. The semiconductor device according to claim 16, wherein the third vertex overlaps the second conductive member when viewed in the thickness direction. Appendix 18. 18. The semiconductor device of claim 16, wherein the second terminal portion is aligned with the first terminal portion in the first direction and overlaps the first terminal portion when viewed in the first direction. Appendix 19. a resin member that covers the plurality of first semiconductor elements and the plurality of second semiconductor elements; 19. The semiconductor device according to claim 15, wherein the first terminal portion, the second terminal portion, and the third terminal portion are exposed from the resin member. Appendix 20. each of the plurality of first semiconductor elements further includes a first control electrode insulated from the first main surface electrode and formed on the first element main surface, and the first main surface electrode and the first back surface electrode are electrically connected in response to a first drive signal input to the first control electrode; 19. The semiconductor device according to claim 12, wherein each of the plurality of second semiconductor elements further includes a second control electrode insulated from the second main surface electrode and formed on the second element main surface, and wherein the second main surface electrode and the second back surface electrode are electrically connected in response to a second drive signal input to the second control electrode. Appendix 21. 21. The semiconductor device according to any one of claims 11 to 20, further comprising an insulating substrate on which the first conductive member and the second conductive member are mounted. Appendix 22. 22. The semiconductor device according to claim 11, wherein the electrical resistivity of the second conductive member is lower than the electrical resistivity of the pad portion. [Explanation of symbols]

[0106] A1 to A4: Semiconductor device 10, 20: Semiconductor element 10A, 20A: outer element 10B, 20B: inner element 10a, 20a: element main surface 10b, 20b: element back surface 11, 21: Principal surface electrodes 12, 22: Control electrodes 13, 23: rear electrode 14, 24: insulating film 30: Support substrate 31A, 31B: Insulating substrate 311: Main surface 312: Back surface 32A, 32B: Conductive substrate 321: Main surface 322: Back surface 320a: Pad portion 320b: Connecting part 320c: Part 1 320d: Part 2 320z: Contact edge 33A, 33B: Insulation layer 34A, 34B: Gate layer 341: Belt 342: Uncinate 35A, 35B: detection layer 351: strip portion 352: Hook 36: Insulating substrate 361: Main surface 362: Back surface 37A, 37B: Main surface metal layer 38: Back surface metal layer 41: Input terminal 411: Pad section 412: Terminal part 419: Block material 42: Input terminal 421: Pad section 421a: Contact edge 422: Terminal part 423: Connecting part 424: Part 1 424a: Edge 425: Part 2 426: Part 3 429: Block material 43: Output terminal 431: Pad section 432: Terminal part 439: Block material 44A, 44B: Control terminal 441: Pad section 442: Terminal section 45A, 45B: Detection terminal 451: Pad section 452: Terminal section 51: Gate wire 52: Detection wire 53: First connecting wire 54: Second connecting wire 55: Lead plate 551, 552: Joint 559: Block material 60: Resin material 61: Resin main surface 62: Resin back surface 631: Resin side 632: Resin side 633: Resin side 634: Resin side 65: Concave R1, R2: Closed area L12, L23, L31, L45, L56, L64: Line segments L0,L9: Perpendicular bisector P1,P4: 1st vertex P2, P5: Second vertex P3, P6: Third vertex

Claims

1. a plurality of first semiconductor elements each having a first element main surface and a first element back surface spaced apart in a thickness direction and electrically connected in parallel to one another; a plurality of second semiconductor elements each having a second element main surface and a second element back surface spaced apart in the thickness direction and electrically connected in parallel to one another; a pad portion electrically connected to the plurality of first semiconductor elements; a first terminal portion electrically connected to the pad portion; It is equipped with the plurality of first semiconductor elements and the plurality of second semiconductor elements are electrically connected in series, The plurality of first semiconductor elements are arranged along a first direction perpendicular to the thickness direction when viewed in the thickness direction, the pad portion is formed to include a closed area surrounded by three line segments formed by connecting two each of a first vertex, a second vertex, and a third vertex that are not on the same line, the first vertex overlaps with an outermost first semiconductor element on one side in the first direction among the plurality of first semiconductor elements as viewed in the thickness direction, the second vertex overlaps with an outermost first semiconductor element on the other side of the first direction among the plurality of first semiconductor elements as viewed in the thickness direction, the third vertex is located on the perpendicular bisector of the line segment connecting the first vertex and the second vertex when viewed in the thickness direction, the pad portion extends across the plurality of first semiconductor elements and the plurality of second semiconductor elements when viewed in the thickness direction, a semiconductor device in which, when viewed in the thickness direction, a portion of each of the plurality of first semiconductor elements and a portion of each of the plurality of second semiconductor elements do not overlap the pad portion.

2. a connecting portion that connects the pad portion and the first terminal portion, the connecting portion includes a first portion that contacts the pad portion, The semiconductor device according to claim 1 , wherein the first portion overlaps the perpendicular bisector when viewed in the thickness direction.

3. the first portion has a pair of edges spaced apart from each other in the first direction and each extending along the thickness direction and a second direction perpendicular to the first direction; 3. The semiconductor device according to claim 2, wherein each of said pair of edges is connected to said pad portion when viewed in said thickness direction.

4. the pad portion and the first portion each have a rectangular shape when viewed in the thickness direction, The semiconductor device according to claim 3 , wherein the first portion has a dimension in the first direction smaller than that of the pad portion.

5. the plurality of first semiconductor elements include two inner elements that are located between a first semiconductor element that overlaps the first vertex when viewed in the thickness direction and a first semiconductor element that overlaps the second vertex when viewed in the thickness direction and that are adjacent to each other across the perpendicular bisector, 5. The semiconductor device according to claim 3, wherein each of the pair of edges is located above one of the two inner elements when viewed in the second direction.

6. 6. The semiconductor device according to claim 3, wherein each of the plurality of first semiconductor elements has a portion that does not overlap with the pad portion when viewed in the thickness direction.

7. each of the plurality of first semiconductor elements includes a first main surface electrode formed on a main surface of the first element and a first back surface electrode formed on a back surface of the first element; 7. The semiconductor device according to claim 3, wherein the pad portion is located on the first element main surface in the thickness direction and is electrically connected to the first main surface electrode of each of the plurality of first semiconductor elements.

8. a first conductive member on which the plurality of first semiconductor elements are mounted; The semiconductor device according to claim 7 , wherein the first back surface electrode of each of the plurality of first semiconductor elements is joined to the first conductive member.

9. 9. The semiconductor device according to claim 8, wherein said pad portion, said first terminal portion, and said connecting portion are each plate-shaped and integrally formed.

10. a second conductive member on which the plurality of second semiconductor elements are mounted; 10. The semiconductor device according to claim 8, wherein the first conductive member and the second conductive member are arranged side by side and spaced apart from each other in the second direction.

11. 11. The semiconductor device according to claim 10, wherein each of the plurality of second semiconductor elements includes a second main surface electrode formed on the second element main surface and a second back surface electrode formed on the second element back surface.

12. The semiconductor device according to claim 11 , wherein the second back surface electrode of each of the plurality of second semiconductor elements is joined to the second conductive member.

13. The semiconductor device according to claim 12 , further comprising a plurality of connection members that electrically connect said first conductive member to said second principal surface electrodes of said plurality of second semiconductor elements.

14. a second terminal portion electrically connected to the second conductive member; The semiconductor device according to claim 13 , further comprising: a third terminal portion electrically connected to the first conductive member.

15. 15. The semiconductor device according to claim 14, wherein said pad portion straddles said first conductive member and said second conductive member when viewed in said thickness direction.

16. the first apex and the second apex overlap the first conductive member when viewed in the thickness direction, The semiconductor device according to claim 15 , wherein the third apex overlaps the second conductive member when viewed in the thickness direction.

17. 17. The semiconductor device according to claim 15, wherein the second terminal is aligned with the first terminal in the first direction and overlaps with the first terminal when viewed in the first direction.

18. a resin member that covers the plurality of first semiconductor elements and the plurality of second semiconductor elements; 18. The semiconductor device according to claim 14, wherein the first terminal portion, the second terminal portion, and the third terminal portion are exposed from the resin member.

19. each of the plurality of first semiconductor elements further includes a first control electrode insulated from the first principal surface electrode and formed on the first element principal surface, and the first principal surface electrode and the first back surface electrode are electrically connected in response to a first drive signal input to the first control electrode; each of the plurality of second semiconductor elements further includes a second control electrode insulated from the second main surface electrode and formed on the second element main surface, and the second main surface electrode and the second back surface electrode are electrically connected in response to a second drive signal input to the second control electrode; 19. The semiconductor device according to claim 11.

20. 20. The semiconductor device according to claim 10, further comprising an insulating substrate on which the first conductive member and the second conductive member are mounted.

21. 21. The semiconductor device according to claim 11, wherein the electrical resistivity of the second conductive member is lower than the electrical resistivity of the pad portion.

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