Isolator

Abstract

To provide an isolator capable of improving a manufacturing yield.SOLUTION: An isolator includes a substrate, first to third insulating films, first wiring, and first and second coils. The first insulating film is provided on the substrate, and the second insulating film is provided on the first insulating film. The first wiring is provided in the second insulating film and has a thickness same as a film thickness of the second insulating film in a first direction directed toward the second insulating film from the substrate. The first coil extends in the second insulating film and the first insulating film and has a length in the first direction from a front surface of the second insulating film into the first insulating film. The length in the first direction of the first coil is greater than the thickness in the first direction of the first wiring. The third insulating film is provided on the second insulating film and covers the first wiring and the first coil. The second coil is provided at a front side of the third insulating film and faces the first coil.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to an isolator. [Background technology]

[0002] Isolators used for power control are required to be low cost. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-16799 Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments provide an isolator that improves manufacturing yield. [Means for solving the problem]

[0005] An isolator according to an embodiment includes a substrate, first to third insulating films, a first wiring, and first and second coils. The first insulating film is provided on the substrate, and the second insulating film is provided on the first insulating film. The first wiring is provided in the second insulating film and has the same thickness as the second insulating film in a first direction from the substrate toward the second insulating film. The first coil extends through the second insulating film and the first insulating film and has a length in the first direction from a surface of the second insulating film opposite a back surface facing the first insulating film to the first insulating film, and the length of the first coil in the first direction is greater than the thickness of the first wiring in the first direction. The third insulating film is provided on the second insulating film and covers the first wiring and the first coil. The second coil is provided on a surface of the third insulating film opposite a back surface facing the second insulating film and faces the first coil. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an isolator according to an embodiment. [Figure 2] FIG. 1 is a schematic plan view showing an isolator according to an embodiment. [Figure 3] 5A to 5C are schematic cross-sectional views illustrating a manufacturing process of the isolator according to the embodiment. [Figure 4] 4A to 4C are schematic cross-sectional views showing the manufacturing process following FIG. 3. [Figure 5] 5A to 5C are schematic cross-sectional views showing a manufacturing process of an isolator according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing an isolator 1 according to an embodiment. The isolator 1 is configured to transmit a signal from a primary side to a secondary side via magnetic coupling between a primary side coil (hereinafter referred to as a first coil C1) and a secondary side coil (hereinafter referred to as a second coil C2).

[0010] As shown in FIG. 1, the isolator 1 includes a substrate 10, a first insulating film 20, a second insulating film 30, a third insulating film 40, a first wiring IC1, a second wiring IC2, a first coil C1, and a second coil C2.

[0011] The first insulating film 20 is provided on a substrate 10. The second insulating film 30 is provided on the first insulating film 20. The substrate 10 is, for example, a silicon substrate. The first insulating film 20 is, for example, an interlayer insulating film. The first insulating film 20 and the second insulating film 30 are, for example, silicon oxide films.

[0012] The first insulating film 20 includes, for example, interlayer wirings IL1 to IL3. For example, a control circuit (not shown) is provided on the surface side of the substrate 10 facing the first insulating film 20. The interlayer wirings IL1 to IL3 are connected to the control circuit (not shown).

[0013] The first coil C1 is provided to extend through the first insulating film 20 and the second insulating film 30. That is, the first coil C1 is provided to extend from the front surface 30F side of the second insulating film 30 into the first insulating film 20. The front surface 30F of the second insulating film 30 is located opposite the back surface 30B facing the first insulating film 20. The first coil C1 is a metal wire containing, for example, copper, aluminum, or the like.

[0014] The third insulating film 40 is provided on the second insulating film 30. The second coil C2 is provided on the front surface side of the third insulating film 40 opposite to the back surface facing the second insulating film 30. The first coil C1 and the second coil C2 face each other with the third insulating film 40 in between. That is, the second coil C2 is magnetically coupled to the first coil C1.

[0015] The first wiring IC1 and the second wiring IC2 are provided in the second insulating film 30. The first wiring IC1 and the second wiring IC2 are metal wirings containing, for example, copper, aluminum, or the like. The thickness Tc of the first wiring IC1 and the second wiring IC2 is the same as the film thickness of the second insulating film 30 in a first direction from the substrate 10 toward the second insulating film 30, for example, the Z direction. The first wiring IC1 has a first width Wc1 in a second direction along the surface 30F of the second insulating film 30, for example, the X direction. The second wiring IC2 has a second width Wc2 in the X direction.

[0016] The first coil C1 has a length Lpc in the Z direction from the surface 30F of the second insulating film 30 to the inside of the first insulating film 20. The length Lpc of the first coil C1 is longer than the thickness Tc of the first wiring IC1 and the second wiring IC2. The first coil C1 also has, for example, a line width Wpc in the X direction. The line width Wpc of the first coil C1 is narrower than the width Wc1 of the first wiring IC1 and the width Wc2 of the second wiring IC2.

[0017] The third insulating film 40 is provided to cover the first coil C1, the first wiring IC1, and the second wiring IC2. The third insulating film 40 includes, for example, a first film 41, a second film 43, a third film 45, and a fourth film 47.

[0018] The first film 41 is provided on the second insulating film 30. The first film 41 is, for example, a surface protection film. The first film 41 is, for example, a silicon nitride film. The first film 41 is provided to prevent diffusion of metal atoms from the first coil C1, the first wiring IC1, and the second wiring IC2 into the third insulating film 40.

[0019] The second film 43 is provided on the first film 41. The second film 43 is provided so as to maintain a high dielectric strength voltage between the first coil C1 and the second coil C2. The second film 43 has a thickness of, for example, 5 to 10 micrometers. For this reason, it is preferable to use a material for the second film 43 that reduces internal stress within the film. The second film 43 is, for example, a SiON film.

[0020] The third film 45 is provided on the second film 43. The second coil C2 is provided in the third film 45. The third film 45 is, for example, a silicon oxide film. The second coil C2 is, for example, a metal wire embedded in the third film 45. The second coil C2 includes, for example, copper or aluminum.

[0021] The fourth film 47 is provided between the second film 43 and the third film 45. The fourth film 47 is provided, for example, as an etching stop film. That is, the fourth film 47 is provided so as not to etch the second film 43 when forming a groove for burying the second coil C2 (see FIG. 5(a)). The fourth film 47 is, for example, a silicon nitride film.

[0022] The isolator 1 further includes an upper layer terminal UC1, a fourth insulating film 50, and a fifth insulating film 60. The upper layer terminal UC1 is provided in a third film 45 of the third insulating film 40. The fourth insulating film 50 is provided between the first insulating film 20 and the second insulating film 30.

[0023] The upper layer terminal UC1 is provided at the same level as the second coil C2 and contains the same material as the second coil C2. The upper layer terminal UC1 is electrically connected to the first wiring IC1 via a contact plug CP that extends into the first film 41 and the second film 43 of the third insulating film 40. The upper layer terminal UC1 is electrically connected to, for example, a control circuit (not shown) via the contact plug CP, the first wiring IC1, and the interlayer wiring IL3.

[0024] The fourth insulating film 50 has a composition different from that of the second insulating film 30. The fourth insulating film 50 also has a composition different from that of the first insulating film 20. The fourth insulating film 50 is, for example, a silicon nitride film. The fourth insulating film 50 is provided as an etching stopper film when forming grooves in the second insulating film 30 in which the first wiring IC1 and the second wiring IC2 are to be embedded (see FIG. 4(a)).

[0025] The first wiring IC1 and the second wiring IC2 are provided between the third insulating film 40 and the fourth insulating film 50, and are in contact with the third insulating film 40 and the fourth insulating film 50. The fourth insulating film 50 is provided in a position not in contact with the first coil C1.

[0026] The first wiring IC1 and the second wiring IC2 are connected to the interlayer wiring IL3 via contact holes CH provided in the first insulating film 20 and the fourth insulating film 50, respectively. The first wiring IC1 is connected to a control wiring (not shown) via the interlayer wiring IL3. The second wiring IC2 is connected to, for example, the potential (reference potential) of the substrate 10 via the interlayer wiring IL3.

[0027] The fifth insulating film 60 is provided on the third insulating film 40 and covers the second coil C2 and the upper-layer terminal UC1. The fifth insulating film 60 is provided to prevent diffusion of metal elements from the second coil C2 and the upper-layer terminal UC1 to further upper layers (not shown).

[0028] Fig. 2 is a schematic plan view showing the isolator 1 according to the embodiment. Fig. 2 is a partial plan view showing a part of the layout on the primary side. Fig. 1 is a cross-sectional view taken along line AA shown in Fig. 2.

[0029] 2, the first coil C1 is a spiral planar coil. The first wiring IC1 and the second wiring IC2 are provided adjacent to the first coil C1. For example, the first wiring IC1 and the second wiring IC2 surround at least one of the first coils C1 in a planar view. The second coil C2 has the same planar shape as the first coil C1.

[0030] For example, increasing the number of turns of each coil can improve the efficiency of magnetic coupling between the first coil C1 and the second coil C2. However, increasing the number of turns increases the size of the coil. Therefore, it is preferable to narrow the line width Wpc of each coil, but this increases the electrical resistance of each coil. Therefore, in this embodiment, the length Lpc of each coil in the Z direction is increased (see FIG. 1). For example, the first coil C1 is provided so as to extend from the surface 30F of the second insulating film 30 into the first insulating film 20.

[0031] Next, a method for manufacturing the isolator 1 will be described with reference to Figures 3(a) to 4(b). Figures 3(a) to 4(b) are schematic cross-sectional views showing the manufacturing process of the isolator 1 according to the embodiment.

[0032] As shown in FIG. 3(a), a fourth insulating film 50 is formed on a first insulating film 20. The first insulating film 20 is an interlayer insulating film provided on a substrate 10. The first insulating film 20 includes a plurality of interlayer wirings IL1 to IL3. The first insulating film 20 is, for example, a silicon oxide film formed using CVD (Chemical Vapor Deposition).

[0033] The fourth insulating film 50 is, for example, a silicon nitride film. The fourth insulating film 50 is formed by, for example, CVD. The fourth insulating film 50 is selectively removed by, for example, wet etching using an etching mask (not shown). The fourth insulating film 50 is removed in a region where the first coil C1 is to be provided (see FIG. 1), and has an opening 50ch located above the interlayer wiring IL3.

[0034] 3(b), a third insulating film 30 is formed on the first insulating film 20 and the fourth insulating film 50. The third insulating film 30 is, for example, a silicon oxide film. The third insulating film 30 is formed by using, for example, CVD.

[0035] Furthermore, an etching mask EM1 is formed on the third insulating film 30. The etching mask EM1 is, for example, a resist mask formed by photolithography. The etching mask EM1 has an opening Ch above a region where the first coil C1 is to be provided. The opening Ch has the same planar shape as the first coil C1 (see FIG. 2). The etching mask EM1 also has a first opening Ich1 and a second opening Ich2 located above the interlayer wiring IL3. The first opening Ich1 and the second opening Ich2 have the same planar shapes as the first wiring IC1 and the second wiring IC2, respectively (see FIG. 2).

[0036] 4(a), the etching mask EM1 is used to selectively etch the second insulating film 30 and the first insulating film 20. The first insulating film 20 and the second insulating film 30 are selectively removed by, for example, dry etching.

[0037] In the region where the first coil C1 is to be formed, a coil groove CG is formed through an opening Ch in the etching mask EM1. The coil groove CG is formed so as to extend from the surface 30F of the second insulating film 30 into the first insulating film.

[0038] For example, due to uneven etching within the wafer surface, the coil groove CG may be formed to an unintended depth. For this reason, it is preferable that the first insulating film 20 is configured so that no conductive member is interposed between the coil groove CG and the substrate 10. In other words, it is possible to prevent the first coil C1 from coming into contact with the conductive member in the first insulating film 20 and causing a short circuit.

[0039] Furthermore, in the region where the first wiring IC1 and the second wiring IC2 are provided, a first wiring groove IG1 and a second wiring groove IG2 are formed through the first opening Ich1 and the second opening Ich2 of the etching mask EM1. The fourth insulating film 50 is exposed at the bottom surfaces of the first wiring groove IG1 and the second wiring groove IG2. That is, in the region where the first wiring IC1 and the second wiring IC2 are provided, etching is stopped by the fourth insulating film 50. Therefore, the depths of the first wiring groove IG1 and the second wiring groove IG2 are shallower than the depth of the coil groove CG.

[0040] At the bottom of the first wiring groove IG1, the first insulating film 20 is selectively removed through the opening 50ch formed in the fourth insulating film 50. As a result, a contact hole CH is formed that communicates from the first wiring groove IG1 to the interlayer wiring IL3. At the same time, another contact hole CH is formed that communicates from the second wiring groove IG2 to another interlayer wiring IL3.

[0041] 4(b), a first coil C1, a first wiring IC1, and a second wiring IC2 are formed in the coil groove CG, the first wiring groove IG1, and the second wiring groove IG2, respectively. The first wiring IC1 is connected to an interlayer wiring IL3 via a contact hole CH. The second wiring IC2 is connected to another interlayer wiring IL3 via another contact hole CH.

[0042] The first coil C1, the first wiring IC1 and the second wiring IC2 are formed by selectively removing the conductive layer (see Figure 5(b)) filling the coil groove CG, the first wiring groove IG1 and the second wiring groove IG2, while leaving the portions formed in each groove.

[0043] The first wiring IC1 and the second wiring IC2 formed in this manner are so-called damascene wirings. In the process of forming the first wiring IC1 and the second wiring IC2, it is preferable that the difference between the etching rate of the second insulating film 30 and the etching rate of the fourth insulating film 50 is large.

[0044] For example, due to non-uniform etching of the second insulating film 30 within the wafer surface, the time during which the fourth insulating film 50 is exposed to the etching atmosphere also becomes non-uniform. If the time during which the fourth insulating film 50 is exposed to the etching atmosphere becomes long, the fourth insulating film 50 is removed, exposing the underlying first insulating film 20. If the difference between the etching rates of the second insulating film 30 and the fourth insulating film 50 is small, the allowable range of the time during which the fourth insulating film 50 is exposed to the etching atmosphere becomes small, and the first insulating film 20 is unintentionally etched. This increases the risk of a short circuit occurring between the first wiring IC1 or the second wiring IC2 and the interlayer wiring IL3.

[0045] In the isolator 1, for example, a silicon oxide film is used as the second insulating film 30, and for example, a silicon nitride film is used as the fourth insulating film 50. It is easy to perform etching that makes the etching rate of the silicon nitride film sufficiently slower than the etching rate of the silicon oxide film.

[0046] Meanwhile, during the manufacturing process of the isolator 1, it is preferable to reduce the internal stress of the insulating film between the first coil C1 and the second coil C2. Therefore, it is conceivable to use, for example, a SiON film as the second insulating film 30 instead of a silicon oxide film. This would reduce the stress within the insulating film. However, this would reduce the difference in etching rate between the second insulating film 30 and the fourth insulating film 50, increasing the risk of a reduction in yield due to a short circuit between the first wiring IC1 or the second wiring IC2 and the interlayer wiring IL3. In other words, it is preferable to select the materials of the second insulating film 30 and the fifth insulating film 50 so that the difference in etching rate is large.

[0047] 5(a) to 5(c) are schematic cross-sectional views showing a manufacturing process of an isolator according to a comparative example, and are cross-sectional views corresponding to the cross section taken along line AA in FIG.

[0048] 5(a), the fourth insulating film 50 is provided so as to cover the entire upper surface of the first insulating film 20. The second insulating film 30 is formed on the fourth insulating film 50 and has a coil groove CG, a first wiring groove IG1, and a second wiring groove IG2. The fourth insulating film 50 is exposed at the bottom surface of each groove. A contact hole CH is formed at the bottom surface of each of the first wiring groove IG1 and the second wiring groove IG2.

[0049] In this case, the second insulating film 30 is formed so that its film thickness (Tc) in the Z direction is the same as the length Lpc of the first coil C1 in the Z direction. Therefore, the first wiring groove IG1 and the second wiring groove IG2 are deeper than in the example shown in FIG. 4(a).

[0050] 5(b), a conductive layer 101 is formed so as to fill the coil groove CG, the first wiring groove IG1, and the second wiring groove IG2. The conductive layer 101 is, for example, a metal layer containing copper. The conductive layer 101 is formed by, for example, plating.

[0051] 5(c), a first coil C1, a first wiring IC1, and a second wiring IC2 are formed in the coil groove CG, the first wiring groove IG1, and the second wiring groove IG2, respectively. The first coil C1, the first wiring IC1, and the second wiring IC2 are formed by selectively removing the conductive layer 101 while leaving the portions embedded in the respective grooves.

[0052] The conductive layer 101 is removed by, for example, chemical mechanical polishing (CMP). At this time, since the widths of the first wiring groove IG1 and the second wiring groove IG2 in the X direction are large, the first wiring IC1 and the second wiring IC2 have depressions, so-called dishing DS, on the upper surface side.

[0053] The deeper the first wiring groove IG1 and the second wiring groove IG2, the thicker the conductive layer 101 filling them becomes, and the longer it takes to completely remove the conductive layer 101 from the second insulating film 30. As a result, due to unevenness in the amount of polishing by CMP, dishing DS becomes deeper in regions of the second insulating film 30 where the conductive layer 101 is removed early, and CMP residues are more likely to remain inside the dishing. As a result, impurities resulting from the CMP residues diffuse into the third insulating film 40 covering the first wiring IC1 and the second wiring IC2, causing problems such as a decrease in dielectric strength.

[0054] In the isolator 1 according to the embodiment, the first wiring groove IG1 and the second wiring groove IG2 are shallower than the coil groove CG, thereby making it possible to reduce the thickness of the conductive layer 101. This reduces the CMP time and suppresses dishing DS. As a result, it is possible to improve the dielectric strength voltage between the first coil C1 and the second coil C2.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0056] (Appendix 1) A substrate; a first insulating film provided on the substrate; a second insulating film provided on the first insulating film and having a back surface facing the first insulating film and a front surface opposite the back surface; a first wiring provided in the second insulating film and having the same thickness as the second insulating film in a first direction from the substrate toward the second insulating film; a first coil extending into the second insulating film and the first insulating film and having a length in the first direction from the surface of the second insulating film to the first insulating film, the length of the first coil in the first direction being greater than a thickness of the first wiring in the first direction; a third insulating film provided on the second insulating film and covering the first wiring and the first coil; a second coil provided on a front surface side of the third insulating film opposite to a back surface facing the second insulating film and facing the first coil; An isolator equipped with (Appendix 2) further comprising a fourth insulating film provided between the first insulating film and the second insulating film; 2. The isolator according to claim 1, wherein the first wiring is provided so as to be in contact with the fourth insulating film. (Appendix 3) 3. The isolator according to claim 2, wherein the fourth insulating film has a composition different from the compositions of the first insulating film and the second insulating film. (Appendix 4) 4. The isolator according to claim 2, wherein the fourth insulating film is provided at a position not in contact with the first coil. (Appendix 5) an interlayer wiring provided in the first insulating film and positioned between the substrate and the first wiring; 5. The isolator according to claim 2, wherein the first wiring is connected to the interlayer wiring via a contact hole provided in the first insulating film and the fourth insulating film. (Appendix 6) 6. The isolator according to claim 1, wherein the first insulating film does not include a conductive member located between the substrate and the first coil. (Appendix 7) 7. The isolator according to claim 1, wherein the third insulating film has a different composition from the second insulating film. (Appendix 8) 8. The isolator according to claim 1, wherein in a second direction along the surface of the second insulating film, the first wiring has a width wider than the line width of the first coil. [Explanation of symbols]

[0057] 1...isolator, 10...substrate, 20...first insulating film, 30...second insulating film, 30B...rear surface, 30F...front surface, 40...third insulating film, 41...first film, 43...second film, 45...third film, 47...fourth film, 50...fourth insulating film, 50ch, Ch...opening, 60...fifth insulating film, 101...conductive layer, C1...first coil, C2...second coil, CH...contact hole, IG1...first wiring groove, IG2...second wiring groove, CP...contact plug, CG...coil groove, DS...dishing, EM1...etching mask, IC1...first wiring, IC2...second wiring, IL1 to IL3...interlayer wiring, Ich1...first opening, Ich2...second opening, UC1...upper layer terminal

Claims

1. A substrate; a first insulating film provided on the substrate; a second insulating film provided on the first insulating film and having a back surface facing the first insulating film and a front surface opposite the back surface; a first wiring provided in the second insulating film and having the same thickness as the second insulating film in a first direction from the substrate toward the second insulating film; a first coil extending into the second insulating film and the first insulating film and having a length in the first direction from the surface of the second insulating film to the first insulating film, the length of the first coil in the first direction being greater than a thickness of the first wiring in the first direction; a third insulating film provided on the second insulating film and covering the first wiring and the first coil; a second coil provided on a front surface side of the third insulating film opposite to a back surface facing the second insulating film, the second coil facing the first coil; An isolator equipped with

2. a fourth insulating film provided between the first insulating film and the second insulating film; The isolator according to claim 1 , wherein the first wiring is provided so as to be in contact with the fourth insulating film.

3. 3. The isolator according to claim 2, wherein the fourth insulating film has a composition different from the compositions of the first insulating film and the second insulating film.

4. The isolator according to claim 2 , wherein the fourth insulating film is provided at a position not in contact with the first coil.

5. an interlayer wiring provided in the first insulating film and positioned between the substrate and the first wiring; 3. The isolator according to claim 2, wherein the first wiring is connected to the interlayer wiring via a contact hole provided in the first insulating film and the fourth insulating film.

6. 2. The isolator according to claim 1, wherein the first insulating film does not include a conductive member located between the substrate and the first coil.

7. 2. The isolator according to claim 1, wherein the third insulating film has a different composition from the second insulating film.

8. 8. The isolator according to claim 1, wherein the first wiring has a width greater than a line width of the first coil in a second direction along the surface of the second insulating film.

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