Cycle loop

Abstract

[Problem] To achieve frequency division with respect to an analog signal. [Solution] This frequency dividing circuit is provided with an inverter and an input circuit. The inverter includes a transistor. The input circuit converts a first signal, which is an analog differential signal, to a second signal which is a differential analog signal for driving the transistor.

Description

[Technical Field]

[0001] The present disclosure relates to a frequency divider circuit. [Background technology]

[0002] A frequency divider circuit is a circuit that converts high-frequency signals into low-frequency signals and is widely used in electronic devices that use high-frequency signals, such as for processing high-frequency received signals in wireless communications and for processing clock signals in processors such as central processing units (CPUs).

[0003] Generally, the clock signal of a frequency divider circuit is a square wave (digital signal). Therefore, when a clock signal is generated by a sine wave oscillator, a buffer amplifier is required to convert this sine wave into a square wave. However, there is a demand for reducing the power consumption and circuit area of various circuits, and in some cases, installing a buffer amplifier is not desirable. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2012-503443 [Patent Document 2] WO 10 / 134257 [Patent Document 3] JP 2019-180000 A Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the present disclosure provides a frequency divider circuit that can handle analog signals. [Means for solving the problem]

[0006] According to one embodiment, the frequency divider circuit includes an inverter and an input circuit, the inverter including a transistor, the input circuit converting a first signal, which is an analog differential signal, into a second signal, which is a differential analog signal for driving the transistor.

[0007] The transistor may be a MOSFET, and the input circuit may superimpose a bias voltage on the AC component of the first signal to convert it into the second signal that oscillates between a voltage lower than a threshold voltage of the transistor and a voltage higher than the threshold voltage of the transistor.

[0008] The inverter may include an nMOS and a pMOS, and the input circuit may generate a signal obtained by superimposing a threshold voltage of the nMOS and an AC component of the differential signal, and a signal obtained by superimposing a threshold voltage of the pMOS and an AC component of the differential signal.

[0009] The input circuit may include a capacitor that extracts an AC component of a first differential signal, which is one of the signals that make up the differential signal, and a capacitor that extracts an AC component of a second differential signal, which is the other of the signals that make up the differential signal.

[0010] A latch circuit may also be provided.

[0011] The inverter may include a first transistor which is a p-type MOSFET and has a source connected to a positive power supply voltage, a second transistor which is a p-type MOSFET and has a source connected to a drain of the first transistor, a third transistor which is an n-type MOSFET and has a drain connected to a drain of the second transistor, and a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to a gate of the first transistor, The latch circuit may include a fifth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a sixth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a drain connected to a gate of the fifth transistor, and a gate connected to a drain of the fifth transistor, a seventh transistor which is an n-type MOSFET and has a drain connected to the drain of the fifth transistor and a source connected to the negative power supply voltage, and an eighth transistor which is an n-type MOSFET and has a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, a source connected to the negative power supply voltage, and a gate connected to the drain of the seventh transistor, The frequency divider circuit may include a first inverter, a second inverter, a third inverter, and a fourth inverter, a first latch circuit, a second latch circuit, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, the first output terminal is connected to a gate of the first transistor of the first inverter, a drain of the second transistor of the fourth inverter, and a drain of the sixth transistor of the second latch circuit, and outputs a first output signal; the second output terminal is connected to a gate of the first transistor of the second inverter, a drain of the second transistor of the third inverter, and a drain of the fifth transistor of the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal; the third output terminal is connected to a gate of the first transistor of the fourth inverter, a drain of the second transistor of the second inverter, and a drain of the sixth transistor of the first latch circuit, and outputs a third output signal having a predetermined phase shift from the first output signal; The fourth output terminal may be connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit, and may output a fourth output signal that forms a differential signal with the third output signal.

[0012] The input circuit may include: a first input terminal to which one of the first signals is input; a second input terminal to which the other of the first signals is input; a first capacitor connected between the first input terminal and a gate of the second transistor of the first inverter and a gate of the second transistor of the third inverter; a second capacitor connected between the second input terminal and a terminal connected to the gate of the second transistor of the second inverter and a gate of the second transistor of the fourth inverter; a third capacitor connected between the first input terminal and a terminal connected to the gate of the third transistor of the first inverter and a gate of the third transistor of the third inverter; and a fourth capacitor connected between the second input terminal and a terminal connected to the gate of the third transistor of the second inverter and a gate of the third transistor of the fourth inverter.

[0013] The input circuit may include a first bias circuit that applies a first bias voltage to the output of the first capacitor, a second bias circuit that applies a second bias voltage to the output of the second capacitor, a third bias circuit that applies a third bias voltage to the output of the third capacitor, and a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor.

[0014] The first bias voltage and the second bias voltage may be a threshold voltage of the second transistor, and the third bias voltage and the fourth bias voltage may be a threshold voltage of the third transistor.

[0015] The input circuit may include a first constant voltage source connected to the positive power supply voltage and a second constant voltage source connected to the negative power supply voltage; The first bias circuit may include the first constant voltage source and a first resistor connected to the first constant voltage source; The second bias circuit may include the first constant voltage source and a second resistor connected to the first constant voltage source; The third bias circuit may include the second constant voltage source and a third resistor connected to the second constant voltage source, The fourth bias circuit may include the second constant voltage source and a fourth resistor connected to the second constant voltage source.

[0016] The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit may be capable of variably controlling voltages.

[0017] The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit may each include at least one current source whose output current varies depending on fluctuations in at least one of the positive power supply voltage and the negative power supply voltage.

[0018] The current source may include a transistor having a gate connected to the positive power supply voltage or the negative power supply voltage.

[0019] The current source may include a resistor connected to the positive power supply voltage or the negative power supply voltage.

[0020] The power gate transistor may further be provided between the source of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor and the negative power supply voltage.

[0021] The predetermined phase may be π / 2.

[0022] A signal may be generated by dividing the frequency of the first signal by n (n is an integer of 2 or more). [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 2 is a diagram illustrating a frequency divider circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a frequency divider according to an embodiment; [Figure 3] FIG. 2 is a circuit diagram of an inverter according to an embodiment. [Figure 4] FIG. 1 is a circuit diagram illustrating a frequency divider unit using MOSFETs according to an embodiment. [Figure 5] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 6] 4 is a timing chart of input and output signals of an input circuit according to an embodiment. [Figure 7] 4 is a timing chart of input and output signals of a frequency divider according to an embodiment. [Figure 8] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 9] FIG. 2 is a circuit diagram of a frequency divider circuit according to an embodiment. [Figure 10] FIG. 2 is a circuit diagram of a frequency divider circuit according to an embodiment. [Figure 11] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 12] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 13] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 14] FIG. 2 is a circuit diagram of an input circuit according to an embodiment. [Figure 15] FIG. 2 is a circuit diagram of a current source according to an embodiment. [Figure 16] FIG. 2 is a circuit diagram of a current source according to an embodiment. [Figure 17] FIG. 2 is a circuit diagram of a current source according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0025] 1 is a diagram illustrating an example of a frequency divider circuit according to an embodiment of the present disclosure. The frequency divider circuit 1 includes an input circuit 10 and a frequency divider section 20.

[0026] The input circuit 10 is a circuit that receives an analog differential signal IN (first signal), converts this differential signal IN into an analog signal Vdr (second signal) for driving a transistor provided in the frequency divider section 20, and outputs the converted signal. Hereinafter, the differential signal may be expressed by adding + or - as necessary. For example, the above analog differential signal may be expressed as signals IN+ and IN-.

[0027] The frequency divider unit 20 outputs a digital signal obtained by dividing the differential signal IN. This frequency divider unit 20 may be a general frequency divider circuit. As an example, the frequency divider circuit 1 outputs a digital differential clock signal Q and a differential clock signal I that is shifted in phase from the clock signal Q by a predetermined amount from the frequency divider unit 20. For example, when the frequency divider circuit 1 operates as a 2-frequency divider circuit, it outputs differential clock signals Q+ / Q- and differential clock signals I+ / I- that are shifted in phase from the clock signal Q by π / 2.

[0028] 2 is a diagram showing an example of a general frequency divider circuit, and first, a frequency divider unit 20, which is a basic configuration, will be described using this FIG.

[0029] In a typical frequency divider circuit, a digital differential clock signal Vdr is input to an inverter, which outputs divided signals Q and I. However, when a differential signal represented by an analog sine wave is input to this frequency divider circuit, a large amplitude is required. In this embodiment, an input circuit 10 generates an analog signal Vdr as a drive signal that can appropriately drive a frequency divider unit 20, and divides the sine wave differential signal IN.

[0030] The combination of two inverters between signals Q+ and Q-, and the combination of two inverters between signals I+ and I- each form a latch circuit. This latch circuit allows each combination to generate and output a differential signal even when the output from the inverter is stopped.

[0031] Fig. 3 is a circuit diagram showing the inverter circuit in Fig. 2 using MOSFETs. Fig. 3 is a circuit showing, for example, the inverter in Fig. 2 that receives the signal I+ as input and outputs the signal Q+.

[0032] The inverter includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

[0033] The first transistor M1 is, for example, a pMOS, and has a source connected to the positive power supply voltage Vdd and a gate to which I+ is applied.

[0034] The second transistor M2 is, for example, a pMOS, and has a source connected to the drain of the first transistor M1 and a gate to which Vdr- is applied.

[0035] The third transistor M3 is, for example, an nMOS, and its drain is connected to the drain of the second transistor M2, and Vdr+ is applied to its gate.

[0036] The fourth transistor M4 is, for example, an nMOS, and has a drain connected to the source of the third transistor M3, a source connected to the negative power supply voltage Vss, and a gate connected to the gate of the first transistor M1.

[0037] An input signal is applied to the gate of the first transistor M1 and the gate of the fourth transistor M4, and an output signal is output from the drain of the second transistor M2 and the drain of the third transistor M3.

[0038] The signal Q+ outputs a value that is the negation of the signal I+ at the timing when the second transistor M2 and the third transistor M3 are driven.

[0039] The drive signals Vdr+ / Vdr- are analog signals whose values cross the thresholds of the second transistor M2 and the third transistor M3. In the frequency divider circuit 1 according to this embodiment, the input circuit 10 controls the analog differential signal IN so that the drive signals oscillate appropriately based on the thresholds of the respective transistors.

[0040] Although the power supply voltages are described as positive and negative, these may be understood to refer to general power supply voltages Vdd and Vss. For example, more generally, the negative power supply voltage Vss may be connected to the ground point.

[0041] The order of the transistors is not limited to the above. For example, the second transistor M2, the first transistor M1, the fourth transistor M4, and the third transistor M3 may be connected in order from the positive power supply voltage Vdd, and the source of the third transistor M3 may be connected to the negative power supply voltage Vss.

[0042] Fig. 4 is a diagram in which the configuration of the frequency divider 20 is rewritten using MOSFETs, using the inverter configuration of Fig. 3. The latch circuit is also rewritten using MOSFETs in the same way.

[0043] 4, the frequency dividing unit 20 according to this embodiment includes a first inverter 200, a second inverter 202, a third inverter 204, a fourth inverter 206, a first latch circuit 210, and a second latch circuit 212. When analog signals Vn and Vp are input, the frequency dividing unit 20 generates and outputs frequency-divided signals I and Q based on the frequencies of the analog signals. The analog signals Vn and Vp are signals generated by the input circuit 10 based on the analog differential signal IN. The generation of these signals will be described in detail below.

[0044] The first inverter 200 includes a first transistor M11, a second transistor M12, a third transistor M13, and a fourth transistor M14, connected in the same manner as in FIG. 3. Similarly, the second inverter 202 includes a first transistor M21, a second transistor M22, a third transistor M23, and a fourth transistor M24. The third inverter 204 includes a first transistor M31, a second transistor M32, a third transistor M33, and a fourth transistor M34. The fourth inverter 206 includes a first transistor M41, a second transistor M42, a third transistor M43, and a fourth transistor M44.

[0045] The latch circuit includes a fifth transistor and a sixth transistor, which are pMOS, and a seventh transistor and an eighth transistor, which are nMOS. The fifth transistor has a source connected to a positive power supply voltage Vdd. The sixth transistor has a source connected to a positive power supply voltage Vdd, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor. The seventh transistor has a source connected to a negative power supply voltage Vss, and a drain connected to the drain of the fifth transistor. The eighth transistor has a source connected to the negative power supply voltage Vss, a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, and a gate connected to the drain of the seventh transistor. With this configuration, the outputs from the drains of the fifth and seventh transistors and the outputs from the drains of the sixth and eighth transistors are inverted values, regardless of the clock signal.

[0046] The connections of each transistor in Figure 4 will be described based on the connections in Figure 2. A first inverter 200, a second inverter 202, a third inverter 204, and a fourth inverter 206 correspond to the inverters located at the bottom left, top left, bottom right, and top right in Figure 2, respectively. A first latch circuit and a second latch circuit correspond to the latch circuits located at the left and right in Figure 2, respectively.

[0047] The connections in FIG. 4 will be explained.

[0048] Vp-, Vp+, Vn-, and Vn+ are signals in which a bias voltage is superimposed on the AC component of the analog differential signal to be divided, and are output from the input circuit 10. As described above, Q+, Q-, I+, and I- are divided clock signals that are output from the frequency divider circuit 1. For convenience, the terminal that outputs Q+ is referred to as the first output terminal, the terminal that outputs Q- as the second output terminal, the terminal that outputs I+ as the third output terminal, and the terminal that outputs I- as the fourth output terminal. In communications, Q and I may need to be distinguished from each other, but in this disclosure, they are used merely as symbols, and the names of the signals are not particularly limited. However, Q+ and Q-, and I+ and I- each constitute a differential signal.

[0049] The first output terminal is connected to the drain of the second transistor M42 and the drain of the third transistor M43 of the fourth inverter 206, the gate of the first transistor M11 and the gate of the fourth transistor M14 of the first inverter 200, and the drain of the sixth transistor M26 and the drain of the eighth transistor M28 of the second latch circuit 212. A Q+ signal output from the fourth inverter 206 based on the input Vp- and Vn+ signals is input to the first inverter 200 and the second latch circuit 212 and is also output via the first output terminal. When the Vp- and Vn+ signals turn off the second transistor M42 and the third transistor M43 of the fourth inverter 206, the Q+ signal held in the second latch circuit 212 is output.

[0050] The second output terminal is connected to the drains of the second transistor M32 and the third transistor M33 of the third inverter 204, the gates of the first transistor M21 and the fourth transistor M24 of the second inverter 202, and the drains of the fifth transistor M25 and the seventh transistor M27 of the second latch circuit 212. A Q- signal output from the third inverter 204 based on the input Vp- and Vn+ signals is input to the second inverter 202 and the second latch circuit 212 and is also output via the second output terminal. When the Vp- and Vn+ signals turn off the second transistor M32 and the third transistor M33 of the third inverter 204, the Q- signal held in the second latch circuit 212 is output.

[0051] The third output terminal is connected to the drain of the second transistor M22 and the drain of the third transistor M23 of the second inverter 202, the gate of the first transistor M41 and the gate of the fourth transistor M44 of the fourth inverter 206, and the drain of the sixth transistor M16 and the drain of the eighth transistor M18 of the first latch circuit 210. The I+ signal output from the second inverter 202 based on the input Vp+ and Vn- signals is input to the fourth inverter 206 and the first latch circuit 210 and is also output via the third output terminal. When the Vp+ and Vn- signals turn off the second transistor M22 and the third transistor M23 of the second inverter 202, the I+ signal held in the first latch circuit 210 is output.

[0052] The fourth output terminal is connected to the drain of the second transistor M12 and the drain of the third transistor M13 of the first inverter 200, the gate of the first transistor M31 and the gate of the fourth transistor M34 of the third inverter 204, and the drain of the fifth transistor M15 and the drain of the seventh transistor M17 of the first latch circuit 210. The I- signal output from the first inverter 200 based on the input Vp+ and Vn- signals is input to the third inverter 204 and the first latch circuit 210 and is also output via the fourth output terminal. When the Vp+ and Vn- signals turn off the second transistor M12 and the third transistor M13 of the second inverter 202, the I- signal held in the first latch circuit 210 is output.

[0053] In this way, the frequency dividing section 20 is controlled by the input signals Vp−, Vp+, Vn−, Vn+.

[0054] Vp- is a signal whose voltage value oscillates across the threshold voltages of the second transistor M32 of the third inverter 204 and the second transistor M42 of the fourth inverter 206. Vp+ is a signal whose voltage value oscillates across the threshold voltages of the second transistor M12 of the first inverter 200 and the second transistor M22 of the second inverter 202. The AC components of Vp- and Vp+ form a differential signal. If the second transistor Mx2 in each inverter is the same element, for example, Vp- and Vp+ are generated as signals in which the threshold voltage of the second transistor Mx2 is superimposed on the AC component of the differential clock signal.

[0055] Vn- is a signal whose voltage value oscillates across the threshold voltages of the third transistor M13 of the first inverter 200 and the third transistor M23 of the second inverter 202. Vn+ is a signal whose voltage value oscillates across the threshold voltages of the third transistor M33 of the third inverter 204 and the third transistor M43 of the fourth inverter 206. The AC components of Vn- and Vn+ form a differential signal. If the third transistor Mx3 in each inverter is the same element, for example, Vn- and Vn+ are generated as signals in which the threshold voltage of the third transistor Mx3 is superimposed on the AC component of the differential clock signal.

[0056] Note that the configuration of the present disclosure is not limited to the configuration of FIG. 4, and other general frequency divider circuits such as inverters and latch circuits can also be used as the frequency divider unit 20 as long as they are circuits that can appropriately divide by an analog drive signal.

[0057] In the embodiments of the present disclosure, the input circuit 10 appropriately generates the analog AC signals Vn-, Vn+, Vp-, and Vp+, thereby making it possible to obtain frequency-divided signals without passing through a buffer for A / D conversion from the analog signals. Several specific embodiments of the input circuit 10 will be described below.

[0058] (First embodiment) 5 is a diagram showing an example of an input circuit 10. The input circuit 10 includes capacitors C1, C2, C3, and C4, constant voltage sources E1 and E2, and resistors R1, R2, R3, and R4. The input circuit 10 includes a first input terminal to which an analog signal IN+ is applied as an input terminal, and a second input terminal to which an analog signal IN- is applied.

[0059] The first input terminal is connected to a positive power supply voltage Vdd via a capacitor C1, a resistor R1, and a constant voltage source E1. The positive power supply voltage is controlled to at least the threshold voltage (first bias voltage) of the second transistors M12 and M22 of the first inverter 200 and the second inverter 202 via the constant voltage source E1 and the resistor R1. An AC component of the analog signal IN+ is extracted via the capacitor C1, and this AC component is superimposed on the threshold voltage of the second transistors M12 and M22, which is the first bias voltage generated by the positive power supply voltage Vdd, the constant voltage source E1, and the resistor R1. Therefore, the input circuit 10 outputs, as Vp+, a signal in which the threshold voltages of the second transistors M12 and M22 and the AC component of the input analog signal IN+ are superimposed.

[0060] The first input terminal is connected to a negative power supply voltage Vss via a capacitor C2, a resistor R2, and a constant voltage source E2. The negative power supply voltage is controlled to at least the threshold voltage (second bias voltage) of the third transistors M33 and M43 of the third inverter 204 and the fourth inverter 206 via the constant voltage source E2 and the resistor R2. An AC component of the signal IN+ is extracted via the capacitor C2, and this AC component is superimposed on the threshold voltage of the third transistors M33 and M43, which is the second bias voltage generated by the negative power supply voltage Vss, the constant voltage source E2, and the resistor R2. Therefore, the input circuit 10 outputs, as Vn-, a signal in which the threshold voltages of the third transistors M33 and M34 and the AC component of the input analog signal IN+ are superimposed.

[0061] The second input terminal is connected to the negative power supply voltage Vss via a capacitor C3, a resistor R3, and a constant voltage source E2. The negative power supply voltage is controlled to at least the threshold voltage (third bias voltage) of the third transistors M13 and M23 of the first inverter 200 and the second inverter 202 via the constant voltage source E3 and the resistor R3. An AC component of the signal IN− is extracted via the capacitor C3, and this AC component is superimposed on the threshold voltage of the third transistors M13 and M23, which is the third bias voltage generated by the negative power supply voltage Vss, the constant voltage source E3, and the resistor R3. Therefore, the input circuit 10 outputs, as Vn+, a signal in which the threshold voltages of the third transistors M13 and M23 and the AC component of the input analog signal IN− are superimposed.

[0062] The second input terminal is connected to a positive power supply voltage Vdd via a capacitor C4, a resistor R4, and a constant voltage source E1. The positive power supply voltage is controlled to at least the threshold voltage (fourth bias voltage) of the second transistors M32 and M42 of the third inverter 204 and the fourth inverter 206 via the constant voltage source E1 and the resistor R4. An AC component of the signal IN− is extracted via the capacitor C4, and this AC component is superimposed on the threshold voltage of the second transistors M32 and M42, which is the fourth bias voltage generated by the positive power supply voltage Vdd, the constant voltage source E1, and the resistor R4. Therefore, the input circuit 10 outputs, as Vp−, a signal in which the threshold voltage of the second transistors M32 and M32 and the AC component of the input analog signal IN− are superimposed.

[0063] Preferably, the second transistor Mx2 of each inverter uses the same element, and similarly, the third transistor Mx3 of each inverter uses the same element. In this preferred embodiment, Vdd - E1 is the threshold voltage of the second transistor, and E2 is the threshold voltage of the third transistor. Each resistor is controlled to prevent AC components from propagating to the power supply side. In this case, the first bias voltage and the fourth bias voltage are the same value, and the second bias voltage and the third bias voltage are the same value.

[0064] The circuit for generating the bias voltages may be, for example, a first bias circuit to a fourth bias circuit that generate the first bias voltage to the fourth bias voltage separately. In the above-mentioned preferable another example, it is sufficient to be able to generate the first bias voltage and the second bias, and in this case, it is sufficient to provide a first bias circuit and a second bias circuit.

[0065] Furthermore, it is desirable that the bias voltages and the threshold voltages are equal to each other, but this is not a limitation. As long as the bias voltages are sufficiently close to the threshold voltages, the same frequency division can be achieved.

[0066] Figure 6 is a timing chart of the input / output signals IN, Vp, and Vn of the input circuit 10. As shown in Figure 6, Vn+ / - is a signal in which the AC component of IN+ / - is increased by E2, i.e., the threshold voltage of the third transistor. Similarly, Vp+ / - is a signal in which the AC component of IN+ / - is biased by Vdd - E1, i.e., the threshold voltage of the second transistor.

[0067] 7 is a timing chart of Vp, Vn, Q, and I, which are input and output signals of frequency divider unit 20. As shown in this diagram, Q+, I+, Q-, and I- are converted into clock signals with a period twice that of the original analog signal IN, with a phase shift of π / 2 relative to signals Vn and Vp.

[0068] As described above, according to this embodiment, it is possible to output a frequency-divided digital clock signal without converting an analog signal generated by an oscillator to digital before dividing it. This circuit simply adds components such as capacitors and resistors to a conventional frequency divider circuit for analog signals. This eliminates the need for an analog-to-digital conversion buffer, thereby reducing the circuit area and power consumption.

[0069] (Second embodiment) 8 is a diagram showing another example of the input circuit 10. As shown in this diagram, instead of the constant voltage sources E1 and E2 used in the input circuit 10, a variable voltage power supply can be used.

[0070] In this embodiment, instead of the constant voltage source of the previous embodiment, variable transistors T1 and T2 are used to vary the bias voltage superimposed on IN. The current mirror circuit located on the left outputs the current of the constant current source. The gate potential of this current mirror is the same as the gate potential of variable transistor T1. Therefore, a current mirror is also formed with variable transistor T1, and the magnification of the output current can be changed by changing the element coefficient of variable transistor T1. This output is converted to a variable voltage by connecting it to the positive power supply voltage Vdd via a capacitor. This voltage is converted to an appropriate voltage by diode-connected transistors and superimposed on the AC component output from the input-side capacitor via the corresponding resistors to generate signal Vn.

[0071] The current of the current mirror on the right is further mirrored to the current mirror circuit in the next stage. Here, the magnification of the left current mirror can be changed by changing the element coefficient of variable transistor T2. After this, the signal Vp is generated by the same operation as the operation on the Vn side described above.

[0072] As described above, this embodiment makes it possible to appropriately change the voltage value superimposed on the AC component of the clock signal. In high-frequency bands, depending on the performance of the MOSFET, there is a possibility that the gate-source voltage may not be able to follow the expected performance when it becomes larger or smaller than the threshold voltage. In such cases, stable performance may be obtained by making the voltage value superimposed on the clock signal larger (nMOS) or smaller (pMOS) than the threshold voltage. By controlling the voltage of the signal to be superimposed in the input circuit 10 using a variable transistor, it becomes possible to accommodate clock signals of a wider variety of frequencies, and it is also possible to prevent an increase in power consumption in frequency bands where control is possible according to the threshold voltage.

[0073] Furthermore, when the same elements are used for the same transistors in each inverter, differences may occur between wafers due to process variations. Due to such individual differences, if the constant voltage source is set to a threshold voltage as in the first embodiment, the frequency division operation may not be appropriate. Even in such cases, if the bias voltage can be controlled as in this embodiment, appropriate frequency division can be achieved regardless of individual differences. Furthermore, even when the coefficients of the elements change due to temperature changes, etc., appropriate frequency division can be achieved by appropriately controlling the bias voltage.

[0074] (Third embodiment) 9 is a diagram showing a frequency divider circuit 1 in which a power gate is provided in the frequency divider unit 20. The source of the transistor T3 is connected to the negative power supply voltage Vss, the drain is connected to the sources of the fourth transistor of each inverter and the seventh and eighth transistors of each latch circuit, and an enable signal is input to the gate. That is, the transistors other than the transistor T3 in the frequency divider unit 20 are connected to the negative power supply voltage Vss via the transistor T3.

[0075] The enable signal EN turns on and off the connection between the frequency divider unit 20 and the power supply circuit, which makes it possible to stop the function of the frequency divider circuit 1 when frequency division is not required.

[0076] In FIG. 9, only the transistor T3 is provided as a power gate, but this is not limitative, and a plurality of transistors may be provided in parallel with the transistor T3 as power gates.

[0077] As described above, according to this embodiment, by providing a transistor that serves as a power gate, it is possible to suppress the leakage current when the frequency divider circuit 1 is not in operation, and reduce power consumption.

[0078] This embodiment may be used alone or in combination with other embodiments. For example, the second embodiment described above and each embodiment described below may be provided with a power gate, and the above-mentioned effects can be achieved.

[0079] (Fourth embodiment) 10 shows a frequency divider circuit 1 that summarizes the control of inverters by clock signals. As shown in this figure, the first inverter 200 and the second inverter 202 may share the second transistor M12 and the third transistor M13. Similarly, the third inverter 204 and the fourth inverter 206 may share the second transistor M32 and the third transistor M33.

[0080] In this way, by sharing the transistors to which the signals Vp+ / Vp- and Vn+ / Vn- are input, it is possible to achieve higher speed operation.

[0081] (Fifth embodiment) When the input circuit 10 of Fig. 8 is used, each inverter is not affected by fluctuations in the power supply voltage, but each latch circuit is affected by fluctuations in the power supply voltage. In this embodiment, a circuit that is less susceptible to the influence of the power supply voltage as an entire frequency divider circuit 1 compared to the input circuit 10 of Fig. 8 will be described.

[0082] 11 is a circuit diagram showing an input circuit 10 according to this embodiment. The input circuit 10 includes transistors T4 and T5, whose gates are applied with a power supply voltage, between a current mirror circuit and a transistor that superimposes a DC component on a clock signal. These two transistors T4 and T5 have drain currents that flow due to the power supply voltage, so that fluctuations in the power supply voltage also affect the bias voltage.

[0083] Specifically, the transistor T4 is, for example, a pMOS, with its source connected to the positive power supply voltage Vdd, its drain connected to the drain of the transistor T1, and its gate connected to the negative power supply voltage Vss. By connecting the gate to the negative power supply voltage Vss, the transistor T4 operates as a diode that allows current to flow in one direction from the source to the drain. The performance of this diode depends on the power supply voltage due to the connection relationship between the source and gate.

[0084] Similarly, transistor T5 is, for example, an nMOS, with its source connected to the negative power supply voltage Vss, its drain connected to the drain of transistor T2, and its gate connected to the positive power supply voltage Vdd. By connecting its gate to the positive power supply voltage Vdd, transistor T5 operates as a diode that allows current to flow in one direction from its drain to its source. The performance of this diode depends on the power supply voltage due to the connection relationship between its source and gate.

[0085] In the input circuit 10, by making the bias voltage susceptible to fluctuations in the power supply voltage, the superimposed signal output from the input circuit 10 is susceptible to the power supply voltage. The output of this input circuit 10 becomes the drive voltage for the inverters in the frequency dividing section 20, and therefore each inverter is driven under the influence of fluctuations in the power supply voltage.

[0086] As described above, according to the input circuit 10 of this embodiment, the drive of each circuit in the frequency dividing unit 20 is changed in accordance with fluctuations in the power supply voltage. That is, both the inverter and the latch circuit in the frequency dividing unit 20 are affected by fluctuations in the power supply voltage to the same extent. As a result, the tolerance of the frequency dividing circuit 1 to fluctuations in the power supply voltage can be increased, and more stable operation can be achieved even when the power supply voltage fluctuates.

[0087] For example, if the transistors of the inverter in frequency division unit 20 are in the SS state, and the temperature is low and the power supply voltage is high, the performance of the transistors in the latch circuit will be higher than that of the inverter. Therefore, it is necessary to apply a voltage to the inverter circuit that will reverse the on / off state of the latch circuit, but if the driving capability of the inverter circuit is insufficient, it will be difficult to perform frequency division at a small input amplitude.

[0088] Conversely, if the inverter transistors are in the FF state, the performance of the latch circuit transistors will be reduced when the temperature is high and the power supply voltage is low, making it difficult for the latch circuit to maintain its state. In this case, too, it becomes difficult to perform frequency division with a small input amplitude.

[0089] As in this embodiment, by varying the bias voltage for driving the inverter in the same manner as the power supply voltage on which the latch circuit depends, it becomes possible to operate the inverter and latch circuit appropriately even when such power supply voltage fluctuations occur, and the operation of the frequency divider circuit 1 can be stabilized.

[0090] (Sixth embodiment) As a modification of the fifth embodiment, a general form that depends on voltage fluctuations in a circuit that generates a bias voltage will be described.

[0091] 12 is a circuit diagram of an input circuit 10 according to this embodiment. The input circuit 10 includes current sources Id1 and Id2 for generating a bias voltage. Each of the current sources Id1 and Id2 is dependent on the power supply voltage (easily affected by the power supply voltage). For example, the operation of the transistors T4 and T5 in the circuit of FIG. 11 indicates that the input circuit 10 shown in FIG. 11 is an example of the input circuit 10 shown in FIG. 12.

[0092] 13 is a circuit diagram of another example of the input circuit 10 according to this embodiment. The input circuit 10 includes current sources Id1 and Id2 for generating bias voltages, and further includes current sources Ii1 and Ii2. Each of the current sources Ii1 and Ii2 is a current source that does not depend on the power supply voltage (is less susceptible to the influence of the power supply voltage). By including such current sources Ii1 and Ii2, it is also possible to control the degree to which the bias voltage is influenced by the power supply voltage.

[0093] Fig. 14 shows another example of the input circuit 10 shown in Fig. 13. In addition to current sources Id1, Id2, Ii1, and Ii2, it includes current sources Id3 and Id4 that depend on the power supply voltage and currents Ii3 and Ii4 that do not depend on the power supply voltage.

[0094] In the embodiment of FIG. 14, current sources Id1 and Ii1 are used to generate a bias voltage that generates Vn+. Current sources Id2 and Ii2 are used to generate a bias voltage that generates Vp+. Power sources Id3 and Ii3 are used to generate a bias voltage that generates Vn-. Current sources Id4 and Ii4 are used to generate a bias voltage that generates Vp-. In each of the above-described embodiments, two types of bias voltages were generated: a bias voltage that generates Vn+ and Vn-, and a bias voltage that generates Vp+ and Vp-. However, in this manner, bias voltages may be generated for each signal output by input circuit 10 to drive frequency divider section 20.

[0095] Figure 15 shows an example of a current source that depends on the power supply voltage. The current source shown on the left is for generating a bias voltage for Vn. This is similar to the example shown in Figure 11 and is configured using a pMOS whose source is connected to the positive power supply voltage Vdd and whose gate is connected to the negative power supply voltage Vss.

[0096] The current source for generating the bias voltage for Vp is shown on the right. This is similar to the example shown in Figure 11 and is configured using an nMOS whose source is connected to the negative power supply voltage Vss and whose gate is connected to the positive power supply voltage Vdd.

[0097] FIG. 16 shows another example of a current source that depends on the power supply voltage. The MOSFET in FIG. 15 can be replaced with a resistor, which is simpler. As in the case of FIG. 15, the configuration is simple and the process is simple, but the circuit area needs to be large. Therefore, either option can be selected appropriately depending on the purpose.

[0098] 17 is a diagram showing an example of a power flow that is independent of the power supply voltage. The input circuit 10 may include a circuit using a BGR (Bandgap Reference) and two current mirrors as a current source Ii1 that is independent of the power supply voltage. The BGR is a voltage source that is less dependent on the power supply voltage, and by using the voltage generated by this BGR as the input to the current mirror, a current that is less dependent on the power supply voltage is generated.

[0099] More specifically, in the left current mirror, the gate voltage is generated by BGR. This means that the drain current is less dependent on the power supply voltage, and this current is mirrored. The current that generates the bias voltage on the Vp side is generated based on the current generated by this current mirror, so it is also less dependent on the power supply voltage.

[0100] The current generated by the left current mirror becomes the input to the right current mirror. This makes it possible to replicate a current with a small power supply voltage dependency from the right current mirror as well. This generated current generates the bias voltage on the Vn side. As a result, the current used to generate the bias voltage on the Vn side has a small power supply voltage dependency.

[0101] As described above, according to this embodiment, by using at least one current source dependent on the power supply voltage to generate bias voltages for both p and n, it is possible to reduce the difference in the influence of voltage dependency between the inverter and the latch circuit in the frequency divider unit 20. By generating bias voltages in this manner, the input circuit 10 can generate an analog signal with improved stability against fluctuations in the power supply voltage.

[0102] 11 to 14, a capacitor for noise removal may be further provided as appropriate. For example, a capacitor may be further provided as appropriate between Vdd and the drain of a transistor that serves as the output terminal of constant voltage source E1, which is a bias voltage, or between Vss and the drain of a transistor that serves as the output terminal of constant voltage source E2, which is a bias voltage.

[0103] Seventh embodiment In the frequency divider circuit 1 formed by the input circuit 10 and the frequency divider unit 20 in each of the above-described embodiments, in particular, part of the frequency divider unit 20 (for example, a combination of the first inverter 200, the second inverter 202, and the first latch circuit 210) can be replaced with a D-FF. As a result, a clock signal for the D-FF can be generated as an analog signal using a configuration equivalent to this input circuit 10.

[0104] For this reason, according to the input circuit 10 of all the embodiments of the present disclosure, the input signal of a divider circuit with a divide-by-3 or more can be converted into an analog signal. In the above-described embodiments, a divide-by-2 circuit has been described, but as mentioned above, the input circuit 10 can also be applied to a divider circuit with a divide-by-3 or more.

[0105] The frequency divider circuit according to each of the above-described embodiments may be used, for example, for processing high-frequency signals in an RF transceiver circuit. It may also be used in an ADPLL (All Digital Phase Locked Loop) that generates a clock signal in an image sensor using a CMOS. The applications are not limited to these, and the frequency divider circuit may be used in devices that use frequency division of a clock signal.

[0106] The above-described embodiment may be modified as follows.

[0107] (1) an inverter having a transistor; an input circuit that converts a first signal, which is an analog differential signal, into a second signal, which is a differential analog signal for driving the transistor; A frequency divider circuit comprising:

[0108] (2) the transistor is a MOSFET; the input circuit superimposes a bias voltage on the AC component of the first signal to convert it into the second signal that oscillates between a voltage lower than a threshold voltage of the transistor and a voltage higher than the threshold voltage of the transistor. The frequency divider circuit according to (1).

[0109] (3) the inverter comprises an nMOS and a pMOS, The input circuit a signal obtained by superimposing the threshold voltage of the nMOS and the AC component of the differential signal; a signal obtained by superimposing the threshold voltage of the pMOS and the AC component of the differential signal; Generate (2) The frequency divider circuit according to (2).

[0110] (4) The input circuit a capacitor that extracts an AC component of a first differential signal that is one of the signals that constitute the differential signal; a capacitor that extracts an AC component of a second differential signal that is the other signal that constitutes the differential signal; Equipped with A frequency divider circuit according to (2) or (3).

[0111] (5) a latch circuit. (2) The frequency divider circuit according to (2).

[0112] (6) The inverter is a first transistor, which is a p-type MOSFET and has a source connected to a positive power supply voltage; a second transistor, which is a p-type MOSFET and has a source connected to the drain of the first transistor; a third transistor, which is an n-type MOSFET and has a drain connected to the drain of the second transistor; a fourth transistor, which is an n-type MOSFET, the drain of which is connected to the source of the third transistor, the source of which is connected to a negative power supply voltage, and the gate of which is connected to the gate of the first transistor; Equipped with The latch circuit a fifth transistor, which is a p-type MOSFET and has a source connected to the positive power supply voltage; a sixth transistor, which is a p-type MOSFET, having a source connected to the positive power supply voltage, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor; a seventh transistor, which is an n-type MOSFET, the drain of which is connected to the drain of the fifth transistor and the source of which is connected to the negative power supply voltage; an eighth transistor, which is an n-type MOSFET, the drain of which is connected to the drain of the sixth transistor and the gate of the seventh transistor, the source of which is connected to the negative power supply voltage, and the gate of which is connected to the drain of the seventh transistor; Equipped with The frequency divider circuit comprises: a first inverter, a second inverter, a third inverter, and a fourth inverter; a first latch circuit and a second latch circuit; a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; Equipped with the first output terminal is connected to a gate of the first transistor of the first inverter, a drain of the second transistor of the fourth inverter, and a drain of the sixth transistor of the second latch circuit, and outputs a first output signal; the second output terminal is connected to a gate of the first transistor of the second inverter, a drain of the second transistor of the third inverter, and a drain of the fifth transistor of the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal; the third output terminal is connected to a gate of the first transistor of the fourth inverter, a drain of the second transistor of the second inverter, and a drain of the sixth transistor of the first latch circuit, and outputs a third output signal having a predetermined phase shift from the first output signal; the fourth output terminal is connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit, and outputs a fourth output signal that forms a differential signal with the third output signal. (5) The frequency divider circuit according to (5).

[0113] (7) The input circuit a first input terminal to which one of the first signals is input; a second input terminal to which the other of the first signals is input; a first capacitor connected between the first input terminal and a gate of the second transistor of the first inverter and a gate of the second transistor of the second inverter; a second capacitor connected between the second input terminal and a terminal connected to a gate of the second transistor of the third inverter and a terminal connected to a gate of the second transistor of the fourth inverter; a third capacitor connected between the first input terminal and a terminal connected to a gate of the third transistor of the first inverter and a terminal connected to a gate of the third transistor of the second inverter; a fourth capacitor connected between the second input terminal and a terminal connected to a gate of the third transistor of the third inverter and a terminal connected to a gate of the third transistor of the fourth inverter; The frequency divider circuit according to (6) above,

[0114] (8) The input circuit a first bias circuit that applies a first bias voltage to the output of the first capacitor; a second bias circuit that applies a second bias voltage to the output of the second capacitor; a third bias circuit that applies a third bias voltage to the output of the third capacitor; a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor; Equipped with (7) The frequency divider circuit according to (7).

[0115] (9) the first bias voltage and the second bias voltage are threshold voltages of the second transistor; the third bias voltage and the fourth bias voltage are threshold voltages of the third transistor; (8) The frequency divider circuit according to (8).

[0116] (10) The input circuit a first constant voltage source connected to the positive power supply voltage; a second constant voltage source connected to the negative power supply voltage; Equipped with the first bias circuit includes the first constant voltage source and a first resistor connected to the first constant voltage source; the second bias circuit includes the first constant voltage source and a second resistor connected to the first constant voltage source; the third bias circuit includes the second constant voltage source and a third resistor connected to the second constant voltage source; the fourth bias circuit includes the second constant voltage source and a fourth resistor connected to the second constant voltage source. (8) The frequency divider circuit according to (8).

[0117] (11) the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit are capable of variably controlling voltages; (8) The frequency divider circuit according to (8).

[0118] (12) the first inverter and the second inverter share the second transistor and the third transistor; the third inverter and the fourth inverter share the second transistor and the third transistor; A frequency divider circuit according to any one of (6) to (11).

[0119] (13) the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit each include at least one current source that outputs a current that varies depending on a variation in at least one of the positive power supply voltage and the negative power supply voltage; A frequency divider circuit according to any one of (8) to (10).

[0120] (14) the current source includes a transistor having a gate connected to the positive power supply voltage or the negative power supply voltage; (13) The frequency divider circuit according to (13).

[0121] (15) the current source includes a resistor connected to the positive power supply voltage or the negative power supply voltage; (13) The frequency divider circuit according to (13).

[0122] (16) a power gate transistor is further provided between the source of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor and the negative power supply voltage; A frequency divider circuit according to any one of (6) to (15).

[0123] (17) The predetermined phase is π / 2. A frequency divider circuit according to any one of (6) to (16).

[0124] (18) generating a signal by dividing the frequency of the first signal by n (n is an integer equal to or greater than 2); A frequency divider circuit according to any one of (1) to (17).

[0125] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents. [Explanation of symbols]

[0126] 1: divider circuit, 10: input circuit, 20: frequency divider, 200: first inverter, 202: second inverter, 204: third inverter, 206: fourth inverter, 210: first latch circuit, 212: second latch circuit,

Claims

1. an inverter having a transistor; an input circuit that converts a first signal, which is an analog differential signal, into a second signal, which is a differential analog signal for driving the transistor; A frequency divider circuit comprising:

2. the transistor is a MOSFET; the input circuit superimposes a bias voltage on the AC component of the first signal to convert it into the second signal that oscillates between a voltage lower than a threshold voltage of the transistor and a voltage higher than the threshold voltage of the transistor.

2. The frequency divider circuit according to claim 1.

3. the inverter comprises an nMOS and a pMOS, The input circuit a signal obtained by superimposing the threshold voltage of the nMOS and the AC component of the differential signal; a signal obtained by superimposing the threshold voltage of the pMOS and the AC component of the differential signal; Generate 3. The frequency divider circuit according to claim 2.

4. The input circuit a capacitor that extracts an AC component of a first differential signal that is one of the signals that constitute the differential signal; a capacitor that extracts an AC component of a second differential signal that is the other signal that constitutes the differential signal; Equipped with 3. The frequency divider circuit according to claim 2.

5. a latch circuit.

3. The frequency divider circuit according to claim 2.

6. The inverter is a first transistor, which is a p-type MOSFET and has a source connected to a positive power supply voltage; a second transistor, which is a p-type MOSFET and has a source connected to the drain of the first transistor; a third transistor, which is an n-type MOSFET and has a drain connected to the drain of the second transistor; a fourth transistor, which is an n-type MOSFET, the drain of which is connected to the source of the third transistor, the source of which is connected to a negative power supply voltage, and the gate of which is connected to the gate of the first transistor; Equipped with The latch circuit a fifth transistor, which is a p-type MOSFET and has a source connected to the positive power supply voltage; a sixth transistor, which is a p-type MOSFET, having a source connected to the positive power supply voltage, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor; a seventh transistor, which is an n-type MOSFET, the drain of which is connected to the drain of the fifth transistor and the source of which is connected to the negative power supply voltage; an eighth transistor, which is an n-type MOSFET, the drain of which is connected to the drain of the sixth transistor and the gate of the seventh transistor, the source of which is connected to the negative power supply voltage, and the gate of which is connected to the drain of the seventh transistor; Equipped with The frequency divider circuit comprises: a first inverter, a second inverter, a third inverter, and a fourth inverter; a first latch circuit and a second latch circuit; a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal; Equipped with the first output terminal is connected to a gate of the first transistor of the first inverter, a drain of the second transistor of the fourth inverter, and a drain of the sixth transistor of the second latch circuit, and outputs a first output signal; the second output terminal is connected to a gate of the first transistor of the second inverter, a drain of the second transistor of the third inverter, and a drain of the fifth transistor of the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal; the third output terminal is connected to a gate of the first transistor of the fourth inverter, a drain of the second transistor of the second inverter, and a drain of the sixth transistor of the first latch circuit, and outputs a third output signal having a predetermined phase shift from the first output signal; the fourth output terminal is connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit, and outputs a fourth output signal that forms a differential signal with the third output signal.

6. The frequency divider circuit according to claim 5.

7. The input circuit a first input terminal to which one of the first signals is input; a second input terminal to which the other of the first signals is input; a first capacitor connected between the first input terminal and a gate of the second transistor of the first inverter and a gate of the second transistor of the second inverter; a second capacitor connected between the second input terminal and a terminal connected to a gate of the second transistor of the third inverter and a terminal connected to a gate of the second transistor of the fourth inverter; a third capacitor connected between the first input terminal and a terminal connected to a gate of the third transistor of the first inverter and a terminal connected to a gate of the third transistor of the second inverter; a fourth capacitor connected between the second input terminal and a terminal connected to a gate of the third transistor of the third inverter and a terminal connected to a gate of the third transistor of the fourth inverter; 7. The frequency divider circuit of claim 6, comprising:

8. The input circuit a first bias circuit that applies a first bias voltage to the output of the first capacitor; a second bias circuit that applies a second bias voltage to the output of the second capacitor; a third bias circuit that applies a third bias voltage to the output of the third capacitor; a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor; Equipped with 8. The frequency divider circuit according to claim 7.

9. the first bias voltage and the second bias voltage are threshold voltages of the second transistor; the third bias voltage and the fourth bias voltage are threshold voltages of the third transistor; 9. The frequency divider circuit according to claim 8.

10. The input circuit a first constant voltage source connected to the positive power supply voltage; a second constant voltage source connected to the negative power supply voltage; Equipped with the first bias circuit includes the first constant voltage source and a first resistor connected to the first constant voltage source; the second bias circuit includes the first constant voltage source and a second resistor connected to the first constant voltage source; the third bias circuit includes the second constant voltage source and a third resistor connected to the second constant voltage source; the fourth bias circuit includes the second constant voltage source and a fourth resistor connected to the second constant voltage source.

9. The frequency divider circuit according to claim 8.

11. the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit are capable of variably controlling voltages; 9. The frequency divider circuit according to claim 8.

12. the first inverter and the second inverter share the second transistor and the third transistor; the third inverter and the fourth inverter share the second transistor and the third transistor; 7. The frequency divider circuit according to claim 6.

13. the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit each include at least one current source that outputs a current that varies depending on a variation in at least one of the positive power supply voltage and the negative power supply voltage; 9. The frequency divider circuit according to claim 8.

14. the current source includes a transistor having a gate connected to the positive power supply voltage or the negative power supply voltage; 14. The frequency divider circuit according to claim 13.

15. the current source includes a resistor connected to the positive power supply voltage or the negative power supply voltage; 14. The frequency divider circuit according to claim 13.

16. a power gate transistor is further provided between the source of the fourth transistor, the source of the seventh transistor, and the source of the eighth transistor and the negative power supply voltage; 7. The frequency divider circuit according to claim 6.

17. The predetermined phase is π / 2.

7. The frequency divider circuit according to claim 6.

18. generating a signal by dividing the frequency of the first signal by n (n is an integer equal to or greater than 2); 2. The frequency divider circuit according to claim 1.

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