Doherty Amplifier

Abstract

A Doherty amplifier according to the present disclosure comprises: an input terminal; an output terminal; a first main transistor that is provided to a first signal path which connects the input terminal and the output terminal; a second main transistor that, on the first signal path, is provided further to the output terminal side than the first main transistor; a first peak transistor that is provided to a second signal path which connects the input terminal and the output terminal; and a second peak transistor that, on the second signal path, is provided further to the output terminal side than the first peak transistor. The first main transistor and one of the first peak transistor and the second peak transistor are formed on a first semiconductor chip. The second main transistor and the other one of the first peak transistor and the second peak transistor are formed on a second semiconductor chip.

Description

[Technical Field]

[0001] The present disclosure relates to Doherty amplifiers. [Background technology]

[0002] Patent Document 1 discloses a Doherty amplifier in which two stages of main transistors are integrated into one semiconductor chip, two stages of peak transistors are integrated into one semiconductor chip, and these semiconductor chips are mounted on a resin substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,381,984 Summary of the Invention [Problem to be solved by the invention]

[0004] In amplifiers, it is important to sufficiently minimize the characteristic variations due to manufacturing variations in order to improve yield. Manufacturing variations generally occur for each lot, wafer, or semiconductor chip. In transistors, manufacturing variations are caused by, for example, the parasitic capacitance Cds between the source and drain. In matching circuits, manufacturing variations are caused by, for example, MIM (Metal-Insulator-Metal) capacitance.

[0005] In a Doherty amplifier, it is preferable that the signal amplified in the main transistor path and the signal amplified in the peak transistor path are power-combined without loss. In other words, if the pass phase of the entire main transistor path is θmain and the pass phase of the entire peak transistor path is θpeak, it is preferable that θmain and θpeak are the same. If a phase difference occurs between θmain and θpeak, a composite loss occurs, and the saturated output power of the Doherty amplifier decreases. For this reason, Doherty amplifiers are generally designed so that the difference between θmain and θpeak is zero.

[0006] In Patent Document 1, due to semiconductor manufacturing variations, for example, it is possible that the Cds and MIM capacitance of the main transistor both vary toward the higher side, while the Cds and MIM capacitance of the peak transistor both vary toward the lower side. When the capacitance increases, the passing phase lags, and when the capacitance decreases, the passing phase advances. As a result, in the above case, the difference between θmain and θpeak becomes very large, which may result in a decrease in saturated output power.

[0007] An object of the present disclosure is to provide a Doherty amplifier that can suppress a decrease in saturated output power due to manufacturing variations. [Means for solving the problem]

[0008] Book The disclosed Doherty amplifier comprises an input terminal, an output terminal, a first main transistor provided in a first signal path connecting the input terminal and the output terminal, a second main transistor provided in the first signal path closer to the output terminal than the first main transistor, a first peak transistor provided in a second signal path connecting the input terminal and the output terminal, and a second peak transistor provided in the second signal path closer to the output terminal than the first peak transistor, wherein the second peak transistor and the first main transistor are formed on a first semiconductor chip, and the first peak transistor and the second main transistor are formed on a second semiconductor chip. [Effects of the Invention]

[0010] In the Doherty amplifier according to the first disclosure, one of the first peak transistor and the second peak transistor and the first main transistor are formed on a first semiconductor chip. The other of the first peak transistor and the second peak transistor and the second main transistor are formed on a second semiconductor chip. This allows one of the first peak transistor and the second peak transistor and the first main transistor to have similar variations. Furthermore, the other of the first peak transistor and the second peak transistor and the second main transistor can have similar variations. Therefore, the phase difference between the first signal path and the second signal path can be suppressed. In the Doherty amplifier according to the second disclosure, the first main transistor and the first peak transistor are formed on a first semiconductor chip, and the first matching circuit and the second matching circuit are formed on a second semiconductor chip. This allows the first main transistor and the first peak transistor to have similar variations. Also, the first matching circuit and the second matching circuit can have similar variations. Therefore, the phase difference between the first signal path and the second signal path can be suppressed. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a Doherty amplifier according to a first embodiment. [Figure 2] 1 is a circuit diagram of a Doherty amplifier according to a first embodiment. [Figure 3] FIG. 1 is a diagram illustrating a passing phase of a Doherty amplifier. [Figure 4] FIG. 2 is a plan view of a Doherty amplifier according to a first comparative example. [Figure 5] FIG. 10 is a plan view of a Doherty amplifier according to a second comparative example. [Figure 6] FIG. 10 is a circuit diagram of a Doherty amplifier according to a second comparative example. [Figure 7] FIG. 10 is a diagram showing calculation results of saturated output power of a Doherty amplifier according to a comparative example. [Figure 8] FIG. 4 is a diagram showing calculation results of saturated output power of the Doherty amplifier according to the first embodiment. [Figure 9] FIG. 10 is a diagram illustrating an inter-stage matching circuit according to a first modification of the first embodiment. [Figure 10] FIG. 10 is a diagram illustrating an inter-stage matching circuit according to a second modification of the first embodiment. [Figure 11] FIG. 10 is a diagram illustrating an inter-stage matching circuit according to a third modification of the first embodiment. [Figure 12] FIG. 10 is a diagram illustrating an inter-stage matching circuit according to a fourth modification of the first embodiment. [Figure 13] FIG. 10 is a plan view of a Doherty amplifier according to a second embodiment. [Figure 14] FIG. 10 is a plan view of a Doherty amplifier according to a modification of the second embodiment. [Figure 15] FIG. 10 is a plan view of a Doherty amplifier according to a third embodiment. [Figure 16] FIG. 10 is a plan view of a Doherty amplifier according to a fourth embodiment. [Figure 17] FIG. 13 is a plan view of a Doherty amplifier according to a modification of the fourth embodiment. [Figure 18] FIG. 10 is a plan view of a Doherty amplifier according to a fifth embodiment. [Figure 19] 1A and 1B illustrate a structure of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0012] The Doherty amplifier according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the repeated description may be omitted.

[0013] Embodiment 1 FIG. 1 is a plan view of a Doherty amplifier 100 according to a first embodiment. FIG. 2 is a circuit diagram of the Doherty amplifier 100 according to the first embodiment. The Doherty amplifier 100 is used, for example, in wireless communication. The Doherty amplifier 100 includes an input terminal 1 and an output terminal 2. A first main transistor 40 is provided in a first signal path P1 connecting the input terminal 1 and the output terminal 2. A second main transistor 42 is provided in the first signal path P1, closer to the output terminal 2 than the first main transistor 40. A first peak transistor 41 is provided in a second signal path P2 connecting the input terminal 1 and the output terminal 2. A second peak transistor 43 is provided in the second signal path P2, closer to the output terminal 2 than the first peak transistor 41.

[0014] The first peak transistor 41 and the first main transistor 40 are formed on the semiconductor chip 20. The second peak transistor 43 and the second main transistor 42 are formed on the semiconductor chip 22. That is, the first peak transistor 41 and the first main transistor 40 are formed on the same semiconductor substrate. Also, the second peak transistor 43 and the second main transistor 42 are formed on the same semiconductor substrate.

[0015] In the first signal path P1, a first inter-stage matching circuit 50 is provided between the first main transistor 40 and the second main transistor 42. In the second signal path P2, a second inter-stage matching circuit 51 is provided between the first peak transistor 41 and the second peak transistor 43. The first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on the semiconductor chip 21. That is, the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on the same semiconductor substrate.

[0016] The Doherty amplifier 100 is integrated on a resin substrate 10. The input terminal 1 is connected to a circuit 30 formed on the resin substrate 10. The circuit 30 is composed of a distribution circuit 70, an input delay line 80, an input matching circuit 90 for the main transistor, and an input matching circuit 91 for the peak transistor. The circuit 30 is connected to the gate terminal of the first main transistor 40 and the gate terminal of the first peak transistor 41 via bonding wires 60 and 64, respectively.

[0017] The semiconductor chip 20, the semiconductor chip 21, and the semiconductor chip 22 are die-bonded to the die pad 11. The semiconductor chip 20 and the semiconductor chip 21 are connected by bonding wires 61 and 65. The semiconductor chip 21 and the semiconductor chip 22 are connected by bonding wires 62 and 66. The drain terminal of the second main transistor 42 and the drain terminal of the second peak transistor 43 are connected to a circuit 31 formed on the resin substrate 10 by bonding wires 63 and 67, respectively. The circuit 31 is composed of a combining circuit 71, an output delay line 81, an output matching circuit 92 of the main transistor, and an output matching circuit 93 of the peak transistor. The circuit 31 is connected to the output terminal 2.

[0018] The semiconductor chips 20 and 22 are formed of, for example, a SiC substrate. The first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 are, for example, GaN-HEMTs (High Electron Mobility Transistors). The first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 have a parasitic capacitance Cds between their source and drain.

[0019] The semiconductor chip 21 is formed from an inexpensive substrate such as GaAs or Si. For example, an MIM capacitor is integrated on the semiconductor chip 21. The first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are each composed of, for example, two parallel capacitors, one series capacitor, and one series inductor. The first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 may be designed taking into account the parasitic inductance of the bonding wires 61, 62, 65, and 66.

[0020] The resin substrate 10 is made of a material such as FR4. The thickness of the resin substrate 10 is 200 to 500 μm. By making the resin substrate 10 thinner, the thermal resistance of the transistor can be reduced. On the other hand, by making the resin substrate 10 thicker, multi-layer wiring becomes possible. This increases the degree of circuit integration, making it possible to reduce the size and cost. Note that the drain bias circuit and gate bias circuit are omitted in FIGS. 1 and 2.

[0021] High-efficiency, low-distortion Doherty amplifiers are used, for example, as transmission power amplifiers in communication base stations. In a Doherty amplifier 100, a main transistor biased to class AB or class B and a peak transistor biased to class C are combined in parallel using a λ / 4 line. The λ / 4 line is placed at the output of one amplifier and the input of the other amplifier. The λ / 4 lines correspond to an input delay line 80 and an output delay line 81.

[0022] When a large signal is input, the main transistor and peak transistor operate in the same manner and are combined in phase. This provides the same characteristics as a two-combined amplifier, enabling a large saturated output power. On the other hand, when a small signal is input, only the main transistor operates, and the λ / 4 line connected to the output side of the main transistor functions as an impedance inverter. This allows for high efficiency due to the high load impedance. As a result, the Doherty amplifier 100 can achieve high efficiency over a wide output power range.

[0023] Figure 3 is a diagram explaining the pass phase of a Doherty amplifier. Figure 3 shows the pass phase at each circuit end face of a two-stage Doherty circuit. The pass phase of the entire first signal path P1 on the main transistor side is θmain. θMI is the pass phase from the input signal terminal to the input end of the first-stage transistor chip. θM1 is the pass phase of the first-stage transistor chip. θM2 is the pass phase of the inter-stage matching circuit. θM3 is the pass phase of the final-stage transistor chip. θMO is the pass phase from the output end of the final-stage transistor to the combining point. θmain is the sum of θMI, θM1, θM2, θM3, and θMO.

[0024] Similarly, the pass phase of the entire second signal path P2 on the peak transistor side is θpeak. θPI is the pass phase from the input signal terminal to the input terminal of the first-stage transistor chip. θP1 is the pass phase of the first-stage transistor chip. θP2 is the pass phase of the inter-stage matching circuit. θP3 is the pass phase of the final-stage transistor chip. θPO is the pass phase from the output terminal of the final-stage transistor to the combining point. θ peak is the sum of θPI, θP1, θP2, θP3, and θPO.

[0025] In a Doherty amplifier, θmain and θpeak must be the same in order for the signal amplified in the first signal path P1 and the signal amplified in the second signal path P2 to be power-combined without loss. If a phase difference occurs between the two, a combining loss occurs, and the saturated output power of the Doherty amplifier decreases.

[0026] Next, a comparative example of this embodiment will be described. An example of a Doherty amplifier is an MMIC (Monolithic Microwave Integrated Circuit), in which most of a two-stage Doherty amplifier circuit is integrated onto a single semiconductor chip. In the millimeter-wave band, the circuit size is generally not negligible compared to the wavelength. For this reason, the Doherty amplifier must be configured as a distributed constant circuit. An MMIC allows for manufacturing with precise dimensional accuracy. It also allows for miniaturization of the Doherty amplifier. However, when using a high-performance semiconductor substrate such as GaN on SiC, the chip area of an MMIC is large, which may increase manufacturing costs.

[0027] 4 is a plan view of a Doherty amplifier 800 according to a first comparative example. In the Doherty amplifier 800, the first main transistor 40, the first inter-stage matching circuit 50, and the second main transistor 42 are integrated on separate semiconductor chips 20a to 22a, respectively. The first peak transistor 41, the second inter-stage matching circuit 51, and the second peak transistor 43 are integrated on separate semiconductor chips 20b to 22b, respectively. In this case, the matching circuit can be integrated on an inexpensive GaAs or Si substrate, and only the transistors can be integrated on a high-performance semiconductor substrate. This allows for cost reduction while maintaining performance in low-frequency bands such as the L-band and S-band.

[0028] Fig. 5 is a plan view of a Doherty amplifier 900 according to a second comparative example. Fig. 6 is a circuit diagram of the Doherty amplifier 900 according to the second comparative example. In the Doherty amplifier 900, the first main transistor 40, the inter-stage matching circuit 50a, and the second main transistor 42 are integrated on a single semiconductor chip 23. Furthermore, the first peak transistor 41, the inter-stage matching circuit 51a, and the second peak transistor 43 are integrated on a single semiconductor chip 24. This configuration also enables the Doherty amplifier 900 to be miniaturized.

[0029] In the Doherty amplifiers 800 and 900, semiconductor manufacturing variations can cause the transistor Cds and the matching circuit MIM capacitance to simultaneously increase in the first signal path P1, and the transistor Cds and the matching circuit MIM capacitance to simultaneously decrease in the second signal path P2. When the capacitance increases, the passing phase lags, and when the capacitance decreases, the passing phase advances. In other words, θM1, θM2, and θM3 all increase, and θP1, θP2, and θP3 all decrease, which can result in a very large passing phase difference Δ between θmain and θpeak. When this occurs, the saturated output power decreases.

[0030] In contrast, in this embodiment, the final-stage transistors, the inter-stage matching circuits, and the initial-stage transistors are each integrated onto a single semiconductor chip. Generally, variations within the same chip are similar. Therefore, θM1-θP1, θM2-θP2, and θM3-θP3 are close to zero even if there are variations in Cds or MIM capacitance. Therefore, the passing phase difference Δ due to manufacturing variations can be suppressed, and a decrease in saturated output power can be suppressed. Furthermore, in this embodiment, since the Doherty amplifier 100 is composed of multiple semiconductor chips, manufacturing costs can be reduced compared to an MMIC.

[0031] Next, calculation results of the variation in the RF characteristics of the Doherty amplifier will be described. FIG. 7 is a diagram showing calculation results of the saturated output power of the Doherty amplifier 900 according to the comparative example. FIG. 8 is a diagram showing calculation results of the saturated output power of the Doherty amplifier 100 according to the first embodiment. In the Doherty amplifier 900 according to the comparative example, it was assumed that the inductance of the bonding wires connecting the semiconductor chips to each other is integrated on the semiconductor chip. The variation elements are the Cds of the first main transistor 40, the second main transistor 42, the first peak transistor 41, and the second peak transistor 43, and the MIM capacitance of the inter-stage matching circuit. Calculations were performed for a case where each variation element fluctuated by ±15% from the design center.

[0032] 7 and 8, the Cds and MIM capacitance within the chips are indicated by a plus sign if they vary to the larger side, a minus sign if they vary to the smaller side, and a "typical" sign if they are the center value. In the Doherty amplifier 900 according to the comparative example, the pass phase difference is 0 degrees and the saturated output power is 47.5 dBm at the center of the design. When the Cds and MIM capacitance of the semiconductor chips 23 and 24 both vary to the plus or minus, the pass phase difference is 20 degrees and the saturated output power decreases by only 0.2 dB. However, when the variations in the semiconductor chips 23 and 24 are in opposite directions, the pass phase difference is 102 degrees or more and the saturated output power decreases by 0.9 dB or more.

[0033] On the other hand, in the Doherty amplifier 100 according to this embodiment, even when all combinations of variations are taken into consideration, the maximum value of the passing phase difference is 22 degrees, and the maximum decrease in saturated output power is 0.3 dB. As described above, it can be seen that this embodiment can suppress the fluctuation in the passing phase difference Δ and the decrease in saturated output power.

[0034] As a modification of the present embodiment, first inter-stage matching circuit 50 and second inter-stage matching circuit 51 may be formed on separate semiconductor chips. In this case as well, by integrating the initial stage transistors and the final stage transistors onto a single semiconductor chip, it is possible to suppress fluctuations in passing phase difference Δ compared to Doherty amplifier 900.

[0035] Moreover, the second main transistor 42 and the second peak transistor 43 may be formed on separate semiconductor chips. In this case as well, the first main transistor 40 and the first peak transistor 41 are formed on one semiconductor chip 20, and the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on one semiconductor chip 21, thereby making it possible to suppress fluctuations in the passing phase difference Δ.

[0036] Similarly, the first main transistor 40 and the first peak transistor 41 may be formed on separate semiconductor chips. In this case as well, the second main transistor 42 and the second peak transistor 43 are formed on one semiconductor chip 22, and the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the passing phase difference Δ. In this way, some of the circuits in FIG. 1 may be formed on separate chips depending on the allowable passing phase difference Δ.

[0037] In this embodiment, the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on one semiconductor chip 21. However, the present invention is not limited to this, and the input matching circuits of the main transistor and the peak transistor may be formed on one semiconductor chip. Also, the output matching circuits of the main transistor and the peak transistor may be formed on one semiconductor chip.

[0038] The configurations of first inter-stage matching circuit 50 and second inter-stage matching circuit 51 are not limited, and may be different as long as they have the same functions as the circuit shown in FIG. 2. FIG. 9 is a diagram illustrating an inter-stage matching circuit according to a first modified example of embodiment 1. FIG. 10 is a diagram illustrating an inter-stage matching circuit according to a second modified example of embodiment 1. FIG. 11 is a diagram illustrating an inter-stage matching circuit according to a third modified example of embodiment 1. FIG. 12 is a diagram illustrating an inter-stage matching circuit according to a fourth modified example of embodiment 1. As shown in FIGS. 9 to 12, first inter-stage matching circuit 50 and second inter-stage matching circuit 51 may be, for example, a π-type circuit, a T-type circuit, or a combination thereof. Furthermore, first inter-stage matching circuit 50 and second inter-stage matching circuit 51 may be different circuits. For example, first inter-stage matching circuit 50 may be the circuit shown in FIG. 9, and second inter-stage matching circuit 51 may be the circuit shown in FIG. 10.

[0039] The configuration of circuit 30 is not limited as long as it has the same function as the circuit shown in Figure 2. The same applies to circuit 31. Furthermore, Doherty amplifier 100 may be a symmetric Doherty amplifier, or an asymmetric Doherty amplifier in which the main transistor and the peak transistor have different total gate widths. Die pad 11 is not limited to being located on resin substrate 10, but may also be formed on resin substrate 10 and provided in an opening where the heat sink is exposed.

[0040] The above-described modifications can be applied as appropriate to the Doherty amplifiers according to the following embodiments. Note that the Doherty amplifiers according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0041] Embodiment 2 13 is a plan view of a Doherty amplifier 200 according to the second embodiment. In this embodiment, the first main transistor 40, the first peak transistor 41, the second main transistor 42, and the second peak transistor 43 are formed on a semiconductor chip 220. An input matching circuit 52 for the main transistors and an input matching circuit 53 for the peak transistors are formed on the same semiconductor chip 221 as the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51. The input matching circuits 52 and 53 are parts of input matching circuits 90 and 91, respectively. The input matching circuits 52 and 53 are connected to the circuit 30 via bonding wires 68 and 69. The other configurations are the same as those of the first embodiment.

[0042] The first main transistor 40 and the first peak transistor 41 of the initial stage are arranged outside the second main transistor 42 and the second peak transistor 43 of the final stage. In addition, the input matching circuits 52 and 53 are arranged outside the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51.

[0043] In this embodiment as well, it is possible to suppress the passing phase difference Δ due to manufacturing variations and to suppress a decrease in saturated output power. Moreover, in this embodiment, the number of chips can be reduced compared to the first embodiment, and therefore the Doherty amplifier 200 can be further miniaturized.

[0044] 14 is a plan view of a Doherty amplifier 300 according to a modification of the second embodiment. The first main transistor 40 and the first peak transistor 41 in the initial stage may be arranged inside the second main transistor 42 and the second peak transistor 43 in the final stage. In this case, the input matching circuits 52 and 53 are arranged inside the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51. In this modification, the final-stage transistors, which tend to become hot during operation, can be arranged apart from each other. This makes it possible to suppress an increase in the channel temperature of the final-stage transistors, enabling operation at high ambient temperatures.

[0045] Embodiment 3 15 is a plan view of a Doherty amplifier 400 according to embodiment 3. In this embodiment, the second peak transistor 43 and the first main transistor 40 are formed on a semiconductor chip 420, and the first peak transistor 41 and the second main transistor 42 are formed on a semiconductor chip 422. In this embodiment, the signal paths of the main transistor and the peak transistor are opposite to each other on the semiconductor chip.

[0046] Furthermore, the first main transistor 40 and the first peak transistor 41 may have the same gate width, and the second main transistor 42 and the second peak transistor 43 may have the same gate width.

[0047] A signal from input terminal 1 is input to first peak transistor 41 via distribution circuit 101 and input matching delay circuit 102. Input matching delay circuit 102 has the functions of an input matching circuit and a delay circuit. In addition, the signal from input terminal 1 is input to first main transistor 40 via distribution circuit 101 and input matching circuit 103. The functions of distribution circuit 101, input matching delay circuit 102, and input matching circuit 103 are similar to those of circuit 30.

[0048] The signal from the second main transistor 42 is output from the output terminal 2 via the output matching delay circuit 104 and the combiner circuit 106. The output matching delay circuit 104 has the functions of an output matching circuit and a delay circuit. The signal from the second peak transistor 43 is output from the output terminal 2 via the output matching circuit 105 and the combiner circuit 106. The functions of the output matching delay circuit 104, the output matching circuit 105, and the combiner circuit 106 are similar to those of the circuit 31.

[0049] In this embodiment, even if there are variations in Cds or MIM capacitance, θM3−θP1, θM2−θP2, and θM1−θP3 can be suppressed. Therefore, the passing phase difference Δ due to manufacturing variations can be suppressed, and a decrease in saturated output power can be suppressed.

[0050] Furthermore, the first main transistor 40 and the first peak transistor 41 have the same transistor size, and the second main transistor 42 and the second peak transistor 43 have the same transistor size. Therefore, semiconductor chips of the same type or specifications can be used as the semiconductor chip 420 and the semiconductor chip 422. In other words, the semiconductor chip 420 and the semiconductor chip 422 can be obtained from the same wafer.

[0051] By using adjacent chips on a wafer as the semiconductor chip 420 and the semiconductor chip 422, for example, it is possible to further suppress semiconductor manufacturing variations between chips. Furthermore, while in the first embodiment it was necessary to prepare two types of semiconductor chips 20 and 22, in this embodiment it is sufficient to prepare one type of semiconductor chip 420 and 422. Therefore, productivity can be improved.

[0052] As a modification of the present embodiment, the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 may be formed on separate semiconductor chips. In this case as well, by integrating the first main transistor 40 and the second peak transistor 43, and the second main transistor 42 and the first peak transistor 41 on a single semiconductor chip, it is possible to suppress fluctuations in the passing phase difference Δ compared to the Doherty amplifier 900.

[0053] Furthermore, the second main transistor 42 and the first peak transistor 41 may be formed on separate semiconductor chips. In this case as well, the first main transistor 40 and the second peak transistor 43 are formed on one semiconductor chip 420, and the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on one semiconductor chip 21, thereby making it possible to suppress fluctuations in the passing phase difference Δ.

[0054] Similarly, the first main transistor 40 and the second peak transistor 43 may be formed on separate semiconductor chips. In this case as well, the second main transistor 42 and the first peak transistor 41 are formed on one semiconductor chip 422, and the first inter-stage matching circuit 50 and the second inter-stage matching circuit 51 are formed on one semiconductor chip 21, thereby suppressing fluctuations in the passing phase difference Δ. In this way, some of the circuits in FIG. 15 may be formed on different chips depending on the allowable passing phase difference Δ.

[0055] Embodiment 4 16 is a plan view of a Doherty amplifier 500 according to a fourth embodiment. This embodiment differs from the first embodiment in that the bonding wires connecting the semiconductor chips via the first signal path P1 and the bonding wires connecting the semiconductor chips via the second signal path P2 are non-parallel. The other configurations are the same as those of the first embodiment. In this embodiment, bonding wires 60 and 64, bonding wires 61 and 65, bonding wires 62 and 66, and bonding wires 63 and 67 are non-parallel to each other.

[0056] The spacing between the bonding wires is narrower on the side of the semiconductor chips 20 and 22 on which transistors are integrated. In other words, the spacing between the bonding wires 61 and 65 connecting the semiconductor chip 20 and the semiconductor chip 21 adjacent to the semiconductor chip 20 becomes wider as they approach the semiconductor chip 21. Similarly, the spacing between the bonding wires 62 and 66 connecting the semiconductor chip 22 and the semiconductor chip 21 adjacent to the semiconductor chip 22 becomes wider as they approach the semiconductor chip 21.

[0057] When two transistors are integrated on a single semiconductor chip, the transistors are adjacent to each other. As a result, the bonding wires connected to the transistors are also adjacent to each other. The electromagnetic fields of adjacent bonding wires may couple, degrading RF characteristics. In this embodiment, adjacent bonding wires are arranged non-parallel, thereby suppressing electromagnetic field coupling between wires while reducing chip size.

[0058] Furthermore, by narrowing the spacing between the bonding wires on the semiconductor chips 20 and 22 side, it is possible to reduce the size of the semiconductor chips 20 and 22. This allows the Doherty amplifier 500 to be manufactured at low cost.

[0059] 17 is a plan view of a Doherty amplifier 600 according to a modification of the fourth embodiment. The spacing between the bonding wires may be wider on the side of the semiconductor chips 20 and 22 on which the transistors are integrated. The non-parallel bonding wires of this embodiment may also be applied to the second and third embodiments.

[0060] Embodiment 5 18 is a plan view of a Doherty amplifier 700 according to the fifth embodiment. In this embodiment, the second peak transistor 743 is longer in the signal propagation direction than the second main transistor 42. The signal propagation direction is the direction from the input terminal 1 to the output terminal 2 in FIG. 18. The drain pad 122 of the second main transistor 42 is provided on the signal propagation direction side of the second main transistor 42. The drain pad 121 of the second peak transistor 743 is provided adjacent to the second peak transistor 743 in a direction perpendicular to the signal propagation direction.

[0061] The output of the second peak transistor 743 is connected to a drain pad 121 disposed perpendicular to the gate pad via a lead line 120. A bonding wire 67 connected to the drain pad 121 is connected to the circuit 31 via a pad 123. The bonding wire 67 connected to the drain pad 121 of the second peak transistor 743 is inclined by 90 degrees or more with respect to the bonding wire 63 connected to the drain pad of the second main transistor 42. The other configurations are the same as those of the fourth embodiment.

[0062] The Doherty amplifier 700 of the present embodiment is an asymmetric Doherty amplifier in which the total gate width of the second peak transistor 743 is larger than the total gate width of the second main transistor 42. The asymmetric Doherty amplifier can achieve higher efficiency at lower output power than the symmetric Doherty amplifier.

[0063] FIG. 19 is a diagram illustrating the structure of a transistor. In FIG. 19, D represents the drain, S represents the source, G represents the gate, and W1 represents the unit gate width. The total gate width is the product of the unit gate width W1 and the number of gates. The longer the unit gate width W1, the longer the transistor is in the signal propagation direction. Increasing the number of gates makes the transistor longer in the direction perpendicular to the signal propagation direction. In this embodiment, the second main transistor 42 and the second peak transistor 743 have the same number of gates but different unit gate widths W1.

[0064] When transistors with different unit gate widths W1 are integrated on a single semiconductor chip, there is a problem of a gap occurring due to the difference in unit gate width W1. In this embodiment, the output signal of the second peak transistor 743 is routed to the center of the semiconductor chip 22 using a thin lead-out line 120. This allows a drain pad 121 to be provided between the second main transistor 42 and the second peak transistor 743. This prevents the semiconductor chip 22 from becoming longer in the signal propagation direction, and also reduces the gap due to the difference in unit gate width. Furthermore, a wide gap can be secured between the bonding wires 62 and 66, thereby suppressing electromagnetic field coupling. Furthermore, electromagnetic field coupling between the bonding wires 63 and 68 can also be suppressed.

[0065] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0066] 1 input terminal, 2 output terminal, 10 resin substrate, 11 die pad, 20, 20a, 21, 22, 22a, 23, 24 semiconductor chip, 30, 31 circuit, 40 first main transistor, 41 first peak transistor, 42 second main transistor, 43 second peak transistor, 50 first inter-stage matching circuit, 50a inter-stage matching circuit, 51 second inter-stage matching circuit, 51a inter-stage matching circuit, 52, 53 input matching circuit, 60-68 bonding wire, 70 distribution circuit, 71 combining circuit, 80 input delay line, 81 output delay line, 90, 91 input matching circuit, 92, 93 output matching circuit, 100 Doherty amplifier, 101 distribution circuit, 102 input matching delay circuit, 103 input matching circuit, 104 output matching delay circuit, 105 output matching circuit, 106 combining circuit, 120 Line, 121, 122 drain pad, 123 pad, 200 Doherty amplifier, 220, 221 semiconductor chip, 300, 400 Doherty amplifier, 420, 422 semiconductor chip, 500, 600, 700 Doherty amplifier, 743 second peak transistor, 800, 900 Doherty amplifier, Cds parasitic capacitance, P1 first signal path, P2 second signal path, W1 unit gate width, Δ passing phase difference

Claims

1. An input terminal, An output terminal; a first main transistor provided in a first signal path connecting the input terminal and the output terminal; a second main transistor provided in the first signal path closer to the output terminal than the first main transistor; a first peak transistor provided in a second signal path connecting the input terminal and the output terminal; a second peak transistor provided in the second signal path closer to the output terminal than the first peak transistor; Equipped with the second peak transistor and the first main transistor are formed on a first semiconductor chip; The first peak transistor and the second main transistor are formed on a second semiconductor chip.

2. the first main transistor and the first peak transistor have the same gate width; 2. The Doherty amplifier according to claim 1, wherein the second main transistor and the second peak transistor have the same gate width.

3. 3. The Doherty amplifier according to claim 2, wherein the first semiconductor chip and the second semiconductor chip are the same type of semiconductor chip.

4. 2. The Doherty amplifier according to claim 1, wherein a first bonding wire connecting the semiconductor chips in the first signal path and a second bonding wire connecting the semiconductor chips in the second signal path are non-parallel to each other.

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