Display substrate and display device

Abstract

In the display substrate and display device, the display substrate (01) includes a display area (10). The display area (10) includes a first display area (11), a second display area (12), and a first connecting line (110). The first display area (11) includes a first light-emitting element (411). The second display area (12) includes a first pixel circuit (412). The first connecting line (110) is electrically connected to a first sub-pixel circuit (412a) and an anode of a first sub-light-emitting element (411a). The first connecting line (110) is located on a first connecting layer (21), and the anode of the first sub-light-emitting element (411a) is electrically connected to the first connecting line (110) through a first via (H1) that penetrates a first insulating layer (31) and a second insulating layer (32). The cross section of the first via (H1) in a plane perpendicular to the display substrate (01) is an inverted boss shape, and the opening diameter of the second insulating layer (32) in the first via (H1) is larger than the opening diameter of the first insulating layer (31). The anode of the first sub-light-emitting element (411a) includes a first groove structure (GR1) located in the first via (H1), and the bottom of the first groove structure (GR1) contacts and is electrically connected to the first connecting line (110). This display substrate (01) can reduce processing difficulties and improve the reliability of electrical connection and the uniformity of transmitted light.

Description

[Technical Field]

[0001] This application claims priority from Chinese Patent Application No. 202010580274.8 filed on June 23, 2020, the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0003] Organic light-emitting diode (OLED) display devices have various characteristics, such as a wide viewing angle, high contrast, fast response time, wide color gamut, high screen-to-body ratio, self-luminous, light weight, and thinness. Due to these characteristics and advantages, OLED display devices are gradually gaining widespread attention and can be applied to devices with display functions, such as mobile phones, displays, laptops, smart watches, digital cameras, measuring instruments, and flexible wearable devices. With the further development of display technology, display devices with high screen-to-body ratios are no longer able to meet people's needs, and full-screen display devices are becoming the trend for future display technology development. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display substrate including a display area, the display area including a first display area and a second display area that do not overlap each other, the second display area at least partially surrounding the first display area, a light transmittance of the first display area being greater than a light transmittance of the second display area, the first display area including at least one first light emitting element, the second display area including at least one first pixel circuit, the display area further including at least one first connecting line, the first connecting line including a first end located in the first display area and a second end located in the second display area, the at least one first light emitting element including a first sub-light emitting element, the at least one first pixel circuit including a first sub-pixel circuit, and the first connecting line including a first end connected to the first sub-light emitting element. the first end is electrically connected to the anode of the first sub-light-emitting element, and the second end is electrically connected to the first sub-pixel circuit, the display substrate includes a first connection layer, a first insulating layer, a second insulating layer, and an anode layer stacked in sequence, the first connection line is located on the first connection layer, the anode of the first sub-light-emitting element is located on the anode layer, and the anode of the first sub-light-emitting element is electrically connected to the first connection line through a first via that penetrates the first insulating layer and the second insulating layer, the cross-sectional shape of the first via in a plane perpendicular to the display substrate is an inverted boss shape, and in the first via, the opening diameter of the second insulating layer is larger than the opening diameter of the first insulating layer, the anode of the first sub-light-emitting element includes a first groove structure, the first groove structure is located in the first via, and the bottom of the first groove structure contacts and is electrically connected to the first connection line.

[0005] For example, in a display substrate according to an embodiment of the present disclosure, the display area further includes at least one second connecting line, the second connecting line including a first end located in the first display area and a second end located in the second display area, the at least one first light-emitting element further includes a second sub-light-emitting element, the at least one first pixel circuit further includes a second sub-pixel circuit, and the second connecting line has a first end electrically connected to an anode of the second sub-light-emitting element and a second end electrically connected to the second sub-pixel circuit, The display substrate further includes a second connection layer, the second connection layer being located between the first insulating layer and the second insulating layer, the second connecting line being located on the second connection layer, the anode of the second sub-light-emitting element being located on the anode layer, the anode of the second sub-light-emitting element being electrically connected to the second connecting line through a second via penetrating the second insulating layer, the anode of the second sub-light-emitting element including a second groove structure, the second groove structure being located in the second via, and the bottom of the second groove structure being in contact with and electrically connected to the second connecting line.

[0006] For example, in a display substrate according to an embodiment of the present disclosure, the surface of the first groove structure facing away from the first connecting layer is curved, and the surface of the second groove structure facing away from the second connecting layer is curved.

[0007] For example, in a display substrate according to one embodiment of the present disclosure, each of the first subpixel circuit and the second subpixel circuit includes a first switching transistor, the first switching transistor including a gate, a first pole, and a second pole; the display substrate further includes a source-drain metal layer and a third insulating layer, the third insulating layer being located on the source-drain metal layer, the first connection layer being located on the third insulating layer, the first pole and the second pole of the first switching transistor being located on the source-drain metal layer; a second end of the first connecting line being electrically connected to the first pole or the second pole of the first switching transistor of the first subpixel circuit through a third via that penetrates the third insulating layer; and a second end of the second connecting line being electrically connected to the first pole or the second pole of the first switching transistor of the second subpixel circuit through a fourth via that penetrates the third insulating layer and the first insulating layer.

[0008] For example, in a display substrate according to one embodiment of the present disclosure, the cross-sectional shape of the fourth via in a plane perpendicular to the display substrate is an inverted boss shape, and in the fourth via, the opening diameter of the first insulating layer is larger than the opening diameter of the third insulating layer.

[0009] For example, in a display substrate according to one embodiment of the present disclosure, in the fourth via, the second connecting line contacts and is electrically connected to a transition metal layer, and the transition metal layer contacts and is electrically connected to a first pole or a second pole of a first switching transistor of the second sub-pixel circuit, and the transition metal layer and the first connecting layer are formed in the same process.

[0010] For example, in a display substrate according to one embodiment of the present disclosure, the second display region further includes at least one second light-emitting element and at least one second pixel circuit, the second light-emitting element is electrically connected to the second pixel circuit, the second pixel circuit includes a second switching transistor, the second switching transistor includes a gate, a first pole, and a second pole, the first pole and the second pole of the second switching transistor are located on the source-drain metal layer, the anode of the second light-emitting element is located on the anode layer, the anode of the second light-emitting element is electrically connected to the first pole or the second pole of the second switching transistor through a fifth via that penetrates the first insulating layer, the second insulating layer, and the third insulating layer, the cross-sectional shape of the fifth via in a plane perpendicular to the display substrate is an inverted boss shape, and the opening diameter of the first insulating layer in the fifth via is larger than the opening diameter of the third insulating layer.

[0011] For example, in a display substrate according to an embodiment of the present disclosure, the opening diameter of the fifth via in the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.

[0012] For example, in a display substrate according to one embodiment of the present disclosure, the anode of the second light-emitting element includes a third groove structure, the third groove structure is located within the fifth via, and the bottom of the third groove structure contacts and is electrically connected to the first pole or the second pole of the second switching transistor.

[0013] the first and second poles of the third switching transistor are located on the source-drain metal layer; an anode of the third light-emitting element is located on the anode layer; the anode of the third light-emitting element is electrically connected to the first or second pole of the third switching transistor through a sixth via that penetrates the first insulating layer, the second insulating layer, and the third insulating layer; a cross-sectional shape of the sixth via in a plane perpendicular to the display substrate is an inverted boss shape; and an opening diameter of the sixth via in the first insulating layer is larger than an opening diameter of the third insulating layer.

[0014] For example, in a display substrate according to an embodiment of the present disclosure, the opening diameter of the sixth via in the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.

[0015] For example, in a display substrate according to one embodiment of the present disclosure, the anode of the third light-emitting element includes a fourth groove structure, the fourth groove structure is located within the sixth via, and the bottom of the fourth groove structure is in contact with and electrically connected to the first pole or the second pole of the third switching transistor.

[0016] For example, in a display substrate according to an embodiment of the present disclosure, the first connecting line and the second connecting line each include a transparent conductive wire.

[0017] For example, in a display substrate according to one embodiment of the present disclosure, the at least one first light-emitting element includes a plurality of first light-emitting elements arranged in an array, and both the first connecting line and the second connecting line extend along the row direction of the array consisting of the plurality of first light-emitting elements.

[0018] For example, in a display substrate according to an embodiment of the present disclosure, the first light emitting element, the second light emitting element, and the third light emitting element each include an organic light emitting diode.

[0019] For example, in a display substrate according to one embodiment of the present disclosure, the at least one first light-emitting element includes a plurality of first light-emitting elements, the at least one second light-emitting element includes a plurality of second light-emitting elements, and the at least one third light-emitting element includes a plurality of third light-emitting elements, and the distribution density per unit area of the plurality of first light-emitting elements in the first display region is equal to or less than the distribution density per unit area of the plurality of second light-emitting elements in the second display region, and the distribution density per unit area of the plurality of second light-emitting elements in the second display region is smaller than the distribution density per unit area of the plurality of third light-emitting elements in the third display region.

[0020] At least one embodiment of the present disclosure further provides a display device including the display substrate according to any embodiment of the present disclosure.

[0021] For example, a display device according to one embodiment of the present disclosure further includes a sensor, wherein the display substrate has a first side for display and a second side opposite to the first side, the first display area allows light from the first side to be at least partially transmitted to the second side, and the sensor is disposed on the second side of the display substrate and configured to receive light from the first side.

[0022] For example, in a display device according to an embodiment of the present disclosure, the orthogonal projection of the sensor on the display substrate at least partially overlaps with the first display area.

[0023] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be apparent that the drawings described below do not limit the present disclosure, but only relate to some embodiments of the present disclosure. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of the first display region and the second display region of the display substrate shown in FIG. [Figure 3] FIG. 3 shows an example of the first display area and the second display area of the display substrate shown in FIG. [Figure 4] FIG. 4 is an enlarged view of the partial region REG1 of FIG. [Figure 5A] FIG. 5A is an enlarged view of a partial region REG2 in FIG. [Figure 5B] FIG. 5B is an enlarged view of a region in FIG. 5A that includes only one column of first pixel circuits, one column of first light-emitting elements, one column of second pixel circuits, and one column of second light-emitting elements. [Figure 6A] FIG. 6A is a schematic cross-sectional view taken along line AA' in FIG. 5B. [Figure 6B] FIG. 6B is an enlarged view of the first via H1 in FIG. 6A. [Figure 6C] FIG. 6C is a schematic layout of the area corresponding to the first via H1 and the connected anode in FIG. 6A. [Figure 6D] FIG. 6D is a schematic layout of the area corresponding to the third via H3 and the connected source / drain metal layer in FIG. 6A. [Figure 7A] FIG. 7A is a schematic cross-sectional view taken along line BB' in FIG. 5B. [Figure 7B] FIG. 7B is an enlarged view of the second via H2 in FIG. 7A. [Figure 7C] FIG. 7C is a schematic layout of the area corresponding to the second via H2 and the connected anode in FIG. 7A. [Figure 7D] FIG. 7D is another structural schematic diagram of the fourth via H4. [Figure 7E] FIG. 7E is a schematic layout of the area corresponding to the fourth via H4 and the connected source-drain metal layer in FIG. 7A. [Figure 8A] FIG. 8A is a schematic cross-sectional view taken along line CC' in FIG. 5B. [Figure 8B] FIG. 8B is an enlarged view of the fifth via H5 in FIG. 8A. [Figure 8C] FIG. 8C is a schematic layout of the area corresponding to the fifth via H5 of FIG. 8A and the connected anode and source-drain metal layers. [Figure 9] FIG. 9 is an enlarged view of a partial region REG3 of the third display region of the display substrate shown in FIG. [Figure 10A] FIG. 10A is a schematic cross-sectional view taken along line DD' in FIG. [Figure 10B] FIG. 10B is an enlarged view of the sixth via H6 in FIG. 10A. [Figure 11A] FIG. 11A is a schematic layout corresponding to the partial region REG4 in FIG. [Figure 11B] FIG. 11B is a schematic layout showing only the first connecting line of FIG. 11A. [Figure 11C] FIG. 11C is a schematic layout showing only the second connecting line of FIG. 11A. [Figure 11D] FIG. 11D is a schematic cross-sectional view taken along line EE' in FIG. 11A. [Figure 12A] FIG. 12A is a first schematic layout corresponding to a second light-emitting element in a second display region of a display substrate according to some embodiments of the present disclosure. [Figure 12B] FIG. 12B is a second schematic layout corresponding to the second light-emitting element in the second display region of the display substrate according to some embodiments of the present disclosure. [Figure 13A] FIG. 13A is a structural schematic diagram of a 7T1C pixel circuit. [Figure 13B] FIG. 13B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 13A. [Figure 14] FIG. 14 is a schematic block diagram of a display device in accordance with at least one embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic diagram of a stacked structure of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] In order to clarify the objectives, technical solutions and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that can be obtained by those skilled in the art without requiring creative work fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, technical or scientific terms used in this disclosure have ordinary meanings that can be understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but merely serve to distinguish between different components. Similarly, similar terms such as "one," "an," or "the" do not denote a numerical limitation, but rather mean the presence of at least one. Similar terms such as "comprise" or "include" mean that the element or component listed before the term includes the element or component listed after the term and their equivalents, and do not exclude other elements or components. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but may also include electrical connections, whether directly or indirectly connected. Terms such as "top," "bottom," "left," and "right" are used only to indicate relative positions, and if the absolute position of the described object changes, the relative positions may change accordingly.

[0027] For current display substrates having an in-screen sensor (such as a camera), in order to improve the light transmittance of the display area of the display substrate corresponding to the in-screen sensor (camera), the distribution density per unit area (PPI) of the light-emitting elements in the display area corresponding to the in-screen sensor (camera) may be smaller than the distribution density per unit area of the light-emitting elements in other display areas of the display substrate.

[0028] However, because the distribution density per unit area of light-emitting elements in different regions of the display substrate is different, the arrangement methods of the light-emitting elements and corresponding pixel circuits in different regions are also different, so the wiring method and layout design of the display substrate are different from those of a typical display substrate with uniformly distributed light-emitting elements. As a result, a large number of vias must be installed in the display substrate to achieve electrical connections between film layers. When using a typical via installation method, the presence of many vias in the display substrate affects the stability of the electrical connection, reduces the uniformity of transmitted light, and adversely affects the detection effect of on-screen sensors (such as cameras), thereby degrading the performance of display devices using the display substrate.

[0029] At least one embodiment of the present disclosure provides a display substrate and a display device, which can reduce processing difficulty, improve the reliability of electrical connections, and improve the uniformity of transmitted light, thereby contributing to improving the detection effect of an in-screen sensor (such as a camera).

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, in which the same reference numerals in different drawings represent the same elements being illustrated.

[0031] At least one embodiment of the present disclosure provides a display substrate including a display area. The display area includes a first display area and a second display area that do not overlap each other, the second display area at least partially surrounding the first display area, and the light transmittance of the first display area is greater than that of the second display area. The first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit. The display area further includes at least one first connecting line, the first connecting line having a first end located in the first display area and a second end located in the second display area. The at least one first light-emitting element includes a first sub-light-emitting element, and the at least one first pixel circuit includes a first sub-pixel circuit, the first end of the first connecting line electrically connected to the anode of the first sub-light-emitting element and the second end of the first connecting line electrically connected to the first sub-pixel circuit. The display substrate includes a first connecting layer, a first insulating layer, a second insulating layer, and an anode layer, which are stacked in order. The first connecting line is located on the first connecting layer, the anode of the first sub-light-emitting element is located on the anode layer, and the anode of the first sub-light-emitting element is electrically connected to the first connecting line through a first via that penetrates the first insulating layer and the second insulating layer. The cross-sectional shape of the first via in a plane perpendicular to the display substrate is an inverted boss shape, and the opening diameter of the second insulating layer in the first via is larger than the opening diameter of the first insulating layer. The anode of the first sub-light-emitting element includes a first groove structure that is located in the first via, and the bottom of the first groove structure contacts and is electrically connected to the first connecting line.

[0032] FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1, the display substrate 01 includes a display region 10, which includes a first display region 11, a second display region 12, and a third display region 13. For example, the first display region 11, the second display region 12, and the third display region 13 do not overlap one another. For example, the third display region 13 at least partially surrounds (e.g., partially surrounds) the second display region 12, and the second display region 12 at least partially surrounds (e.g., completely surrounds) the first display region 11. Note that in some examples, the display substrate 01 may further include a peripheral region that at least partially surrounds the third display region 13.

[0033] For example, the light transmittance of the first display region 11 is greater than that of the second display region 12. For example, in some examples, at least the first display region 11 allows light to pass through. For example, the display substrate 01 has a first side for display and a second side opposite to the first side. For example, in some examples, as shown in FIG. 1 , the first side is the front side of the display substrate 01 (i.e., the plane shown in FIG. 1 ), and the second side is the back side of the display substrate 01. For example, a sensor may be installed on the second side of the display substrate 01 at a position corresponding to the first display region 11, and the sensor may be, for example, an image sensor or an infrared sensor. The sensor is configured to receive light from the first side of the display substrate 01, thereby enabling operations such as image capture, distance detection, and light intensity detection. For example, the light may be transmitted through the first display region 11 and irradiated onto the sensor, where it is detected by the sensor.

[0034] Fig. 2 is a schematic plan view of the first display region and the second display region of the display substrate shown in Fig. 1. For example, as shown in Figs. 1 and 2, the second display region 12 at least partially surrounds (e.g., completely surrounds) the first display region 11.

[0035] For example, the shape of the first display area 11 may be circular or elliptical, and the shape of the second display area 12 may be rectangular, but the embodiments of the present disclosure are not limited thereto. For example, the shapes of the first display area 11 and the second display area 12 may both be rectangular or other applicable shapes.

[0036] Fig. 3 shows an example of a first display region and a second display region of the display substrate shown in Fig. 2. Fig. 4 is an enlarged view of a partial region REG1 of Fig. 3, Fig. 5A is an enlarged view of a partial region REG2 of Fig. 3, and Fig. 5B is an enlarged view of a region of Fig. 5A including only one column of first pixel circuits, one column of first light-emitting elements, one column of second pixel circuits, and one column of second light-emitting elements. Note that in order to clearly specify the connection between the first pixel circuits and the first light-emitting elements, Fig. 5B shows adjacent first pixel circuits and first light-emitting elements connected to each other. However, based on Figs. 3, 4, and 5A, it can be understood that another first light-emitting element (not shown) may be further disposed to the left of the first light-emitting element in Fig. 5B, and another first pixel circuit (not shown) may be further disposed to the right of the first pixel circuit.

[0037] For example, as shown in FIGS. 3, 4, 5A, and 5B, the first display region 11 includes at least one (e.g., multiple) first light-emitting elements 411. For clarity, the related drawings schematically illustrate the first light-emitting elements 411 using the anode structure of the first light-emitting elements 411. For example, the first display region 11 includes multiple first light-emitting elements 411 arranged in an array, and the first light-emitting elements 411 are configured to emit light. For example, the first display region 11 does not have pixel circuits, and pixel circuits for driving the first light-emitting elements 411 are installed in the second display region 12. This reduces the metallization area of the first display region 11 and improves the light transmittance of the first display region 11, making the light transmittance of the first display region 11 greater than that of the second display region 12.

[0038] For example, the plurality of first light-emitting elements 411 may be disposed in a plurality of light-emitting units arranged in an array. For example, each light-emitting unit may include one or more first light-emitting elements 411. For example, the plurality of first light-emitting elements 411 may emit light of the same color or different colors, such as white light, red light, blue light, and green light. This may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto. For example, the arrangement of the plurality of first light-emitting elements 411 may refer to the arrangement of common pixel units, such as GGRB, RGBG, and RGB, and the embodiments of the present disclosure are not limited thereto.

[0039] For example, the first display area 11 allows light from a first side of the display substrate 01 to be at least partially transmitted to a second side of the display substrate 01. In this way, a sensor can be easily installed on the second side of the display substrate 01 at a position corresponding to the first display area 11, and the sensor can receive light from the first side, thereby performing operations such as image capture, distance sensing, and light intensity sensing.

[0040] For example, as shown in FIGS. 3, 4, 5A, and 5B, the second display area 12 includes at least one (e.g., multiple) first pixel circuits 412. For example, the first light-emitting elements 411 are electrically connected to the first pixel circuits 412 in a one-to-one correspondence, and the multiple first pixel circuits 412 are used to drive the multiple first light-emitting elements 411 in a one-to-one correspondence. For example, the rectangular blocks (white-painted areas with black frames indicated by reference numeral 412) shown in FIG. 5B represent first pixel driving units, and each first pixel driving unit includes a first pixel circuit 412. For example, the first pixel circuits 412 are configured to drive the multiple first light-emitting elements 411 to emit light in a one-to-one correspondence. That is, one first pixel circuit 412 drives one corresponding first light-emitting element 411, and different first pixel circuits 412 drive different first light-emitting elements 411.

[0041] 3, 4, 5A and 5B, the first pixel driving unit may include one or more first pixel circuits 412. If the light-emitting unit in the first display area 11 includes one first light-emitting element 411, the first pixel driving unit also includes one first pixel circuit 412. If the light-emitting unit in the first display area 11 includes multiple first light-emitting elements 411, the first pixel driving unit also includes multiple first pixel circuits 412, and the number of first light-emitting elements 411 in each light-emitting unit is, for example, equal to the number of first pixel circuits 412 in each first pixel driving unit, thereby realizing one-to-one corresponding driving.

[0042] For example, the plurality of first light-emitting elements 411 are arranged in an array, and the plurality of first pixel circuits 412 are also arranged in an array. Here, the "arrangement in an array" may mean that a plurality of devices are grouped together and the plurality of groups of devices are arranged in an array, or that the plurality of devices themselves are arranged in an array, and the embodiments of the present disclosure are not limited thereto. For example, in some examples, as shown in FIGS. 3, 4, 5A, and 5B, every four first light-emitting elements 411 are grouped together and the plurality of groups of first light-emitting elements 411 are arranged in an array, and correspondingly, every four first pixel circuits 412 are grouped together and the plurality of groups of first pixel circuits 412 are arranged in an array, and in this case, each first pixel driving unit includes four first pixel circuits 412.

[0043] 3, 4, 5A, and 5B, the display area 10 further includes at least one first connecting line 110 and at least one second connecting line 120. The first connecting line 110 has a first end located in the first display area 11 and a second end located in the second display area 12, i.e., the first connecting line 110 extends from the first display area 11 to the second display area 12. Similarly, the second connecting line 120 has a first end located in the first display area 11 and a second end located in the second display area 12, i.e., the second connecting line 120 extends from the first display area 11 to the second display area 12.

[0044] The first light-emitting element 411 includes a first sub-light-emitting element 411a and a second sub-light-emitting element 411b, and the first pixel circuit 412 includes a first sub-pixel circuit 412a and a second sub-pixel circuit 412b. The first connecting line 110 has a first end electrically connected to the anode of the first sub-light-emitting element 411a and a second end electrically connected to the first sub-pixel circuit 412a, and is configured to transmit an electrical signal provided by the first sub-pixel circuit 412a to the anode of the first sub-light-emitting element 411a to drive the first sub-light-emitting element 411a to emit light. The second connecting line 120 has a first end electrically connected to the anode of the second sub-light-emitting element 411b and a second end electrically connected to the second sub-pixel circuit 412b, and is configured to transmit the electrical signal provided by the second sub-pixel circuit 412b to the anode of the second sub-light-emitting element 411b to drive the second sub-light-emitting element 411b to emit light.

[0045] For example, for multiple first light-emitting elements 411 located within the first display area 11, some of the first light-emitting elements 411 (e.g., first sub-light-emitting element 411a) are electrically connected to the first connecting line 110, and other parts of the first light-emitting elements 411 (e.g., second sub-light-emitting element 411b) are electrically connected to the second connecting line 120, so that all of the first light-emitting elements 411 are electrically connected to corresponding first pixel circuits 412 via corresponding connecting lines, thereby realizing driving of the first light-emitting elements 411.

[0046] For example, the first connecting line 110 and the second connecting line 120 are located on different film layers of the display substrate 01, i.e., the first connecting line 110 and the second connecting line 120 are located on two different film layers. Because they are located on different film layers, the orthogonal projection of the first connecting line 110 on the display substrate 01 can overlap with the orthogonal projection of the second connecting line 120 on the display substrate 01, thereby effectively utilizing wiring space, facilitating wiring, and ensuring that all the first light-emitting elements 411 in the first display area 11 are electrically connected to the corresponding connecting lines. Even when there are a large number of first light-emitting elements 411 and corresponding connecting lines, the display substrate 01 can still provide sufficient wiring space.

[0047] Note that different film layers are insulated from each other where no vias are provided. For example, if wiring located on different film layers needs to be electrically connected to each other, the wiring located on the different film layers can be electrically connected by providing vias. For example, these different film layers can be manufactured using different processes, e.g., first manufacturing one of these different film layers in a first process, and then manufacturing the other of these different film layers in a second process. For example, after performing the first process and before performing the second process, an insulating layer can be manufactured in a third process. This insulating layer is located between the different film layers and insulates them from each other where no vias are provided. For example, the first process, the second process, and the third process can be the same or different. For example, if the display substrate 01 includes a base substrate, the distances of the different film layers from the base substrate in the direction perpendicular to the base substrate are different. That is, among the different film layers, one film layer is closer to the base substrate and the other film layer is farther from the base substrate. In the following description, the meaning of different film layers can be referred to the above description, and detailed description will be omitted.

[0048] In addition, in the embodiments of the present disclosure, the connecting lines for realizing the electrical connection between the first light-emitting element 411 and the first pixel circuit 412 are not limited to being located in two different film layers, but may be located in three different film layers, four film layers, or any number of film layers; that is, these connecting lines are not limited to the first connecting line 110 and the second connecting line 120 described above, but may include other connecting lines located in film layers different from the first connecting line 110 and the second connecting line 120, and the embodiments of the present disclosure are not limited to this.

[0049] 5A, a plurality of first connecting lines 110 and a plurality of second connecting lines 120 form a connecting line array, and each connecting line (which may be the first connecting line 110 or the second connecting line 120) of the connecting line array electrically connects one first light-emitting element 411 to one first pixel circuit 412. For example, in order to prevent the difference in length of the plurality of connecting lines from being too large and to improve the balance of the circuit environment, the spacing between the correspondingly connected first light-emitting elements 411 and first pixel circuits 412 can be made substantially close during wiring design. For example, in the example shown in FIG. 5A, a plurality of pixel circuits (including the first pixel circuit 412 and the second pixel circuit 422) are arranged in an array, and a plurality of first light-emitting elements 411 are also arranged in an array. For the pixel circuit and first light-emitting element 411 located in the Qth row, the first pixel circuit 412 in the (P-1)th column and the first light-emitting element 411 in the Wth column are electrically connected via a connecting line (which may be the first connecting line 110 or the second connecting line 120), with a length of, for example, approximately S1. The first pixel circuit 412 in the (P+1)th column and the first light-emitting element 411 in the (W+1)th column are electrically connected via a connecting line (which may be the first connecting line 110 or the second connecting line 120), with a length of, for example, approximately S2. For example, the difference between S1 and S2 is within a predetermined range and is not too large. For example, the specific value of the range of the difference between S1 and S2 may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto. Similarly, the first pixel circuit 412 and the first light-emitting element 411 located in the (Q-1)th row and the (Q-2)th row may use a similar wiring scheme.

[0050] 5A , the difference in length between the first connecting lines 110 is not too large, the difference in length between the second connecting lines 120 is not too large, and the difference in length between the first connecting lines 110 and the second connecting lines 120 is not too large, thereby improving the balance of the circuit environment. Of course, the embodiments of the present disclosure are not limited to the embodiment of FIG. 5A , and the distribution positions of the first pixel circuits 412 and the first light-emitting elements 411 connected by the connecting lines may be different, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0051] The distribution and positional relationship of the plurality of first connecting lines 110 and the plurality of second connecting lines 120 in a plane parallel to the display substrate 01 is not limited and may be determined according to actual wiring needs. For example, in a plane parallel to the display substrate 01, the first connecting lines 110 and the second connecting lines 120 may be spaced apart one by one, spaced apart in groups, or irregularly distributed, and the embodiments of the present disclosure are not limited thereto.

[0052] In addition, in the embodiments of the present disclosure, the first sub-light-emitting element 411a and the second sub-light-emitting element 411b have the same structure and function, and the first sub-pixel circuit 412a and the second sub-pixel circuit 412b have the same structure and function, and the fact that they are called "first" and "second" is merely to distinguish the connecting lines (i.e., the first connecting line 110 and the second connecting line 120) connected to these light-emitting elements and pixel circuits, and does not limit the embodiments of the present disclosure.

[0053] 6A is a schematic cross-sectional view along line A-A' in FIG. 5B, FIG. 6B is an enlarged view of the first via H1 in FIG. 6A, FIG. 6C is a schematic layout of the area corresponding to the first via H1 and the connected anode in FIG. 6A, and FIG. 6D is a schematic layout of the area corresponding to the third via H3 and the connected source-drain metal layer in FIG. 6A.

[0054] 6A to 6D, the display substrate 01 includes a third insulating layer 33, a first connecting layer 21, a first insulating layer 31, a second insulating layer 32, and an anode layer 40, which are sequentially stacked. The first sub-light-emitting element 411a includes an anode 4111, a cathode 4113, and a light-emitting layer 4112 located between the anode 4111 and the cathode 4113. The first connecting line 110 is located on the first connecting layer 21, and the anode 4111 of the first sub-light-emitting element 411a is located on the anode layer 40. The anode 4111 of the first sub-light-emitting element 411a is electrically connected to the first connecting line 110 through a first via H1 that penetrates the first insulating layer 31 and the second insulating layer 32.

[0055] For example, the cross-sectional shape of the first via H1 in a plane perpendicular to the display substrate 01 is an inverted boss shape. In the cross-sectional views shown (e.g., FIGS. 6A and 6B), the inverted boss shape is formed by joining two rectangles of different sizes, with the upper rectangle being larger and the lower rectangle being smaller, thereby forming a staircase on at least one side of the inverted boss shape, e.g., forming staircases on two side surfaces. For example, the orthogonal projection of the portion corresponding to the lower rectangle on the base substrate 74 is completely within the orthogonal projection of the portion corresponding to the upper rectangle on the base substrate 74, and for example, the edges of the orthogonal projection of the portion corresponding to the lower rectangle on the base substrate 74 and the edges of the orthogonal projection of the portion corresponding to the upper rectangle on the base substrate 74 are all spaced apart. For example, in the first via H1, the opening diameter L2 of the second insulating layer 32 is larger than the opening diameter L1 of the first insulating layer 31. For example, the opening diameter L2 of the second insulating layer 32 may be 6 μm×6 μm, or the opening diameter L1 of the first insulating layer 31 may be 6 μm×6 μm. Because the first via H1 needs to penetrate two insulating layers, the first via H1 has a large depth. By setting the first via H1 to an inverted boss shape, the difficulty of processing the first via H1 can be reduced, and it is easy to deposit a conductive material (e.g., the material of the anode 4111) in the first via H1, thereby improving the reliability of the electrical connection.

[0056] For example, the anode 4111 of the first sub-light-emitting element 411a includes a first groove structure GR1, which is located within the first via H1. The bottom of the first groove structure GR1 contacts and is electrically connected to the first connecting line 110. By providing the groove structure for the portion of the anode 4111 deposited within the first via H1, the thickness of this portion can be reduced, and the difference between the thickness of this portion and the thickness of the rest of the anode 4111 can be minimized. This improves the overall uniformity of transmitted light, eliminates significant brightness differences between different regions, and provides good light transmittance to the first display region 11. This further improves the detection effect of an on-screen sensor (such as a camera), e.g., improving imaging clarity. The first via H1 has an inverted boss shape, which facilitates the formation of the groove structure during the manufacturing of the anode 4111, thereby reducing process difficulties.

[0057] For example, in some examples, the surface of the first groove structure GR1 facing away from the first connecting layer 21 is a curved surface. In this way, the light intensity of the transmitted light can be continuously changed, and sudden changes in the light intensity at local positions can be avoided, thereby further improving the uniformity of the transmitted light. Of course, the embodiments of the present disclosure are not limited thereto. In other examples, the surface of the first groove structure GR1 facing away from the first connecting layer 21 can be a flat surface, an inclined surface, etc., which can be determined according to actual needs.

[0058] For example, the anode 4111 may include multiple sub-anode layers, such as an ITO / Ag / ITO three-layer structure (not shown), and the embodiments of the present disclosure do not limit the specific form of the anode 4111. For example, the cathode 4113 may have a structure formed on the entire surface of the display substrate 01, and the cathode 4113 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag). For example, the cathode 4113 can be formed very thin and therefore has good light transmittance. For example, if the anode 4111 includes an ITO / Ag / ITO three-layer structure, its thickness is 86 / 1000 / 86 Å.

[0059] In addition, in the layout shown in Figure 6C, the second connecting line 120 is located on a different film layer from the first connecting line 110 (the film layer on which the second connecting line 120 is located and the corresponding cross-sectional structure will be described below), and the second connecting line 120 and the anode 4111 of the first sub-light-emitting element 411a are also located on different film layers; therefore, although the outline of the second connecting line 120 overlaps with the anode 4111 of the first sub-light-emitting element 411a, the second connecting line 120 is not electrically connected to the anode 4111 of the first sub-light-emitting element 411a.

[0060] 6A, the first sub-pixel circuit 412a includes structures such as a first switching transistor (e.g., a switching thin film transistor 412T) and a storage capacitor 412C. The switching thin film transistor 412T includes a gate 4121, an active layer 4122, a first electrode 4123, and a second electrode 4124. For example, the first electrode 4123 may be a source or a drain, and the second electrode 4124 may be a drain or a source. For example, the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126.

[0061] For example, the active layer 4121 is disposed on the base substrate 74, and a first gate insulating layer 741 is disposed on the side of the active layer 4121 that faces away from the base substrate 74. The gate 4122 and the first capacitor plate 4125 are disposed on the same layer and are located on the side of the first gate insulating layer 741 that faces away from the base substrate 74, and a second gate insulating layer 742 is disposed on the side of the gate 4122 and the first capacitor plate 4125 that faces away from the base substrate 74. The second capacitor plate 4126 is disposed on the side of the second gate insulating layer 742 that faces away from the base substrate 74, and an interlayer insulating layer 743 is disposed on the side of the second capacitor plate 4126 that faces away from the base substrate 74. The first electrode 4123 and the second electrode 4124 (i.e., source and drain) are disposed on the side of the interlayer insulating layer 743 away from the base substrate 74, and are electrically connected to the active layer 4121 through vias located in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. Both the first electrode 4123 and the second electrode 4124 are located on the source and drain metal layer SD, the third insulating layer 33 is located on the source and drain metal layer SD, and the first connection layer 21 is located on the third insulating layer 33. The third insulating layer 33 not only plays an insulating role, but also a planarizing role.

[0062] For example, the second end of the first connecting line 110 is electrically connected to the second pole 4124 of the first switching transistor (e.g., the switching thin film transistor 412T) included in the first sub-pixel circuit 412a through a third via H3 that penetrates the third insulating layer 33. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the second end of the first connecting line 110 may be electrically connected to the first pole 4123 of the switching thin film transistor 412T included in the first sub-pixel circuit 412a. For example, the cross-sectional size of the third via H3 in a plane parallel to the display substrate 01 may be 4 μm × 4 μm.

[0063] For example, the first display region 11 further includes a transparent support layer 78 located on the base substrate 74, and the first sub-light-emitting element 411a is located on the side of the transparent support layer 78 that is away from the base substrate 74. This allows the first sub-light-emitting element 411a of the first display region 11 to be substantially the same height as the light-emitting elements of other display regions (e.g., the second light-emitting element 421 of the second display region 12 and the third light-emitting element 431 of the third display region 13, which will be described below) with respect to the base substrate 74, thereby improving the display effect of the display substrate 01.

[0064] For example, the display substrate 01 may further include structures such as a pixel defining layer 746 and an encapsulation layer 747. For example, the pixel defining layer 746 is disposed on the anode 4111 (e.g., a partial structure of the anode 4111) and includes a plurality of openings for defining different pixels or sub-pixels, and the light-emitting layer 4112 is formed in the openings of the pixel defining layer 746. For example, the horizontal distance between the opening of the pixel defining layer 746 and the first via H1 may be 4.6 μm. For example, the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, and the multi-layer encapsulation structure may include, for example, a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate 01.

[0065] For example, the pixel definition layers 746 of the first display area 11, the second display area 12, and the third display area 13 are disposed on the same layer, and the encapsulation layers 747 of the first display area 11, the second display area 12, and the third display area 13 are disposed on the same layer and are integrally connected in some embodiments, and the embodiments of the present disclosure are not limited thereto.

[0066] For example, in each embodiment of the present disclosure, the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like, and may be a rigid substrate or a flexible substrate, and the embodiments of the present disclosure are not limited thereto.

[0067] For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the pixel defining layer 746, and the encapsulation layer 747 may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not specifically limit the materials used for the functional layers. For example, the thicknesses of the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may each be 10,000 to 15,000 Å.

[0068] For example, the material of the active layer 4121 may include a semiconductor material such as polycrystalline silicon or an oxide semiconductor (e.g., indium gallium zinc oxide). For example, a part of the active layer 4121 may be made conductive by a conductive treatment such as doping so that it has high conductivity.

[0069] For example, the materials of gate 4122, first capacitor plate 4125 and second capacitor plate 4126 may include metal or alloy materials including molybdenum, aluminum, titanium, and the like.

[0070] For example, the material of the first pole 4123 and the second pole 4124 may include a metal material or alloy material such as a metal single layer or multilayer structure formed of molybdenum, aluminum, and titanium, for example, the multilayer structure is a multilayer metal stack such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti).

[0071] For example, the display substrate 01 according to the embodiments of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc., and the embodiments of the present disclosure do not limit the specific type of the display substrate.

[0072] For example, when the display substrate 01 is an organic light-emitting diode display substrate, the light-emitting layer (e.g., the above-mentioned light-emitting layer 4112) may include a small molecule organic material or a polymer molecule organic material, and may be a fluorescent or phosphorescent light-emitting material, and may emit red light, green light, blue light, white light, etc. In addition, according to various practical needs, in different examples, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, etc.

[0073] For example, when the display substrate 01 is a quantum dot light-emitting diode (QLED) display substrate, the light-emitting layer (e.g., the above-mentioned light-emitting layer 4112) may include quantum dot materials such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, and the particle size of the quantum dots is, for example, 2 nm to 20 nm.

[0074] 7A is a schematic cross-sectional view along line B-B' in FIG. 5B, FIG. 7B is an enlarged view of the second via H2 in FIG. 7A, FIG. 7C is a schematic layout of the area corresponding to the second via H2 and the connected anode in FIG. 7A, FIG. 7D is another structural schematic diagram of the fourth via H4, and FIG. 7E is a schematic layout of the area corresponding to the fourth via H4 and the connected source-drain metal layer in FIG. 7A.

[0075] 7A to 7E, the display substrate 01 further includes a second connection layer 22, which is located between the first insulating layer 31 and the second insulating layer 32, and the second connection line 120 is located on the second connection layer 22. The second sub-light-emitting element 411b is disposed in the same manner as the first sub-light-emitting element 411a, and the first switching transistor (e.g., switching thin film transistor 412T) and the storage capacitor 412C included in the second sub-pixel circuit 412b are disposed in the same manner as the first switching transistor and the storage capacitor 412C of the first sub-pixel circuit 412a. For related descriptions, refer to the descriptions of FIGS. 6A to 6D above, and detailed descriptions thereof will be omitted here.

[0076] For example, the anode 4111 of the second sub-light-emitting element 411b is located on the anode layer 40, and the anode 4111 of the second sub-light-emitting element 411b is electrically connected to the second connection line 120 through a second via H2 that penetrates the second insulating layer 32.

[0077] For example, the anode 4111 of the second sub-light-emitting element 411b includes a second groove structure GR2, which is located in the second via H2, and the bottom of the second groove structure GR2 contacts and is electrically connected to the second connecting line 120. By placing the portion of the anode 4111 deposited in the second via H2 in the groove structure, the thickness of this portion can be reduced and the difference between the thickness of this portion and the thickness of the rest of the anode 4111 can be reduced, thereby improving the overall uniformity of the transmitted light.

[0078] For example, in some examples, the surface of the second groove structure GR2 facing away from the second connecting layer 22 is a curved surface. In this way, the light intensity of the transmitted light can be continuously changed, and sudden changes in the light intensity at local positions can be avoided, thereby further improving the uniformity of the transmitted light. Of course, the embodiments of the present disclosure are not limited thereto. In other examples, the surface of the second groove structure GR2 facing away from the second connecting layer 22 can be a flat surface, an inclined surface, etc., which can be determined according to actual needs.

[0079] For example, the second end of the second connecting line 120 is electrically connected to the second pole 4124 of the first switching transistor (e.g., the switching thin film transistor 412T) of the second sub-pixel circuit 412b through a fourth via H4 that penetrates the third insulating layer 33 and the first insulating layer 31. Of course, the embodiments of the present disclosure are not limited thereto, and in other examples, the second end of the second connecting line 120 may be electrically connected to the first pole 4123 of the switching thin film transistor 412T included in the second sub-pixel circuit 412b.

[0080] 7A, the cross-sectional shape of the fourth via H4 in a plane perpendicular to the display substrate 01 is an inverted boss shape. For example, in the fourth via H4, the opening diameter of the first insulating layer 31 is larger than the opening diameter of the third insulating layer 33. Because the fourth via H4 needs to penetrate two insulating layers, the depth of the fourth via H4 is large. By setting the fourth via H4 to an inverted boss shape, the difficulty of processing the fourth via H4 can be reduced and it is easy to deposit a conductive material (e.g., the material of the second connection line 120) in the fourth via H4, thereby improving the reliability of the electrical connection.

[0081] In addition, in the layout shown in Figure 7C, the first connecting line 110 is located on a different film layer from the second connecting line 120, and the first connecting line 110 and the anode 4111 of the second sub-light-emitting element 411b are also located on different film layers.Therefore, although the outline of the first connecting line 110 overlaps with the anode 4111 of the second sub-light-emitting element 411b, the first connecting line 110 is not electrically connected to the anode 4111 of the second sub-light-emitting element 411b.

[0082] 7D , in the fourth via H4, the second connecting line 120 is in contact with and electrically connected to the transition metal layer 23, and the transition metal layer 23 is in contact with and electrically connected to the first pole 4123 or the second pole 4124 of the first switching transistor (e.g., the switching thin film transistor 412T) of the second sub-pixel circuit 412b, thereby achieving an electrical connection between the second connecting line 120 and the switching thin film transistor 412T. For example, the transition metal layer 23 and the first connecting layer 21 may be formed in the same process, i.e., the transition metal layer 23 and the first connecting layer 21 may be the same film layer, with a portion of the film layer forming the first connecting line 110 and another portion of the film layer electrically connecting to the second connecting line 120 and the switching thin film transistor 412T of the second sub-pixel circuit 412b. The provision of the transition metal layer 23 reduces process difficulties and improves the reliability of the electrical connection.

[0083] For example, as shown in FIG. 5B , the second display area 12 further includes at least one (e.g., multiple) second light-emitting elements 421 and at least one (e.g., multiple) second pixel circuits 422. The second light-emitting elements 421 are electrically connected to the second pixel circuits 422 in a one-to-one correspondence, and the second pixel circuits 422 are used to drive the second light-emitting elements 421 to emit light. Note that the rectangular block indicated by the reference numeral 422 in FIG. 5B merely indicates the approximate position of the second pixel circuit 422 and does not represent the specific shape or specific boundaries of the second pixel circuit 422. For example, at least one second light-emitting element 421 and its corresponding second pixel circuit 422 constitute one second pixel driving unit 42.

[0084] 5B, the second pixel driving unit 42 may include one second pixel circuit 422 and one second light-emitting element 421, or may include multiple second pixel circuits 422 and multiple second light-emitting elements 421. When the second pixel driving unit 42 includes multiple second pixel circuits 422 and multiple second light-emitting elements 421, the number of second pixel circuits 422 in each second pixel driving unit 42 is, for example, equal to the number of second light-emitting elements 421, thereby realizing one-to-one corresponding driving.

[0085] For example, the plurality of second light-emitting elements 421 are arranged in an array, and the plurality of second pixel circuits 422 are also arranged in an array. Here, the "arrangement in an array" may refer to a plurality of devices being grouped together and the plurality of groups of devices being arranged in an array, or to a plurality of devices themselves being arranged in an array, and the embodiments of the present disclosure are not limited thereto. For example, in some examples, as shown in FIG. 5B , every four second light-emitting elements 421 are grouped together and the plurality of groups of second light-emitting elements 421 are arranged in an array, and correspondingly, every four second pixel circuits 422 are grouped together and the plurality of groups of second pixel circuits 422 are arranged in an array, and in this case, each second pixel driving unit 42 includes four second pixel circuits 422 and four second light-emitting elements 421.

[0086] 8A is a schematic cross-sectional view along line CC' in FIG. 5B, FIG. 8B is an enlarged view of the fifth via H5 in FIG. 8A, and FIG. 8C is a schematic layout of the area corresponding to the fifth via H5 in FIG. 8A and the connected anode and source / drain metal layer.

[0087] 8A to 8C, the second pixel circuit 422 includes structures such as a second switching transistor (e.g., a switching thin film transistor 422T) and a storage capacitor 422C. The switching thin film transistor 422T includes a gate 4221, an active layer 4222, a first electrode 4223, and a second electrode 4224. For example, the first electrode 4223 may be a source or a drain, and the second electrode 4224 may be a drain or a source. For example, the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226.

[0088] For example, the active layer 4221 is disposed on the base substrate 74, and a first gate insulating layer 741 is disposed on the side of the active layer 4221 that faces away from the base substrate 74. The gate 4222 and the first capacitor plate 4225 are disposed on the same layer and are located on the side of the first gate insulating layer 741 that faces away from the base substrate 74, and a second gate insulating layer 742 is disposed on the side of the gate 4222 and the first capacitor plate 4225 that faces away from the base substrate 74. The second capacitor plate 4226 is disposed on the side of the second gate insulating layer 742 that faces away from the base substrate 74, and an interlayer insulating layer 743 is disposed on the side of the second capacitor plate 4226 that faces away from the base substrate 74. The first electrode 4223 and the second electrode 4224 (i.e., source / drain) are disposed on the side of the interlayer insulating layer 743 away from the base substrate 74, and are electrically connected to the active layer 4221 through vias located in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. Both the first electrode 4223 and the second electrode 4224 are located on the source / drain metal layer SD, and the third insulating layer 33 is located on the source / drain metal layer SD. The third insulating layer 33 not only plays an insulating role, but also a planarizing role.

[0089] For example, the second light-emitting element 421 includes an anode 4211, a cathode 4213, and a light-emitting layer 4212 located between the anode 4211 and the cathode 4213, and the anode 4211 is located on the anode layer 40. The anode 4211 of the second light-emitting element 421 is electrically connected to the first electrode 4223 or the second electrode 4224 of the second switching transistor (e.g., the switching thin film transistor 422T) through a fifth via H5 that penetrates the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33.

[0090] For example, the cross-sectional shape of the fifth via H5 in a plane perpendicular to the display substrate 01 is an inverted boss shape. In the fifth via H5, the opening diameter L3 of the first insulating layer 31 is larger than the opening diameter L4 of the third insulating layer 33. Because the fifth via H5 needs to penetrate three insulating layers, the depth of the fifth via H5 is large. By setting the fifth via H5 to an inverted boss shape, the difficulty of processing the fifth via H5 can be reduced and it is easy to deposit a conductive material (e.g., the material of the anode 4211) in the fifth via H5, thereby improving the reliability of the electrical connection.

[0091] For example, in the fifth via H5, the opening diameter of the second insulating layer 32 is equal to or larger than the opening diameter of the first insulating layer 31. For example, as shown in FIGS. 8A-8B, in some examples, the opening diameter of the second insulating layer 32 is equal to the opening diameter of the first insulating layer 31, i.e., both are equal to L3. Therefore, the same mask can be used to manufacture the openings of the first insulating layer 31 and the second insulating layer 32, thereby reducing the number of masks required and reducing production costs. For example, in some other examples, the opening diameter of the second insulating layer 32 is larger than the opening diameter of the first insulating layer 31, allowing the fifth via H5 to be formed in a three-level stepped shape, further reducing processing difficulty and facilitating deposition of a conductive material (e.g., the material of the anode 4211) in the fifth via H5, thereby improving the reliability of the electrical connection.

[0092] For example, the anode 4211 of the second light-emitting element 421 includes a third groove structure GR3, which is located within the fifth via H5. The bottom of the third groove structure GR3 contacts and is electrically connected to the first electrode 4223 or the second electrode 4224 of the second switching transistor (e.g., the switching thin film transistor 422T). By providing the portion of the anode 4211 deposited within the fifth via H5 as a groove structure, the thickness of the portion can be reduced, reducing the difference between the thickness of the portion and the thickness of the remaining portions of the anode 4211, thereby improving the overall uniformity of transmitted light. The fifth via H5 has an inverted boss shape, which contributes to the formation of the groove structure during the manufacturing of the anode 4211 and reduces process difficulties. For example, the surface of the third groove structure GR3 away from the source / drain metal layer SD may be curved, flat, inclined, or the like, although this is not a limitation of the embodiments of the present disclosure.

[0093] 9 is an enlarged view of a partial region REG3 of the third display region of the display substrate shown in FIG. 1. For example, as shown in FIG. 9, the third display region 13 includes at least one (e.g., multiple) third light-emitting elements 431 and at least one (e.g., multiple) third pixel circuits 432. The third light-emitting elements 431 are electrically connected to the third pixel circuits 432 in a one-to-one correspondence, and the third pixel circuits 432 are used to drive the third light-emitting elements 431 to emit light. Note that the rectangular block indicated by the reference numeral 432 in FIG. 9 merely indicates the approximate position of the third pixel circuit 432 and does not represent the specific shape or specific boundaries of the third pixel circuit 432. For example, at least one third light-emitting element 431 and its corresponding third pixel circuit 432 constitute one third pixel driving unit 43.

[0094] 9, the third pixel driving unit 43 may include one third pixel circuit 432 and one third light-emitting element 431, or may include multiple third pixel circuits 432 and multiple third light-emitting elements 431. When the third pixel driving unit 43 includes multiple third pixel circuits 432 and multiple third light-emitting elements 431, the number of the third pixel circuits 432 in each third pixel driving unit 43 is, for example, equal to the number of the third light-emitting elements 431, thereby realizing one-to-one corresponding driving.

[0095] For example, the plurality of third light-emitting elements 431 are arranged in an array, and the plurality of third pixel circuits 432 are also arranged in an array. Here, the "arrangement in an array" may mean that a plurality of devices are grouped together and the plurality of groups of devices are arranged in an array, or that the plurality of devices themselves are arranged in an array, and the embodiments of the present disclosure are not limited thereto. For example, in some examples, as shown in FIG. 9 , every fourth third light-emitting element 431 is grouped together and the plurality of groups of third light-emitting elements 431 are arranged in an array, and correspondingly, every fourth third pixel circuit 432 is grouped together and the plurality of groups of third pixel circuits 432 are arranged in an array, and in this case, each third pixel driving unit 43 includes four third pixel circuits 432 and four third light-emitting elements 431.

[0096] 10A is a schematic cross-sectional view taken along line DD' in FIG. 9, and FIG. 10B is an enlarged view of the sixth via H6 in FIG. 10A.

[0097] 10A-10B, the third pixel circuit 432 includes structures such as a third switching transistor (e.g., a switching thin film transistor 432T) and a storage capacitor 432C. The switching thin film transistor 432T includes a gate 4321, an active layer 4322, a first electrode 4323, and a second electrode 4324. For example, the first electrode 4323 may be a source or a drain, and the second electrode 4324 may be a drain or a source. For example, the storage capacitor 432C includes a first capacitor plate 4325 and a second capacitor plate 4326.

[0098] For example, the active layer 4321 is disposed on the base substrate 74, and a first gate insulating layer 741 is disposed on the side of the active layer 4321 that faces away from the base substrate 74. The gate 4322 and the first capacitor plate 4325 are disposed on the same layer and are located on the side of the first gate insulating layer 741 that faces away from the base substrate 74, and a second gate insulating layer 742 is disposed on the side of the gate 4322 and the first capacitor plate 4325 that faces away from the base substrate 74. The second capacitor plate 4326 is disposed on the side of the second gate insulating layer 742 that faces away from the base substrate 74, and an interlayer insulating layer 743 is disposed on the side of the second capacitor plate 4326 that faces away from the base substrate 74. The first electrode 4323 and the second electrode 4324 (i.e., source / drain) are disposed on the side of the interlayer insulating layer 743 away from the base substrate 74, and are electrically connected to the active layer 4321 through vias located in the first gate insulating layer 741, the second gate insulating layer 742, and the interlayer insulating layer 743. Both the first electrode 4323 and the second electrode 4324 are located on the source / drain metal layer SD, and the third insulating layer 33 is located on the source / drain metal layer SD. The third insulating layer 33 not only plays an insulating role, but also a planarizing role.

[0099] For example, the third light-emitting element 431 includes an anode 4311, a cathode 4313, and a light-emitting layer 4312 located between the anode 4311 and the cathode 4313, and the anode 4311 is located on the anode layer 40. The anode 4311 of the third light-emitting element 431 is electrically connected to the first electrode 4323 or the second electrode 4324 of the third switching transistor (e.g., the switching thin film transistor 432T) through a sixth via H6 that penetrates the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33.

[0100] For example, the cross-sectional shape of the sixth via H6 in a plane perpendicular to the display substrate 01 is an inverted boss shape. In the sixth via H6, the opening diameter L5 of the first insulating layer 31 is larger than the opening diameter L6 of the third insulating layer 33. Since the sixth via H6 needs to penetrate three insulating layers, the depth of the sixth via H6 is large. By setting the sixth via H6 to an inverted boss shape, the difficulty of processing the sixth via H6 can be reduced and it is easy to deposit a conductive material (e.g., the material of the anode 4311) in the sixth via H6, thereby improving the reliability of the electrical connection.

[0101] For example, in the sixth via H6, the opening diameter of the second insulating layer 32 is equal to or larger than the opening diameter of the first insulating layer 31. For example, as shown in FIGS. 10A-10B, in some examples, the opening diameter of the second insulating layer 32 is equal to the opening diameter of the first insulating layer 31, i.e., both are equal to L5. Therefore, the same mask can be used to manufacture the openings of the first insulating layer 31 and the second insulating layer 32, thereby reducing the number of masks required and reducing production costs. For example, in some other examples, the opening diameter of the second insulating layer 32 is larger than the opening diameter of the first insulating layer 31, allowing the sixth via H6 to be formed in a three-level stepped shape, further reducing processing difficulty and facilitating deposition of a conductive material (e.g., the material of the anode 4311) in the sixth via H6, thereby improving the reliability of the electrical connection.

[0102] For example, the anode 4311 of the third light-emitting element 431 includes a fourth groove structure GR4, which is located within the sixth via H6. The bottom of the fourth groove structure GR4 contacts and is electrically connected to the first electrode 4323 or the second electrode 4324 of the third switching transistor (e.g., the switching thin film transistor 432T). By providing the portion of the anode 4311 deposited within the sixth via H6 as a groove structure, the thickness of the portion can be reduced, reducing the difference between the thickness of the portion and the thickness of the remaining portions of the anode 4311, thereby improving the overall uniformity of transmitted light. The sixth via H6 has an inverted boss shape, which contributes to the formation of the groove structure during the manufacturing of the anode 4311 and reduces process difficulties. For example, the surface of the fourth groove structure GR4 facing away from the source / drain metal layer SD may be curved, flat, inclined, or the like, although this is not a limitation of the embodiments of the present disclosure.

[0103] 11A is a schematic layout corresponding to the partial region REG4 of FIG. 4 , FIG. 11B is a schematic layout showing only the first connecting line of FIG. 11A , FIG. 11C is a schematic layout showing only the second connecting line of FIG. 11A , and FIG. 11D is a schematic cross-sectional view taken along line E-E' of FIG. 11A . For example, as shown in FIGS. 11A to 11C , in the first display region 11, the first connecting line 110 and the second connecting line 120 extend along their respective extension directions in the region where no anode is provided. For example, the extension directions of the first connecting line 110 and the second connecting line 120 may be the same or different. Note that although the projections of the first connecting line 110 and the second connecting line 120 in FIG. 11A overlap, the first connecting line 110 and the second connecting line 120 are located on different film layers, and therefore remain insulated from each other, which does not affect the signal transmission between them. For example, as shown in Figure 11D, the third insulating layer 33, the first connecting line 110 (i.e., the first connecting layer 21), the first insulating layer 31, the second connecting line 120 (i.e., the second connecting layer 22), the second insulating layer 32, and the pixel defining layer 746 are sequentially stacked. Because the first insulating layer 31 is provided, the first connecting line 110 and the second connecting line 120 are insulated from each other and are not short-circuited. For other film layers, please refer to the above content and are not shown in Figure 11D.

[0104] 12A is a first schematic layout corresponding to the second light-emitting element in the second display region of the display substrate according to some embodiments of the present disclosure, and FIG. 12B is a second schematic layout corresponding to the second light-emitting element in the second display region of the display substrate according to some embodiments of the present disclosure. For example, as shown in FIGS. 12A and 12B, in the second display region 12 where the second light-emitting element 421 is installed, the first connecting line 110 and the second connecting line 120 penetrate from below the anode 4211 of the second light-emitting element 421 (i.e., the side of the anode 4211 closer to the base substrate 74) and are still insulated from the anode 4211 of the second light-emitting element 421.

[0105] For example, in the embodiment of the present disclosure, the first connecting line 110 and the second connecting line 120 may each include a transparent conductive wire, which may be made of, for example, indium tin oxide (ITO). By configuring the first connecting line 110 and the second connecting line 120 as transparent conductive wires, the light transmittance of the display substrate 01 can be improved.

[0106] For example, the plurality of first light-emitting elements 411 are arranged in an array, and both the first connecting lines 110 and the second connecting lines 120 extend along the row direction of the array of the plurality of first light-emitting elements 411. Of course, the embodiments of the present disclosure are not limited thereto, and the extension directions of the first connecting lines 110 and the second connecting lines 120 may be any other direction, and the embodiments of the present disclosure are not limited thereto. For example, the extension direction of the first connecting lines 110 and the extension direction of the second connecting lines 120 may be the same or different.

[0107] For example, the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 may each include an organic light-emitting diode (OLED). Of course, embodiments of the present disclosure are not limited thereto, and the first light-emitting element 411, the second light-emitting element 421, and the third light-emitting element 431 may also be a quantum dot light-emitting diode (QLED) or other applicable light-emitting devices, and embodiments of the present disclosure are not limited thereto.

[0108] For example, the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display region 11 is smaller than the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display region 12, and the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display region 12 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 431 in the third display region 13. For example, the first display region 11 and the second display region 12 may be referred to as low-resolution regions of the display substrate 01, and correspondingly, the third display region 13 may be referred to as a high-resolution region of the display substrate 01. For example, the total pixel light-emitting area of the second display region 12 and the first display region 11 may be 1 / 8 to 1 / 2 of the pixel light-emitting area of the third display region 13.

[0109] In addition, in some examples, the distribution density per unit area of the plurality of first light-emitting elements 411 in the first display area 11 may be equal to the distribution density per unit area of the plurality of second light-emitting elements 421 in the second display area 12, which may be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0110] By successively increasing the distribution density per unit area of the light-emitting elements in the first display area 11, the second display area 12, and the third display area 13, it is possible to ensure that the three display areas emit light normally to display the screen, and it is also easy for light from the first side of the display substrate 01 to pass through the first display area 11 and reach the second side, which makes it easy for a sensor installed on the second side of the display substrate 01 to detect the light.

[0111] In the embodiments of the present disclosure, the display substrate 01 is not limited to the structures and components described above and may further include other structures or components. For example, the display substrate 01 may further include one or more barrier layers, buffer layers, etc., and the embodiments of the present disclosure are not limited thereto.

[0112] 13A is a structural schematic diagram of a 7T1C pixel circuit. For example, the first pixel circuit 412 (e.g., the first sub-pixel circuit 412a and the second sub-pixel circuit 412b), the second pixel circuit 422, and the third pixel circuit 432 can all use the 7T1C pixel circuit.

[0113] 13A, the 7T1C pixel circuit 100 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a storage capacitor Cst, where the first transistor CT1 to the seventh transistor CT7 are all P-type transistors.

[0114] As shown in FIG. 13A, the storage capacitor Cst has a first terminal connected to the first power supply voltage terminal VDD to receive the first power supply voltage V1 and a second terminal connected to the first node N1. The light-emitting element EL has a first terminal connected to the fourth node N4 and a second terminal connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2. The first transistor CT1 has a control terminal connected to the first node N1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The second transistor CT2 has a first terminal connected to the second node N2 and a second terminal connected to the data signal terminal DAT to receive a data signal (e.g., a data voltage) Vdata. The third transistor CT3 has a first terminal connected to the first node N1 and a second terminal connected to the third node N3.

[0115] The fourth transistor CT4 has a first terminal connected to the first node N1 and a second terminal connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init1. The fifth transistor CT5 has a first terminal connected to the first power supply voltage terminal VDD and a first terminal connected to the second node N2. The sixth transistor CT6 has a first terminal connected to the fourth node N4 and a second terminal connected to the second reset signal terminal Init2 to receive the second reset signal Vinit2. The seventh transistor CT7 has a first terminal connected to the third node N3 and a second terminal connected to the fourth node N4.

[0116] For example, the control end GAT1 of the second transistor CT2 and the control end GAT2 of the third transistor CT3 are both connected to the scanning signal end GAT (not shown), the control end EM1 of the fifth transistor CT5 and the control end EM2 of the seventh transistor CT7 are both connected to the light emitting control end EM (not shown), the control end of the fourth transistor CT4 is configured to be connected to the first reset control end RST1, and the control end of the sixth transistor CT6 is configured to be connected to the second reset control end RST2. For convenience of explanation, Figure 13A also shows the first node N1, the second node N2, the third node N3, the fourth node N4 and the light emitting element EL.

[0117] Figure 13B is a driving timing diagram of the 7T1C pixel circuit shown in Figure 13A. As shown in Figure 13B, each driving cycle of the 7T1C pixel circuit 100 includes a first stage t1, a second stage t2 and a third stage t3.

[0118] 13A and 13B, at a first stage t1, the first reset control terminal RST1 receives an active level, and the scanning signal terminal GAT, the second reset control terminal RST2, and the light-emitting control terminal EM all receive an inactive level. In this case, the fourth transistor CT4 is turned on, and the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off. The fourth transistor CT4 receives a first reset signal (e.g., a reset voltage) Vinit1 and writes the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst. The voltage of the first node N1 is Vinit1, where Vinit1 is, for example, a negative value. For example, after resetting the storage capacitor Cst, the first transistor CT1 is turned on.

[0119] As shown in FIGS. 13A and 13B, in the second stage t2, the scanning signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the emission control terminal EM receive an inactive level, in this case, the first transistor CT1 to the third transistor CT3 and the sixth transistor CT6 are turned on, and the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off, and the second transistor CT2 receives the data signal Vdata, and the data signal Vdata controls the first transistor CT1 and the third transistor CT3 that are turned on. a data signal Vdata written to the control end of the first transistor CT1 through the sixth transistor CT6; a data signal Vdata written to the control end of the first transistor CT1 is written to the control end of the first transistor CT1 through the sixth transistor CT6; a voltage of the first node N1 is Vdata+Vth; the sixth transistor CT6 receives a second reset signal (e.g., a reset voltage) Vinit2 and writes the second reset signal Vinit2 to the first end of the light-emitting element EL to reset the first end of the light-emitting element EL; a voltage of the fourth node N4 is Vinit2, where Vinit2 is, for example, a negative value.

[0120] 13A and 13B, in the third stage t3, the light emitting control terminal EM receives an enable level, the first reset control terminal RST1, the scanning signal terminal GAT and the second reset control terminal RST2 receive an disable level, in this case, the first transistor CT1, the fifth transistor CT5 and the seventh transistor CT7 are turned on, and the second transistor CT2, the third transistor CT3, the fourth transistor CT4 and the sixth transistor CT6 are turned off, the first transistor CT1 is configured to control the driving current for driving the light emitting element EL from the first power supply voltage terminal VDD to the light emitting element EL according to the data signal (e.g., data voltage) Vdata stored in the storage capacitor Cst and the received first power supply voltage V1, the voltage of the first node N1 is Vdata+Vth, the voltage of the second node N2 is VDD, and the driving current Id is expressed by the following equation:

number

[0121] As is clear from the above equation, the drive current Id generated by the first transistor CT1 is independent of the threshold voltage of the first transistor CT1, and therefore the 7T1C pixel circuit 100 shown in FIGS. 13A and 13B has a threshold compensation function.

[0122] It should be noted that in the embodiments of the present disclosure, the first pixel circuit 412 (e.g., the first sub-pixel circuit 412a and the second sub-pixel circuit 412b), the second pixel circuit 422, and the third pixel circuit 432 are not limited to the above-mentioned 7T1C pixel circuit, and other applicable pixel circuits may be used, and the embodiments of the present disclosure do not limit this. The specific circuit structures of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 may be the same or different from each other, which may be determined according to actual needs, and the embodiments of the present disclosure do not limit this.

[0123] For example, the first switching transistor of the first pixel circuit 412, the second switching transistor of the second pixel circuit 422, and the third switching transistor of the third pixel circuit 432 may all be the seventh transistor CT7 of Figure 13A, and the seventh transistor CT7 provides an electrical signal to the anode of the corresponding light-emitting element EL. For example, the first light-emitting element 411 (e.g., the first sub-light-emitting element 411a and the second sub-light-emitting element 411b), the second light-emitting element 421, and the third light-emitting element 431 may all be the light-emitting element EL of Figure 13A, and the light-emitting element EL may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0124] At least one embodiment of the present disclosure further provides a display device, which includes a display substrate according to any one of the embodiments of the present disclosure, and the display device can reduce processing difficulty, improve the reliability of electrical connection, and improve the uniformity of transmitted light, thereby contributing to improving the detection effect of an in-screen sensor (such as a camera).

[0125] FIG. 14 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure. For example, as shown in FIG. 14, the display device 20 includes a display substrate 210, which may be a display substrate according to any embodiment of the present disclosure, such as the display substrate 01 described above. The display device 20 may be any electronic device with a display function, such as a smartphone, a laptop, a tablet computer, or a television. For example, if the display device 20 is a smartphone or a tablet computer, the smartphone or tablet computer may have a full-screen design, i.e., no peripheral area surrounding the third display area 13. The smartphone or tablet computer may also have an in-screen sensor (e.g., a camera, an infrared sensor, etc.) to perform operations such as image capture, distance detection, and light intensity detection.

[0126] In addition, applicable components may be used for the display substrate 210 and other components of the display device 20 (e.g., image data encoding / decoding device, clock circuit, etc.), all of which should be understood by those skilled in the art, and detailed description will be omitted here, and should not be considered as limiting the embodiments of the present disclosure.

[0127] 15 is a schematic diagram of a stacked structure of a display device according to at least one embodiment of the present disclosure. For example, as shown in FIG. 15, the display device 20 includes a display substrate 210, which may be a display substrate according to any embodiment of the present disclosure, such as the display substrate 01. For example, the display device 20 further includes a sensor 220.

[0128] For example, the display substrate 01 has a first side F1 for display and a second side F2 opposite to the first side F1. That is, the first side F1 is the display side, and the second side F2 is the non-display side. The display substrate 01 is configured to perform a display operation on the first side F1, that is, the first side F1 of the display substrate 01 is the light-emitting side of the display substrate 01 and faces the user. The first side F1 and the second side F2 are opposite to each other in the normal direction of the display surface of the display substrate 01.

[0129] As shown in FIG. 15 , the sensor 220 is disposed on the second side F2 of the display substrate 01 and configured to receive light from the first side F1. For example, the sensor 220 and the first display region 11 are stacked in a normal direction to the display surface of the display substrate 01 (e.g., a direction perpendicular to the display substrate 01), and the sensor 220 can receive and process optical signals passing through the first display region 11, which may be visible light, infrared light, etc. For example, the first display region 11 allows light from the first side F1 to be at least partially transmitted to the second side F2. For example, because no pixel circuits are disposed in the first display region 11, the light transmittance of the first display region 11 can be improved.

[0130] For example, the orthogonal projection of the sensor 220 on the display substrate 01 at least partially overlaps with the first display region 11. For example, in some examples, when a direct-underneath installation method is used, the orthogonal projection of the sensor 220 on the display substrate 01 is within the first display region 11. For example, in some other examples, when light is made incident on the sensor 220 from the side using another light guide element (e.g., a light guide plate, a light guide tube, etc.), the orthogonal projection of the sensor 220 on the display substrate 01 partially overlaps with the first display region 11. In this case, since light can propagate laterally to the sensor 220, the sensor 220 does not need to be located completely at a position corresponding to the first display region 11.

[0131] For example, by installing the first pixel circuit 412 in the second display region 12 and stacking the sensor 220 and the first display region 11 in the normal direction of the display surface of the display substrate 01, it is possible to reduce the blocking of the optical signal incident on the first display region 11 and irradiated to the sensor 220 by the elements in the first display region 11, thereby improving the signal-to-noise ratio of the image output by the sensor 220. For example, the first display region 11 may be referred to as a high-transmittance region of the low-resolution region of the display substrate 01, and the second display region 12 may be referred to as a transition region.

[0132] For example, the sensor 220 may be an image sensor that can collect images of the external environment facing the light-collecting surface of the sensor 220, and may be, for example, a CMOS image sensor or a CCD image sensor. The sensor 220 may also be an infrared sensor, a distance sensor, or the like. For example, if the display device 20 is a mobile terminal such as a mobile phone or a laptop, the sensor 220 may be implemented as a camera of the mobile terminal such as a mobile phone or a laptop, and may further include an optical device such as a lens, a reflector, or an optical waveguide to modulate the light path, as necessary. For example, the sensor 220 may include photosensitive pixels arranged in an array. For example, each photosensitive pixel may include a photosensitive detector (e.g., a photodiode or a phototransistor) and a switching transistor (e.g., a switching thin-film transistor). For example, the photodiode can convert an optical signal illuminated thereon into an electrical signal, and the switching transistor is electrically connected to the photodiode to control whether the photodiode is in a state of collecting the optical signal and the collection time of the optical signal.

[0133] In some examples, when the anode of the first light-emitting element 411 has a stacked structure of ITO / Ag / ITO, only the anode of the first light-emitting element 411 does not transmit light in the first display region 11, that is, the wiring for driving the first light-emitting element 411 (e.g., the first connecting line 110 and the second connecting line 120) is installed as a transparent conductive wiring. In this case, not only can the light transmittance of the first display region 11 be further improved, but also diffraction and reflection by each element in the first display region 11 can be reduced.

[0134] In addition, in the embodiments of the present disclosure, the display device 20 may further include more components and structures, and the embodiments of the present disclosure are not limited thereto. For technical effects and detailed descriptions of the display device 20, please refer to the description of the display substrate 01 above, and detailed descriptions will be omitted here.

[0135] A few points need to be explained:

[0136] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0137] (2) Unless there is a contradiction, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0138] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and should be based on the scope of protection of the claims.

Claims

1. A display substrate including a display area, the display area includes a first display area and a second display area that do not overlap each other, the second display area at least partially surrounds the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; the first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit; the display area further includes at least one first connecting line, the first connecting line including a first end located in the first display area and a second end located in the second display area; the at least one first light-emitting element includes a first sub-light-emitting element, the at least one first pixel circuit includes a first sub-pixel circuit, and the first connecting line has a first end electrically connected to an anode of the first sub-light-emitting element and a second end electrically connected to the first sub-pixel circuit; the display substrate includes a first connection layer, a first insulating layer, a second insulating layer, and an anode layer, which are sequentially stacked; the first connecting line is located on the first connecting layer, the anode of the first sub light-emitting element is located on the anode layer, and the anode of the first sub light-emitting element is electrically connected to the first connecting line through a first via that penetrates the first insulating layer and the second insulating layer; a cross-sectional shape of the first via in a plane perpendicular to the display substrate is an inverted boss shape, and an opening diameter of the second insulating layer in the first via is larger than an opening diameter of the first insulating layer; the anode of the first sub-light-emitting element includes a first groove structure, the first groove structure is located within the first via, and the bottom of the first groove structure is in contact with and electrically connected to the first connecting line.

2. the display area further includes at least one second connecting line, the second connecting line including a first end located in the first display area and a second end located in the second display area; the at least one first light-emitting element further includes a second sub-light-emitting element, the at least one first pixel circuit further includes a second sub-pixel circuit, and the second connecting line has a first end electrically connected to an anode of the second sub-light-emitting element and a second end electrically connected to the second sub-pixel circuit; the display substrate further includes a second connection layer, the second connection layer being located between the first insulating layer and the second insulating layer, and the second connection line being located on the second connection layer; an anode of the second sub light-emitting element is located on the anode layer, and the anode of the second sub light-emitting element is electrically connected to the second connecting line through a second via that penetrates the second insulating layer; 2. The display substrate of claim 1, wherein the anode of the second sub-light-emitting element includes a second groove structure, the second groove structure is located within the second via, and the bottom of the second groove structure contacts and is electrically connected to the second connecting line.

3. The display substrate according to claim 2 , wherein a surface of the first groove structure facing away from the first connecting layer is a curved surface, and a surface of the second groove structure facing away from the second connecting layer is a curved surface.

4. each of the first sub-pixel circuit and the second sub-pixel circuit includes a first switching transistor, the first switching transistor including a gate, a first pole, and a second pole; the display substrate further includes a source / drain metal layer and a third insulating layer, the third insulating layer being located on the source / drain metal layer, the first connection layer being located on the third insulating layer, and the first pole and the second pole of the first switching transistor being located on the source / drain metal layer; a second end of the first connection line is electrically connected to a first pole or a second pole of a first switching transistor of the first sub-pixel circuit through a third via that penetrates the third insulating layer; 4. The display substrate of claim 2, wherein a second end of the second connecting line is electrically connected to a first pole or a second pole of a first switching transistor of the second sub-pixel circuit through a fourth via that penetrates the third insulating layer and the first insulating layer.

5. The display substrate according to claim 4, wherein the cross-sectional shape of the fourth via in a plane perpendicular to the display substrate is an inverted boss shape, and the opening diameter of the first insulating layer in the fourth via is larger than the opening diameter of the third insulating layer.

6. 6. The display substrate of claim 4, wherein in the fourth via, the second connection line contacts and is electrically connected to a transition metal layer, the transition metal layer contacts and is electrically connected to a first pole or a second pole of a first switching transistor of the second sub-pixel circuit, and the transition metal layer and the first connection layer are formed in the same process.

7. the second display area further includes at least one second light-emitting element and at least one second pixel circuit, the second light-emitting element being electrically connected to the second pixel circuit; the second pixel circuit includes a second switching transistor, the second switching transistor including a gate, a first pole, and a second pole, the first pole and the second pole of the second switching transistor being located on the source-drain metal layer; an anode of the second light-emitting element is located on the anode layer, and the anode of the second light-emitting element is electrically connected to a first pole or a second pole of the second switching transistor through a fifth via that penetrates the first insulating layer, the second insulating layer, and the third insulating layer; A display substrate described in any one of claims 4 to 6, wherein the cross-sectional shape of the fifth via in a plane perpendicular to the display substrate is an inverted boss shape, and in the fifth via, the opening diameter of the first insulating layer is larger than the opening diameter of the third insulating layer.

8. The display substrate according to claim 7 , wherein the opening diameter of the fifth via in the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.

9. 9. The display substrate of claim 7, wherein the anode of the second light-emitting element includes a third groove structure, the third groove structure is located within the fifth via, and the bottom of the third groove structure is in contact with and electrically connected to the first pole or the second pole of the second switching transistor.

10. the display area further includes a third display area, the third display area at least partially surrounding the second display area, the third display area not overlapping the first display area and the second display area; the third display area includes at least one third light-emitting element and at least one third pixel circuit, the third light-emitting element being electrically connected to the third pixel circuit; the third pixel circuit includes a third switching transistor, the third switching transistor includes a gate, a first pole, and a second pole, the first pole and the second pole of the third switching transistor are located on the source-drain metal layer; an anode of the third light emitting element is located on the anode layer, and the anode of the third light emitting element is electrically connected to a first electrode or a second electrode of the third switching transistor through a sixth via that penetrates the first insulating layer, the second insulating layer, and the third insulating layer; A display substrate described in any one of claims 7 to 9, wherein the cross-sectional shape of the sixth via in a plane perpendicular to the display substrate is an inverted boss shape, and in the sixth via, the opening diameter of the first insulating layer is larger than the opening diameter of the third insulating layer.

11. The display substrate of claim 10 , wherein the opening diameter of the sixth via in the second insulating layer is equal to or larger than the opening diameter of the first insulating layer.

12. 12. The display substrate of claim 10, wherein the anode of the third light-emitting element includes a fourth groove structure, the fourth groove structure is located within the sixth via, and the bottom of the fourth groove structure is in contact with and electrically connected to the first pole or the second pole of the third switching transistor.

13. 13. The display substrate of claim 2, wherein the first connecting line and the second connecting line each include a transparent conductive wiring.

14. The display substrate of any one of claims 2 to 12, wherein the at least one first light-emitting element includes a plurality of first light-emitting elements arranged in an array, and both the first connecting line and the second connecting line extend along the row direction of the array consisting of the plurality of first light-emitting elements.

15. 13. The display substrate of claim 10, wherein the first light emitting element, the second light emitting element, and the third light emitting element each include an organic light emitting diode.

16. the at least one first light-emitting element includes a plurality of first light-emitting elements, the at least one second light-emitting element includes a plurality of second light-emitting elements, and the at least one third light-emitting element includes a plurality of third light-emitting elements; A display substrate described in any one of claims 10 to 12, wherein the distribution density per unit area of the plurality of first light-emitting elements in the first display region is equal to or less than the distribution density per unit area of the plurality of second light-emitting elements in the second display region, and the distribution density per unit area of the plurality of second light-emitting elements in the second display region is smaller than the distribution density per unit area of the plurality of third light-emitting elements in the third display region.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. further comprising a sensor; the display substrate has a first side for display and a second side opposite the first side, the first display area allowing light from the first side to be at least partially transmitted to the second side; 18. The display device of claim 17, wherein the sensor is located on a second side of the display substrate and configured to receive light from the first side.

19. 20. The display device of claim 18, wherein an orthogonal projection of the sensor on the display substrate at least partially overlaps the first display area.

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