Substrate, high frequency circuit, antenna device, wireless communication device, and method for manufacturing substrate

Abstract

To provide a substrate capable of reducing deterioration of transmission properties for high-frequency signals and improving long-term reliability of the substrate.SOLUTION: A substrate includes: a first dielectric substrate 101a having a first through hole 105; a second dielectric substrate 101b having a first conductor via 103a; a first signal line 102a provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate 101c having a second conductor via 103b; a first planar conductor provided between the second dielectric substrate and the third dielectric substrate and separated from the first conductor via and the second conductor via; a fourth dielectric substrate 101d; and a second signal line 102b provided between the third dielectric substrate and the fourth dielectric substrate. At least part of a first inner wall in the first through hole 105 is not covered by a conductor. The first through hole 105 and the first conductor via 103a partially overlap each other in a first direction. The first conductor via and the second conductor via partially overlap each other in the first direction. The second conductor via 103b and the second signal line 102b partially overlap each other in the first direction.SELECTED DRAWING: Figure 1(A)

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a substrate, a high-frequency circuit, an antenna device, a wireless communication device, and a method for manufacturing the substrate. [Background technology]

[0002] A known method for transmitting high-frequency signals between signal lines formed inside a multi-layer PCB is to use conductive vias (through holes) that penetrate the PCB. However, the signal lines may be electrically connected to conductive vias in layers external to the signal lines, or the high-frequency signal may be partially transmitted from the signal lines to the conductive vias in these external layers. In this case, the conductive vias in these external layers may become stubs, potentially degrading the transmission characteristics of the high-frequency signal. Furthermore, if no conductive vias are formed in these external layers and no through holes are provided, air may remain in the conductive vias in layers internal to the signal lines. In this case, the pressure of the remaining air may fluctuate due to changes in atmospheric pressure or temperature, causing stress that causes peeling or adhesion in some of the layers that make up the PCB, potentially reducing the long-term reliability of the PCB. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-262989 [Patent Document 2] International Publication No. 2019 / 207930 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the embodiments of the present invention is to provide a substrate, a high-frequency circuit, an antenna device, a wireless communication device, and a method for manufacturing the substrate that reduce degradation of the transmission characteristics of high-frequency signals and improve the long-term reliability of the substrate. [Means for solving the problem]

[0005] In order to solve the above problem, the substrate of this embodiment includes a first dielectric substrate having a first surface and a second surface and a first through hole penetrating from the first surface to the second surface; a second dielectric substrate having a third surface and a fourth surface and a first conductive via provided penetrating from the third surface to the fourth surface; a first signal line provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate having a fifth surface and a sixth surface and a second conductive via provided penetrating from the fifth surface to the sixth surface; and a third dielectric substrate provided between the second dielectric substrate and the third dielectric substrate and a first conductive via and a second conductive via. the first through hole and the first conductor via at least partially overlap in a first direction in which at least one of the first conductor via and the second conductor via passes through; the first conductor via and the second conductor via at least partially overlap in the first direction; and the second conductor via and the second signal line at least partially overlap in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1(A)] 1 is a three-dimensional view of a substrate 100 according to a first embodiment. [Figure 1(B)] 2 is an xz cross-sectional view of the substrate 100 according to the first embodiment. [Figure 2(A)] FIG. 2 is a three-dimensional view of a substrate 100′ applicable to the first embodiment. [Figure 2(B)] FIG. 2 is an xz cross-sectional view of a substrate 100′ applicable to the first embodiment. [Figure 2(C)] FIG. 1 is a three-dimensional view of a substrate 100″ applicable to the first embodiment. [Figure 3] FIG. 2 is an xz cross-sectional view of a substrate 110 applicable to the first embodiment. [Figure 4(A)] FIG. 3 is a three-dimensional view of a substrate 120 applicable to the first embodiment. [Figure 4(B)] FIG. 2 is an xz cross-sectional view of a substrate 120 applicable to the first embodiment. [Figure 4(C)] FIG. 10 is a three-dimensional view of a substrate 120′ applicable to the first embodiment. [Figure 5] FIG. 2 is an xz cross-sectional view of a substrate 120A applicable to the first embodiment. [Figure 6(A)] FIG. 10 is a three-dimensional view of a substrate 120B applicable to the first embodiment. [Figure 6(B)] FIG. 10 is an xz cross-sectional view of a substrate 120B applicable to the first embodiment. [Figure 7] FIG. 10 is an xz cross-sectional view of a substrate 120C applicable to the first embodiment. [Figure 8] FIG. 10 is an xz cross-sectional view of a substrate 120D applicable to the first embodiment. [Figure 9] FIG. 10 is an xz cross-sectional view of a substrate 120E applicable to the first embodiment. [Figure 10] FIG. 10 is an xz cross-sectional view of a substrate 120F applicable to the first embodiment. [Figure 11(A)] FIG. 3 is a three-dimensional view of a substrate 130 applicable to the first embodiment. [Figure 11(B)] FIG. 2 is an xz cross-sectional view of a substrate 130 applicable to the first embodiment. [Figure 12] FIG. 2 is an xz cross-sectional view of a substrate 140 applicable to the first embodiment. [Figure 13] FIG. 2 is an xz cross-sectional view of a substrate 150 applicable to the first embodiment. [Figure 14] FIG. 2 is an xz cross-sectional view of a substrate 160 applicable to the first embodiment. [Figure 15(A)] FIG. 10 is a three-dimensional view of a substrate 200 according to a second embodiment. [Figure 15(B)] FIG. 10 is an xz cross-sectional view of a substrate 200 according to a second embodiment. [Figure 16] FIG. 10 is an xz cross-sectional view of a substrate 200′ applicable to the second embodiment. [Figure 17] FIG. 10 is an xz cross-sectional view of a substrate 200″ applicable to the second embodiment. [Figure 18(A)] FIG. 10 is a three-dimensional view of a substrate 210 applicable to the second embodiment. [Figure 18(B)] FIG. 10 is an xz cross-sectional view of a substrate 210 applicable to the second embodiment. [Figure 19]10 is a frequency characteristic diagram of the transmission coefficient of a high frequency signal in substrates 130 and 210. FIG. [Figure 20] FIG. 10 is a configuration diagram of a high-frequency circuit 300 according to a third embodiment. [Figure 21] FIG. 10 is a configuration diagram of an antenna device 400 according to a fourth embodiment. [Figure 22] FIG. 10 is a diagram showing the configuration of a wireless communication device 500 according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. The disclosure is merely an example, and the invention is not limited to the contents described in the following embodiments. Modifications that can be easily conceived by a person skilled in the art are naturally included within the scope of the disclosure. For clearer explanation, the size, shape, etc. of each part may be changed from the actual embodiment and shown schematically in the drawings. In multiple drawings, corresponding elements may be given the same reference numerals, and detailed descriptions may be omitted.

[0008] (First embodiment) FIG. 1A is a three-dimensional view of a substrate 100 according to the first embodiment. The substrate 100 includes dielectric substrates 101a, 101b, 101c, and 101d, signal lines 102a and 102b, conductive vias 103a and 103b, and a planar conductor 104. A through-hole 105 is formed in the dielectric substrate 101a. The substrate 100 is formed by laminating multiple dielectric substrates. For ease of visualization, FIG. 1A illustrates the substrate 100 before lamination, with the dielectric substrates 101a to 101d spaced apart from one another. In the drawing, the direction in which the dielectric substrates 101a to 101d are laminated is represented as the z-direction. FIG. 1B is an x-z cross-sectional view of the substrate 100 after lamination. As an example, the x-z cross-sectional view is an x-z cross-sectional view passing through the through-hole 105. The substrate 100 may also be referred to as a multilayer substrate.

[0009] High-frequency signals propagate through the substrate 100. The high-frequency signals input from the signal line 102a or 102b pass through the conductor vias 103a and 103b and are output from the signal line 102b or 102a. The high-frequency signals are signals in a frequency band used for, for example, wireless communication, RFID, and satellite communication Ku-band, and are, for example, signals of several hundred MHz or higher.

[0010] The dielectric substrates 101a to 101d are insulating dielectric substrates. Examples of materials for the dielectric substrates 101a to 101d include PTFE (Poly Tetra Fluoro Ethylene), PPE (Poly Phenylene Ether), resin foam, liquid crystal polymer, COP (cycloolefin copolymer), glass epoxy, LTCC (Low Temperature Co-fired Ceramics), paper phenol, MgO (magnesium oxide), and glass. A composite material in which PTFE is mixed with ceramic filler or glass cloth may also be used. The dielectric substrates 101a to 101d may all have the same base material and thickness, or may differ from one another. A protective layer such as solder resist may be applied to the surfaces of the dielectric substrates 101a to 101d. The dielectric substrates 101a to 101d may be secured together with screws or clamps after being stacked. If the base material of the dielectric substrates 101a to 101d is thermoplastic, such as PTFE, they may be bonded by applying heat and pressure.

[0011] The dielectric substrate 101a is sometimes referred to as the first dielectric substrate, the dielectric substrate 101b as the second dielectric substrate, the dielectric substrate 101c as the third dielectric substrate, and the dielectric substrate 101d as the fourth dielectric substrate. Furthermore, the surface of the dielectric substrate 101a parallel to the xy plane in the +z direction is referred to as the a1 plane, the surface of the dielectric substrate 101a parallel to the xy plane in the -z direction is referred to as the a2 plane, the surface of the dielectric substrate 101b parallel to the xy plane in the +z direction is referred to as the b1 plane, the surface of the dielectric substrate 101b parallel to the xy plane in the -z direction is referred to as the b2 plane, the surface of the dielectric substrate 101c parallel to the xy plane in the +z direction is referred to as the c1 plane, the surface of the dielectric substrate 101c parallel to the xy plane in the -z direction is referred to as the c2 plane, the surface of the dielectric substrate 101d parallel to the xy plane in the +z direction is referred to as the d1 plane, and the surface of the dielectric substrate 101a parallel to the xy plane in the -z direction is referred to as the d2 plane. Side a1 is sometimes called side 1, side a2 is called side 2, side b1 is called side 3, side b2 is called side 4, side c1 is called side 5, side c2 is called side 6, side d1 is called side 7, and side d2 is called side 8.

[0012] The signal lines 102a and 102b transmit high-frequency signals. That is, the signal lines 102a and 102b are signal lines for transmitting high-frequency signals from one signal line to the other. The signal line 102a is provided between the dielectric substrates 101a and 101b. The signal line 102b is provided between the dielectric substrates 101c and 101d. As an example, in FIG. 1A, the signal line 102a is provided on the b1 surface of the dielectric substrate 101b, and the signal line 102b is provided on the d1 surface of the dielectric substrate 101d. The signal lines 102a and 102b are made of materials such as copper, nickel, gold, and silver. The surfaces of the signal lines 102a and 102b may be plated with different types of conductors, or may be coated with solder resist, flux, solder labeler, or the like. The material and shape of the signal lines 102a and 102b may be the same or different. Furthermore, an impedance matching element such as a stub or a step structure may be connected to the signal lines 102a and 102b. Note that the signal line 102a may also be referred to as a first signal line, and the signal line 102b may also be referred to as a second signal line.

[0013] Conductive vias 103a and 103b propagate a high-frequency signal from one of signal lines 102a and 102b to the other signal line. That is, a high-frequency signal input to one of signal lines 102a and 102b propagates to the other signal line through conductor vias 103a and 103b. Conductive via 103a penetrates from the b1 surface to the b2 surface of dielectric substrate 101b, and conductor via 103b penetrates from the c1 surface to the c2 surface of dielectric substrate 101c. Note that conductor via 103a may also be referred to as a first conductor via, and conductor via 103b may also be referred to as a second conductor via. In FIG. 1(A), conductor vias 103a and 103b are shown as cylindrical, but they may have any shape, such as an elliptical shape, a rectangular shape, or a shape that includes at least a partial curve.

[0014] The signal line 102a and the conductor via 103a are electrically connected or are provided at a distance that allows high-frequency signals to propagate due to capacitance. The conductor via 103a and the through-hole 105 at least partially overlap in the direction in which at least one of the conductor vias 103a and 103b penetrates (the z-direction in this embodiment). Hereinafter, the direction in which at least one of the conductor vias 103a and 103b penetrates may also be referred to as the first direction. The conductor vias 103a and 103b at least partially overlap in the first direction. Furthermore, the conductor via 103b and the signal line 102b at least partially overlap in the first direction. This connects the space of the through-hole 105, the space of the conductor via 103a, and the space of the conductor via 103b (providing a path for air). This allows the air pressure in these spaces to be made approximately the same as the air pressure outside the substrate 100, even if changes in temperature or air pressure occur outside the substrate 100, thereby reducing stress that causes peeling or adhesion to parts of the layers (dielectric substrate) that form the substrate 100. As a result, the long-term reliability of the substrate 100 is improved.

[0015] The planar conductor 104a forms a microstrip line together with the signal lines 102a and 102b. The planar conductor 104a is disposed between the dielectric substrate 101b and the dielectric substrate 101c. As an example, in FIG. 1A, the planar conductor 104a is disposed on the c1 surface of the dielectric substrate 101c. The planar conductor 104a is made of a conductor such as copper, nickel, gold, or silver. The surface of the planar conductor 104a may be plated with a different type of conductor. The surface of the planar conductor 104a may be coated with solder resist, flux, solder labeler, or the like. The area of the planar conductor 104a is larger than that of the signal line 102a. The area of the planar conductor 104a is also larger than that of the signal line 102b. The planar conductor 104a may also be referred to as the first planar conductor 104a.

[0016] Conductive vias 103a and 103b are separated from planar conductor 104a and are not electrically connected. Signal line 102a and planar conductor 104a form a microstrip line. Similarly, signal line 102b and planar conductor 104a form a microstrip line. Note that a conductor pattern (not shown) may be added near signal lines 102a and 102b to form a coplanar line or a fin-line line.

[0017] The through hole 105 penetrates from the a1 surface to the a2 surface of the dielectric substrate 101a. The through hole 105 can be formed by any method, for example, by drilling or laser. Although the through hole 105 is shown as having a cylindrical shape in FIG. 1(A), the through hole 105 can have any shape other than a cylindrical shape, such as an elliptical shape, a rectangular shape, or a shape including at least a partial curve. The through hole 105 may also have a bent midway.

[0018] The inner wall of the through hole 105, i.e., at least a portion of the dielectric substrate 101a where the through hole 105 is formed, is not covered with a conductor. More specifically, the inner wall of the through hole 105 is not covered with a conductor within a predetermined distance in the first direction from the signal line 102a. This predetermined distance is determined based on at least one of the diameter of the through hole 105, the diameter of the conductor via 103a, and the width of the signal line 102a. This reduces the possibility that a high-frequency signal will propagate to a portion of the dielectric substrate 101a and the possibility that the through hole 105 will become a stub. As a result, deterioration of the transmission characteristics of high-frequency signals can be reduced. The through hole 105 may also be referred to as a first through hole, and the inner wall of the through hole 105 may also be referred to as a first inner wall.

[0019] The components of the substrate 100 have been described above. This embodiment is merely an example, and various modifications can be implemented. Modifications that can be applied to this embodiment will be described below. Hereinafter, components that are the same as those in this embodiment will be assigned the same reference numerals and descriptions thereof will be omitted.

[0020] (Variation 1) The substrate 100 is manufactured by stacking dielectric substrates 101a to 101d. The dielectric substrates 101a to 101d are manufactured individually. Using FIG. 1(A) as an example, the substrate 100 is manufactured by stacking, in order from the +z direction, a dielectric substrate 101a having a through-hole 105, a signal line 102a, a dielectric substrate 101b having a conductive via 103a, a planar conductor 104a, a dielectric substrate 101c having a conductive via 103b, the signal line 102b, and a dielectric substrate 101d. The signal line 102a may be formed on the b1 surface in the manufacture of the dielectric substrate 101b, the planar conductor 104a may be formed on the c1 surface in the manufacture of the dielectric substrate 101c, or the signal line 102b may be formed on the d1 surface in the manufacture of the dielectric substrate 101d.

[0021] (Variation 2) FIG. 2(A) is a three-dimensional view of a substrate 100′ in Modification 2. The substrate 100′ is stacked by bonding the dielectric substrates 101a to 101d together with adhesive layers. An adhesive layer 106a is provided between the dielectric substrates 101a and 101b, bonding the dielectric substrates 101a and 101b together. An adhesive layer 106b is provided between the dielectric substrates 101b and 101c, bonding the dielectric substrates 101b and 101c together. An adhesive layer 106c is provided between the dielectric substrates 101c and 101d, bonding the dielectric substrates 101c and 101d together. For ease of visibility, FIG. 2(A) shows the substrate 100′ before stacking with the dielectric substrates 101a to 101d spaced apart from one another. FIG. 2(B) is an xz cross-sectional view of the substrate 100′ after stacking.

[0022] The adhesive layers 106a to 106c are insulators that bond the dielectric substrates together, and examples of such materials include bonding film and prepreg. At least one of the adhesive layers 106a to 106c may be composed of multiple adhesive layers. For example, the adhesive layer 106a may be composed of two adhesive layers. The adhesive layer 106a may also be referred to as the first adhesive layer, the adhesive layer 106b as the second adhesive layer, and the adhesive layer 106c as the third adhesive layer.

[0023] In the substrate 100′, the adhesive layer 106b may not electrically connect the conductor vias 103a and 103b, and the adhesive layer 106c may not electrically connect the conductor via 103b and the signal line 102b. In these cases, DC signals do not propagate. However, high-frequency signals can propagate due to the capacitance between the conductor vias 103a and 103b and the capacitance between the conductor via 103b and the signal line 102b. The capacitance can be increased by increasing the area of the conductors facing each other via the adhesive layer and by reducing the thickness of the adhesive layer. For example, this can be achieved by increasing the area of the land of the opposing conductor via 103, increasing the area of the signal line 103, or reducing the thickness of the adhesive layer 106 in the first direction. Increasing the capacitance can improve the transmission characteristics (also referred to as passing characteristics) of high-frequency signals.

[0024] 2(A), in substrate 100' before lamination, adhesive layers 106a and 106b do not have holes corresponding to through-hole 105 and conductive vias 103a and 103b. However, due to the heating and pressurizing process when dielectric substrates 101a to 101d are laminated, the adhesive layers of adhesive layers 106a and 106b in the portions corresponding to through-hole 105 and conductive vias 103a and 103b flow into through-hole 105 and conductive vias 103a and 103b. As a result, holes corresponding to through-hole 105 and conductive vias 103a and 103b are formed in adhesive layers 106a and 106b.

[0025] FIG. 2(C) is a three-dimensional view of the substrate 100" when holes are drilled in the adhesive layers 106a and 106b before lamination. Holes corresponding to the through-hole 105 and the conductive vias 103a and 103b may be drilled in the adhesive layers 106a and 106b before lamination. Similarly, in the substrate 100', holes corresponding to the through-hole 105 and the conductive vias 103a and 103b may be drilled in the adhesive layers 106a and 106b after lamination.

[0026] As described above, in Modification 2, the dielectric substrates 101a to 101d can be bonded together by the adhesive layers 106a to 106c.

[0027] (Variation 3) FIG. 3 is an xz cross-sectional view of the substrate 110 in Modification 3. The substrate 110 further includes planar conductors 104b and 104c in the substrate 100′. The signal line 102a is provided between the planar conductors 104b and 104a, and the signal line 102b is provided between the planar conductors 104a and 104c. As an example, in FIG. 3, the planar conductor 104b is provided on the a1 surface of the dielectric substrate 101a, and the planar conductor 104c is provided on the d2 surface of the dielectric substrate 101d. Note that the planar conductor 104b may also be referred to as the second planar conductor, and the planar conductor 104c may also be referred to as the third planar conductor.

[0028] The planar conductors 104b and 104c can be the same as those described for the planar conductor 104a. At least one of the planar conductors 104a, 104b, and 104c may be different. The planar conductors 104a, 104b, and 104c may have the same shape or at least one different shape. The area of the planar conductor 104b is larger than that of the signal line 102a, and the area of the planar conductor 104c is larger than that of the signal line 102b. This allows the planar conductors 104b, the signal line 102a, and the planar conductor 104a to form a stripline. Similarly, the planar conductors 104a, the signal line 102b, and the planar conductor 104c also form a stripline. This allows for suppression of high-frequency signal radiation from the signal lines 102a and 102b to the outside of the substrate 110. As a result, degradation of the transmission characteristics of high-frequency signals can be reduced.

[0029] (Variation 4) The substrate 110 may further include a planar conductor 104a and a planar conductor facing each other via an adhesive layer 106b. FIG. 4A is a three-dimensional view of a substrate 120 according to Modification 4. The substrate 120 further includes a planar conductor 104d in the substrate 110. The planar conductor 104d is provided between the signal line 102a and the planar conductor 104a, or between the planar conductor 104a and the signal line 102b. The planar conductors 104a and 104d face each other via the adhesive layer 106b. As an example, in FIG. 4A, the planar conductor 104a is provided on the c1 surface of the dielectric substrate 101c, and the planar conductor 104d is provided on the b2 surface of the dielectric substrate 101b. For ease of visibility, FIG. 4A illustrates the substrate 120 before stacking with the dielectric substrates 101a to 101d spaced apart from each other. FIG. 4B is an x-z cross-sectional view of the substrate 120 after stacking. The planar conductor 104d may also be referred to as a fourth planar conductor.

[0030] The planar conductor 104d can be the same as the planar conductor 104a. At least one of the planar conductors 104a to 104d may be different. The planar conductors 104a to 104d may have the same shape, or at least one of them may be different. The area of the planar conductor 104d is larger than the area of the signal line 102a. Like the planar conductor 104a, the planar conductor 104d is separated from and electrically disconnected from the conductor vias 103a and 103b. This allows the planar conductor 104b, the signal line 102a, and the planar conductor 104d to form a stripline. Similarly, the planar conductor 104a, the signal line 102b, and the planar conductor 104c to form a stripline. This prevents the characteristic impedance of the stripline formed by the planar conductor 104b, the signal line 102a, and the planar conductor 104d from changing even if the thickness of the adhesive layer 106b changes. When the planar conductor 104a is provided on the b2 surface of the dielectric substrate 101b, the planar conductor 104d is provided on the c1 surface of the dielectric substrate 101c. In this case, the planar conductor 104b, the signal line 102a, and the planar conductor 104a form a stripline, and the planar conductor 104d, the signal line 102b, and the planar conductor 104c form a stripline. Similarly, even if the thickness of the adhesive layer 106b changes, the characteristic impedance of the stripline formed by the planar conductor 104d, the signal line 102b, and the planar conductor 104c does not change. This further suppresses radiation of high-frequency signals from the signal lines 102a and 102b to the outside of the substrate 120. As a result, degradation of the transmission characteristics of high-frequency signals can be reduced.

[0031] Furthermore, in the substrates 110 and 120, the through-holes 105 are provided so as to penetrate the planar conductor 104b as well. This allows the through-holes 105 to act like capacitance that cancels out the inductance components of the conductive vias 103a and 103b. As a result, it is possible to reduce the degradation of the transmission characteristics of high-frequency signals.

[0032] Similar to Modification 2, holes corresponding to the through-hole 105 and the conductive vias 103a and 103b may or may not be drilled in the adhesive layers 106a and 106b before lamination. Fig. 4(A) shows the substrate 120 when no holes are drilled in the adhesive layers 106a and 106b, and Fig. 4(C) is a three-dimensional view of the substrate 120' when holes are drilled in the adhesive layers 106a and 106b before lamination. In the substrate 120, holes corresponding to the through-hole 105 and the conductive vias 103a and 103b may also be drilled in the adhesive layers 106a and 106b after lamination.

[0033] (Variation 5) In the substrate 120, the signal line 102a was provided on the b1 surface of the dielectric substrate 101b. The signal line 102a may be provided facing the b1 surface via the adhesive layer 106a. FIG. 5 is an xz cross-sectional view of the substrate 120A. The substrate 120A has the same components as the substrate 120, but the signal line 102a is provided on the a2 surface of the dielectric substrate 101a. In this case, the signal line 102a and the conductor via 103a may not be electrically connected by the adhesive layer 106a, but a high-frequency signal can be propagated by the capacitance between the signal line 102a and the conductor via 103a. Note that the thickness of the adhesive layer 106a in this case is thick enough to allow a high-frequency signal to be propagated by the capacitance between the signal line 102a and the conductor via 103a.

[0034] In this case, the distance between the planar conductor 104b and the signal line 102a does not change depending on the thickness of the adhesive layer 106a. If an element (not shown) is provided on the planar conductor 104b, the element will operate due to electromagnetic coupling between the planar conductor 104b and the signal line 102a. Since the distance between the planar conductor 104b and the signal line 102a does not change, the element can operate stably. An example of such an element is an antenna element (patch antenna) used for proximity coupling feeding or slot coupling.

[0035] (Variation 6) The signal line 102a is provided in the +x direction from the conductor via 103a, but may also be provided in the -x direction. Fig. 6(A) shows a substrate 120B in Modification 6. The substrate 120B has the same components as the substrate 120, but the signal line 102a is also provided in the -x direction. For ease of visibility, Fig. 6(A) shows the substrate 120B before lamination with the dielectric substrates 101a to 101d spaced apart. Fig. 6(B) is an xz cross-sectional view of the substrate 120B after lamination.

[0036] When a high-frequency signal is input to signal line 102b on substrate 120B, it is output from signal line 102a, but is divided into two and output in the ±x directions along which signal line 102a is provided. This allows the high-frequency signal to be divided and output.

[0037] In the sixth modification, the signal line 102a is arranged in the ±x direction, but the direction in which the signal line is arranged and the number of high-frequency signal distributions are arbitrary. For example, the signal line 102a may be arranged in the ±y direction to distribute the signal in two directions, or the signal line 102a may be arranged in both the ±x and +y directions to distribute the signal in three directions, or the signal line 102a may be arranged in both the ±x and ±y directions to distribute the signal in four directions. Furthermore, the signal line 102b may be arranged in any direction, similar to the signal line 102a, from the conductor via 103b, not just in the +x direction, to distribute the high-frequency signal to any number of directions. This allows the construction of a one-input / multiple-output, multiple-input / single-output, or multiple-input / multiple-output board.

[0038] (Variation 7) In the present embodiment, it has been described that it is sufficient that the through hole 105 and the conductor via 103a, the conductor via 103a and the conductor via 103b, and the conductor via 103b and the signal line 102b overlap at least partially in the first direction.

[0039] 7 is an xz cross-sectional view of the substrate 120C after lamination. The substrate 120C has the same components as the substrate 120, but the through-hole 105 and the conductor via 103a are misaligned in the xy plane. Even in this case, the through-hole 105 and the conductor via 103a at least partially overlap in the first direction, so the substrate operates in the same manner as the present embodiment and provides the same effects. Furthermore, the design freedom can be improved regarding the position where the through-hole 105 is provided.

[0040] FIG. 8 is an xz cross-sectional view of the substrate 120D after lamination. The substrate 120D has the same components as the substrate 120, but a vent is provided in the through-hole 105. This vent can be provided, for example, by end-milling or drilling the dielectric substrate 101a. Even if a vent is provided, the through-hole 105 is a hole that penetrates from the a1 surface to the a2 surface of the dielectric substrate 101a. Even in this case, the through-hole 105 and the conductor via 103a at least partially overlap in the first direction, so the device operates similarly to the present embodiment and achieves similar effects. Furthermore, the design freedom for the position of the through-hole 105 can be improved. For example, when placing a circuit element (not shown) on the planar conductor 104b, the freedom of placement can be improved. The circuit element is, for example, an electronic component such as a resistor or a chip capacitor.

[0041] FIG. 9 is an x-z cross-sectional view of the substrate 120E after lamination. The substrate 120E has the same components as the substrate 120, but the positions of the through hole 105 and the conductor via 103a in the x-y plane and the positions of the conductor vias 103a and 103b in the x-y plane are shifted, and the length of the signal line 102b is changed. Even in this case, the through hole 105 and the conductor via 103a at least partially overlap in the first direction, the conductor vias 103a and 103b at least partially overlap in the first direction, and the conductor via 103b and the signal line 102b at least partially overlap in the first direction. Therefore, the substrate 120E operates similarly to the present embodiment and achieves similar effects. Furthermore, the design freedom can be improved with regard to the positions of the through hole 105 and the conductor vias 103a and 103b.

[0042] (Variation 8) In this embodiment, at least a portion of the inner wall of the through hole 105 is not covered with a conductor. FIG. 10 is an xz cross-sectional view of the substrate 120F after lamination in Modification 8. The substrate 120F has the same components as the substrate 120, but a portion of the inner wall of the through hole 105 is covered with a conductor. However, the inner wall of the through hole 105 is not covered with a conductor within a distance D from the signal line 102a in the first direction. In the substrate 120F, the dielectric substrate 101a and the dielectric substrate 101b are bonded with an adhesive layer 106a. In this case, the distance D is determined based on at least one of the diameter of the through hole 105, the diameter of the conductor via 103a, the width of the signal line 102a, the material of the adhesive layer 106a, and the thickness of the adhesive layer 106a in the first direction. This reduces the possibility that a high-frequency signal will propagate to a portion of the dielectric substrate 101a and the possibility that the through hole 105 will become a stub. As a result, the deterioration of the transmission characteristics of high frequency signals can be reduced.

[0043] (Variation 9) FIG. 11(A) is a three-dimensional view of a substrate 130 in Modification Example 9. In addition to the components of the substrate 120, the substrate 130 includes a plurality of conductor vias 131a in the dielectric substrate 101a, a plurality of conductor vias 131b in the dielectric substrate 101b, a plurality of conductor vias 131c in the dielectric substrate 101c, and a plurality of conductor vias 131d in the dielectric substrate 101d. For ease of visibility, FIG. 11(A) illustrates the substrate 130 before lamination with the dielectric substrates 101a to 101d spaced apart from one another. FIG. 11(B) is an xz cross-sectional view of the substrate 130 after lamination. Note that the conductor via 131a may also be referred to as the third conductor via, the conductor via 131b as the fourth conductor via, the conductor via 131c as the fifth conductor via, and the conductor via 131d as the sixth conductor via.

[0044] The conductor vias 131a penetrate from the a1 surface to the a2 surface of the dielectric substrate 101a and are electrically connected to the planar conductor 104b. The conductor vias 131a are provided around the through-holes 105, and the spacing between the conductor vias 131a in the xy plane is equal to or less than half the guide wavelength of the high-frequency signal. In Fig. 11(A), the conductor vias 131a are provided so as to surround the through-holes 105, but this arrangement is not limiting and it is sufficient that at least one side of the periphery of the through-holes 105 is covered.

[0045] The conductor via 131b penetrates from the b1 surface to the b2 surface of the dielectric substrate 101b and is electrically connected to the planar conductor 104d. The conductor vias 131b are provided around the conductor via 103a and the signal line 102a, and the distance between the conductor vias 131b in the xy plane is equal to or less than half the guide wavelength of the high-frequency signal. Note that in FIG. 11(A), the conductor vias 131b are provided so as to surround the conductor via 103a and the signal line 102a, but this arrangement is not limited thereto; it is sufficient that at least one side of the periphery of the conductor via 103a and the signal line 102a is covered. Furthermore, the conductor vias 131a and 131b at least partially overlap each other in the first direction. The conductor vias 131a and 131b are not electrically connected when the adhesive layer 106a is present, but high-frequency signals can be propagated due to the capacitance between the conductor vias 131a and 131b. Conductive vias 131a and 131b can reduce leakage of high frequency signals due to the parallel plate mode in conductor via 103a and signal line 102a, thereby reducing deterioration in the transmission characteristics of high frequency signals.

[0046] The conductor via 131c penetrates from the c1 surface to the c2 surface of the dielectric substrate 101c and is electrically connected to the planar conductor 104a. The conductor vias 131c are arranged around the conductor vias 103b, and the spacing between the conductor vias 131c in the xy plane is equal to or less than half the guide wavelength of the high-frequency signal. Note that in Fig. 11(A), the conductor vias 131c are arranged to surround the conductor via 103b, but this arrangement is not limited thereto, and it is sufficient that at least one side of the periphery of the conductor via 103b is covered.

[0047] The conductor via 131d penetrates the dielectric substrate 101d from the d1 plane to the d2 plane and is electrically connected to the planar conductor 104c. The conductor vias 131d are provided around the conductor vias 103b and the signal line 102b, and the distance between the conductor vias 131d in the xy plane is equal to or less than half the guide wavelength of the high-frequency signal. Note that in FIG. 11(A), the conductor vias 131d are provided so as to surround the conductor vias 103b and the signal line 102b, but this arrangement is not limited thereto; it is sufficient that at least one side of the periphery of the conductor vias 103b and the signal line 102b is covered. Furthermore, the conductor vias 131c and 131d at least partially overlap in the first direction. The conductor vias 131c and 131d are not electrically connected when the adhesive layer 106c is present, but high-frequency signals can be propagated due to the capacitance between the conductor vias 131c and 131d. The conductor vias 131c and 131d can reduce leakage of high frequency signals due to the parallel plate mode in the conductor via 103b and the signal line 102b, thereby reducing deterioration in the transmission characteristics of high frequency signals.

[0048] The conductor vias 131b and 131c may at least partially overlap in the first direction as shown in Figures 11(A) and 11(B). Also, Figures 11(A) and 11(B) show the case where the conductor vias 131a to 131d are provided, but only the conductor vias 131a and 131b or only the conductor vias 131c and 131d may be provided.

[0049] (Variation 10) Although the above description concerns a substrate composed of four dielectric substrates 101a to 101d, a substrate composed of five or more laminated dielectric substrates may also be used. FIG. 12 is an xz cross-sectional view of substrate 140 after lamination. In addition to the components of substrate 120, substrate 140 further includes dielectric substrate 101e, conductor via 103c, planar conductors 104e and 104f, and adhesive layer 106d. Substrate 140 has a structure in which dielectric substrate 101e is provided between dielectric substrates 101c and 101d of substrate 120. Furthermore, the surface of dielectric substrate 101e parallel to the xy plane in the +z direction is referred to as plane e1, and the surface of dielectric substrate 101e parallel to the xy plane in the -z direction is referred to as plane e2.

[0050] Dielectric substrate 101e is provided between dielectric substrates 101c and 101d. The same materials as those described for dielectric substrates 101a to 101d can be used. Conductive via 103c is provided penetrating the e1 and e2 surfaces of dielectric substrate 101e, and the same materials as those described for conductor vias 103a and 103b can be used. In substrate 140, conductor vias 103b and 103c at least partially overlap in the first direction, and conductor via 103c and signal line 102b at least partially overlap in the first direction. This allows connection between the outside of substrate 140 and the spaces between through-hole 105 and conductor vias 103a to 103c.

[0051] The planar conductors 104e and 104f are provided between the dielectric substrates 101c and 101e. In FIG. 12, the planar conductor 104e is provided on the c2 surface of the dielectric substrate 101c, and the planar conductor 104f is provided on the e1 surface of the dielectric substrate 101e. The planar conductors 104e and 104f can be made of the same materials as those described for the planar conductors 104a to 104d. The area of the planar conductors 104e and 104f is larger than the area of the signal lines 102a and 102b. The role of the planar conductors 104e and 104f, like the planar conductors 104d and 104a, is to suppress radiation of high-frequency signals outside the substrate 140.

[0052] Adhesive layer 106d is provided between dielectric substrates 101c and 101e and bonds dielectric substrates 101c and 101e together. In this case, adhesive layer 106c bonds dielectric substrates 101e and 101d together. Planar conductors 104e and 104f face each other via adhesive layer 106d. The adhesive layer 106d can be made of the same material as described for adhesive layers 106a to 106c.

[0053] Like the substrate 120, the substrate 140 propagates a high-frequency signal input from one of the signal lines 102a and 102b to the other signal line. The high-frequency signal propagates from one signal line to the other signal line via the conductive vias 103a, 103b, and 103c. The conductive vias 103b and 103c, and the conductive via 103c and the signal line 102b may not be electrically connected by the adhesive layers 106d and 106c. However, the high-frequency signal can be propagated by the capacitance between the conductive vias 103b and 103c, and the capacitance between the conductive via 103c and the signal line 102b. As described above, even if one layer of the dielectric substrate 101 having the conductive via 103 is added, the operation is the same as in this embodiment. Even if two or more layers of the dielectric substrate 101 having the conductive via 103 are added, the operation is the same as in this modification. Increasing the number of layers of the dielectric substrate 101 increases the rigidity of the substrate. Here, at least one of the planar conductors 101d to 101f does not have to be provided, which can reduce the number of manufacturing steps for the substrate 140 and keep manufacturing costs down.

[0054] Although the case where the dielectric substrate 101 having the conductor via 103 is added to the substrate 140 has been described, the dielectric substrate 101 having the through-hole 105 may also be added. FIG. 13 is an xz cross-sectional view of the substrate 150 after lamination. In addition to the components of the substrate 120, the substrate 150 further includes a dielectric substrate 101f and an adhesive layer 106e. The dielectric substrate 101f has a through-hole 105b. Here, the through-hole 105 of the dielectric substrate 101a is referred to as 105a. The substrate 150 has a structure in which the dielectric substrate 101a of the substrate 120 is further provided with a dielectric substrate 101f. Furthermore, the surface of the dielectric substrate 101f parallel to the xy plane in the +z direction is referred to as the f1 plane, and the surface of the dielectric substrate 101f parallel to the xy plane in the -z direction is referred to as the f2 plane.

[0055] Dielectric substrate 101f is provided on dielectric substrate 101a, and may be made of the same materials as those described for dielectric substrates 101a to 101e. Through-hole 105b is provided penetrating dielectric substrate 101f from the f1 plane to the f2 plane. The method and shape of through-hole 105b may be the same as those described for through-hole 105.

[0056] The inner wall of the through hole 105b, i.e., the portion of the dielectric substrate 101f where the through hole 105b is formed, may or may not be covered with a conductor. This is because the dielectric substrate 101a having the through hole 105a provides a sufficient distance to prevent degradation of the transmission characteristics of high-frequency signals. In the substrate 150, the through holes 105b and 105a at least partially overlap in the first direction. This allows connection between the outside of the substrate 150 and the spaces of the through holes 105b, 105a, and the conductive vias 103a, 103b.

[0057] Adhesive layer 106e is provided between dielectric substrates 101f and 101a to bond dielectric substrates 101f and 101a together. Adhesive layer 106e can be made of the same materials as those described for adhesive layers 106a to 106c.

[0058] The propagation of a high-frequency signal from one of the signal lines 102a and 102b to the other is the same as in the case of the substrate 120. As described above, even if one more layer of the dielectric substrate 101 having the through-hole 105 is added, the operation can be the same as in this embodiment. Even if two or more layers of the dielectric substrate 101 having the through-hole 105 are added, the operation is the same as in this modified example. By increasing the number of layers of the dielectric substrate 101, the rigidity of the substrate can be increased. Note that the increase in the number of the dielectric substrate 101 having the conductive via 103 and the increase in the number of the dielectric substrate 101 having the through-hole 105 may be performed in combination.

[0059] (Variation 11) In the above, the through hole 105 and the conductive vias 103a and 103b are arranged in the -z direction, but they may also be arranged in the +z direction. FIG. 14 is an x-z cross-sectional view of the substrate 160 after lamination. In addition to the components of the substrate 120, the substrate 160 further includes dielectric substrates 101g and 101h, a signal line 102c, conductive vias 103d and 103e, planar conductors 104g, 104h, 104i, and 104j, and adhesive layers 106f and 106g. The dielectric substrate 101h has a through hole 105c. The substrate 160 outputs a high-frequency signal input to one of the signal lines 102a and 102c from the other of the signal lines 102a and 102c via the conductive vias 103a and 103b, the signal line 102b, and the conductive vias 103d and 103e. In this modification, the through-hole 105 in the dielectric substrate 101a is referred to as 105a.

[0060] The dielectric substrates 101g and 101h can be made of the same materials as those described for the dielectric substrates 101a to 101f. The surface of the dielectric substrate 101g parallel to the xy plane in the +z direction is referred to as the g1 surface, the surface of the dielectric substrate 101g parallel to the xy plane in the -z direction is referred to as the g2 surface, the surface of the dielectric substrate 101h parallel to the xy plane in the +z direction is referred to as the h1 surface, and the surface of the dielectric substrate 101h parallel to the xy plane in the -z direction is referred to as the h2 surface. Note that the dielectric substrate 101g may also be referred to as the fifth dielectric substrate, the dielectric substrate 101h as the sixth dielectric substrate, the g1 surface as the ninth surface, the g2 surface as the tenth surface, the h1 surface as the eleventh surface, and the h2 surface as the twelfth surface.

[0061] The signal line 102c propagates a high-frequency signal. The signal line 102c is a signal line for propagating a high-frequency signal from one of the signal lines 102a and 102c to the other. The signal line 102c is provided between the dielectric substrates 101g and 101h. As an example, in FIG. 14, the signal line 102c is provided on the h1 surface of the dielectric substrate 101h. The material, surface treatment, connected elements, etc. of the signal line 102c can be the same as those described for the signal lines 102a and 102b. The signal line 102c is also sometimes referred to as a third signal line.

[0062] Conductive vias 103d and 103e propagate high-frequency signals from one of signal lines 102b and 102c to the other signal line. That is, a high-frequency signal propagated to signal line 102b propagates to signal line 102c through conductor vias 103d and 103e, and a high-frequency signal input to signal line 102c propagates to signal line 102b through conductor vias 103e and 103d. Conductive via 103d penetrates from the d1 surface to the d2 surface of dielectric substrate 101d, and conductor via 103e penetrates from the g1 surface to the g2 surface of dielectric substrate 101g. Conductive via 103d is sometimes referred to as the seventh conductor via, and conductor via 103e is sometimes referred to as the eighth conductor via. In FIG. 14, conductor vias 103d and 103e are depicted as cylindrical, but they may have any shape, such as an elliptical shape, a rectangular shape, or a shape including at least a partial curve.

[0063] The signal line 102b and the conductor via 103d, and the conductor via 103e and the signal line 102c are electrically connected or are located at a distance that allows high-frequency signals to propagate due to capacitance. The conductor via 103e and the through-hole 105c at least partially overlap in the direction in which at least one of the conductor vias 103d and 103e penetrates (the z-direction in this modification). Hereinafter, the direction in which at least one of the conductor vias 103d and 103e penetrates may also be referred to as the second direction. In this modification, the first direction and the second direction will be described as the same direction. The conductor vias 103d and 103e at least partially overlap in the second direction. This connects the space of the through-hole 105c, the space of the conductor via 103d, and the space of the conductor via 103e (providing a path for air). This allows the air pressure in these spaces to be made approximately equal to the air pressure outside the substrate 160, even if changes in temperature or air pressure occur outside the substrate 160, thereby reducing stress that could cause peeling or adhesion to a portion of the layer (dielectric substrate) that forms the substrate 160. As a result, the long-term reliability of the substrate 160 is improved. Note that the conductor vias 103b and 103d do not overlap in at least one of the first and second directions. By providing separate air paths for the through-hole 105a, the conductor vias 103a, and 103b, and the through-hole 105c, the conductor vias 103d and 103e, a transmission path for a high-frequency signal can be constructed, avoiding other conductor patterns (planar conductors) not shown.

[0064] Planar conductors 104g, 104h, 104i, and 104j, together with other planar conductors 104 and signal lines 102b and 102c, form a microstrip line. Planar conductors 104g and 104h are provided between dielectric substrates 101c and 101d, facing each other via adhesive layer 106c. Planar conductor 104i is provided between dielectric substrates 101d and 101g, facing planar conductor 104c via adhesive layer 106f. Planar conductor 104j is provided so that signal line 102c is located between planar conductors 104i and 104j. 14, the planar conductor 104g is provided on the c2 surface of the dielectric substrate 101c, the planar conductor 104h is provided on the d1 surface of the dielectric substrate 101d, the planar conductor 104i is provided on the g1 surface of the dielectric substrate 101g, and the planar conductor 104j is provided on the h2 surface of the dielectric substrate 101h. The materials, shapes, and surface treatments of the planar conductors 104g to 104j can be the same as those described for the planar conductor 104a. The planar conductor 104j is sometimes referred to as the fifth planar conductor.

[0065] The area of the planar conductors 104g to 104h is larger than the area of the signal lines 102b and 102c. The conductive vias 103d and 103e are separated from the planar conductor 104c and are not electrically connected. The signal line 102b and the planar conductor 104c form a microstrip. Similarly, the signal line 102c and the planar conductor 104i form a microstrip. Note that a conductor pattern (not shown) may be added near the signal lines 102b and 102c to form a coplanar line or a fin-line line. Furthermore, the planar conductors 104g and 104h are separated from the signal line 102b, the conductive via 103b, and the conductive via 103d and are not electrically connected. The planar conductors 104c and 104i are separated from the conductive vias 103d and 103e and are not electrically connected. As a result, the planar conductor 104i, the signal line 102c, and the planar conductor 104j form a strip line. Similarly, the planar conductors 104g and 104h are also configured as strip lines with other planar conductors and signal lines, which makes it possible to suppress radiation of high-frequency signals from the signal lines 102b and 102c to the outside of the substrate 160. As a result, it is possible to reduce deterioration in the transmission characteristics of high-frequency signals.

[0066] The through hole 105c is provided so as to penetrate from the h1 surface to the h2 surface of the dielectric substrate 101h. The method and shape of the through hole 105c can be the same as those described for the through holes 105 and 105b.

[0067] The inner wall of the through hole 105c, i.e., at least a portion of the dielectric substrate 101h where the through hole 105c is formed, is not covered with a conductor. More specifically, the inner wall of the through hole 105c is not covered with a conductor within a predetermined distance in the second direction from the signal line 102c. This predetermined distance is determined based on at least one of the diameter of the through hole 105c, the diameter of the conductor via 103e, the width of the signal line 102c, the material of the adhesive layer 106g, and the thickness of the adhesive layer 106g in the second direction. This reduces the possibility that a high-frequency signal will propagate to a portion of the dielectric substrate 101h and the possibility that the through hole 105c will become a stub. As a result, degradation of the transmission characteristics of high-frequency signals can be reduced. Note that the through hole 105c may also be referred to as a second through hole, and the inner wall of the through hole 105c may also be referred to as a second inner wall.

[0068] Furthermore, in the substrate 160, the through-hole 105c is provided so as to penetrate the planar conductor 104j as well. This allows the through-hole 105c to act like a capacitance that cancels out the inductance components of the conductive vias 103d and 103e. As a result, it is possible to reduce the deterioration of the transmission characteristics of high-frequency signals.

[0069] Adhesive layer 106f is provided between dielectric substrates 101d and 101e to bond them together. Adhesive layer 106g is provided between dielectric substrates 101e and 101f to bond them together. Planar conductors 104c and 104i face each other via adhesive layer 106f. Planar conductors 104c and 104i face each other via adhesive layer 106f. Adhesive layers 106f and 106g can be made of the same materials as those described for adhesive layers 106a to 106c.

[0070] The components of this modification have been described above. In the substrate 160, the conductive vias 103d and 103e may not be electrically connected by the adhesive layer 106f, and the conductive via 103e may not be electrically connected to the signal line 102c by the adhesive layer 106g. In these cases, a DC signal will not propagate. However, a high-frequency signal can propagate due to the capacitance between the conductive vias 103d and 103e and the capacitance between the conductive via 103e and the signal line 102c.

[0071] In the substrate 160 of this modification, a high-frequency signal input to one of the signal lines 102a and 102c is output from the other of the signal lines 102a and 102c via the conductive vias 103a and 103b, the signal line 102b, and the conductive vias 103d and 103e. By providing separate air passages for the through-hole 105a and the conductive vias 103a and 103b and the through-hole 105c and the conductive vias 103d and 105e, a transmission path for the high-frequency signal can be established while avoiding other conductor patterns (planar conductors, not shown). Furthermore, increasing the number of layers in the dielectric substrate can increase the rigidity of the substrate. Here, at least one of the planar conductors 101d and 101g to 101i may not be provided. The number of manufacturing steps for the substrate 160 can be reduced, thereby reducing manufacturing costs.

[0072] The above describes a modified example of this embodiment. The modified example of this embodiment may be applied to the substrate described above or the substrate described below, or may be applied in combination with other modified examples, as long as no contradictions arise. The substrate of this embodiment propagates a high-frequency signal between the internal signal lines 102a and 102b. Since at least a portion of the inner wall of the through hole 105 is not covered with a conductor, the possibility of the through hole 105 becoming a stub is reduced, thereby reducing degradation of the transmission characteristics of the high-frequency signal. Furthermore, by connecting the space of the through hole 105, the space of the conductor via 103a, and the space of the conductor via 103b, the air pressure outside the substrate can be made approximately equal to the air pressure in these spaces, thereby reducing stress that causes peeling or adhesion to a portion of the layer (dielectric substrate) that forms the substrate. As a result, the long-term reliability of the substrate is improved.

[0073] (Second embodiment) In the first embodiment, the high-frequency signal is propagated between the signal lines 102a and 103b through the conductive vias 103a and 103b. This high-frequency signal may also be propagated through slots. FIG. 15(A) is a three-dimensional view of a substrate 200 according to a second embodiment. The substrate 200 has the same components as the substrate 120, and includes a slot 201a in the planar conductor 104a and a slot 201b in the planar conductor 104d. The substrate 200 can improve the transmission coefficient of high-frequency signals by propagating the high-frequency signal between the signal lines 102a and 103b through the conductive vias 103a and 103b and through the slots 201a and 201b. Here, between the propagation through the conductive vias 103a and 103b and the propagation through the slots 201a and 201b, the propagation through the slots 201a and 201b is dominant. For ease of visibility, in Fig. 15(A), the substrate 200 before lamination is shown with gaps between the dielectric substrates 101a to 101d. Fig. 15(B) is an xz cross-sectional view of the substrate 200 after lamination.

[0074] The slots 201a and 201b are used to transmit high-frequency signals between the signal lines 102a and 102b. The high-frequency signals are transmitted through the slots 201a and 201b by electromagnetic coupling. The length of the slots 201a and 201b is approximately half the guide wavelength of the high-frequency signals. The slots may have any shape, such as a straight slot as shown in FIG. 15(A), a slot having at least one bent, a slot having at least a curved shape, or multiple slots. The slots 201a and 201b may have the same shape or different shapes. If the planar conductor 104d is not provided, the high-frequency signals may be transmitted through the slot 201a alone.

[0075] In propagation through the conductive vias 103a and 103b, depending on the thickness of the adhesive layers 106b and 106c in the first direction, the capacitance between the conductive vias 103a and 103b and the capacitance between the conductive via 103b and the signal line 102b may be reduced. If the signal line 102a is provided on the a2 surface of the dielectric substrate 101a, the capacitance between the signal line 102a and the conductive via 103a may be reduced. On the other hand, in propagation using the slots 201a and 201b, the propagation is performed by electromagnetic field coupling, which reduces the impact of deterioration in the transmission characteristics of high-frequency signals due to reduced capacitance. As a result, deterioration in the transmission characteristics of high-frequency signals is reduced, and propagation of high-frequency signals between the signal lines 102a and 102b can be stabilized.

[0076] The components of the substrate 200 have been described above. This embodiment is an example, and various modifications can be implemented. For example, the first embodiment and the modifications described in the first embodiment can be applied. Modifications that can be applied to this embodiment will be described below.

[0077] (Variation 12) Various shapes of the slots 201a and 201b are possible. FIG. 16 is an xz cross-sectional view of the substrate 200′ after lamination. The shape of the slot 201a′ in the substrate 200′ is H-shaped. The shape of the slot 201b′ can also be H-shaped. FIG. 17 is an xz cross-sectional view of the substrate 200″ after lamination. The shape of the slot 201a″ in the substrate 200″ is C-shaped. The shape of the slot 201b″ can also be C-shaped. Both the substrates 200′ and 200″ can propagate high-frequency signals, just like the substrate 200. By making the shape of the slot 201a H-shaped or C-shaped, the substrate can be made smaller in the y direction. As a result, the substrate can be made more compact, and costs can be reduced.

[0078] (Variation 13) The substrate 130 described in Modification 9 may be provided with the slots described in this embodiment. FIG. 18(A) is a three-dimensional view of a substrate 210 in Modification 13. The substrate 210 has the slot 201a″ described in Modification 12 provided in the planar conductor 104a of the substrate 130, and the slot 201b″ provided in the planar conductor 104d. For ease of visibility, FIG. 18(A) illustrates the substrate 210 before lamination with the dielectric substrates 101a to 101d spaced apart from one another. FIG. 18(B) is an xz cross-sectional view of the substrate 210 after lamination. Like the substrate 200, the substrate 210 can also propagate high-frequency signals. Furthermore, the conductor vias 131a, 131b, 131c, and 131d described in Modification 9 can reduce leakage of high-frequency signals due to the parallel plate mode in the signal lines 102a, 102b and the conductor vias 103a and 103b. As a result, deterioration of the transmission characteristics (pass characteristics) of high-frequency signals can be reduced.

[0079] FIG. 19 shows the frequency characteristics of the transmission coefficient of high-frequency signals in the substrates 130 and 210. That is, it shows the transmission coefficient relative to the normalized frequency of the high-frequency signal. The larger the numerical value of the transmission coefficient (the smaller the absolute value), the less deterioration of the transmission characteristics of the high-frequency signal. The substrate 130 (0 μm) is represented by a dashed line and represents the case where the planar conductors 104a and 104d are electrically connected in the substrate 130, i.e., the case where the adhesive layer 106b is not present. The substrate 130 (30 μm) is represented by a long-dashed line and represents the case where the planar conductors 104a and 104d are separated by 30 μm by the adhesive layer 106b in the substrate 130. The substrate 210 (0 μm) is represented by a solid line and represents the case where the planar conductors 104a and 104d are electrically connected in the substrate 210, i.e., the case where the adhesive layer 106b is not present. Substrate 210 (30 μm) is represented by a dashed line, and represents the case where planar conductors 104a and 104d are separated by 30 μm by adhesive layer 106b.

[0080] When the planar conductors 104a and 104d are electrically connected (0 μm), the substrate 210 has a higher transmission coefficient over a wider frequency range than the substrate 130, but there is no significant difference.

[0081] When the distance between planar conductors 104a and 104d is 30 μm, in substrate 130, which propagates high-frequency signals through conductive vias 103a and 103b, the transmission coefficient deteriorates by approximately -2.7 dB to -4.2 dB in the normalized frequency range of 0.95 to 1.05. On the other hand, in substrate 210, which propagates high-frequency signals through slots 201a″ and 201b″ in addition to conductive vias 103a and 103b, the deterioration of the transmission coefficient is suppressed to approximately -0.6 dB to -0.9 dB in the normalized frequency range of 0.95 to 1.05.

[0082] In the substrate 130, which propagates high-frequency signals via the conductive vias 103a and 103b, the capacitance between the conductive vias 103a and 103b decreases as the distance between the planar conductors 104a and 104d increases, i.e., as the thickness of the adhesive layer 106b increases, the transmission characteristics of the high-frequency signals deteriorate. On the other hand, in the substrate 210, which propagates high-frequency signals via the slots 201a″ and 201b″ in addition to the conductive vias 103a and 103b, the influence of the distance between the planar conductors 104a and 104d, i.e., the thickness of the adhesive layer 106b, can be reduced more than in the substrate 210. Therefore, by propagating high-frequency signals using the slots 201 as well as the conductive vias 103, it is possible to reduce the degradation of the transmission characteristics of high-frequency signals over a wide frequency range.

[0083] The above describes the modified examples of this embodiment. The modified examples of this embodiment may be applied to the previously described boards as long as no contradictions arise, or the modified examples may be combined and applied. The board of this embodiment propagates high-frequency signals between internal signal lines 102a and 102b. By conducting this propagation not only through conductive vias 103a and 103b but also through slots 201a and 201b, the transmission characteristics of high-frequency signals can be improved.

[0084] (Third embodiment) Fig. 20 is a configuration diagram of a high-frequency circuit 300 according to the third embodiment. The high-frequency circuit 300 includes a substrate 100 (or 200) and a signal circuit 301 that supplies a high-frequency signal propagating through this substrate. While Fig. 20 refers to the substrate 100 (or 200), hereinafter the substrate 100 (or 200) refers to any of the substrates described in the first embodiment, second embodiment, and modified examples.

[0085] The signal circuit 301 generates a high-frequency signal and supplies it to the substrate 100 (or 200). The substrate 100 (or 200) receives this high-frequency signal at one of the signal lines 102a and 102b (for example, the signal line 102a) and transmits it to the other signal line (for example, the signal line 102b). In the case of the substrate 160, the high-frequency signal is received at one of the signal lines 102a and 102c and transmits it to the other signal line. By configuring the high-frequency circuit 300 using the substrate 100 (or 200), it is possible to reduce deterioration in the transmission characteristics of the high-frequency signal and improve the long-term reliability of the high-frequency circuit 300.

[0086] (Fourth embodiment) 21 is a configuration diagram of an antenna device 400 according to the fourth embodiment. The antenna device 400 includes a substrate 100 (or 200) and an antenna element 401 that radiates a high-frequency signal propagated from this substrate.

[0087] The antenna element 401 emits a high-frequency signal propagated from the substrate 100 (or 200) as a radio wave. The antenna element 401 receives the radio wave and inputs it to the substrate 100 (or 200) as a high-frequency signal. The substrate 100 (or 200) outputs the signal to the antenna element 401 from one of the signal lines 102a and 102b (for example, signal line 102a). The substrate 100 (or 200) receives the high-frequency signal from the antenna element 401 that has received the radio wave from one of the signal lines 102a and 102b, and propagates it to the other signal line (for example, signal line 102b). In the substrate 160, the signal lines are 102a and 102c instead of 102a and 102b.

[0088] Antenna element 401 may be configured on the same substrate as substrate 100 (or 200), or may be configured by combining a substrate different from substrate 100 (or 200), and may propagate a high frequency signal via a coaxial cable or the like.

[0089] By configuring the antenna device 400 using the substrate 100 (or 200), it is possible to reduce deterioration in the transmission characteristics of high frequency signals and improve the long-term reliability of the antenna device 400.

[0090] (Fifth embodiment) 22 is a configuration diagram of a wireless communication device 500 according to the fifth embodiment. The wireless communication device 500 includes a radio signal circuit 501 and a conversion circuit 502 in addition to the antenna device 400 according to the fourth embodiment.

[0091] The radio signal circuit 501 generates a signal used for radio communication (hereinafter also referred to as a radio signal) and sends it to the conversion circuit 502. The radio signal circuit 501 also receives a signal demodulated by the conversion circuit 502 (hereinafter also referred to as a demodulated signal) and processes the demodulated signal.

[0092] The conversion circuit 502 modulates the radio signal sent from the radio communication circuit 501, converts it into a high-frequency signal, and sends it to the antenna device 400. The conversion circuit 502 also demodulates the high-frequency signal sent from the antenna device 400, and sends the demodulated signal to the radio signal circuit 501.

[0093] The substrate 100 (or 200) receives the converted high-frequency signal from the conversion circuit 502 via one of the signal lines 102a and 102b (for example, signal line 102a) and propagates it to the other signal line (for example, signal line 102b). The high-frequency signal is sent from this other signal line to the antenna element 401 and radiated as a radio wave. When the antenna element 401 receives a radio wave, it sends it to the other signal line (102b) as a high-frequency signal. The substrate 100 (or 200) receives the high-frequency signal from the antenna element 401 via the other signal line (102b), propagates it to the other signal line (102a), and sends it to the conversion circuit 502. On the substrate 160, the signal lines are 102a and 102c instead of 102a and 102b.

[0094] By configuring the wireless communication device 500 using the substrate 100 (or 200), it is possible to reduce deterioration in the transmission characteristics of high frequency signals and improve the long-term reliability of the wireless communication device 500.

[0095] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0096] 100, 100', 100": Substrate 101a to 101h: dielectric substrate 102a~102c: Signal line 103a to 103e: Conductor vias 104a to 104j: Planar conductors 105, 105a~105c: Through hole 106a~106g: Adhesive layer 120, 120', 120A~120F: PCB 130: Circuit board 131a to 131d: Conductor vias 140: Circuit board 150: Circuit board 160: Circuit board 200, 200', 200": Substrate 201a, 201a', 201a”, 201b, 201b', 201b”: slots 210: Substrate 300: High frequency circuit 301: Signal circuit 400: Antenna device 401: Antenna element 500: Wireless communication device 501: Radio signal circuit 502: Conversion circuit

Claims

1. a first dielectric substrate having a first surface and a second surface and a first through hole extending from the first surface to the second surface; a second dielectric substrate having a third surface and a fourth surface, and a first conductor via provided in a direction connecting the third surface and the fourth surface; a first signal line provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate having a fifth surface and a sixth surface and a second conductor via provided in a direction connecting the fifth surface and the sixth surface; a first planar conductor disposed between the second dielectric substrate and the third dielectric substrate and spaced apart from the first conductive via and the second conductive via; a fourth dielectric substrate; a second signal line provided between the third dielectric substrate and the fourth dielectric substrate; a first adhesive layer provided between the first dielectric substrate and the second dielectric substrate, the first adhesive layer having a first hole overlapping the first through hole and the first conductive via; a second adhesive layer provided between the second dielectric substrate and the third dielectric substrate, the second adhesive layer having a second hole overlapping the first conductive via and the second conductive via; a third adhesive layer provided between the third dielectric substrate and the fourth dielectric substrate; Equipped with At least a portion of a first inner wall of the first dielectric substrate in the first through hole is not covered with a conductor, the first through hole and the first conductor via at least partially overlap in a first direction connecting the first dielectric substrate and the second signal line; the first conductor via and the second conductor via at least partially overlap in the first direction; the second conductor via and the second signal line at least partially overlap in the first direction; In the first direction, a portion of the conductor of the first conductive via overlaps with the third surface, and another portion of the conductor of the first conductive via overlaps with the fourth surface. substrate.

2. a first dielectric substrate having a first surface and a second surface and a first through hole extending from the first surface to the second surface; a second dielectric substrate having a third surface and a fourth surface, and a first conductor via provided in a direction connecting the third surface and the fourth surface; a first signal line provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate having a fifth surface and a sixth surface and a second conductor via provided in a direction connecting the fifth surface and the sixth surface; a first planar conductor disposed between the second dielectric substrate and the third dielectric substrate and spaced apart from the first conductive via and the second conductive via; a fourth dielectric substrate; a second signal line provided between the third dielectric substrate and the fourth dielectric substrate; a first adhesive layer provided between the first dielectric substrate and the second dielectric substrate, the first adhesive layer having a first hole overlapping the first through hole and the first conductive via; a second adhesive layer provided between the second dielectric substrate and the third dielectric substrate, the second adhesive layer having a second hole overlapping the first conductive via and the second conductive via; a third adhesive layer provided between the third dielectric substrate and the fourth dielectric substrate; Equipped with At least a portion of a first inner wall of the first dielectric substrate in the first through hole is not covered with a conductor, the first through hole and the first conductor via at least partially overlap in a first direction connecting the first dielectric substrate and the second signal line; the first conductor via and the second conductor via at least partially overlap in the first direction; the second conductor via and the second signal line at least partially overlap in the first direction; In the first direction, a portion of the conductor of the second conductive via overlaps with the fifth surface, and another portion of the conductor of the second conductive via overlaps with the sixth surface. substrate.

3. a first dielectric substrate having a first surface and a second surface and a first through hole extending from the first surface to the second surface; a second dielectric substrate having a third surface and a fourth surface, and a first conductor via provided in a direction connecting the third surface and the fourth surface; a first signal line provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate having a fifth surface and a sixth surface and a second conductor via provided in a direction connecting the fifth surface and the sixth surface; a first planar conductor disposed between the second dielectric substrate and the third dielectric substrate and spaced apart from the first conductive via and the second conductive via; a fourth dielectric substrate; a second signal line provided between the third dielectric substrate and the fourth dielectric substrate; a first adhesive layer provided between the first dielectric substrate and the second dielectric substrate, the first adhesive layer having a first hole overlapping the first through hole and the first conductive via; a second adhesive layer provided between the second dielectric substrate and the third dielectric substrate, the second adhesive layer having a second hole overlapping the first conductive via and the second conductive via; a third adhesive layer provided between the third dielectric substrate and the fourth dielectric substrate; Equipped with At least a portion of a first inner wall of the first dielectric substrate in the first through hole is not covered with a conductor, the first through hole and the first conductor via at least partially overlap in a first direction connecting the first dielectric substrate and the second signal line; the first conductor via and the second conductor via at least partially overlap in the first direction; the second conductor via and the second signal line at least partially overlap in the first direction; the fourth surface is between the third surface and the sixth surface; the fifth surface is between the third surface and the sixth surface; a portion of the conductor of the first conductor via overlaps with the fourth surface in the first direction, a portion of the conductor of the second conductor via overlaps with the fifth surface in the first direction, and the portion of the conductor of the first conductor via overlaps with the portion of the conductor of the second conductor via in the first direction; substrate.

4. a high frequency signal is propagated from the first signal line to the second signal line, or a high frequency signal is propagated from the second signal line to the first signal line; The substrate according to any one of claims 1 to 3.

5. The first inner wall has a first surface side covered with a conductor and a second surface side not covered with a conductor. The substrate according to any one of claims 1 to 4.

6. a second planar conductor provided on the first dielectric substrate; the first signal line is provided between the first planar conductor and the second planar conductor; The substrate according to any one of claims 1 to 5.

7. the first dielectric substrate has a plurality of third conductor vias that are provided in a direction connecting the first surface and the second surface and are electrically connected to the second planar conductors; the second dielectric substrate has a plurality of fourth conductor vias that are provided in a direction connecting the third surface and the fourth surface and are electrically connected to the first planar conductors; the plurality of third conductor vias and the plurality of fourth conductor vias at least partially overlap in the first direction; the intervals between the third conductor vias or the fourth conductor vias are equal to or less than half of the guide wavelength of a high frequency signal; The substrate of claim 6.

8. a third planar conductor is further provided on the fourth dielectric substrate; the second signal line is provided between the first planar conductor and the third planar conductor; A substrate according to any one of claims 1 to 7.

9. the third dielectric substrate has a plurality of fifth conductor vias provided in a direction connecting the fifth surface and the sixth surface and electrically connected to the first planar conductors; the fourth dielectric substrate has a plurality of sixth conductor vias provided in a direction connecting the seventh surface and the eighth surface and electrically connected to the third planar conductor; the plurality of fifth conductor vias and the plurality of sixth conductor vias at least partially overlap in the first direction; the intervals between the fifth conductor vias or the sixth conductor vias are equal to or less than half of the guide wavelength of a high frequency signal; The substrate of claim 8.

10. a fourth planar conductor between the first signal line and the first planar conductor or between the first planar conductor and the second signal line; the fourth planar conductor is spaced apart from the first conductive via and the second conductive via; The substrate according to any one of claims 1 to 9.

11. the fourth dielectric substrate has a seventh conductor via provided in a direction connecting the seventh surface and the eighth surface, moreover, a fifth dielectric substrate having a ninth surface and a tenth surface, and an eighth conductor via provided in a direction connecting the ninth surface and the tenth surface; a third planar conductor disposed between the fourth dielectric substrate and the fifth dielectric substrate and spaced apart from the seventh conductive via and the eighth conductive via; a sixth dielectric substrate having an eleventh surface and a twelfth surface, and a second through hole provided in a direction connecting the eleventh surface and the twelfth surface; a third signal line provided between the fifth dielectric substrate and the sixth dielectric substrate; At least a portion of a second inner wall of the sixth dielectric substrate in the second through hole is not covered with a conductor, the second through hole and the eighth conductor via at least partially overlap in a second direction connecting the fifth dielectric substrate and the sixth dielectric substrate, the seventh conductor via and the eighth conductor via at least partially overlap in the second direction; the second conductor via and the seventh conductor via do not overlap in at least one of the first direction and the second direction; The substrate according to any one of claims 1 to 10.

12. The second inner wall is covered with a conductor on the twelfth surface side and is not covered with a conductor on the eleventh surface side. The substrate of claim 11.

13. a fifth planar conductor is further provided on the sixth dielectric substrate; the third signal line is provided between the third planar conductor and the fifth planar conductor; 13. The substrate according to claim 11 or 12.

14. the first planar conductor has a slot for propagating a high-frequency signal between the first signal line and the second signal line; A substrate according to any one of claims 1 to 13.

15. A substrate according to any one of claims 1 to 14; a signal circuit that supplies a high-frequency signal to be propagated through the first signal line and the second signal line; High frequency circuits.

16. A substrate according to any one of claims 1 to 14; an antenna element that radiates a high-frequency signal propagated from the first signal line or the second signal line; Equipped with Antenna device.

17. an antenna device according to claim 16; a wireless signal circuit for generating a wireless signal used in wireless communication; a conversion circuit that converts the wireless signal into a high-frequency signal and supplies the high-frequency signal to the first signal line or the second signal line; Equipped with Wireless communication device.

18. a first dielectric substrate having a first surface and a second surface and a first through hole extending from the first surface to the second surface; a second dielectric substrate having a third surface and a fourth surface, and a first conductor via provided in a direction connecting the third surface and the fourth surface; a first signal line provided between the first dielectric substrate and the second dielectric substrate; a third dielectric substrate having a fifth surface and a sixth surface and a second conductor via provided in a direction connecting the fifth surface and the sixth surface; a first planar conductor disposed between the second dielectric substrate and the third dielectric substrate and spaced apart from the first conductive via and the second conductive via; a fourth dielectric substrate; a second signal line provided between the third dielectric substrate and the fourth dielectric substrate; a first adhesive layer provided between the first dielectric substrate and the second dielectric substrate, the first adhesive layer having a first hole overlapping the first through hole and the first conductive via; a second adhesive layer provided between the second dielectric substrate and the third dielectric substrate, the second adhesive layer having a second hole overlapping the first conductive via and the second conductive via; a third adhesive layer provided between the third dielectric substrate and the fourth dielectric substrate; At least a portion of a first inner wall of the first dielectric substrate in the first through hole is not covered with a conductor, the first through hole and the first conductor via at least partially overlap in a first direction connecting the first dielectric substrate and the second signal line; the first conductor via and the second conductor via at least partially overlap in the first direction; the second conductor via and the second signal line at least partially overlap in the first direction; the fourth surface is between the third surface and the sixth surface; the fifth surface is between the third surface and the sixth surface; a portion of the conductor of the first conductor via overlaps with the fourth surface in the first direction, a portion of the conductor of the second conductor via overlaps with the fifth surface in the first direction, and the portion of the conductor of the first conductor via overlaps with the portion of the conductor of the second conductor via in the first direction; A method for manufacturing a substrate.

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