Memory access controller and memory access control method

Abstract

To provide a memory access controller for suppressing a decrease in throughput of memory access requested by a user.SOLUTION: A memory access controller includes: a request issuing part for issuing a user request in response to an inputted memory request, issuing a refresh request at a first issue interval, and issuing a scrubbing request at a second issue interval; and a command issuing part for issuing an active via a row command path and M reads via a column command path after issuing an active to a memory each in execution of a user's request, issuing a refresh via a row command path in execution of a refresh request, and issuing an active via a row command path and N reads (N>M) via the column command path after issuing an active to a memory each in execution of a scrubbing request.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a memory access controller and a memory access control method. Regarding. [Background technology]

[0002] A memory access controller (MAC) responds to memory requests issued by a processor core or a cache circuit and issues commands corresponding to the memory specifications to control the memory requests. Memory requests are, for example, memory access requests from application programs, and mainly include read requests, write requests, etc. Such memory requests issued by a processor core or a cache circuit are hereinafter referred to as user memory requests or user requests.

[0003] On the other hand, in addition to user requests, the MAC issues memory requests to maintain data stored in the memory, such as refresh requests and scrubbing requests, due to the structure of dynamic random access memory (DRAM).

[0004] Refresh is a process of reading and rewriting stored data before the charge state of the DRAM cell capacitor is lost in order to prevent the charge state from being lost. Scrubbing is a process of detecting bit inversions in stored data caused by exposure of the memory chip to cosmic rays such as alpha rays, and correcting data errors. Refresh must be performed on all memory cells within a first predetermined time. Similarly, scrubbing must be performed on all memory cells within a second predetermined time.

[0005] The MAC issues row commands to the memory via a row command bus and column commands via a column command bus, and also inputs (reads) and outputs (writes) data to the memory via a data bus.

[0006] In the case of a refresh, the MAC issues an active row command, drives the memory word line, amplifies the charge state of the cell, and refreshes the charge state of the cell. In a refresh, the MAC does not need to issue a column command. In the case of a scrub, the MAC issues an active row command and then issues a read column command to read the cell data. The MAC then detects errors in the read data and writes the error-corrected data to the cell. In this write, the MAC issues an active row command and then issues a write column command.

[0007] The following patent documents disclose memory access control using MAC: [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-260472 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-107614 Summary of the Invention [Problem to be solved by the invention]

[0009] In the case of a user request, the MAC issues an active command via the row command bus to drive the word line of the memory, and issues a read command via the column command bus the number of times corresponding to the access length to read data from the memory. The MAC controls user-requested memory access with a fixed access length, taking into account the decrease in throughput during consecutive accesses. For example, if a user-requested memory access is performed with an access length of 4, the MAC issues a read command four times for one active command. For example, depending on the software-requested access length, the hardware MAC executes user-requested memory access with a fixed access length. Or, for example, the MAC executes user-requested memory access twice.

[0010] By setting the memory access requested by the user to a fixed access length, it is possible to simplify the constraints on the timing of issuing commands to the memory, and to avoid the memory access control by the MAC becoming complicated.

[0011] On the other hand, a scrubbing request is a read request that the MAC performs on its own initiative, regardless of a user request from the LLC. However, both a read request due to a scrubbing request and a read request due to a user request are the same read request to the memory. Therefore, the MAC performs memory access with the fixed access length described above, even when a read request due to a scrubbing request is performed.

[0012] In recent deep learning calculations, there has been an increase in single-granularity memory accesses, such as low-precision calculations such as single-precision and half-precision. The increased memory accesses are mainly reads. As the frequency of memory accesses increases, the frequency of issuing active commands due to user requests also increases.

[0013] On the other hand, as the memory capacity increases, the number of refreshes and scrubs per unit time also increases. The increase in the number or frequency of refreshes and scrubs also leads to an increase in the frequency of issuing active signals.

[0014] As a result, an increase in the frequency of issuing active commands due to user requests induces a bottleneck on the row command bus, resulting in a decrease in the throughput of memory access due to user requests. Furthermore, if the memory capacity increases, the frequency of issuing active commands due to the accompanying refresh requests and scrubbing requests increases, resulting in a bottleneck on the row command bus. As a result, active commands issued due to user requests are hindered by the issuance of active commands for refresh and scrubbing, resulting in a restriction that active commands issued due to user requests cannot be issued. This is because refresh and scrubbing are processes necessary for saving data in memory, and the issuance of these active commands cannot be reduced. This results in a decrease in the throughput of user requests.

[0015] Therefore, an object of a first aspect of this embodiment is to provide a memory access controller and a memory access control method that suppress a decrease in the throughput of memory accesses requested by users. [Means for solving the problem]

[0016] A first aspect of this embodiment is a memory control system including: a request issuing unit that issues a user request in response to an input memory request, issues a refresh request at a first issuing interval, and issues a scrubbing request at a second issuing interval; When executing the memory access requested by the user, an active is issued to the memory via a row command bus, and after issuing the active, M reads are issued to the memory via a column command bus; When executing the memory access of the refresh request, a refresh is issued to the memory via the row command bus; a command issuing unit that, when executing the memory access of the scrubbing request, issues the active to the memory via the row command bus, and issues N reads, which is greater than M, to the memory via the column command bus after issuing the active. [Effects of the Invention]

[0017] According to the first aspect, a decrease in throughput of memory accesses requested by users is suppressed. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a diagram illustrating an example of the configuration of a processor CPU having a memory access controller (MAC) according to the present embodiment. [Figure 2A] FIG. 10 is a timing chart illustrating an example of memory access control. [Figure 2B] FIG. 10 is a timing chart illustrating an example of memory access control. [Figure 3] FIG. 3 is a diagram showing a schematic flowchart of memory access control of the MAC shown in FIGS. 2A and 2B. [Figure 4A] FIG. 4 is a timing chart illustrating an example of memory access control in the first embodiment. [Figure 4B] FIG. 4 is a timing chart illustrating an example of memory access control in the first embodiment. [Figure 5] FIG. 5 is a diagram showing a schematic flowchart of memory access control of the MAC shown in FIGS. 4A and 4B. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of a memory access controller according to the present embodiment. [Figure 7] FIG. 10 is a flowchart showing an outline of the overall process of the MAC. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of a refresh requester REF_RQTR. [Figure 9] FIG. 10 is a diagram illustrating an example of the configuration of a scrubbing requester SCB_RQTR. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a user requester USR_RQTR. [Figure 11] FIG. 10 is a diagram illustrating a configuration example of a request selector (request selection unit). [Figure 12] FIG. 10 is a flowchart illustrating the operation of the refresh busy check circuit REF_BSY_CHECK. [Figure 13]FIG. 10 is a flowchart illustrating the operation of the scrubbing busy check circuit SCB_BSY_CHECK. [Figure 14] FIG. 10 is a flowchart illustrating the operation of the user busy check circuit USR_BSY_CHECK. [Figure 15] FIG. 10 is a flowchart illustrating the operation of the select circuit SELECT_1 of the request selector REQ_SEL. [Figure 16] FIG. 10 is a diagram illustrating an example of the configuration of a row command issuing unit R_CMD_GEN. [Figure 17] FIG. 10 is a flowchart illustrating an example of the operation of a row command issuing unit. [Figure 18] FIG. 10 is a diagram illustrating an example of the configuration of a column command issuing unit C_CMD_GEN. [Figure 19] FIG. 10 is a flowchart illustrating an example of the operation of a column command issuing unit. [Figure 20] FIG. 11 is a schematic flowchart of memory access control by a MAC according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] 1 is a diagram showing an example of the configuration of a processor CPU having a memory access controller (MAC) according to this embodiment. The processor CPU is, for example, a central processing unit. The processor CPU has multiple, for example, eight processor cores CORE (hereinafter simply referred to as cores). Each core CORE has, for example, an instruction decoder, an arithmetic unit that executes the decoded instructions, a level 1 (L1) cache unit, etc., and issues memory requests that request memory access in conjunction with program execution.

[0020] The processor further includes a last level cache unit LLC, which is shared by, for example, the L1 caches of multiple cores, and a MAC that controls memory requests to the memory MEM. In Fig. 1, the MAC is provided within the processor CPU chip. However, the MAC may also be provided outside the processor CPU chip.

[0021] When the LLC detects a cache miss for a memory request issued by a processor core, it issues a memory request to the MAC. The request issued by the LLC to the MAC is called a user request USR_REQ to distinguish it from memory requests such as scrubbing requests and refresh requests issued by the MAC itself.

[0022] The MAC issues row commands R_CMD via a row command bus R_CMD_BS and column commands C_CDM via a column command bus C_CMD_BS to control memory requests to the memory MEM. Furthermore, the MAC is connected to the memory MEM via a data bus DQ_BS, and receives data from the memory MEM in the case of a read, and transmits data to the memory MEM in the case of a write, via the data bus DQ_BS.

[0023] FIG. 1 shows a schematic configuration of a memory MEM. The memory has multiple, e.g., four, bank groups BG, and each bank group is identified by a two-bit bank group address BG[1:0]. Although not shown in FIG. 1, each bank group BG has multiple, e.g., eight, banks, and each bank is identified by a three-bit bank address BA[2:0]. Each bank has multiple word lines and multiple bit lines, and cells that store data are located at the intersections of the word lines and bit lines. Each cell is identified by a row address RA that identifies the word line and a column address CA that identifies the bit line. An address that identifies the minimum unit of access is called adrs. In this specification, ba[4:0] is an address that identifies a bank, and ba[4:0] = BG[1:0], BA[2:0].

[0024] In this embodiment, it is assumed that the memory access control to the memory MEM by the MAC is a closed page memory access control method. In the closed page memory access control method, an active row command is issued to drive a word line, a read or write column command is issued to read or write data, and finally a precharge command is issued to end the driving of the word line. After that, a new active command is applied to the memory to perform the next memory access. Therefore, one memory request starts with an active command and ends with a precharge command.

[0025] [Example of memory access control where user requests are hindered by refresh and scrubbing requests] 2A and 2B are timing charts showing an example of memory access control. This memory access control example explains an example in which a user request is blocked by a refresh request and a scrubbing request. In the diagram, the clock numbers 1, 2, 3, 4, 5, and 6 are shown in the clock CLK row. In other words, each of FIGS. 2A and 2B shows a timing chart divided into two sections, top and bottom, for a total of four consecutive sections.

[0026] FIG. 3 is a schematic flowchart of memory access control by the MAC shown in FIGS. 2A and 2B. When the MAC executes a scrubbing request (YES in S1), it issues an active ACT to the memory via the row command bus, and then issues a read RD to the memory M times via the column command bus (S2). For example, M times is four. When the MAC executes a refresh request (YES in S3), it issues a refresh Refresh to the memory via the row command bus (S4). No reads or other commands are issued to the column command bus. When the MAC executes a user request (YES in S5), it issues an active ACT to the memory via the row command bus, and then issues a read RD to the memory M times via the column command bus (S6). M times is four, the same as scrubbing. A scrubbing request and a user request are the same read access control from the memory's perspective. Therefore, the MAC's hardware circuitry performs common circuit operations in which the access length (number of reads) for a scrubbing request and a user request is the same, M times.

[0027] Next, the memory access control shown in the timing charts of FIGS. 2A and 2B will be explained in the order of a user request, a scrubbing request, and a refresh request.

[0028] [User Request] First, we will explain the DQ terminal, which is the active, read, and data terminal for a user request. At clocks CLK1 and CLK2, the MAC issues the first user request active ACT BG0_u. This active is for bank group BG0. The bank group ID (GB0) and user request u are added to the active code ACT. Then, at clocks CLK9 and CLK10, after the command issue constraint tRRDS from the issuance of the first active ACT BG0_u (CLK1), the MAC issues the second memory request active ACT BG1_u (CLK9). The command issue constraint tRRDS means the RAS to RAS Delay among different memory bank groups. In this example, the command issue constraint tRRDS is 8 clocks.

[0029] The MAC issues the first read R BG0u (CLK16) at clock CLK16 after the command issuance constraint tRCDRD following the issuance of the first active ACT BG0_u (CLK1). The command issuance constraint tRCDRD is the RAS to CAS Delay for Read, which is 15 clocks. Furthermore, the second read R BG0_u (CLK20) is issued at clock CLK20 after the command issuance constraint tCCDL (=4) following the issuance of the first read R BG0u (CLK16), and the third and fourth reads R BG0_u (CLK24) and R BG0_u (CLK28) are issued at clocks CLK24 and CLK28, respectively, after a further tCCDL (=4). As described above, the user request has an access length of 4, and the MAC issues one active ACT followed by four consecutive reads R as a row command ROW and a column command COL, respectively.

[0030] Four sets of data are output from the data terminal DQ at clocks CLK27 and CLK28 after a latency of tRL (=11) from the issuance of the first read R BG0_u (CLK16). That is, as is known from the double data rate of DDR SDRAM (Double Data Rate Synchronous DRAM), data is output from the data terminal DQ at the rising and falling edges of the clock. Then, four sets of data are output from the data terminal DQ at CLK31, CLK35, and CLK39, which are tRL (=11) after the issuance of the second, third, and fourth reads CLK20, CLK24, and CLK28. This completes memory access control by the first user-requested active ACT BG0_u (CLK1).

[0031] In the figure, the active states of the four bank groups BG0 to BG3 are indicated by ACTIVE. In the case of bank group BG0, the active state is from the row command active ACT BG0 (CLK1) to the last column command read R BG0 (CLK28). A precharge PRE (not shown) is added to the fourth read R BG0_u (CLK28), and the memory is returned to the state before activation.

[0032] After issuing a memory request active ACT BG1_u (CLK9) to the second bank group BG1, the MAC issues four read R BG1u at intervals of the command issuance constraint tCCDL (=4) (CLK30, CLK34, CLK38) starting from CLK26 after the command issuance constraint tRCDRD+2 (=15+2=17). Then, data is output to the data terminal DQ from each read at CLK37, CLK41, CLK45, CLK47 after tRL=11.

[0033] For the second memory request, active ACT BG1_u (CLK9), its read R BG1u (CLK26) is issued at CLK26 after the command issuance constraint tRCDRD+tCCDS (=15+2=17) to avoid conflict with the third read R BG0u (CLK24) of the first memory request, active AVT_BG0_u (CLK1). tCCDS=2 is the CAS-to-CAS delay between different bank groups. This differs from the first memory request, active ACT BG0_u (CLK1). As a result, the third and fourth read R BG0u (CLK24, CLK28) of the first memory request, active ACT BG0_u (CLK1), and the first and second read R BG1u (CLK26, CLK30) of the second memory request, active ACT BG1_u (CLK9), are issued alternately at intervals of tCCDS=2. Similarly, on the DQ terminal, the third and fourth data pairs (CLK35, CLK39) of the first memory request active ACT BG0_u (CLK1) and the first and second data pairs (CLK37, CLK41) of the second memory request active ACT BG1_u (CLK9) are output alternately at intervals of tCCDS=2.

[0034] The third memory request active ACT BG3_u (CLK25) is after the scrubbing active ACT BG2_s (CLK17) and is an even-numbered active. Therefore, like the second memory request active ACT BG1_u (CLK9), four read R BG3u (CLK46, CLK50, CLK54) are issued at intervals of tCCDL=4 starting from CLK42 after the command issue constraint tRCDRD+tCCDS (=17) from active ACT BG3_u (CLK25). Furthermore, data is output to the data terminal DQ at CLK53, CLK57, CLK61, and CLK65 after tRL=11 from each read.

[0035] The fourth memory request active ACT BG1_u (CLK41) is after the refresh Refresh (CLK33) and is an even-numbered active. The fifth memory request active ACT BG0_u (CLK49) is an odd-numbered active. The issuance of these read commands and the data on the DQ pins are the same as described above.

[0036] [Scrubbing Request] In the examples of Figures 2A and 2B, a scrubbing request active ACT BG2_s (CLK17) is issued at clock CLK17. This active is controlled as an odd-numbered active. Therefore, similar to the first memory request active ACT BG0_u (CLK1), four read R BG2s (CLK32, CLK36, CLK40, CLK44) are issued at intervals of tCCDL=4 from CLK32 after command issuance constraint tRCDRD (=15) from active ACT BG2_s (CLK17). Furthermore, data is output to the data terminal DQ from each read at CLK43, CLK47, CLK51, and CLK55 after tRL=11.

[0037] In a scrubbing request, the MAC issues one active and four reads, similar to a read user request, to read data from the memory. The MAC then checks the read data for errors, corrects any errors, and executes the write user request to the memory. However, Figures 2A and 2B do not show the row and column commands of the write user request.

[0038] Assume that any row command, including a user request active, a scrubbing request active, or a refresh request refresh, can be issued with clock CLK17. However, in the examples of FIGS. 2A and 2B, the scrubbing request active is issued when its issuance timing arrives. Therefore, the issuance of a user request active that could have been issued is prevented by scrubbing. A state in which a user request active can be issued means a state in which the row command issuance constraint is satisfied and the column command and DQ terminal are not competing with other memory requests.

[0039] [Refresh Request] A refresh command, Refresh BG0 (CLK33), is issued at clock CLK33. During refresh, just as when an active command is issued, the word lines in the memory are driven, the charge state of the memory cell is read onto the bit lines, the bit line potential is amplified by the sense amplifier, the charge state of the memory cell is refreshed to the write state, the word line drive is terminated, and the data is rewritten. Therefore, the MAC does not issue a read command as requested by the user, nor does it read data from the memory. Therefore, no commands are issued to the column command bus COL at CLK48, CLK52, CLK56, or CLK60, which are tCCDL=4 intervals after the command issuance constraint tRCDRD (=15) from Refresh BG0 (CLK33). Similarly, data is not output to the data terminal DQ at CLK59, CLK63, CLK67, or CLK71, which are tRL=11 after CLK48, CLK52, CLK56, or CLK60, respectively.

[0040] Assume that any row command, including a user request active, a scrubbing request active, or a refresh request refresh, can be issued with clock CLK33. In the examples of Figures 2A and 2B, the refresh BG0 (CLK33) whose issuance timing has arrived is issued. Therefore, the issuance of a user request active, which could have been issued, is prevented by the refresh.

[0041] [Example of memory access control in the first embodiment. Example of improving the throughput of user requests by concealing the performance degradation of user requests due to refresh] 4A and 4B are timing charts showing an example of memory access control in the first embodiment. In this example of memory access control, performance degradation of a user request due to refresh is concealed.

[0042] FIG. 5 is a schematic flowchart of memory access control by the MAC shown in FIGS. 4A and 4B. When the MAC executes a scrubbing request (YES in S1), it issues an active ACT to the memory via the row command bus, and then issues a read RD to the memory via the column command bus N times (S2_A). N times is more than M times, for example, twice M times, which is 8 times, or K times M times, which is 4K times (K=3, 4, etc.). This differs from FIG. 3 in that the access length N of the scrubbing request is longer than the access length M of the memory request.

[0043] Furthermore, when the MAC executes a refresh request (YES in S3), it issues a refresh command (Refresh) to the memory via the row command bus (S4). It does not issue a read command or the like to the column command bus. When the MAC executes a user request (YES in S5), it issues an active command (ACT) to the memory via the row command bus, and then issues a read command (RD) to the memory M times via the column command bus (S6). M times is four. This is the same as in Figure 3.

[0044] That is, in this embodiment, the hardware circuit of the MAC sets the access length (number of reads) N of the scrubbing request to be greater than the access length (number of reads) M of the user request. That is, the command issuing unit of the MAC issues different numbers of read commands for the scrubbing request and the user request.

[0045] Note that the schematic flowchart shown in Fig. 5 does not indicate the priority order in which the MAC executes a scrubbing request, a refresh request, and a user request. In other words, if a scrubbing request, a refresh request, and a user request occur simultaneously, it does not indicate that the scrubbing request, the refresh request, and the user request are executed in the order shown in Fig. 5. Fig. 5 only indicates the issuance of an active ACT and a read RD or a refresh Refresh for each request.

[0046] Next, the memory access control shown in the timing charts of FIGS. 4A and 4B will be explained in the order of a user request, a scrubbing request, and a refresh request.

[0047] [User Request] The data output from the read R BG#_u (# is the BG number) and DQ terminals for each of the user-requested column commands Active ACT BG0_u (CLK1), Active ACT BG1_u (CLK9), Active ACT BG3_u (CLK25), Active ACT BG1_u (CLK41), and Active ACT BG0_u (CLK49) in Figures 4A and 4B are the same as those in Figures 2A and 2B.

[0048] [Scrubbing Request] Next, as in FIGS. 2A and 2B, an active ACT BG2_s (CLK17) scrubbing request is issued at clock CLK17. In this embodiment, the scrubbing access length is eight times, longer than the user request of four times. Therefore, eight reads R BG2s (CLK32, CLK36, CLK40, CLK44, CLK48, CLK52, CLK56, CLK60) are issued at intervals of tCCDL=4 after the command issuance constraint tRCDRD (=15) from the active ACT BG2_s (CLK17). In other words, unlike FIGS. 2A and 2B, the latter four reads R BG2s (CLK48, CLK52, CLK56, CLK60) indicated by bold frames are additionally issued. As a result, data is output from each read to the data terminal DQ at CLK43, CLK47, CLK51, CLK55, CLK59, CLK63, CLK67, and CLK71 after tRL=11.

[0049] [Refresh Request] As in FIGS. 2A and 2B, a refresh command Refresh BG0 (CLK33) is issued at clock CLK33. As described above, during refresh, the MAC does not issue a read command, as requested by the user, and does not read data from the memory. Therefore, no read command is issued on the column command bus COL, and no data is output from the data terminal. Instead, in this embodiment, four reads R BG2s (CLK48, CLK52, CLK56, CLK60) are issued at intervals of tCCDL=4 after the command issuance constraint tRCDRD (=15) from Refresh BG0 (CLK33) at CLK48, CLK52, CLK56, and CLK60. Similarly, scrubbing data is output to the data terminal DQ at CLK59, CLK63, CLK67, and CLK71 after a latency of tRL=11 from each of the four reads R BG2s.

[0050] A user-requested active cannot be issued in clock CLK33. This is because if a user-requested active is issued in clock CLK33, the read for that active will collide with the last four reads R BG2s (CLK48, CLK52, CLK56, CLK60) for the scrubbing request active ACT BG2_s (CLK17). Similarly, if a user-requested active is issued in clock CLK33, the DQ terminals that output the read data for that active will collide with the DQ terminals (CLK59, CLK63, CLK67, CLK71) that output the data for the last four reads R BG2s (CLK48, CLK52, CLK56, CLK60) that correspond to the scrubbing request active.

[0051] Therefore, if a refresh request is issued at timing CLK33 when an active user request cannot be issued, the issuance of the refresh request will not hinder the issuance of the user request. In other words, the cause of the performance degradation of the user request due to the refresh can be concealed. As a result, the throughput of memory accesses of user requests can be improved. In other words, the degradation of the throughput of memory accesses of user requests due to the refresh can be suppressed.

[0052] In summary, in the memory access control of Figures 2A and 2B, user requests are 4 reads per active, 4 reads per scrubbing request, and 0 reads per refresh. In contrast, in the memory access control of Figures 4A and 4B, user requests are 4 reads per active, 8 reads per scrubbing request, and 0 reads per refresh.

[0053] Therefore, assume that I user requests, J scrubbing requests, and K refresh requests (K>J) are issued. In the memory access control of FIGS. 2A and 2B, the total number of row commands (active and refresh) is I+J+K. In contrast, in the memory access control of FIGS. 4A and 4B, the total number of row commands (active and refresh) is a minimum of I+KJ. This is the case when refresh is issued after J active scrubbing requests. In this case, the J refreshes do not prevent the issuance of active user requests. Also, even if L (J>L) refreshes are issued among the J active scrubbing requests, the total number of row commands (active and refresh) is I+J+KL. In this case, the number of row commands is reduced, and the decrease in the issuance throughput of active user requests is mitigated.

[0054] [Memory access controller configuration example] 6 is a diagram showing an example of the configuration of a memory access controller in this embodiment. The MAC has requesters REF_RQTR, SCB_RQTR, and USR_RQTR that output refresh requests, scrubbing requests, and user requests, respectively, and a request selection unit REQ_SEL that checks whether the output requests satisfy memory command issuance constraints and are therefore issuable, and selects issuable requests in accordance with a predetermined priority.

[0055] The MAC also has a timing signal generator TICK_GEN that counts the system clock CLK and outputs a timing signal TICK indicating a refresh request is required. The timing signal TICK is supplied to the refresh request and scrubbing request requesters REF_RQTR and SCB_RQTR. The user request requester USR_RQTWR is supplied with a user request USR_REQ from the processor's last level cache LLC. That is, the user request requester USR_RQTWR outputs the user request USR_REQ supplied from the processor to the request selector REQ_SEL. Meanwhile, the refresh request and scrubbing request requesters REF_RQTR and SCB_RQTR spontaneously output refresh requests and scrubbing requests to the request selector REQ_SEL based on the memory's refresh and scrubbing periods.

[0056] The request selection unit REQ_SEL has busy check circuits REF_BSY_CHECK, SCB_BSY_CHECK, and USR_BSY_CHECK that check whether an input request satisfies command issuance constraints and can be issued, and a select circuit SELECT_1 that selects issuable requests in accordance with a predetermined priority.

[0057] Furthermore, the MAC has a command issuing unit CMD_GEN. The command issuing unit CMD_GEN has a request pipeline REQ_PIPE that holds a selected request REQ, a row command issuing unit R_CMD_GEN, and a column command issuing unit C_CMD_GEN. The request pipeline REQ_PIPE has multiple pipeline stages ST0 to STn through which the selected request REQ flows. The request REQ input to the request pipeline REQ_PIPE outputs a row command issuance request in the first pipeline stage ST0, and a row command R_CMD is issued from the row command issuing unit R_CMD_GEN. Furthermore, each request REQ in the multiple pipeline stages ST0 to STn holds a cycle Cycle that counts clocks after the row command is issued from the row command issuing unit after being input to the request pipeline, and request information (opcode and address). When the cycle Cycle matches the issuance timing of a column command, that request is selected by a select circuit SELECT_2. Then, the column command issuing unit C_CMD_GEN issues the column command C_CMD of the selected request REQ to the column command bus at the respective timings.

[0058] The MAC further comprises an error checking and correction circuit ECC, which checks the data read from the memory in response to a scrubbing request for errors and performs correction of error bits.

[0059] 7 is a flowchart showing the outline of the overall processing of the MAC. When it is time to queue a refresh (YES in S11), the MAC queues a refresh request REF_REQ in a queue in the refresh requester REF_RQTR (S12). When it is time to queue a scrubbing (YES in S13), the MAC queues a scrubbing request SCB_REQ in a queue in the scrubbing requester SCB_RQTR (S14). Then, when the MAC receives a user request USR_REQ from the core and LLC (YES in S15), it queues the user request USR_REQ in a queue in the user requester USR_RQTR (S16).

[0060] The queued refresh requests, scrubbing requests, and user requests are output to the request selection unit REQ_SEL. Note that the queuing timing for refresh is the timing at which refresh is executed. Similarly, the queuing timing for scrubbing is the timing at which scrubbing is executed.

[0061] Next, the MAC performs a busy check of each request REQ using the three busy check circuits of the request selection unit REQ_SEL (S17). If the busy check finds a scrubbing request SCB_REQ that satisfies the issuance conditions (YES in S18), the select circuit SELECT_1 issues the scrubbing request SCB_REQ to the command issue unit CMD_GEN (S19). If there is no scrubbing request that satisfies the issuance conditions (NO in S18), but there is a refresh request REF_REQ that satisfies the issuance conditions (YES in S20), the select circuit SELECT_1 issues the refresh request to the command issue unit CMD_GEN (S21).

[0062] Furthermore, if there is no refresh request that satisfies the issuance condition (NO in S20), and there is a user request USR_REQ that satisfies the issuance condition (YES in S22), the select circuit SELECT_1 issues the user request USR_REQ to the command issuing unit CMD_GEN (S22). MAC repeats the above process.

[0063] [Requester configuration and operation] Figure 8 shows an example of the configuration of the refresh requester REF_RQTR. Refresh is performed on all cells in the memory at a predetermined period. Refresh must be performed before the cell's charge state is lost due to leakage, and the refresh period is set based on the rate at which the cell's charge state is lost. In this embodiment, the timing signal generator TICK_GEN shown in Figure 6 counts the clock CLK and generates a timing signal TICK at a period obtained by dividing the set refresh period by the number of banks in the memory.

[0064] The refresh requester REF_RQTR has a request queue REQ_QUE and a bank address generator BA_GEN. The refresh requester sets the valid data VAL[0] to VAL

[31] of 32 entries in the request queue REQ_QUE to "1" in order in synchronization with the timing signal TICK becoming "1", and queues the refresh requests. The refresh requester also has a bank address generator BA_GEN. In synchronization with the timing signal TICK becoming "1", the bank address generator BA_GEN generates a new bank address BA[4:0] to be refreshed and registers it in the corresponding entry in the request queue REQ_QUE.

[0065] The select circuit SELECT_3 ​​selects the valid data VAL[#] that has become "1" and the corresponding bank address BA[4:0], and outputs a refresh request including the refresh valid REF_VAL and the refresh bank address REF_BA[4:0] to the refresh busy check circuit REF_BSY_CHECK of the request selector.

[0066] Then, as will be described later, when the request selection unit REQ_SEL issues a refresh request to the command issuing unit CMD_GEN, it issues a release signal RLS to release the refresh request. In response to this release signal RLS, the refresh requester REF_RQTR changes the corresponding valid data in the request queue to "0".

[0067] FIG. 9 shows an example of the configuration of the scrubbing requester SCB_RQTR. Scrubbing is performed on all cells in the memory at a predetermined interval. Scrubbing must be performed before the bit inversion of a cell becomes too great for the error check and correction circuit to correct the error. The scrubbing interval is set based on the probability of bit inversion of a cell due to irradiation by cosmic rays or the like.

[0068] In this embodiment, the timing for executing scrubbing is set to once every K timing signals TICK. K is, for example, four. Therefore, the scrubbing requester has a TICK counter TICK_CNT that counts the timing signals TICK, and outputs a scrubbing trigger signal SCB_TRIG every time the TICK counter counts K timing signals TICK.

[0069] The scrubbing requester has a request queue REQ_QUE with one entry and a scrubbing address generation circuit ADRS_GEN. Every time a scrubbing trigger signal SCB_TRIG is generated, the validity of the entry in the request queue REQ_QUE becomes "1," and the scrubbing address generation circuit increments the scrubbing address. Then, the select circuit SELECT_4 outputs a scrubbing request including the scrubbing validity SCR_VAL and the scrubbing address SCB_ADRS[27:0] to the scrubbing busy check circuit SCB_BSY_CHECK of the request selector.

[0070] As will be described later, when the request selection unit REQ_SEL issues a scrubbing request to the command issuing unit CMD_GEN, it issues a release signal RLS to release the scrubbing request. In response to this release signal RLS, the scrubbing requester SCB_RQTR changes the valid data in the request queue REQ_QUE to "0".

[0071] 10 is a diagram showing an example of the configuration of the user requester USR_RQTR. The request queue REQ_QUE in the user requester has multiple, for example, N+1 entries, and registers information on user requests USR_REQ from the core and LLC in available entries. The registered information is user valid USR_VAL_#, user opcode USR_OPCD_#, and user address USR_ADRS_#, where # is the entry number 0 to N. Then, the information in all entries is output as user requests to the user busy check circuit USR_BSY_CHECK of the request selection unit REQ_SEL.

[0072] Similarly, when the request selection unit REQ_SEL issues a user request to the command issuing unit CMD_GEN, it issues a release signal RLS to release the user request. In response to this release signal RLS, the user requester USR_RQTR changes the user valid USR_VAL_# of the corresponding entry in the request queue REQ_QUE to "0".

[0073] [Configuration and operation of the request selector] FIG. 11 is a diagram showing an example of the configuration of a request selector (request selection unit). The request selection unit REQ_SEL has three busy check circuits: REF_BSY_CHECK, SCB_BSY_CHECK, and USR_BSY_CHECK. These busy check circuits check whether the corresponding requests satisfy the issuance conditions. The valid VAL, address BA[4:0], ADRS, operation code OPCD, etc. output by each requester REF_RQTR, SCB_RQTR, and USR_RQTR are input to the respective busy check circuits. In addition, a busy signal MEM_BSY corresponding to the command issuance constraints of the memory is supplied to the busy check circuits. As described above, the memory has multiple command issuance constraints, and the busy signal MEM_BSY includes busy signals corresponding to the multiple command issuance constraints. The busy signal is, for example, a signal that is at a predetermined level (0 or 1) during the period when command issuance is prohibited.

[0074] If each request satisfies the issuance conditions, the busy check circuit sets the ready signals REF_READY, SCB_READY, and USR_READY to "1" to notify that the request is a candidate for selection by the select circuit SELECT_1.

[0075] The request selection unit REQ_SEL also has a select circuit SELECT_1. When any of the ready signals REF_READY, SCB_READY, and USR_READY output by the three busy check circuits is "1," the select circuit SELECT_1 selects one of the refresh request, scrubbing request, and user request whose ready signal has become "1" based on a predetermined priority.

[0076] The operations of the three busy check circuits will be explained below, and further the operation of the select circuit SELECT_1 will be explained.

[0077] 12 is a flowchart showing the operation of the refresh busy check circuit REF_BSY_CHECK. If the refresh valid REF_VAL is 1 (YES in S31) and if issuing a refresh does not violate the command issuance constraints (YES in S32), the refresh busy check circuit outputs a refresh ready signal REF_REDY=1 (S33).

[0078] Refresh command generation constraints include, for example, the delay between active and refresh operations in different bank groups, tRRDS (=8), and the delay between refresh operations in different bank groups, tRREFD. tRRDS (=8) exists between CLK25 and CLK33 in FIG. 4A.

[0079] Furthermore, if refresh valid REF_VAL=0 (NO in S31) or if issuing a refresh violates the command issuance constraint (NO in S32), the refresh busy check circuit outputs refresh ready signal REF_REDY=0 (S34).

[0080] 13 is a flowchart showing the operation of the scrubbing busy check circuit SCB_BSY_CHECK. The scrubbing busy check circuit outputs a scrubbing ready signal SCB_REDY=1 (S44) if the scrubbing valid signal SCB_VAL=1 (YES in S41), if the issuance of the scrubbing does not violate the command issuance constraints (YES in S42), and if the issuance of the scrubbing does not cause a conflict between the column command C_CMD and the DQ terminal (YES in S43).

[0081] The constraints on issuing a scrubbing command are, for example, the delay between actives of different bank groups, tRRDS (=8), and the delay between refresh and actives of different bank groups, tRREFD. In FIG. 4A, tRRDS (=8) exists between CLK9 and CLK17.

[0082] Column command C_CMD contention refers to the conflict between the issuance of eight read R BG2s (CLK32, CLK36, CLK40, CLK44, CLK48, CLK52, CLK56, CLK60) to the active scrubbing ACT BG2_s (CLK17) and the issuance of other active reads in Figure 4A. DQ pin contention refers to the conflict between the data output at CLK43, CLK47, CLK51, CLK55, CLK59, CLK63, CLK67, CLK71 from each of the eight read R BG2s for scrubbing after a latency of tRL=11 and other data outputs in Figure 4B.

[0083] In addition, the scrubbing busy check circuit outputs a scrubbing ready signal SCB_REDY=0 (S45) if the scrubbing valid SCB_VAL=0 (NO in S41), if issuing a scrubbing violates the command issuance constraints (NO in S42), or if issuing a scrubbing results in a conflict between the column command C_CMD and the DQ terminal (NO in S43).

[0084] 14 is a flowchart showing the operation of the user busy check circuit USR_BSY_CHECK. The operation of the user busy check circuit is similar to that of the scrubbing busy check circuit in FIG.

[0085] That is, the user busy check circuit outputs a user ready signal USR_REDY=1 (S54) if the user valid USR_VAL=1 (YES in S51), if the issuance of the user request does not violate the command issuance constraints (YES in S52), and if the issuance of the user request does not cause a conflict between the column command C_CMD and the DQ terminal (YES in S53).

[0086] In addition, the user busy check circuit outputs a user ready signal USR_REDY=0 (S55) if the user valid USR_VAL=0 (NO in S51), if the issuance of the user request violates the command issuance constraints (NO in S52), or if the issuance of the user request results in a conflict between the column command C_CMD and the DQ terminal (NO in S53).

[0087] 15 is a flowchart showing the operation of the select circuit SELECT_1 of the request selector REQ_SEL. The select circuit selects in the order of scrubbing request, user request, and refresh request, that is, in order of priority.

[0088] The select circuit first checks whether scrubbing ready SCB_READY = 1 (S61). If SCB_READY = 1 (YES in S61), the select circuit outputs a scrubbing request including the following data to the request pipeline REQ_PIPE of the command issuing unit CMD_GEN (S64): REQ_VAL =1 REQ_OPCD = RD(SCB) REQ_ADRS = SCB_ADRS SCB_RLS = 1 REF_RLS = 0 USR_RLS = 0 Here, REQ_VAL is the request valid signal, REQ_OPCD is the request opcode, REQ_ADRS is the address of the request, SCB_ADRS is the scrubbing address, and RLS is the release signal. As shown in Figure 6, when the select circuit issues a scrubbing, it returns a release signal to the scrubbing requester SCB_RQTR as a signal to withdraw the scrubbing request.

[0089] Second, if scrubbing ready SCB_READY = 0 (NO in S61), the select circuit checks whether user ready USR_READY = 1 (S62). If USR_READY = 1 (YES in S62), the select circuit outputs a user request having the following data to the request pipeline REQ_PIPE of the command issuing unit CMD_GEN (S65): REQ_VAL =1 REQ_OPCD = RD / WR(USR) REQ_ADRS = USR_ADRS SCB_RLS = 0 REF_RLS = 0 USR_RLS = 1 Here, RD / WR(USR) is read or write, and USR_ADRS is the user address.

[0090] Third, if user ready USR_READY = 1 (NO in S62), the select circuit checks whether refresh ready REF_READY = 1 (S63). If REF_READY = 1 (YES in S63), the select circuit outputs a refresh request having the following data to the request pipeline REQ_PIPE of the command issuing unit CMD_GEN (S65): REQ_VAL =1 REQ_OPCD = REF REQ_ADRS = REF_BA SCB_RLS = 0 REF_RLS = 1 USR_RLS = 0 Here, REF is the refresh and REF_BA is the refresh bank address.

[0091] As shown in the flowchart of Figure 15, when all three ready signals are 1, the select circuit SELECT_1 selects a scrubbing request and issues it to the request pipeline REQ_PIPE of the command issuing unit CMD_GEN. For example, assume that the ready signals for the user request to bank group BG0, the refresh request to BG0, and the scrubbing request to BG2 are 1 at clock CLK17 in Figure 4A. In this case, the select circuit issues the scrubbing request with priority.

[0092] As a result of issuing the scrubbing request active ACT BG2_s (CLK17), the ready signal for that scrubbing request returns to 0. Then, at the timing of clock CLK33, the issuance of the four user-requested reads assumed to have been issued at CLK33 occurs at CLK48 to CLK60, and conflicts with the latter four reads R BG2s (CLK48 to CLK60) for the scrubbing request active ACT BG2_s (CLK17). Therefore, based on FIG. 14, the ready signal for that user request becomes 0. As a result, the select circuit selects the refresh request to BG0, and the row command issuing unit R_CMD_GEN of the command issuing unit issues a refresh Refresh BG0 (CLK33).

[0093] When the select circuit issues a refresh request to the command issuing unit, it feeds back a refresh request release signal to the refresh busy check circuit. As a result, the refresh ready signal becomes 0, and then the select circuit selects the user request that was not issued due to a conflict at the timing of issuing the read command, and issues it to the request pipeline of the command issuing unit.

[0094] In this embodiment, the requesters REF_RQTR and SCB_RQTR synchronously issue refresh requests and scrubbing requests based on the refresh timing signal TICK. This allows the select circuit SELECT_1 to reliably issue the refresh request row command Refresh BG0 (CLK33) at clock CLK33 in synchronization with the timing of the issuance of the scrubbing request (active ACT BG2_s (CLK17)). Clock CLK33 is a timing when active user requests cannot be issued. As a result, it is possible to conceal with a high probability the degradation of user request issuance performance due to refresh.

[0095] Of course, even if the refresh request and the scrubbing request are not synchronized, if the issuance of the scrubbing request and the issuance of the refresh request are probabilistically close in time, the refresh request will be issued at a timing when the active user request cannot be issued after the active scrubbing request is issued. In this case, as in the above, it is possible to conceal the degradation of the performance of issuing user requests due to the refresh.

[0096] [Configuration and operation of the command issuing unit] 6, the command issuing unit R_CMD_GEN has a request pipeline REQ_PIPE, a row command issuing unit R_CMD_GEN, and a column command issuing unit C_CMD_GEN. The configurations and operations of these units will be described below.

[0097] As explained in FIG. 6, the request pipeline REQ_PIPE has a plurality of pipeline stages ST0 to STn, each of which holds information on a selected request REQ. The request REQ input to the request pipeline REQ_PIPE outputs a row command issue request to the row command issue unit R_CMD_GEN in the first pipeline stage ST0. Furthermore, when the timing for issuing a column command for each of the requests REQ in the plurality of pipeline stages ST0 to STn arrives, the request REQ is selected by the select circuit SELECT_2 and output to the column command issue unit C_CMD_GEN. Each of the pipeline stages ST0 to STn holds a cycle CYCLE, which indicates the number of clocks CLK after issuing a row command. This cycle CYCLE is used to determine the timing for issuing the first of consecutive column commands.

[0098] Fig. 16 is a diagram showing a configuration example of the row command issue unit R_CMD_GEN. Also, Fig. 17 is a diagram showing a flowchart of an operation example of the row command issue unit. The row command issue unit R_CMD_GEN has an issue determination circuit ISSUE_DET and a row command issue circuit R_CMD_GEN_CIR. The issue determination circuit ISSUE_DET receives request valid REQ_VAL, request opcode REQ_OPCD, and cycle CYCLE as request information from the first pipeline stage ST0 of the request pipeline REQ_PIPE.

[0099] As shown in FIG. 17, the row command issuing unit determines whether the request valid is REQ_VAL=1 and the cycle is CYCLE=1 (S71). If the determination in S71 is NO, the row command issuing unit does not issue a row command. If the determination in S71 is YES, the row command issuing unit determines whether the request opcode is refresh REF or read or write RD / WR (S72). If the determination in S72 is read or write RD / WR, the row command issuing circuit R_CMD_GEN_CIR issues an active command ACT_CMD to the row command bus (S73). On the other hand, if the determination in S72 is refresh, the row command issuing circuit R_CMD_GEN_CIR issues a refresh command REF_CMD to the row command bus (S74). The active command ACT_CMD is the active ACT in FIGS. 2 and 4. The refresh command REF_CMD is the refresh Refresh in FIGS. 2 and 4. The above-mentioned determinations S71 and S72 are made by the issue determination circuit ISSUE_DET.

[0100] Fig. 18 is a diagram showing an example of the configuration of the column command issuing unit C_CMD_GEN. Fig. 19 is a diagram showing a flowchart of an example of the operation of the column command issuing unit. The column command issuing unit C_CMD_GEN is divided into an even-side issuing unit EVEN and an odd-side issuing unit ODD. The even-side and odd-side column command issuing units each have an issue determination circuit ISSUE_DET_e / o, a counter CNT_e / o, an information holding unit INF_HLD_e / o, and a column command issuing circuit C_CMD_GEN_CIR_e / o.

[0101] The issue determination circuit ISSUE_DET_e / o receives request information from multiple pipeline stages ST0 to STn of the request pipeline REQ_PIPE, including request valid REQ_VAL, request opcode REQ_OPCD, cycle CYCLE, and address ADRS.The issue determination circuit then determines, based on this information, which pipeline stage's requested column command to issue.This determination corresponds to the selection process of the selector circuit SELECT_2 in the request pipeline REQ_PIPE shown in Figure 6.Specific determination process will be described in Figure 19.

[0102] The counters CNT_e / o are set with an initial value corresponding to the number of column commands to be issued, and count down in synchronization with the clock CLK, and the count value is used to control the issuance timing of consecutively issued column commands. The counters have as many counters as the number of column command issuance requests, for example, n+1 counters, the same number as the number of pipeline stages ST0 to STn. This process will also be explained with reference to FIG. 19.

[0103] The information holding unit INF_HLD_e / o holds information from each pipeline stage and is referenced by the issue determination circuit and the column command issue circuit.

[0104] The operation of the column command issuing unit will be described with reference to Fig. 19. The issue determination circuit ISSUE_DETe / o, counter CNTe / o, and column command issuing circuit C_CMD_GEN_CIR_e / o cooperate to perform the following operation. First, for each piece of information on pipeline stages ST0 to STn, if the request valid REQ_VAL is REQ_VAL = 1 (YES in S81), the column command issuing unit C_CMD_GEN determines whether the request opcode REQ_OPCD is a read RD or a write WR (S82).

[0105] In the case of a read RD, when the cycle CYCLE reaches the command issuance constraint tRCDRD+α (YES in S83), the column command issuing unit determines whether the request opcode REQ_OPCD is a user-requested read RD (USR) or a scrubbing-requested read RD (SCB) (S85).

[0106] If the request opcode REQ_OPCD is a user-requested read RD(USR) (RD(USR) in S85), the column command issue unit sets the counter CNT of that request to CNT=16 (S86). The issue determination circuit ISSUE_DET_e / o executes the process up to this point.

[0107] Thereafter, the column command issuing circuit C_CMD_GEN_e / o decrements the counter value CNT (CNT=CNT-1) in synchronization with the clock CLK, issues a read command RD_CMD when the counter value CNT is 15, 11, or 7, and issues a read command RD with PRECHARGE_CMD when the counter value CNT is 3 (S87). The process of S87 is repeated until the counter value CNT becomes CNT=0 (S88). Here, it can be seen that the read command is issued four times in response to the user request.

[0108] If the request opcode REQ_OPCD is a read RD (SCR) for a scrubbing request (RD (SCB) in S85), the column command issue unit sets the counter CNT for that request to CNT = 32 (S89). Up to this point, the issue determination circuit ISSUE_DET_e / o executes the process.

[0109] Thereafter, the column command issuing circuit C_CMD_GEN_e / o decrements the counter value CNT (CNT = CNT - 1) in synchronization with the clock CLK, issues a read command RD_CMD when the counter value CNT is 31, 27, 23, 19, 15, 11, or 7, and issues a precharge read command RD with PRECHARGE_CMD when the counter value CNT is 3 (S90). The process of S90 is repeated until the counter value CNT becomes CNT = 0 (S91). It can be seen that eight read commands are issued for the scrubbing request. This eight is greater than the four read commands issued by the user request. When a precharge read command is issued, the memory outputs the read data from the data terminal DQ and precharges the word lines, thereby terminating the operation requested by the user.

[0110] On the other hand, if the determination in S82 is write WR, when the cycle CYCLE indicating the number of clocks CLK after issuing the row command active ACT reaches the command issue constraint tRCDWR+α (YES in S84), the column command issue unit sets the counter CNT of that request to CNT = 16 (S92). Up to this point, the issue determination circuit ISSUE_DET_e / o executes.

[0111] Thereafter, the column command issuing circuit C_CMD_GEN_e / o decrements the counter value CNT (CNT=CNT-1) in synchronization with the clock CLK, issues a write command WR_CMD when the counter value CNT is 15, 11, or 7, and issues a write command WR with PRECHARGE_CMD when the counter value CNT is 3 (S93). The process of S93 is repeated until the counter value CNT becomes CNT=0 (S94). In response to a user request for a write, the write command is issued four times.

[0112] As described above, in the first embodiment, the MAC issues an active command to the row command bus in a memory access requested by a user, and then sequentially issues M read commands to the memory via the column command bus. Furthermore, in a memory access requested by a scrubbing, the MAC issues N read commands (greater than M) to the memory via the column command bus after issuing an active command. Therefore, the MAC can issue a refresh command at a timing when it cannot issue a user-requested active command after issuing a scrubbing request. This makes it possible to conceal a degradation in user-request issuance performance, which occurs when a user-requested active command cannot be issued due to the issuance of a refresh command. In other words, the degradation in user-request issuance performance that accompanies the issuance of a refresh command is suppressed.

[0113] In the first embodiment, M times is set to 4 times and N times is set to 8 times, but this is not limiting and N times may be set to an integer K times M times (K is an integer greater than 3). However, if the number of times N that a scrubbing request read is issued is set too large, active and read user requests cannot be issued for a long period of time. Therefore, it is preferable to set the scrubbing access length (number of reads) N to the shortest length that can conceal refreshes. If N is set to 8, user request issuance is inhibited in the last four of the eight scrubbing reads, and even if a refresh is issued, the decrease in user request issuance throughput can be concealed. Alternatively, N times may be set based on the amount of time that inhibition of user request issuance is tolerable.

[0114] In the first embodiment, a scrubbing request is issued in synchronization with the issuance timing of a refresh request. Typically, the first issuance interval of a refresh request is shorter than the second issuance interval of a scrubbing request. Therefore, as explained in FIG. 9, the request issuing unit issues a scrubbing request every K (four) refresh requests. However, the issuance timing of a refresh request and the issuance timing of a scrubbing request do not necessarily have to be synchronized. Even if they are not synchronized, as long as there is a non-zero probability that the issuance of a refresh request coincides with or is close to the issuance of a scrubbing request, it is possible to conceal to some extent the performance degradation that occurs when the issuance of a refresh request inhibits the issuance of an active user request.

[0115] [Second embodiment] In the first embodiment, the MAC performs memory access requested by the user by issuing four reads for one active.

[0116] In contrast, in the second embodiment, the MAC executes either (1) control of issuing four reads for one active access, or (2) control of issuing two reads for one active access, for a user-requested memory access. For example, in the case of a user request in which only two short accesses are required, the MAC can omit issuing two unnecessary reads.

[0117] In the second embodiment, when the above two types of user requested memory accesses are performed, the MAC controls the memory access of the scrubbing request to issue four reads for one active. This makes it possible to conceal the performance degradation of the access control of the user request (2) that issues two reads for one active due to the issuance of a refresh command.

[0118] In the second embodiment, when the above two types of user requested memory accesses are performed, the MAC may control the memory access of the scrubbing request by issuing eight reads for one active. In this case, the performance degradation of the access control of the user requests (1) and (2) above due to the issuance of the refresh command can be concealed.

[0119] 20 is a schematic flowchart of memory access control by the MAC in the second embodiment. When the MAC executes a scrubbing request (YES in S1), it issues an active ACT to the row command bus, and then issues a read RD to the column command bus N times (S2_A). N times is, for example, four times.

[0120] Furthermore, when the MAC executes a refresh request (YES in S3), it issues a refresh command to the row command bus (S4), but does not issue a read command or the like to the column command bus.

[0121] When the MAC executes the user request (YES in S5), if the access length of the user request is M1 times (M1 in S7), it issues an active ACT to the row command bus, and then issues a read RD to the column command bus M1 times (S6_A), where M1 times is, for example, 4 times.

[0122] On the other hand, when executing the user request (YES in S5), if the access length of the user request is M2 (M1>M2) times (M2 in S7), the MAC issues an active ACT to the row command bus, and then issues a read RD to the column command bus M2 times (S6_B). M2 times is, for example, 2 times. This is different from Figure 5.

[0123] That is, in this embodiment, the hardware circuit of the MAC makes the access length (number of reads) N of the scrubbing request greater than the shorter access length (number of reads) M2 of the user request (N>M2). That is, the command issuing unit of the MAC makes the number of times N that a read command of the scrubbing request is issued greater than the number M2 of times that a read command of the user request with a shorter access length is issued.

[0124] As a modification of the second embodiment, N>M1>M2 may be set. In this case, N is, for example, 8, and M1 and M2 are, for example, 4 and 2. In this case, it is possible to conceal both the performance degradation of the user request for read M1 due to refresh and the performance degradation of the user request for read M2.

[0125] [Example] Next, an example of the first embodiment will be described. First, a memory access request by a MAC is assumed to consist of one active row command and four read or write column commands. In this case, if one column command can read or write 16 bytes of data, one user request can access 64 bytes of data.

[0126] In addition, the system uses a close-page memory access method that completes a user request with a single activation. The memory has 32 banks (BG[1:0], BA[2:0]).

[0127] The refresh frequency is set to once every 0.062 μsec (62 nsec). To prevent bit inversion of stored data due to charge leakage from memory cells, the refresh of the entire memory area must be completed within the refresh completion time tREFI. Let's assume tREFI = 2 μsec, and use a single-bank refresh interface that issues refresh commands in units of one bank. In other words, 32 or more refresh commands are issued within tREFI = 2 μsec. In this case, tREFI = 2 μsec divided by the number of refresh commands (32) is 0.0625 μsec, which means the refresh frequency should be set to once every 0.062 μsec (62 nsec).

[0128] The memory access for a scrubbing request is performed eight times as a column command for one active command. In this case, error check and correction are performed in 128-byte units for one memory access for a scrubbing request. The memory access for a scrubbing request is performed once for every 10 refreshes. The reason for this is as follows.

[0129] The ECC (Error Checking and Correction) circuit in a normal memory can repair a single-bit error in the data that is subject to ECC. Assume that one scrub cycle is performed every hour for a memory with a memory capacity of 512 GB. The scrub issuance interval is calculated by dividing the time in one day (24h x 60 min x 60 sec) by 24 scrubs per day and the total memory capacity of 512 GB divided by 128 Bytes (the number of times the entire memory is scrubbed), resulting in 0.84 μsec.

[0130] Therefore, since the refresh frequency is once every 0.062 μsec and the scrubbing frequency is once every 0.84 μsec, scrubbing should be performed once every 10 refreshes. In this case, one refresh in ten occurs at a time when a user-requested active cannot be issued, so the performance degradation due to refreshes is reduced to 90%. [Explanation of symbols]

[0131] CPU: Processor, Central Processing Unit MAC: Memory Access Controller USR_RQTR: User requester (user request circuit) REF_RQTR: Refresh requester (refresh request circuit) SCB_RQTR: Scrubbing Requestor (Scrubbing Request Circuit) REQ: Memory access request, memory request USR_REQ: User request REF_REQ: Refresh request SCB_REQ: Scrubbing request REQ_SEL: Request selector, request selection unit (request selection circuit) CMD_GEN: Command issuing unit (command issuing circuit) REQ_PIPE: Request Pipeline Circuit (Request Pipeline) R_CMD_GEN: Row command issuing unit R_CMD_GEN_CIR: Row command issuing circuit C_CMD_GEN: Column command issuing unit C_CMD_GEN_CIR: Column command issuing circuit tRRDS: Restriction on issuing active / refresh commands after active between different bank groups tRREFD: Restriction on issuing active / refresh commands after refresh between different bank groups tREFI: The time a memory cell can retain charge without refreshing tRCDRD: Restriction on issuing a read command after an active command in the same bank tCCDL: Minimum interval between column commands within the same bank group tCCDS: Minimum spacing between column commands between different bank groups tRL: Latency until data is output to the data pin DQ after reading

Claims

1. a request issuing unit that issues user requests in response to input memory requests, issues refresh requests at a first issuing interval, and issues scrubbing requests at a second issuing interval; When executing the memory access requested by the user, an active is issued to the memory via a row command bus, and after issuing the active, M reads are issued to the memory via a column command bus; When executing the memory access of the refresh request, a refresh is issued to the memory via the row command bus; a command issuing unit that, when executing the memory access of the scrubbing request, issues the active to the memory via the row command bus, and issues N reads, which is greater than M, to the memory via the column command bus after issuing the active.

2. N is an integer multiple of M, The command issuing unit The memory access controller according to claim 1 , wherein the refresh is issued at a timing when the active state of the user request cannot be issued after the active state of the scrubbing request is issued.

3. the second issuing interval is K times the first issuing interval, where K is a positive integer; the request issuing unit issues a refresh request at the first issue interval and issues a scrubbing request every K refresh requests; 3. The memory access controller according to claim 2, wherein the command issuing unit issues the scrubbing request active and the refresh in response to the refresh request and the scrubbing request issued by the request issuing unit.

4. Furthermore, a user request busy check unit that checks whether the user request issued by the request issuing unit satisfies a command issuing constraint and a data terminal contention constraint of the memory; a refresh request busy check unit that checks whether the refresh request issued by the request issuing unit satisfies the command issuing constraint; a scrubbing request busy check unit that checks whether the scrubbing request issued by the request issuing unit satisfies the command issuing constraint and the data terminal contention constraint; 3. The memory access controller according to claim 2, further comprising a request selector that, when the scrubbing request, the user request, and the refresh request all satisfy the command issuance constraint and the necessary data terminal conflict constraint, selects the scrubbing request as the execution target with first priority and notifies the command issuing unit.

5. a request issuing process that issues a user request in response to an input memory request, issues a refresh request at a first issuing interval, and issues a scrubbing request at a second issuing interval; When executing the memory access requested by the user, an active is issued to the memory via a row command bus, and after issuing the active, M reads are issued to the memory via a column command bus; When executing the memory access of the refresh request, a refresh is issued to the memory via the row command bus; a command issuing process for issuing the active to the memory via the row command bus when executing the memory access of the scrubbing request, and issuing N reads, which is greater than M, to the memory via the column command bus after issuing the active.

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